K6X4008T1F Family CMOS SRAM Document Title 512Kx8 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Initial Draft July 29, 2002 Preliminary 0.1 Revised - Added 55ns product( Vcc = 3.0V~3.6V) October 14, 2002 Preliminary 0.2 Revised - Added Commercial product December 2, 2002 Preliminary 0.21 Revised - Errata correction : corrected commercial product family name from K6X4008T1F-F to K6X4008T1F-B in PRODUCT FAMILY. March 26, 2003 Preliminary 1.0 Finalized - Changed ICC from 4mA to 2mA - Changed ICC1 from 4mA to 3mA - Changed ICC2 from 30mA to 25mA - Changed ISB1(Commercial) from 15µA to 10µA - Changed ISB1(industrial) from 20µA to 10µA - Changed ISB1(Automotive) from 30µA to 20µA - Changed IDR(Commercial) from 15µA to 10µA - Changed IDR(industrial) from 20µA to 10µA - Changed IDR(Automotive) from 30µA to 20µA September 16, 2003 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.0 September 2003 K6X4008T1F Family CMOS SRAM 512K×8 bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology: Full CMOS • Organization: 512K×8 • Power Supply Voltage: 2.7~3.6V • Low Data Retention Voltage: 2V(Min) • Three State Outputs • Package Type: 32-SOP-525, 32-TSOP2-400F/R 32-TSOP1-0813.4F The K6X4008T1F families are fabricated by SAMSUNG′s advanced full CMOS process technology. The families support various operating temperature range and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Product Family Operating Temperature K6X4008T1F-B Power Dissipation Vcc Range Speed Standby Operating (ISB1, Max) (ICC2, Max) Commercial(0~70°C) 10µA 32-SOP-525, 32-TSOP1-0813.4F 32-TSOP2-400F/R 551)/702)/85ns K6X4008T1F-F Industrial(-40~85°C) K6X4008T1F-Q Automotive(-40~125°C) 10µA 2.7~3.6V 702)/85ns PKG Type 25mA 32-SOP-525, 32-TSOP1-0813.4F 32-TSOP2-400F 20µA 1. This parameter is measured in the voltage range of 3.0V~3.6V with 30pF test load. 2. This parameter is measured with 30pF test load. PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM A18 1 32 VCC VCC 32 1 A16 2 31 A15 31 2 A18 A16 A14 3 30 A17 A15 A17 30 3 A14 A12 4 29 WE WE 29 4 A12 A7 5 28 A13 A13 28 5 A7 A6 6 27 A8 A8 27 6 A6 A5 7 26 A9 A9 26 7 A5 A4 8 25 A11 A11 25 8 A4 A3 9 24 OE OE 24 9 A3 A2 10 23 A10 A10 23 10 A2 A1 11 22 CS CS 22 11 A1 32-SOP 32-TSOP2 (Forward) 32-TSOP2 (Reverse) A0 12 21 I/O8 I/O8 21 12 A0 I/O1 13 20 I/O7 I/O7 20 13 I/O1 I/O2 14 19 I/O6 I/O6 19 14 I/O2 I/O3 15 18 I/O5 I/O5 18 15 I/O3 VSS 16 17 I/O4 I/O4 17 16 VSS A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-STSOP1 (Forward) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Clk gen. OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 Row Addresses Row select I/O1 Data cont I/O8 Function A0~A18 Address Inputs WE Write Enable Input CS Chip Select Input OE Output Enable Input Name Power Vss Ground I/O Circuit Column select Column Addresses CS Function Vcc Memory array Data cont WE Name Precharge circuit. Control logic OE I/O1~I/O8 Data Inputs/Outputs SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 September 2003 K6X4008T1F Family CMOS SRAM PRODUCT LIST Commercial Products(0~70°°C) Part Name Industrial Products(-40~85°°C) Function K6X4008T1F-GB551) K6X4008T1F-GB70 K6X4008T1F-GB85 K6X4008T1F-YB551) K6X4008T1F-YB70 K6X4008T1F-YB85 K6X4008T1F-VB551) K6X4008T1F-VB70 K6X4008T1F-VB85 K6X4008T1F-MB551) K6X4008T1F-MB70 K6X4008T1F-MB85 Part Name K6X4008T1F-GF551) K6X4008T1F-GF70 K6X4008T1F-GF85 K6X4008T1F-YF551) K6X4008T1F-YF70 K6X4008T1F-YF85 K6X4008T1F-VF551) K6X4008T1F-VF70 K6X4008T1F-VF85 K6X4008T1F-MF551) K6X4008T1F-MF70 K6X4008T1F-MF85 32-SOP, 55ns, LL 32-SOP, 70ns, LL 32-SOP, 85ns, LL 32-sTSOP1-F, 55ns, LL 32-sTSOP1-F, 70ns, LL 32-sTSOP1-F, 85ns, LL 32-TSOP2-F, 55ns, LL 32-TSOP2-F, 70ns, LL 32-TSOP2-F, 85ns, LL 32-TSOP2-R, 55ns, LL 32-TSOP2-R, 70ns, LL 32-TSOP2-R, 85ns, LL Automotive Products(-40~125°°C) Function Part Name 32-SOP, 55ns, LL 32-SOP, 70ns, LL 32-SOP, 85ns, LL 32-sTSOP1-F, 55ns, LL 32-sTSOP1-F, 70ns, LL 32-sTSOP1-F, 85ns, LL 32-TSOP2-F, 55ns, LL 32-TSOP2-F, 70ns, LL 32-TSOP2-F, 85ns, LL 32-TSOP2-R, 55ns, LL 32-TSOP2-R, 70ns, LL 32-TSOP2-R, 85ns, LL K6X4008T1F-GQ70 K6X4008T1F-GQ85 K6X4008T1F-YQ70 K6X4008T1F-YQ85 K6X4008T1F-VQ70 K6X4008T1F-VQ85 Function 32-SOP, 70ns, L 32-SOP, 85ns, L 32-sTSOP1-F, 70ns, L 32-sTSOP1-F, 85ns, L 32-TSOP2-F, 70ns, L 32-TSOP2-F, 85ns, L 1. Operating voltage range is 3.0V~3.6V FUNCTIONAL DESCRIPTION CS OE WE 1) 1) I/O Mode Power High-Z Deselected Standby H High-Z Output Disabled Active H Dout Read Active Din Write Active H X L H L L L X1) L X 1. X means don′t care (Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol Ratings Unit Remark VIN, VOUT -0.2 to VCC+0.3(max. 3.9V) V - VCC -0.2 to 3.9 V - PD 1.0 W - TSTG -65 to 150 °C - 0 to 70 °C K6F4008T1F-B TA -40 to 85 °C K6F4008T1F-F -40 to 125 °C K6F4008T1F-Q 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 1.0 September 2003 K6X4008T1F Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Min Typ Max Unit Supply voltage Vcc 2.7 3.0/3.3 3.6 V Ground Vss 0 0 0 V Input high voltage VIH 2.2 - Vcc+0.22) V Input low voltage VIL -0.23) - 0.6 V Note: 1. Commercial Product: TA=0 to 70°C, otherwise specified Industrial Product: TA=-40 to 85°C, otherwise specified Automotive Product: TA=-40 to 125°C, otherwise specified 2. Overshoot: VCC+2.0V in case of pulse width ≤ 30ns 3. Undershoot: -2.0V in case of pulse width ≤ 30ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTICS Item Input leakage current Symbol ILI Test Conditions Min Typ Max Unit VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 2 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA CS≤0.2V,VIN≤0.2V or VIN≥Vcc-0.2V - - 3 mA ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - - 25 mA Average operating current Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS=VIH, Other inputs = VIL or VIH - - 0.3 mA - - 10 µA K6X4008T1F-B Standby Current (CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc 4 K6X4008T1F-F - - 10 µA K6X4008T1F-Q - - 20 µA Revision 1.0 September 2003 K6X4008T1F Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load(see right): CL=100pF+1TTL CL1)=30pF+1TTL CL1) 1. Including scope and jig capacitance 1. 55ns, 70ns product AC CHARACTERISTICS (VCC=2.7~3.6V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40 to 125°C) Speed Bins Parameter List Symbol Write 70ns Units 85ns Min Max Min Max Min Max tRC 55 - 70 - 85 - ns Address access time tAA - 55 - 70 - 85 ns Chip select to output tCO - 55 - 70 - 85 ns Output enable to valid output tOE - 25 - 35 - 40 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 25 0 25 ns Output disable to high-Z output tOHZ 0 20 0 25 0 25 ns Output hold from address change tOH 10 - 10 - 10 - ns Write cycle time tWC 55 - 70 - 85 - ns Chip select to end of write tCW 45 - 60 - 70 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 45 - 60 - 70 - ns Write pulse width tWP 40 - 55 - 55 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 0 25 ns Data to write time overlap tDW 25 - 30 - 35 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns Read cycle time Read 55ns 1) 1. Voltage range is 3.0V~3.6V for commercial and industrial product. DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS≥Vcc-0.2V Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V Data retention set-up time tSDR Recovery time tRDR Min Typ1) Max Unit 2.0 - 3.6 V 10 µA 10 µA 20 µA K6X4008T1F-B - K6X4008T1F-F - K6X4008T1F-Q - See data retention waveform 0.5 0 - - 5 - - ms 1. Typical values are measured at TA = 25°C and not 100% tested. 5 Revision 1.0 September 2003 K6X4008T1F Family CMOS SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO1 CS tHZ tOE OE Data out High-Z tOHZ tOLZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.0 September 2003 K6X4008T1F Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 2.7V 2.2V VDR CS≥VCC - 0.2V CS GND 7 Revision 1.0 September 2003 K6X4008T1F Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeters(inches) 32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil) 0~8° #17 14.12±0.30 0.556±0.012 #1 #16 20.87 0.822 MAX 20.47±0.20 0.806±0.008 13.34 0.525 #32 11.43±0.20 0.450±0.008 2.74±0.20 0.108±0.008 3.00 0.118 MAX 0.80±0.20 0.031±0.008 0.20 +0.10 -0.05 0.008+0.004 -0.002 0.10 MAX 0.004 MAX +0.100 -0.050 +0.004 0.016 -0.002 0.41 ( 0.71 ) 0.028 1.27 0.050 0.05 0.002 MIN 32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F) +0.10 -0.05 0.008+0.004 -0.002 0.20 13.40±0.20 0.528±0.008 #1 #32 8.40 0.331 MAX #17 #16 0.25 0.010 TYP 1.00±0.10 0.039±0.004 1.20 0.047 MAX 11.80±0.10 0.465±0.004 +0.10 -0.05 0.006+0.004 -0.002 0.05 0.002 MIN 0.15 0~8° 0.45 ~0.75 0.018 ~0.030 ( 8 1.10 MAX 0.004 MAX 0.50 0.0197 0.25 ) 0.010 8.00 0.315 ( 0.50 ) 0.020 Revision 1.0 September 2003 K6X4008T1F Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeters(inches) 32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 0.25 ( 0.010 ) #32 0~8° #17 11.76±0.20 0.463±0.008 #1 10.16 0.400 0.45~0.75 0.018 ~ 0.030 #16 21.35 0.841 MAX 1.00±0.10 0.039±0.004 1.20 0.047MAX 20.95±0.10 0.825±0.004 ( 0.15 +0.10 -0.05 0.006 +0.004 -0.002 0.50 ) 0.020 0.10 MAX 0.004 MAX ( 0.95 ) 0.037 0.40±0.10 0.016±0.004 0.05 0.002MIN 1.27 0.050 32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) 0~8° ( 0.25 ) 0.010 #1 #16 11.76±0.20 0.463±0.008 #32 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 #17 21.35 0.841 MAX 1.00±0.10 0.039±0.004 +0.10 -0.05 0.006 +0.004 -0.002 0.15 ( 0.50 ) 0.020 1.20 0.047 MAX 20.95±0.10 0.825±0.004 0.10 MAX 0.004 MAX ( 0.95 ) 0.037 0.40±0.10 0.016±0.004 1.27 0.050 0.05 0.002MIN 9 Revision 1.0 September 2003