350 mA, Low VIN, Low Quiescent Current,
CMOS Linear Regulator
ADP130
TYPICAL APPLICATION CIRCUITS
350 mA maximum output current
Input voltage supply range
VBIAS = 2.3 V to 5.5 V
VIN = 1.2 V to 3.6 V
2.3 V < VIN < 3.6 V, VIN can be tied to VBIAS
Very low dropout voltage: 17 mV @ 100 mA load
Low quiescent current: 25 μA @ no load
Low shutdown current: <1 μA
±1% accuracy @ 25°C
Excellent PSRR performance: 70 dB @ 10 kHz
Excellent load/line transient response
Optimized for small 1 μF ceramic capacitors
Current limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
VIN = 1.8V
1µF
1
+
VIN
VOUT
5
ADP130
2
GND
3
EN
VBIAS
VOUT = 1.2V
1µF
4
+
VBIAS = 3.6V
1µF
+
06963-001
FEATURES
Figure 1.
1µF
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
1
+
VIN
VOUT
5
ADP130
2
GND
3
EN
VBIAS
VOUT = 1.8V
1µF
4
+
VBIAS = 5V
+
1µF
06963-002
VIN = 2.8V
Figure 2.
GENERAL DESCRIPTION
The ADP130 is a low quiescent current, low dropout linear regulator. It is designed to operate in dual-supply mode with an input
voltage as low as 1.2 V to increase efficiency and provide up to
350 mA of output current. The low 17 mV dropout voltage at
a 100 mA load improves efficiency and allows operation over
a wider input voltage range.
A dual-supply power solution typically improves conversion
efficiency over a single-supply solution because the higher VBIAS
supply powers the part, and the lower VIN supply delivers current
to the load. The power dissipated in the device is thereby reduced.
The ADP130 is available in the following 31 fixed output voltage
options:
•
•
0.80 V to 2.00 V in 50 mV steps
1.875 V, 2.25 V, 2.50 V, 2.775 V, 2.80 V, and 3.0 V
The ADP130 has a typical internal soft start time of 200 μs. Shortcircuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP130 is available
in a tiny 5-lead TSOT package for the smallest footprint solution to
meet a variety of portable power applications.
The ADP130 is optimized for stable operation with small 1 μF
ceramic output capacitors. The ADP130 delivers good transient
performance with minimal board area.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADP130
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications....................................................................................... 1
Theory of Operation ...................................................................... 12
Typical Application Circuits............................................................ 1
Applications Information .............................................................. 13
General Description ......................................................................... 1
Capacitor Selection .................................................................... 13
Revision History ............................................................................... 2
Undervoltage Lockout ............................................................... 14
Specifications..................................................................................... 3
Enable Feature ............................................................................ 14
Input and Output Capacitor, Recommended Specifications.. 4
Current Limit and Thermal Overload Protection ................. 15
Absolute Maximum Ratings............................................................ 5
Thermal Considerations............................................................ 15
Thermal Data ................................................................................ 5
Junction Temperature Calculations ......................................... 16
Thermal Resistance ...................................................................... 5
Printed Circuit Board Layout Considerations ....................... 17
ESD Caution.................................................................................. 5
Outline Dimensions ....................................................................... 18
Pin Configuration and Function Descriptions............................. 6
Ordering Guide .......................................................................... 18
REVISION HISTORY
7/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADP130
SPECIFICATIONS
VIN = VOUT + 0.4 V, VBIAS = 5 V, IOUT = 10 mA, CIN = 1 μF, COUT = 1 μF, CBIAS = 1 μF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
BIAS VOLTAGE RANGE
OPERATING SUPPLY CURRENT
Symbol
VIN
VBIAS
IVIN 1
BIAS OPERATING CURRENT
IBIAS
SHUTDOWN CURRENT
ISD-VIN
ISD-VBIAS
FIXED OUTPUT VOLTAGE ACCURACY
VOUT
LINE REGULATION
LOAD REGULATION 2
∆VOUT/∆VIN
∆VOUT/∆IOUT
DROPOUT VOLTAGE 3
VDROPOUT
Conditions
TJ = −40°C to +125°C
TJ = −40°C to +125°C
IOUT = 0 μA
IOUT = 0 μA, TJ = −40°C to +125°C
IOUT = 1 mA
IOUT = 1 mA, TJ = −40°C to +125°C
IOUT = 100 mA
IOUT = 100 mA, TJ = −40°C to +125°C
IOUT = 350 mA
IOUT = 350 mA, TJ = −40°C to +125°C
Typ
Max
3.6
5.5
25
44
40
58
100
130
160
220
16
TJ = −40°C to +125°C
EN = GND
EN = GND, TJ = −40°C to +85°C
EN = GND, TJ = +85°C to +125°C
EN = GND
EN = GND, TJ = −40°C to +125°C
IOUT = 10 mA
1 mA < IOUT < 350 mA, VIN = (VOUT + 0.4 V) to 3.6 V
1 mA < IOUT < 350 mA, VIN = (VOUT + 0.4 V) to 3.6 V,
TJ = −40°C to +125°C
VIN = (VOUT + 0.4 V) to 3.6 V, TJ = –40°C to +125°C
IOUT = 10 mA to 350 mA
IOUT = 10 mA to 350 mA, TJ = −40°C to +125°C
IOUT = 10 mA, VBIAS = 2.3 V, VOUT = 3 V
IOUT = 10 mA, VBIAS = 2.3 V, VOUT = 3 V,
TJ = −40°C to +125°C
IOUT = 100 mA, VBIAS = 2.3 V, VOUT = 3 V
IOUT = 100 mA, VBIAS = 2.3 V, VOUT = 3 V,
TJ = −40°C to +125°C
IOUT = 350 mA, VBIAS = 2.3 V, VOUT = 3 V
IOUT = 350 mA, VBIAS = 2.3 V, VOUT = 3 V,
TJ = −40°C to +125°C
VOUT = 1.2 V
START-UP TIME 4
CURRENT LIMIT THRESHOLD 5
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TSSD
TSSD-HYS
TJ rising
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Leakage Current
VIH
VIL
VI-LEAKAGE
2.3 V ≤ VBIAS ≤ 5.5 V
2.3 V ≤ VBIAS ≤ 5.5 V
EN = BIAS or GND
EN = BIAS or GND, TJ = −40°C to +125°C
UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
Hysteresis
UVLO
UVLORISE
UVLOFALL
UVLOHYS
TSTART-UP
ILIMIT
Min
1.2
2.3
28
0.1
1.0
20
0.1
−1
−2
−3
1.0
+1
+2
+3
−0.10
+0.10
3.5
%/ V
%/A
%/A
mV
mV
28
mV
mV
100
mV
mV
1000
μs
mA
0.001
0.005
2
17
70
400
200
550
°C
°C
150
15
TJ = −40°C to +125°C
TJ = −40°C to +125°C
1.2
0.4
0.1
1
2.1
1.5
180
Rev. 0 | Page 3 of 20
Unit
V
V
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
%
%
%
V
V
μA
μA
V
V
mV
ADP130
Parameter
OUTPUT NOISE
Symbol
OUTNOISE
POWER SUPPLY REJECTION RATIO
PSRR
Conditions
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 0.8 V
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.2 V
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.5 V
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 2.5 V
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 3.0 V
Modulated bias, 10 kHz, VOUT = 3.0 V, VIN = 3.6 V,
VBIAS = 5 V
Modulated bias, 100 kHz, VOUT = 3.0 V, VIN = 3.6 V,
VBIAS = 5 V
Modulated VIN, 10 kHz, VOUT = 1.2 V, VIN = VOUT + 1 V,
VBIAS = 5 V
Modulated VIN, 100 kHz, VOUT = 1.2 V, VIN = VOUT + 1 V,
VBIAS = 5 V
Modulated VIN, 10 kHz, VOUT = 0.8 V, VIN = VOUT + 1 V,
VBIAS = 5 V
Modulated VIN, 100 kHz, VOUT = 0.8 V, VIN = VOUT + 1 V,
VBIAS = 5 V
Min
Typ
29
38
43
61
77
70
Max
Unit
μV rms
μV rms
μV rms
μV rms
μV rms
dB
53
dB
70
dB
54
dB
70
dB
55
dB
1
IVIN = IGND − IBIAS, where IGND is the current flowing from the GND pin.
Based on an endpoint calculation using 1 mA and 350 mA loads.
3
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 1.3 V.
4
Start-up time is defined as the time from the rising edge of EN to VOUT being at 90% of its nominal value.
5
Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 2.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 2.0 V, or 1.8 V.
2
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
MINIMUM INPUT AND OUTPUT
CAPACITANCE 1
CAPACITOR ESR
1
Symbol
CMIN
Conditions
TJ = −40°C to +125°C
Min
0.70
RESR
TJ = −40°C to +125°C
.001
Typ
1
Max
Unit
μF
1
Ω
The minimum input and output capacitance should be >0.70 μF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and
Z5U capacitors are not recommended for use with any LDO.
Rev. 0 | Page 4 of 20
ADP130
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VBIAS to GND
EN to GND
VOUT to GND
Storage Temperature Range
Operating Temperature Range
Operating Junction Temperature
Lead Temperature (Soldering, 10 sec)
Rating
−0.3 V to +3.6 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to VIN
−65°C to +150°C
−40°C to +125°C
125°C
300°C
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply only individually, not in combination. The ADP130 may be damaged when junction temperature
limits are exceeded. Monitoring ambient temperature does not
guarantee that the junction temperature is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated. In applications with moderate power
dissipation and low PCB thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the junction
temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature
(TA), the power dissipation of the device (PD), and the junction-toambient thermal resistance of the package (θJA). TJ is calculated
using the following formula:
The junction-to-ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a four-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The specified
values of θJA are based on a four-layer, 4 in × 3 in circuit board.
For details about board construction, refer to JEDEC JESD51-7.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a four-layer board. The JEDEC JESD51-12
document, Guidelines for Reporting and Using Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. ΨJB measures the component
power flowing through multiple thermal paths rather than a single
path, as in thermal resistance (θJB). Therefore, ΨJB thermal paths
include convection from the top of the package as well as radiation
from the package, factors that make ΨJB more useful in real world
applications. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD), using
the following formula:
TJ = TB + (PD × ΨJB)
Refer to the JEDEC JESD51-8 and JESD51-12 documents for
more detailed information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
TJ = TA + (PD × θJA)
ESD CAUTION
Rev. 0 | Page 5 of 20
θJA
170
ΨJB
43
Unit
°C/W
ADP130
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN 1
EN 3
VOUT
4
VBIAS
ADP130
TOP VIEW
(Not to Scale)
06963-003
GND 2
5
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
VIN
GND
EN
4
5
VBIAS
VOUT
Description
Regulator Input Supply. Bypass VIN to GND with a capacitor of 1 μF or greater.
Ground.
Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup,
connect EN to VBIAS
Bias Input Supply. Connect a capacitor of 1 μF or greater between VBIAS and GND.
Regulated Output Voltage. Bypass VOUT to GND with a capacitor of 1 μF or greater.
Rev. 0 | Page 6 of 20
ADP130
TYPICAL PERFORMANCE CHARACTERISTICS
VBIAS = 5 V, VIN = 2.2 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = CBIAS = 1 μF, TA = 25°C, unless otherwise noted.
1.805
200
LOAD = 1mA
LOAD = 10mA
160
IVIN CURRENT (µA)
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
1.795
1.790
LOAD = 350mA
1.785
140
120
100
80
60
40
LOAD = 1mA
LOAD = 10mA
LOAD = 50mA
20
–40
–5
+25
+85
0
06963-004
1.775
+125
JUNCTION TEMPERATURE (°C)
–40
Figure 4. Output Voltage vs. Junction Temperature
30
BIAS CURRENT (µA)
VOUT (V)
+85
+125
LOAD = 350mA
LOAD = 200mA
LOAD = 100mA
LOAD = 50mA
LOAD = 10mA
LOAD = 1mA
25
1.803
1.801
1.799
1.797
20
15
10
5
10
100
1000
0
06963-005
1
ILOAD (mA)
–40
160
140
1.801
1.800
1.799
1.798
120
100
80
60
40
1.797
20
2.4
2.6
2.8
3.0
3.2
VIN (V)
3.4
3.6
06963-006
1.796
1.795
2.2
+125
Figure 6. Output Voltage vs. Input Voltage
0
06963-009
1.802
+85
180
LOAD = 1mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
LOAD = 350mA
IVIN CURRENT (µA)
1.803
+25
JUNCTION TEMPERATURE (°C)
1.805
1.804
–5
Figure 8. Bias Current vs. Junction Temperature
Figure 5. Output Voltage vs. Load Current
VOUT (V)
+25
Figure 7. IVIN Current vs. Junction Temperature
1.805
1.795
–5
JUNCTION TEMPERATURE (°C)
06963-007
1.780
06963-008
VOUT (V)
LOAD = 100mA
LOAD = 200mA
LOAD = 350mA
180
1.800
1
10
100
ILOAD (mA)
Figure 9. IVIN Current vs. Load Current
Rev. 0 | Page 7 of 20
1000
ADP130
60
25
50
DROPOUT VOLTAGE (mV)
20
15
10
5
40
30
20
0
1
10
100
0
10
1000
100
ILOAD (mA)
Figure 13. Dropout Voltage vs. Load Current, VOUT = 3 V
Figure 10. Bias Current vs. Load Current
200
80
180
DROPOUT VOLTAGE (mV)
LOAD = 350mA
LOAD = 200mA
140
120
100
80
60
20
LOAD = 1mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
0
2.2
2.4
60
VOUT = 1.8V
50
40
20
10
2.6
2.8
3.0
3.2
3.4
3.6
VIN (V)
0
10
1000
Figure 14. Dropout Voltage vs. Output Voltage and Load Current
3.05
25
3.00
20
2.95
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
LOAD = 350mA
2.90
VOUT (V)
15
LOAD = 1mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
LOAD = 350mA
2.85
2.80
2.75
5
2.70
0
2.2
2.4
2.6
2.8
3.0
3.2
VIN (V)
3.4
3.6
2.65
2.75
06963-012
BIAS CURRENT (µA)
100
ILOAD (mA)
Figure 11. Ground Current vs. Input Voltage
10
VOUT = 3.0V
30
06963-014
40
TA = 25°C
70
06963-011
GROUND CURRENT (µA)
160
1000
ILOAD (mA)
06963-013
06963-010
10
2.80
2.85
2.90
2.95
3.00
VIN (V)
Figure 12. Bias Current vs. Input Voltage
3.05
3.10
3.15
3.20
06963-015
BIAS CURRENT (µA)
VOUT = 3V
TA = 25°C
Figure 15. Output Voltage vs. Input Voltage (in Dropout), VOUT = 3 V
Rev. 0 | Page 8 of 20
ADP130
600
0
VRIPPLE = 50mV
VIN = 2.8V
VOUT = 1.8V
COUT = 1µF
–10
–20
–30
400
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
LOAD = 350mA
300
PSRR (dB)
200
–40
–50
–60
–70
–80
LOAD = 100µA
LOAD = 10mA
LOAD = 100mA
LOAD = 350mA
–90
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
VIN (V)
–100
06963-016
0
2.75
10
0
100k
1M
10M
VRIPPLE = 50mV
VIN = 2.2V
VOUT = 1.2V
COUT = 1µF
–10
17
–20
LOAD = 350mA
LOAD = 200mA
–30
16
PSRR (dB)
LOAD = 100mA
LOAD = 50mA
LOAD = 10mA
–40
–50
–60
–70
14
–80
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
VIN (V)
06963-017
13
2.75
LOAD = 100µA
LOAD = 10mA
–90 LOAD = 100mA
LOAD = 350mA
–100
10
100
0
–20
0
VRIPPLE = 50mV
VIN = 3.6V
VOUT = 3.0V
COUT = 1µF
–40
PSRR (dB)
–50
–60
LOAD = 100µA
LOAD = 10mA
LOAD = 100mA
LOAD = 350mA
LOAD = 100µA
LOAD = 10mA
LOAD = 100mA
LOAD = 350mA
–60
100
–100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–120
06963-018
10
10M
–80
–70
–100
1M
VRIPPLE = 50mV
VIN = 1.8V
VOUT = 0.8V
COUT = 1µF
–20
–40
–90
100k
Figure 20. Power Supply Rejection Ratio vs. Frequency, VIN Input
–30
–80
10k
FREQUENCY (Hz)
Figure 17. Bias Current vs. Input Voltage (in Dropout), VOUT = 3 V
–10
1k
06963-020
BIAS CURRENT (µA)
10k
Figure 19. Power Supply Rejection Ratio vs. Frequency, VIN Input
18
PSRR (dB)
1k
FREQUENCY (Hz)
Figure 16. Ground Current vs. Input Voltage (in Dropout), VOUT = 3 V
15
100
06963-019
100
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 18. Power Supply Rejection Ratio vs. Frequency, VIN Input
Figure 21. Power Supply Rejection Ratio vs. Frequency, VIN Input
Rev. 0 | Page 9 of 20
06963-021
GROUND CURRENT (µA)
500
ADP130
0
0
VRIPPLE = 50mV
VOUT = 1.8V
IOUT = 100mA
COUT = 1µF
–20
–20
–30
PSRR (dB)
–40
PSRR (dB)
VRIPPLE = 50mV
VIN = 2.2V
VOUT = 1.2V
COUT = 1µF
–10
1V HEADROOM
0.5V HEADROOM
–60
–80
LOAD = 350mA
LOAD = 100mA
LOAD = 10mA
LOAD = 100µA
–40
–50
–60
–70
–80
–100
10k
100k
1M
10M
FREQUENCY (Hz)
–20
0
–10
–20
PSRR (dB)
–40
–50
–70
–70
–80
–80
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–90
10
–20
1k
10k
100k
1M
10M
10
VRIPPLE = 50mV
VIN = 2.8V
VOUT = 1.8V
COUT = 1µF
3.0V
–30
PSRR (dB)
100
Figure 26. Power Supply Rejection Ratio vs. Frequency, VBIAS Input
LOAD = 350mA
LOAD = 100mA
LOAD = 10mA
LOAD = 100µA
–40
–50
NOISE (µV/√Hz)
0
10M
FREQUENCY (Hz)
Figure 23. Power Supply Rejection Ratio vs. Frequency, VBIAS Input
–10
1M
–50
–60
100
100k
LOAD = 350mA
LOAD = 100mA
LOAD = 10mA
LOAD = 100µA
–40
–60
–90
10
10k
VRIPPLE = 50mV
VIN = 1.8V
VOUT = 0.8V
COUT = 1µF
–30
LOAD = 350mA
LOAD = 100mA
LOAD = 10mA
LOAD = 100µA
06963-023
PSRR (dB)
–30
1k
Figure 25. Power Supply Rejection Ratio vs. Frequency, VBIAS Input
VRIPPLE = 50mV
VIN = 3.6V
VOUT = 3.0V
COUT = 1µF
–10
100
FREQUENCY (Hz)
Figure 22. Power Supply Rejection Ratio vs. Headroom, VIN Input
0
10
06963-026
1k
06963-022
100
–100
06963-025
–90
–120
10
–60
–70
1.5V
1
0.8V
0.1
–80
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0.01
10
100
1k
10k
FREQUENCY (Hz)
Figure 27. Noise Spectrum vs. VOUT
Figure 24. Power Supply Rejection Ratio vs. Frequency, VBIAS Input
Rev. 0 | Page 10 of 20
100k
06963-027
–100
06963-024
–90
ADP130
90
1.8V
2.5V
3.0V
80
VIN
70
3V TO 3.5V INPUT VOLTAGE STEP
2V/µs
NOISE (µV rms)
60
50
40
2
30
20
06963-031
VOUT
5mV/DIV
0.8V
1.2V
1.5V
10
1
1
10
100
1000
ILOAD (mA)
ILOAD
1mA TO 350mA LOAD STEP
2.5A/µs
200mA/DIV
2
06963-029
M40µs
T 10.40%
A CH1
06963-030
VOUT
2mV/DIV
1
CH2 2mV
M40µs
T 10.20%
A CH1
CH2 5mV
M20µs
T 10.20%
A CH1
3.27V
Figure 32. VIN Line Transient Response, VBIAS = 5 V, IOUT = 350 mA
VBIAS
3V TO 3.5V INPUT VOLTAGE STEP
2V/µs
500mV/DIV
CH1 500mV
VOUT
5mV/DIV
CH1 500mV
VIN = 3.6V
2
3.37V
1
92mA
Figure 29. Load Transient Response
1
A CH1
VIN
VOUT
50mV/DIV
CH2 50mV
M20µs
T 10.20%
3V TO 3.5V INPUT VOLTAGE STEP
2V/µs
2
CH1 200mA
CH2 5mV
Figure 31. VIN Line Transient Response, VBIAS = 5 V, IOUT = 1 mA
Figure 28. Output Noise vs. Load Current and Output Voltage
1
CH1 500mV
06963-032
0.1
06963-028
0
0.01
3.35V
Figure 30. VBIAS Line Transient Response, VIN = 3.6 V, IOUT = 350 mA
Rev. 0 | Page 11 of 20
ADP130
THEORY OF OPERATION
Internally, the ADP130 consists of a reference, an error amplifier, a feedback voltage divider, and a pass device. The output
current is delivered via the pass device, which is controlled by
the error amplifier, forming a negative feedback system that
ideally drives the feedback voltage to equal the reference voltage.
If the feedback voltage is lower than the reference voltage, the
negative feedback drives more current, increasing the output
voltage. If the feedback voltage is higher than the reference voltage,
the negative feedback drives less current, decreasing the output
voltage. The VBIAS pin is the positive supply for all circuitry
except the pass device.
The ADP130 has an internal soft start that limits the output
voltage ramp period to approximately 200 μs. All internal devices
are controlled by the enable pin, EN. When EN is high, the
output is on; when EN is low, the output is off.
VOUT
VIN
R1
GND
EN
SHORT-CIRCUIT,
UVLO, AND
THERMAL
PROTECT
SHUTDOWN
VBIAS
0.5V
REF
R2
06963-033
The ADP130 is a low dropout, linear regulator that uses an
advanced proprietary architecture to achieve low quiescent
current and high efficiency regulation. It also provides high
power supply rejection ratio (PSRR) and excellent line and load
transient response using a small 1 μF ceramic output capacitor. The
device operates from a 2.3 V to 5.5 V bias rail and a 1.2 V to 3.6 V
input rail to provide up to 350 mA of output current. Supply
current in shutdown mode is typically less than 1 μA.
Figure 33. Internal Block Diagram
The ADP130 is available in 31 output voltage options, ranging from
0.8 V to 3.0 V. The ADP130 uses the EN pin to enable and disable
the VOUT pin under normal operating conditions. When EN is
high, VOUT turns on. When EN is low, VOUT turns off. For automatic startup, EN can be tied to VBIAS.
Rev. 0 | Page 12 of 20
ADP130
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Input Bypass Capacitor
Output Capacitor
Connecting a 1 μF capacitor from VIN to GND reduces the circuit
sensitivity to printed circuit board (PCB) layout, especially when
long input traces or high source impedance are encountered.
If >1 μF of output capacitance is required, the input capacitor
should be increased to match it.
The ADP130 is designed for operation with small, space-saving
ceramic capacitors, but it functions with most commonly used
capacitors as long as care is taken regarding the effective series
resistance (ESR) value. The ESR of the output capacitor affects
the stability of the LDO control loop. A minimum of 0.70 μF
capacitance with an ESR of 1 Ω or less is recommended to ensure
stability of the ADP130. Transient response to changes in load
current is also affected by output capacitance. Using a larger value
of output capacitance improves the transient response of the
ADP130 to large changes in load current. Figure 34 and Figure 35
show the transient responses for output capacitance values of
1 μF and 10 μF, respectively.
ILOAD
1mA TO 350mA LOAD STEP
2.5A/µs
200mA/DIV
1
2
06963-034
VOUT
50mV/DIV
–VOUT = 1.8V
CIN = COUT = 1µF
CH1 200mA
CH2 50mV
M400ns
T 14%
A CH1
192mA
Figure 34. Output Transient Response, COUT = 1 μF
Bias Capacitor
Connecting a 1 μF capacitor from VBIAS to GND reduces the
circuit sensitivity to PCB layout, especially when long input traces
or high source impedance are encountered.
Input, Bias, and Output Capacitor Properties
Any good quality ceramic capacitor can be used with the ADP130,
as long as it meets the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics
are not recommended for use with any LDO, due to their poor
temperature and dc bias characteristics.
Figure 36 shows the capacitance vs. voltage bias characteristics
of the 0402 1μF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40 to +85°C temperature
range and is not a function of the package or voltage rating.
1.2
ILOAD
CAPACITANCE (µF)
VOUT
50mV/DIV
CH2 50mV
0.6
0.4
0.2
–VOUT = 1.8V
CIN = COUT = 10µF
CH1 200mA
0.8
M400ns
T 13%
A CH1
0
160mA
0
2
4
6
8
VOLTAGE (V)
Figure 36. Capacitance vs. Voltage Characteristics
Figure 35. Output Transient Response, COUT = 10 μF
Rev. 0 | Page 13 of 20
10
06963-036
2
06963-035
1
1.0
1mA TO 350mA LOAD STEP
2.5A/µs
200mA/DIV
ADP130
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)
As shown in Figure 37, the EN pin has built-in hysteresis. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
(1)
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
COUT = 0.94 μF at 1.8 V, as shown in Figure 36.
Substituting these values in Equation 1 yields the following:
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
The EN pin active and inactive thresholds are derived from the
VIN voltage. Therefore, these thresholds vary with changing input
voltage. Figure 38 shows typical EN active and inactive thresholds
when the VBIAS voltage varies from 2.3 V to 5.5 V.
1.10
1.05
1.00
0.95
THRESHOLD (V)
Use Equation 1 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component tolerance, and voltage.
0.90
EN ACTIVE
0.85
0.80
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage.
0.75
To guarantee the performance of the ADP130, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
0.60
2.3
0.70
The ADP130 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.1 V. This ensures that the ADP130 inputs
and the output behave in a predictable manner during power-up.
ENABLE FEATURE
The ADP130 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 37,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive
threshold, VOUT turns off.
3.1
3.5
3.9
4.3
4.7
5.1
5.5
06963-038
2.7
VBIAS (V)
Figure 38. Typical EN Pin Thresholds vs. Input
The ADP130 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for the 0.8 V option
is approximately 180 μs from the time at which the EN active
threshold is crossed to when the output reaches 90% of its final
value. The start-up time depends somewhat on the output voltage
setting and increases slightly as the output voltage increases.
5.0
VBIAS = 2.3V
VIN = 3.6V
ILOAD = 10mA
4.5
4.0
ENABLE
3.0V
1.8V
1.2V
0.8V
3.5
VOLTAGE (V)
UNDERVOLTAGE LOCKOUT
–VOUT = 1.8V
CIN = COUT = 1µF
EN INACTIVE
0.65
3.0
2.5
2.0
1.5
VOUT
500mV/DIV
1.0
0
100
200
300
400
500
600
700
Figure 39. Typical Start-Up Time
06963-037
1
2
CH1 500mV
0
TIME (µs)
EN
500mV/DIV
CH2 500mV
M10ms
T 30%
A CH2
640mV
Figure 37. Typical EN Pin Operation
Rev. 0 | Page 14 of 20
800
900 1000
06963-039
0.5
ADP130
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP130 is protected against damage due to excessive power
dissipation by current limit and thermal overload protection
circuits. The ADP130 is designed to current limit when the
output load reaches 550 mA (typical). When the output load
exceeds 550 mA, the output voltage is reduced to maintain
a constant current limit.
Thermal overload protection limits the junction temperature to
a maximum of 150°C typical. Under extreme conditions (that is,
high ambient temperature and power dissipation) when the
junction temperature starts to rise above 150°C, the output is
turned off, reducing output current to zero. When the junction
temperature drops below 135°C, the output is turned on again and
output current is restored to its nominal value.
Consider the case where a hard short from VOUT to GND occurs.
At first, the ADP130 current limits so that only 550 mA is conducted into the short. If self-heating of the junction is great enough
to cause its temperature to rise above 150°C, thermal shutdown
activates, turning off the output and reducing the output current to
zero. As the junction temperature cools and drops below 135°C,
the output turns on and conducts 550 mA into the short, again
causing the junction temperature to rise above 150°C. This
thermal oscillation between 135°C and 150°C causes a current
oscillation between 550 mA and 0 mA that continues as long
as the short remains at the output.
Current limit and thermal overload protections protect the device
against accidental overload conditions. For reliable operation,
device power dissipation must be externally limited so that
junction temperatures do not exceed 125°C.
THERMAL CONSIDERATIONS
To guarantee reliable operation, the junction temperature of the
ADP130 must not exceed 125°C. To ensure that the junction temperature stays below this maximum value, the user needs to be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The value of θJA is dependent on
the package assembly compounds used and the amount of copper
to which the GND pins of the package are soldered on the PCB.
Table 6 shows typical θJA values of the 5-lead TSOT package for
various PCB copper sizes.
Table 6. Typical θJA Values for Specified PCB Copper Sizes
Copper Size (mm2)
01
50
100
300
500
1
θJA (°C/W)
170
152
146
134
131
Device soldered to minimum size pin traces.
The junction temperature of the ADP130 can be calculated from
the following equation:
TJ = TA + (PD × θJA)
(2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND)
(3)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation can
be simplified as follows:
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(4)
As shown in Equation 4, for a given ambient temperature, inputto-output voltage differential, and continuous load current,
a minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 40
through Figure 46 show junction temperature calculations for
different ambient temperatures, load currents, VIN to VOUT
differentials, and areas of PCB copper.
Rev. 0 | Page 15 of 20
ADP130
JUNCTION TEMPERATURE CALCULATIONS
140
140
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
120
120
100
100
80
80
TJ (°C)
60
60
0
0.4
1mA
10mA
0.8
50mA
100mA
1.2
150mA
250mA
1.6
350mA
(LOAD CURRENT)
2.0
2.4
20
06963-040
20
0
0.4
2.8
1mA
10mA
0.8
50mA
100mA
1.2
Figure 40. 500 mm2 of PCB Copper, TA = 25°C, TSOT
2.0
2.4
2.8
Figure 43. 500 mm2 of PCB Copper, TA = 50°C, TSOT
140
140
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
120
120
100
100
80
80
TJ (°C)
60
40
60
40
0
0.4
1mA
10mA
0.8
50mA
100mA
1.2
150mA
250mA
1.6
350mA
(LOAD CURRENT)
2.0
2.4
20
06963-041
20
0
0.4
2.8
1mA
10mA
0.8
50mA
100mA
1.2
VIN – VOUT (V)
1.6
350mA
(LOAD CURRENT)
2.0
2.4
2.8
VIN – VOUT (V)
Figure 41. 100 mm2 of PCB Copper, TA = 25°C, TSOT
Figure 44. 100 mm2 of PCB Copper, TA = 50°C, TSOT
140
140
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
120
100
100
80
80
TJ (°C)
120
60
60
40
20
1mA
10mA
0.8
50mA
100mA
1.2
150mA
250mA
1.6
350mA
(LOAD CURRENT)
2.0
2.4
06963-042
40
0
0.4
150mA
250mA
06963-044
TJ (°C)
1.6
350mA
(LOAD CURRENT)
VIN – VOUT (V)
VIN – VOUT (V)
TJ (°C)
150mA
250mA
06963-043
40
40
2.8
20
0
0.4
1mA
10mA
0.8
50mA
100mA
1.2
150mA
250mA
1.6
350mA
(LOAD CURRENT)
2.0
2.4
VIN – VOUT (V)
VIN – VOUT (V)
Figure 42. 0 mm2 of PCB Copper, TA = 25°C, TSOT
Figure 45. 0 mm2 of PCB Copper, TA = 50°C, TSOT
Rev. 0 | Page 16 of 20
06963-045
TJ (°C)
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
2.8
ADP130
In cases where board temperature is known, use the thermal characterization parameter, ΨJB, to estimate the junction temperature
rise. Maximum junction temperature (TJ) is calculated from the
board temperature (TB) and power dissipation (PD), using the
following formula:
TJ = TB + (PD × ΨJB)
(5)
The typical value of ΨJB is 42.8°C/W for the 5-lead TSOT package.
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP130.
However, as shown in Table 6, a point of diminishing returns is
eventually reached, beyond which an increase in the copper size
does not yield significant heat dissipation benefits.
The input capacitor should be placed as close as possible to the
VIN and GND pins. The output capacitor should be placed as
close as possible to the VOUT and GND pins. Using 0402 or 0603
size capacitors and resistors achieves the smallest possible footprint solution on boards where the area is limited.
140
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
120
100
GND
ANALOG DEVICES
ADP130-xx-EVALZ
60
C1
U1
C2
40
0
0.4
1mA
10mA
0.8
50mA
100mA
1.2
150mA
250mA
1.6
350mA
(LOAD CURRENT)
2.0
2.4
J1
2.8
VIN
VIN – VOUT (V)
VOUT
Figure 46. TSOT, TA = 85°C
C3
GND
EN
VBIAS
GND
Figure 47. Example TSOT PCB Layout
Rev. 0 | Page 17 of 20
06963-047
20
06963-046
TJ (°C)
GND
80
ADP130
OUTLINE DIMENSIONS
2.90 BSC
5
4
2.80 BSC
1.60 BSC
1
2
3
PIN 1
0.95 BSC
1.90
BSC
*0.90
0.87
0.84
*1.00 MAX
0.10 MAX
0.50
0.30
0.20
0.08
SEATING
PLANE
8°
4°
0°
0.60
0.45
0.30
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 48. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions show in millimeters
ORDERING GUIDE
Model
ADP130AUJZ-0.8-R7 1
ADP130AUJZ-1.2-R71
ADP130AUJZ-1.5-R71
ADP130AUJZ-1.8-R71
ADP130AUJZ-2.5-R71
ADP130-0.8-EVALZ1
ADP130-1.2-EVALZ1
ADP130-1.5-EVALZ1
ADP130-1.8-EVALZ1
ADP130-2.5-EVALZ1
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output
Voltage (V)
0.8
1.2
1.5
1.8
2.5
0.8
1.2
1.5
1.8
2.5
Z = RoHS Compliant Part.
Rev. 0 | Page 18 of 20
Package Description
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Package
Option
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
Branding
LCH
LCJ
LCK
LCL
LCM
ADP130
NOTES
Rev. 0 | Page 19 of 20
ADP130
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06963-0-7/08(0)
Rev. 0 | Page 20 of 20