D a t a S h e e t , V 1 . 0 , A u g . 2 00 3 HYS64D64020GBDL–5–B HYS64D64020GBDL–6–B HYS64D64020GBDL–7–B HYS64D64020GBDL–8–B 200- Pi n Small Outli ne Dual -In- Line Memor y Modules S O -D I M M DDR SDRAM M e m or y P r o du c t s N e v e r s t o p t h i n k i n g . Edition 2003-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a t a S h e e t , V 1 . 0 , A u g . 2 00 3 HYS64D64020GBDL–5–B HYS64D64020GBDL–6–B HYS64D64020GBDL–7–B HYS64D64020GBDL–8–B 200- Pi n Small Outli ne Dual -In- Line Memor y Modules S O -D I M M DDR SDRAM M e m or y P r o du c t s N e v e r s t o p t h i n k i n g . HYS64D64020GBDL–5–B, HYS64D64020GBDL–6–B, HYS64D64020GBDL–7–B, HYS64D64020GBDL–8–B Revision History: V1.0 2003-08 Previous Version: 0.6 2003-03 Page Subjects (major changes since last revision) all New data sheet template 21 Changed SPD programming byte tQHS for BGA package from 0.6ns to 0.5ns (SCR-050) 16 editorial change: tQHS set to 0.5ns in electrical characteristics, and tDQSQ to 0.4ns 6,7,15,21 added DDR 400 15 updated Idd currents We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Template: mp_a4_v2.0_2003-06-06.fm HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules Table of Contents 1 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 3.1 3.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data Sheet 5 V1.0, 2003-08 200-Pin Small Outline Dual-In-Line Memory Modules SO-DIMM 1 Overview 1.1 Features • • • • • • • • • • • HYS64D64020GBDL–5–B HYS64D64020GBDL–6–B HYS64D64020GBDL–7–B HYS64D64020GBDL–8–B Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules Two ranks 64M × 64 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5 V (± 0.2 V) power supply Built with 256 Mbit DDR SDRAMs organised as × 8 in P–FBGA–60–1 packages Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Serial Presence Detect with E2PROM Jedec standard form factor: 67.60 mm × 31.75 mm × 3.80 mm Gold plated contacts Table 1 Performance Part Number Speed Code –5 –6 –7 –8 Unit Speed Grade Component DDR400B DDR333B DDR266A DDR200 — Module PC3200–3033 PC2700–2533 PC2100–2033 PC1600–2022 — fCK3 200 @CL2.5 fCK2.5 166 @CL2 fCK2 133 max. Clock Frequency @CL3 1.2 166 — — MHz 166 143 125 MHz 133 133 100 MHz Description The HYS64D64020GBDL–[5/6/7/8]–B are industry standard 200-Pin Small Outline Dual-In-Line Memory Modules (SO-DIMMs) organized 64M × 64. The memory array is designed with Double Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. Data Sheet 6 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules Overview Table 2 Ordering Information Type Compliance Code Description SDRAM Technology PC3200 (CL=3) HYS64D64020GBDL-5-B PC3200S–3033–0–Z two ranks 512 MB SO-DIMM 256 Mbit (× 8) PC2700 (CL=2,5) HYS64D64020GBDL-6-B PC2700S-2533-0-Z two ranks 512 MB SO-DIMM 256 Mbit (× 8) PC2100 (CL=2) HYS64D64020GBDL-7-B PC2100S-2033-0-Z two ranks 512 MB SO-DIMM 256 Mbit (× 8) PC1600 (CL=2) HYS64D64020GBDL-8-B PC1600S-2022-0-Z two ranks 512 MB SO-DIMM 256 Mbit (× 8) Notes 1. All part numbers end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components. 2. The Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the latencies and SPD code definition (for example “2033–0” means CAS latency of 2.0 clocks, RCD1) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module. 1) RCD: Row-Column-Delay Data Sheet 7 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules Pin Configuration 2 Pin Configuration Table 3 Pin Definitions and Functions Symbol Type1) Function A0 - A12 I Address Inputs BA0, BA1 I Bank Address DQ0 - DQ63 I/O Data Input/Output RAS, CAS, WE I Command Input CKE0 - CKE1 I Clock Enable DQS0 - DQS7 I/O SDRAM Data Strobe CK0 - CK1, I SDRAM Clock (true signal) CK0 - CK1 I SDRAM Clock (complementary signal) DM0 - DM8 I Data Mask I Chip Select VDD PWR Power (+ 2.5 V) VSS GND Ground VDDQ PWR I/O Driver power supply VDDID PWR VDD Indentification flag VREF AI I/O reference supply VDDSPD PWR Serial EEPROM power supply SCL I Serial bus clock SDA I/O Serial bus data line SA0 - SA2 I slave address select NC NC Not Connected NU NU Not Usable, reserved for future use S0, S1 2) 1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not Connected; NU: Not Usable 2) CKE1 and S1 are used on two bank modules only Table 4 Address Format Density Organization Memory Ranks SDRAMs # of SDRAMs # of row/bank/ columns bits Refresh Period Interval 512MB 64M × 64 2 32M × 8 16 13/2/10 8K 64 ms 7.8 µs Data Sheet 8 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules Pin Configuration Table 5 Pin Configuration Front side Back side Front side Back side Front side Back side Pin # Symbol Pin # Symbol Pin # Symbol Pin # Symbol Pin # Symbol Pin # Symbol 1 2 DQ26 66 DQ30 133 DQS4 134 DM4 4 VREF VSS 65 3 VREF VSS 67 DQ27 68 DQ31 135 DQ34 136 DQ38 5 DQ0 6 DQ4 69 VDD 70 VDD 137 VSS 138 VSS 7 DQ1 8 DQ5 71 (CB0) 72 (CB4) 139 DQ35 140 DQ39 9 VDD 10 VDD 73 (CB1) 74 (CB5) 141 DQ40 142 DQ44 11 DQS0 12 DM0 75 VSS 76 VSS 143 VDD 144 VDD 13 DQ2 14 DQ6 77 (DQS8) 78 (DM8) 145 DQ41 146 DQ45 15 VSS 16 VSS 79 (CB2) 80 (CB6) 147 DQS5 148 DM5 17 DQ3 18 DQ7 81 VDD 82 VDD 149 VSS 150 VSS 19 DQ8 20 DQ12 83 (CB3) 84 (CB7) 151 DQ42 152 DQ46 21 VDD 22 VDD 85 DU 86 DU 153 DQ43 154 DQ47 23 DQ9 24 DQ13 87 VSS 88 155 VDD DQS1 26 DM1 89 (CK2) 90 158 CK1 27 VSS 28 VSS 91 (CK2) 92 160 CK1 29 DQ10 30 DQ14 93 VDD 94 161 VDD VDD VSS VSS 156 25 VSS VSS VDD VDD 162 VSS 31 DQ11 32 DQ15 95 CKE1 96 CKE0 163 DQ48 164 DQ52 33 VDD 34 97 DU 98 DU 165 DQ49 166 DQ53 35 CK0 36 99 A12 100 A11 167 VDD 168 VDD 37 CK0 38 101 A9 102 A8 169 DQS6 170 DM6 39 VSS VDD VDD VSS VSS 103 VSS 104 VSS 171 DQ50 172 DQ54 105 A7 106 A6 173 VSS 174 VSS 107 A5 108 A4 175 DQ51 176 DQ55 40 Key 157 159 41 DQ16 42 DQ20 109 A3 110 A2 177 DQ56 178 DQ60 43 DQ17 44 DQ21 111 A1 112 A0 179 VDD 180 VDD 45 VDD 46 VDD 113 VDD 114 VDD 181 DQ57 182 DQ61 47 DQS2 48 DM2 115 A10/AP 116 BA1 183 DQS7 184 DM7 49 DQ18 50 DQ22 117 BA0 118 RAS 185 VSS 186 VSS 51 VSS 52 VSS 119 WE 120 CAS 187 DQ58 188 DQ62 53 DQ19 54 DQ23 121 S0 122 S1 189 DQ59 190 DQ63 55 DQ24 56 DQ28 123 DU 124 DU 191 VDD 192 VDD 57 VDD 58 VDD 125 VSS 126 VSS 193 SDA 194 SA0 59 DQ25 60 DQ29 127 DQ32 128 DQ36 195 SCL 196 SA1 61 DQS3 62 DM3 129 DQ33 130 DQ37 197 198 SA2 63 VSS 64 VSS 131 VDD 132 VDD 199 VDDSPD VDDID 200 DU Data Sheet 9 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules pin 199 pin 39 pin 41 pin 40 pin 42 front side pin 200 pin 1 pin 2 Pin Configuration back side Figure 1 Data Sheet Pin Configuration 10 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules Pin Configuration S1 S0 DQS4 DM4/DQS13 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS D0 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS D8 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS D1 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D9 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS D2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D10 VDD SPD VDD/VDDQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS D3 VSS D0 - D15 BA0-BA1: SDRAMs D0 - D15 A0 - A13 A0-A13: SDRAMs D0 - D15 CKE: SDRAMs D8 - D15 RAS: SDRAMs D0 - D15 CAS CAS: SDRAMs D0 - D15 CKE0 CKE: SDRAMs D0 - D7 WE WE: SDRAMs D0 - D15 Data Sheet S DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D11 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S S DQS D12 DQS D5 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS D13 DQS D6 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS D14 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S D7 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS D15 Serial PD SCL Strap: see Note 4 BA0 - BA1 Figure 2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 - D15 D0 - D15 CKE1 RAS S D4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SPD VREF VDDID DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS7 DM7/DQS16 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 S DQS6 DM6/DQS15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DM5/DQS14 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 SDA WP A0 A1 A2 SA0 SA1 SA2 * Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 4 SDRAMs 6 SDRAMs 6 SDRAMs * Wire per Clock Loading Table/Wiring Diagrams Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%. 4. VDDID strap connections (for memory device VDD, V DDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): V DD ≠ VDDQ 5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms +5% Block Diagram - Two Rank 64M × 64 DDR SDRAM SO-DIMM HYS64D64020GBDL–[5/6/7/8]–B 11 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules Electrical Characteristics 3 Electrical Characteristics 3.1 Operating Conditions Table 6 Absolute Maximum Ratings Parameter Symbol Values min. Voltage on I/O pins relative to VSS VIN, VOUT –0.5 typ. max. Unit Note/ Test Condition – VDDQ + V – 0.5 Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current VIN VDD VDDQ TA TSTG PD IOUT –1 – +3.6 V – –1 – +3.6 V – –1 – +3.6 V – 0 – +70 °C – -55 – +150 °C – – 1 – W – – 50 – mA – Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Table 7 Electrical Characteristics and DC Operating Conditions Parameter Symbol Unit Note/Test Condition 1) Values Min. Typ. Max. 2.3 2.5 2.7 V 2.5 2.6 2.7 V 2.3 2.5 2.7 V 2.5 2.6 2.7 V fCK ≤166 MHz fCK > 166 MHz 2) fCK ≤166 MHz 3) fCK > 166 MHz 2)3) 2.3 2.5 3.6 V — 0 V — 0.51 × V 4) VDDQ VDDQ VREF – 0.04 VDDQ VREF + 0.04 V 5) Input High (Logic1) Voltage VIH(DC) VREF + 0.15 8) Input Low (Logic0) Voltage VIL(DC) –0.3 Input Voltage Level, CK and CK Inputs VIN(DC) –0.3 VDDQ + 0.3 V VREF – 0.15 V VDDQ + 0.3 V Input Differential Voltage, CK and CK Inputs VID(DC) 0.36 VDDQ + 0.6 V 8)6) VI-Matching Pull-up Current to Pull-down Current VIRatio 0.71 1.4 7) VDD Device Supply Voltage VDD Output Supply Voltage VDDQ Output Supply Voltage VDDQ EEPROM supply voltage VDDSPD Supply Voltage, I/O Supply VSS, Voltage VSSQ VREF Input Reference Voltage Device Supply Voltage I/O Termination Voltage (System) Data Sheet VTT 0 0.49 × 0.5 × 12 — 8) 8) V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules Electrical Characteristics Table 7 Electrical Characteristics and DC Operating Conditions (cont’d) Parameter Symbol Unit Note/Test Condition 1) Values Min. Typ. Max. Input Leakage Current II –2 2 µA Any input 0 V ≤VIN ≤VDD; All other pins not under test = 0 V 8)9) Output Leakage Current IOZ –5 5 µA DQs are disabled; 0 V ≤VOUT ≤VDDQ 8) Output High Current, Normal Strength Driver IOH — –16.2 mA VOUT = 1.95 V 8) Output Low Current, Normal Strength Driver IOL 16.2 — mA VOUT = 0.35 V 8) 1) 0 ° C ≤TA ≤70 ° C 2) DDR400 conditions apply for all clock frequencies above 166 MHz 3) Under all conditions, VDDQ must be less than or equal to VDD. 4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 6) VID is the magnitude of the difference between the input level on CK and the input level on CK. 7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) Inputs are not recognized as valid until VREF stabilizes. 9) Values are shown per DDR SDRAM component Data Sheet 13 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules Electrical Characteristics 3.2 Current Specification and Conditions Table 8 IDD Conditions Parameter Symbol Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. IDD0 Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. IDD1 Precharge Power-Down Standby Current all banks idle; power-down mode; CKE ≤VIL,MAX IDD2P Precharge Floating Standby Current CS ≥ VIH,MIN, all banks idle; CKE ≥ VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. IDD2F Precharge Quiet Standby Current CS ≥ VIH,MIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at ≥ VIH,MIN or ≤VIL,MAX. IDD2Q Active Power-Down Standby Current one bank active; power-down mode; CKE ≤VILMAX; VIN = VREF for DQ, DQS and DM. IDD3P Active Standby Current one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. IDD3N Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA IDD4R Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B IDD4W Auto-Refresh Current tRC = tRFCMIN, burst refresh IDD5 Self-Refresh Current CKE ≤0.2 V; external clock on IDD6 Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet. IDD7 Data Sheet 14 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules Electrical Characteristics HYS64D64020GBDL–6–B HYS64D64020GBDL–7–B HYS64D64020GBDL–8–B IDD Specification HYS64D64020GBDL–5–B Part Number & Organization Table 9 512 MB 512 MB 512 MB 512 MB × 64 × 64 × 64 × 64 2 Ranks 2 Ranks 2 Ranks 2 Ranks –5 –6 –7 –8 Unit Note1)2) Symbol typ. max. typ. max. typ. max. typ. max. IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 1280 1552 1208 1480 1032 1320 912 1160 mA 3) 1400 1672 1336 1560 1168 1400 1000 1240 mA 3)4) 96 144 96 144 88 128 80 112 mA 5) 736 896 720 880 560 640 480 560 mA 5) 384 544 395 448 320 400 288 352 mA 5) 272 384 288 336 240 288 208 256 mA 5) 960 1184 1008 1120 832 960 672 800 mA 5) 1600 1992 1496 1840 1272 1520 1048 1280 mA 3)4) 1680 2032 1632 1880 1368 1600 1104 1360 mA 3) 1720 2152 1652 2080 1496 1920 1346 1760 mA 3) 21 38 20 36 20 36 20 36 mA 5) 2560 3072 2248 2840 1856 2360 1600 2160 mA 3)4) 1) DRAM component currents only 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component] Data Sheet 15 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules AC Characteristics 4 AC Characteristics Table 10 AC Timing - Absolute Specifications –8/–7 Parameter Symbol tAC DQS output access time from CK/CK tDQSCK CK high-level width tCH CK low-level width tCL Clock Half Period tHP Clock cycle time tCK3 tCK2.5 tCK2 tCK1.5 DQ and DM input hold time tDH DQ and DM input setup time tDS Control and Addr. input pulse width (each input) tIPW DQ and DM input pulse width (each input) tDIPW Data-out high-impedance time from CK/CK tHZ Data-out low-impedance time from CK/CK tLZ st Write command to 1 DQS latching transition tDQSS DQS-DQ skew (DQS and associated DQ tDQSQ DQ output access time from CK/CK –8 –7 DDR200 DDR266A Max. Unit Note/ Test Conditio n 1) Min. Max. Min. –0.8 +0.8 –0.75 +0.75 ns 2)3)4)5) –0.8 +0.8 –0.75 +0.75 ns 2)3)4)5) 0.45 0.55 0.45 0.55 2)3)4)5) 0.45 0.55 0.45 0.55 tCK tCK 2)3)4)5) min. (tCL, tCH) min. (tCL, tCH) ns 2)3)4)5) 8 12 7 12 ns CL = 3.0 2)3)4)5) 8 12 7 12 ns CL = 2.5 2)3)4)5) 10 12 7.5 12 ns CL = 2.0 2)3)4)5) 10 12 — — ns CL = 1.5 2)3)4)5) 0.6 — 0.5 — ns 2)3)4)5) 0.6 — 0.5 — ns 2)3)4)5) 2.5 — 2.2 — ns 2)3)4)5)6) 2.0 — 1.75 — ns 2)3)4)5)6) 2)3)4)5)7) –0.8 +0.8 –0.75 +0.75 ns –0.8 +0.8 –0.75 +0.75 ns 2)3)4)5)7) 0.75 1.25 0.75 1.25 tCK 2)3)4)5) — +0.6 — +0.5 ns TFBGA2)3)4)5) — 1.0 — 0.75 ns TFBGA2)3)4)5) tHP — tHP – — tQHS ns 2)3)4)5) 0.35 — 2)3)4)5) 0.2 — 0.2 — tCK tCK tCK 2)3)4)5) signals) Data hold skew factor DQ/DQS output hold time tQHS tQH – tQHS tDQSL,H 0.35 — DQS falling edge to CK setup time (write cycle) tDSS 0.2 — DQS falling edge hold time from CK (write tDSH 0.2 — DQS input low (high) pulse width (write cycle) 2)3)4)5) 2)3)4)5) cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input setup time tMRD tWPRES tWPST tWPRE tIS 2 — 2 — tCK 0 — 0 — ns 2)3)4)5)8) 2)3)4)5)9) 0.40 0.60 0.40 0.60 0.25 — 0.25 — tCK tCK 1.1 0.9 — ns — 2)3)4)5) fast slew rate 3)4)5)6)10) 1.1 — 1.0 — ns slow slew rate 3)4)5)6)10) Address and control input hold time tIH 1.1 — 0.9 — ns fast slew rate 3)4)5)6)10) 1.1 — 1.0 — ns slow slew rate 3)4)5)6)10) Data Sheet 16 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules AC Characteristics Table 10 AC Timing - Absolute Specifications –8/–7 (cont’d) Parameter Symbol –8 –7 DDR200 DDR266A Min. Max. Read preamble tRPRE 0.9 tRPRE1.5 0.9 tRPRES Read postamble tRPST Active to Precharge command tRAS Active to Active/Auto-refresh command period tRC Auto-refresh to Active/Auto-refresh command tRFC Read preamble setup time 1.5 Min. Max. 1.1 0.9 1.1 1.1 NA — 0.40 0.60 NA 0.40 0.60 Unit Note/ Test Conditio n 1) tCK tCK CL > 1.5 2)3)4)5) CL = 1.5 2)3)4)5)11) ns 2)3)4)5)12) tCK 2)3)4)5) 50 120E+3 45 120E+3 ns 2)3)4)5) 70 — 65 — ns 2)3)4)5) 80 — 75 — ns 2)3)4)5) 20 — 20 — ns 2)3)4)5) 20 — 20 — ns 2)3)4)5) 20 — 20 — ns 2)3)4)5) 15 — 15 — ns 2)3)4)5) 15 — 15 — ns 2)3)4)5) 2)3)4)5)13) period tRCD Precharge command period tRP Active to Autoprecharge delay tRAP Active bank A to Active bank B command tRRD Write recovery time tWR Auto precharge write recovery + precharge time tDAL Internal write to read command delay tWTR tWTR1.5 Exit self-refresh to non-read command tXSNR Exit self-refresh to read command tXSRD Average Periodic Refresh Interval tREFI Active to Read or Write delay (twr/tCK) + (trp/tCK) 1 — 1 — 2 — — — tCK tCK tCK 80 — 75 — ns 2)3)4)5) 200 — 200 — tCK 2)3)4)5) — 7.8 — 7.8 µs 2)3)4)5)14) CL > 1.5 2)3)4)5) CL = 1.5 2)3)4)5) 1) 0 ° C ≤TA ≤70 ° C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V 2) Input slew rate ≥ 1 V/ns for DDR400, DDR333, DDR266, and = 1 V/ns for DDR200 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ ns, measured between VOH(ac) and VOL(ac). 11) CAS Latency 1.5 operation is supported on DDR200 devices only 12) tRPRES is defined for CL = 1.5 operation only 13) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. Data Sheet 17 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules AC Characteristics Table 11 AC Timing - Absolute Specifications –6/–5 Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time Symbol tAC tDQSCK tCH tCL tHP tCK –6 –5 DDR333 DDR400B Unit Note/ Test Condition 1) Min. Max. Min. Max. –0.7 +0.7 –0.6 +0.6 ns 2)3)4)5) –0.6 +0.6 –0.5 +0.5 ns 2)3)4)5) 0.45 0.55 0.45 0.55 2)3)4)5) 0.45 0.55 0.45 0.55 tCK tCK ns 2)3)4)5) min. (tCL, tCH) 6 12 min. (tCL, tCH) 5 12 ns 2)3)4)5) CL = 3.0 2)3)4)5) 6 12 6 12 ns CL = 2.5 2)3)4)5) 7.5 12 7.5 12 ns CL = 2.0 2)3)4)5) tDH tDS tIPW 0.45 — 0.4 — ns 2)3)4)5) 0.45 — 0.4 — ns 2)3)4)5) 2.2 — 2.2 — ns 2)3)4)5)6) DQ and DM input pulse width (each input) tDIPW 1.75 — 1.75 — ns 2)3)4)5)6) Data-out high-impedance time from CK/CK tHZ –0.7 +0.7 –0.6 +0.6 ns 2)3)4)5)7) Data-out low-impedance time from CK/ tLZ CK –0.7 +0.7 –0.6 +0.6 ns 2)3)4)5)7) Write command to 1st DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK 2)3)4)5) DQS-DQ skew (DQS and associated DQ signals) tDQSQ — +0.40 — +0.40 ns Data hold skew factor tQHS — tQH tHP – tQHS — tHP – tQHS — ns 2)3)4)5) 0.35 — 0.35 — tCK 2)3)4)5) DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ/DQS output hold time DQS input low (high) pulse width (write tDQSL,H cycle) TFBGA 2)3)4)5) +0.50 — +0.50 ns TFBGA 2)3)4)5) DQS falling edge to CK setup time (write cycle) tDSS 0.2 — 0.2 — tCK 2)3)4)5) DQS falling edge hold time from CK (write cycle) tDSH 0.2 — 0.2 — tCK 2)3)4)5) 2 — 2 — tCK 2)3)4)5) 0 — 0 — ns 2)3)4)5)8) 0.40 0.60 0.40 0.60 2)3)4)5)9) 0.25 — 0.25 — tCK tCK Mode register set command cycle time tMRD Write preamble setup time Write postamble Write preamble Data Sheet tWPRES tWPST tWPRE 18 2)3)4)5) V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules AC Characteristics Table 11 AC Timing - Absolute Specifications –6/–5 (cont’d) Parameter Address and control input setup time Symbol tIS –6 –5 DDR333 DDR400B Min. Max. Min. Max. 0.75 — 0.6 — Unit ns Note/ Test Condition 1) fast slew rate 3)4)5)6)10) 0.8 — 0.7 — ns slow slew rate 3)4)5)6)10) Address and control input hold time tIH 0.75 — 0.6 — ns fast slew rate 3)4)5)6)10) 0.8 — 0.7 — ns slow slew rate 3)4)5)6)10) tRPRE Read postamble tRPST Active to Precharge command tRAS Active to Active/Auto-refresh command tRC Read preamble 2)3)4)5) 0.60 tCK tCK 40 70E+3 ns 2)3)4)5) — 55 — ns 2)3)4)5) 0.9 1.1 0.9 1.1 0.40 0.60 0.40 42 70E+3 60 2)3)4)5) period Auto-refresh to Active/Auto-refresh command period tRFC 72 — 65 — ns 2)3)4)5) Active to Read or Write delay tRCD tRP tRAP tRRD 18 — 15 — ns 2)3)4)5) 18 — 15 — ns 2)3)4)5) 18 — 15 — ns 2)3)4)5) 12 — 10 — ns 2)3)4)5) tWR tDAL 15 — 15 — ns 2)3)4)5) tCK 2)3)4)5)11) Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time tWTR Exit self-refresh to non-read command tXSNR Exit self-refresh to read command tXSRD Average Periodic Refresh Interval tREFI Internal write to read command delay 1 — 1 — tCK 2)3)4)5) 75 — 75 — ns 2)3)4)5) 200 — 200 — tCK 2)3)4)5) — 7.8 — 7.8 µs 2)3)4)5)12) 1) 0 ° C ≤TA ≤70 ° C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400) 2) Input slew rate ≥ 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. Data Sheet 19 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules AC Characteristics 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ ns, measured between VOH(ac) and VOL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. Data Sheet 20 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules HYS64D64020GBDL–8–B SPD Codes for HYS64D64020GBDL–[5/6/7/8]–B HYS64D64020GBDL–7–B Table 12 HYS64D64020GBDL–5–B SPD Contents Part Number & Organization 5 HYS64D64020GBDL–6–B SPD Contents 512 MB 512 MB 512 MB 512 MB × 64 × 64 × 64 × 64 2 Ranks 2 Ranks 2 Ranks 2 Ranks –5 –6 –7 –8 Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 80 1 Total number of Bytes in E2PROM 08 08 08 08 2 Memory Type DDR-I = 07h 07 07 07 07 3 # of Row Addresses 0D 0D 0D 0D 4 # Number of Column Addresses 0A 0A 0A 0A 5 # of DIMM Banks 02 02 02 02 6 Data Width (LSB) 40 40 40 40 7 Data Width (MSB) 00 00 00 00 8 Interface Voltage Levels 04 04 04 04 9 tCK @ CLmax (Byte 18) [ns] 50 60 70 80 10 tAC SDRAM @ CLmax (Byte 18) [ns] 50 70 75 80 11 DIMM Configuration Type (non- / ECC) 00 00 00 00 12 Refresh Rate 82 82 82 82 13 Primary SDRAM width 08 08 08 08 14 Error Checking SDRAM width 00 00 00 00 15 tCCD [cycles] 01 01 01 01 16 Burst Length Supported 0E 0E 0E 0E 17 Number of Banks on SDRAM 04 04 04 04 18 CAS Latency 1C 0C 0C 0C 19 CS Latency 01 01 01 01 20 WE (Write) Latency 02 02 02 02 21 DIMM Attributes 20 20 20 20 22 Component Attributes C1 C1 C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 75 75 A0 24 tAC SDRAM @ CLmax -0.5 [ns] 50 70 75 80 25 tCK @ CLmax -1 (Byte 18) [ns] 75 00 00 00 26 tAC SDRAM @ CLmax -1 [ns] 50 00 00 00 27 tRPmin (ns) 3C 48 50 50 Data Sheet 21 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules SPD Contents HYS64D64020GBDL–5–B HYS64D64020GBDL–6–B HYS64D64020GBDL–7–B HYS64D64020GBDL–8–B SPD Codes for HYS64D64020GBDL–[5/6/7/8]–B Part Number & Organization Table 12 512 MB 512 MB 512 MB 512 MB × 64 × 64 × 64 × 64 2 Ranks 2 Ranks 2 Ranks 2 Ranks –5 –6 –7 –8 Byte# Description HEX HEX HEX HEX 28 tRRDmin [ns] 28 30 3C 3C 29 tRCDmin [ns] 3C 48 50 50 30 tRASmin [ns] 28 2A 2D 32 31 Module Density per Bank 40 40 40 40 32 tAS, tCS [ns] 60 75 90 B0 33 tAH, TCH [ns] 60 75 90 B0 34 tDS [ns] 40 45 50 60 35 tDH [ns] 40 45 50 60 36 - 40 not used 00 00 00 00 41 tRCmin [ns] 37 3C 41 46 42 tRFCmin [ns] 41 48 4B 50 43 tCKmax [ns] 28 30 30 30 44 tDQSQmax [ns] 28 28 32 3C 45 tQHSmax [ns] 50 50 75 A0 46 - 61 not used 00 00 00 00 62 SPD Revision 00 00 00 00 63 Checksum of Byte 0-62 (LSB only) FE F8 B4 A9 64 JEDEC ID Code for Infineon C1 C1 C1 C1 65 JEDEC ID Code for Infineon 49 49 49 49 66 JEDEC ID Code for Infineon 4E 4E 4E 4E 67 JEDEC ID Code for Infineon 46 46 46 46 68 JEDEC ID Code for Infineon 49 49 49 49 69 JEDEC ID Code for Infineon 4E 4E 4E 4E 70 JEDEC ID Code for Infineon 45 45 45 45 71 JEDEC ID Code for Infineon 4F 4F 4F 4F 72 Module Manufacturer Location xx xx xx xx 73 Part Number, Char 1 36 36 36 36 74 Part Number, Char 2 34 34 34 34 75 Part Number, Char 3 44 44 44 44 Data Sheet 22 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules SPD Contents HYS64D64020GBDL–5–B HYS64D64020GBDL–6–B HYS64D64020GBDL–7–B HYS64D64020GBDL–8–B SPD Codes for HYS64D64020GBDL–[5/6/7/8]–B Part Number & Organization Table 12 512 MB 512 MB 512 MB 512 MB × 64 × 64 × 64 × 64 2 Ranks 2 Ranks 2 Ranks 2 Ranks –5 –6 –7 –8 Byte# Description HEX HEX HEX HEX 76 Part Number, Char 4 36 36 36 36 77 Part Number, Char 5 34 34 34 34 78 Part Number, Char 6 30 30 30 30 79 Part Number, Char 7 32 32 32 32 80 Part Number, Char 8 30 30 30 30 81 Part Number, Char 9 47 47 47 47 82 Part Number, Char 10 42 42 42 42 83 Part Number, Char 11 44 44 44 44 84 Part Number, Char 12 4C 4C 4C 4C 85 Part Number, Char 13 35 36 37 38 86 Part Number, Char 14 42 42 42 42 87 Part Number, Char 15 20 20 20 20 88 Part Number, Char 16 20 20 20 20 89 Part Number, Char 17 20 20 20 20 90 Part Number, Char 18 20 20 20 20 91 Module Revision Code xx xx xx xx 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx 99 - 127 not used 00 00 00 00 Data Sheet 23 V1.0, 2003-08 HYS64D64020GBDL–[5/6/7/8]–B Small Outline DDR SDRAM Modules Package Outlines 6 Package Outlines 67.6 3.8 MAX. 31.75 4 ±0.1 1.8 ±0.05 63.6 ±0.1 (2.15) 1 (2.45) 18.45 ±0.1 100 1±0.1 1.8 ±0.1 0.15 (2.4) 11.4 ±0.1 47.4 ±0.1 63 ±0.1 (2.7) (2.15) 1.5 ±0.1 4 ±0.1 1±0.1 200 20 ±0.1 101 6 ±0.1 (2.45) 2 MIN. 2.55 0.25 -0.18 Detail of contacts 0.45 ±0.03 0.6 ±0.1 Burnished, no burr allowed L-DIM-200-006 Figure 3 Data Sheet Package Outlines – DDR-SDRAM SO-DIMM HYS64D64020GBDL–[5/6/7/8]–B 24 V1.0, 2003-08 www.infineon.com Published by Infineon Technologies AG