DA9279.003 13 July 2006 MAS9279 IC FOR 10.00 – 52.00 MHz VCTCXO Fourth Order Compensation Frequency Stability +/- 0.3 ppm Wide Frequency Range Very Low Phase Noise Low Voltage Minimum Operating Temperature –40 °C Tri State CMOS Output • • • • • • • DESCRIPTION The MAS9279 is an integrated circuit well suited to build high end VCTCXO for telecommunication. The trimming is done through a serial bus and the calibration information is stored in an internal PROM. This means no rework for trimming is needed. To build a VCTCXO only crystal is required in addition to MAS9279. The compensation method is fully analog, working continuously without generating any steps or other interference. FEATURES • • • • • • • APPLICATIONS Very small size Minimal current consumption Wide operating temperature range Very low phase noise Programmable VC-sensitivity Minimum operating temperature –40 °C Oscillator frequency output f0/2 version available • • VCTCXO for high end telecommunications systems TCXO for high end telecommunication systems BLOCK DIAGRAM DA CLK PV Fourth Term CUB INF SENS LIN VC CDAC1 VDD CDAC2 VSS 4 TE1 f(T) Σ 5 3 8 T f(T) Vref TMux TE2 6 4 OUT X2 X1 1 (10) DA9279.003 13 July 2006 PIN DESCRIPTION Pin Description Symbol x-coordinate y-coordinate Power Supply Voltage Programming Input Serial Bus Clock Input VDD PV CLK 149 561 1000 1340 1340 1340 Serial Bus Data Input Temperature Output Test Multiplexer Output Voltage Control Input Crystal Oscillator Output Crystal/Varactor Oscillator Input Power Supply Ground Buffer Output DA TE1 TE2 VC X1 X2 VSS OUT 1565 2024 2016 147 1261 518 1549 1810 1340 1340 140 140 140 140 140 140 Note 3 3 Note: Because the substrate of the die is internally connected to GND, the die has to be connected to GND or left floating. Make sure that GND is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Pad coordinates are measured from the left bottom corner of the chip to the center of the pads. The coordinates may vary depending on sawing width and location, however, distances between pads are accurate. Note 3: Valid for MAS9279A1, A3, A5 and A7. In MAS9279A2, A4, A6 and A8 TE1 and TE2 pins have been swapped. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Unit Supply Voltage Input Pin Voltage Power Dissipation Storage Temperature ESD Rating; HBM VDD - VSS -0.3 VSS -0.3 6.0 VDD + 0.3 100 150 2 V V mW o C kV PMAX TST -55 Note 1) 2) Note 1: Not valid for programming pin PV Note 2: In X1 and X2 pins maximum ESD rating is 1.5kV RECOMMENDED OPERATION CONDITIONS Parameter Supply Voltage Supply Current Operating Temperature Crystal Pulling Sensitivity Crystal Pulling Sensitivity Crystal Load Capacitance Crystal Load Capacitance Symbol VDD ICC TOP S S CL CL Conditions Min Typ Max Unit 2.7 3.3 6.0 5.5 V mA o C ppm/pF ppm/pF pF pF Vdd = 3.3 Volt -40 24 28 Vc = 1.2V Vc = 1.2V 28 33 8 10 +85 35 38 Note 1 2 3 2 3 Note 1: At 26MHz crystal Note 2: MAS9279A1, MAS9279A3, MAS9279A5, MAS9279A7 Note 3: MAS9279A2, MAS9279A4, MAS9279A6, MAS9279A8 2 (10) DA9279.003 13 July 2006 ELECTRICAL CHARACTERISTICS (recommended operation conditions) Parameter Symbol Min Frequency Range fo Voltage Control Range Typ Max Unit Note 10.00 52.00 MHz VC 0 Vdd V 1) Voltage Control Sensitivity VCSENS 7.3 10.4 ppm/V 2) Voltage Control Sensitivity VCSENS 8.8 13.4 ppm/V 3) Voltage Control Sensitivity VCSENS 10.1 14.5 ppm/V 4) Frequency vs. Supply Voltage dfo ±0.2 ppm 5) Frequency vs. Load Change dfo ±0.2 ppm 6) Output Voltage (10 pF, VDD 2.7 V) Vout 2.3 Vpp Output Voltage (10 pF, VDD 5.0 V) Vout 4.5 Vpp 3 ns Rise and Fall Time (10 - 50 pF) Output Symmetry Compensation Range ± 1.0 ppm Compensation Range ± 0.75 ppm 45-55 TC TC -40 -20 % 85 o 70 o o Compensation Range ± 0.3 ppm TC 10 50 Compensation Range Linear Part a1 -0.4 -0.1 C ppm/K 9) o INF Compensation Range Cubic Part a3 Compensation CDAC1 (4 Bit) CX1 -1.5 2.4 ppm 2) 7) Compensation CDAC2 (6 Bit) CX2 -21 27 ppm 2) 8) Compensation CDAC1 (4 Bit) CX1 -2.6 2.1 ppm 3) 7) Compensation CDAC2 (6 Bit) CX2 -26 32 ppm 3) 8) Compensation CDAC1 (4 Bit) CX1 -3.0 2.6 ppm 4) 7) CX2 -32 36 ppm 4) 8) Amplitude Start up Time Tri State Output Buffer ON State OFF State Note 1: In TCXO leave Vc floating Note 2: With 23 ppm/pF crystal Note 3: With 28 ppm/pF crystal. Note 4: With 33 ppm/pF crystal Note 5: VDD +/- 5% TSTART DA 31 C Compensation Inflection Point Compensation CDAC2 (6 Bit) 23 C ppm2/K3 95 2 C ms V 0 0.55 1.6 VDD Note 6: R=10 kohm +/- 10%, C=10 pF +/- 10% Note 7: CDAC2=6. Note 8: CDAC1=4. Note 9: With LIN=255 temperature compensation is in off mode 3 (10) DA9279.003 13 July 2006 IC OUTLINES VDD CLK PV DA TE1 VDD MAS9279 1506um VC X2 X1 VSS OUT PV CLK MAS9279 1506um TE2 Die map reference TE2 DA VC X2 X1 VSS OUT TE1 Die map reference 2202um 2202um Figure 1. MAS9279A1, A3, A5, A7 Figure 2. MAS9279A2, A4, A6, A8 Note 1: MAS9279 pads are round with 80 µm diameter at opening. Note 2: Pin CLK can either be connected to VSS or left floating, pin PV should be connected to Ground or left floating and pin TE1 must be left floating in VCTCXO module end-user application. Note 3: Die map reference is the actual left bottom corner of the sawn chip. SAMPLES IN SB20 DIL PACKAGE 1 20 TE2 2 19 OUT 3 18 VSS TE1 4 CLK 6 PV 7 MAS9279 YYWW XXXXX.X DA 5 17 X1 16 Top marking: YYWW = Year, Week XXXXX.X = Lot number 15 X2 14 VC VDD 8 13 9 12 10 11 4 (10) DA9279.003 13 July 2006 DEVICE OUTLINE CONFIGURATION QFN10 3x3 QFN10 3x3 Top View VDD PV CLK DA TE1 A = product version X = Load / Output version 1, 3, 5, 7 Y = year WW = week Top View VC X2 X1 VSS OUT 9279 AX YWW X1 VSS OUT 9279 AX YWW VC X2 VDD PV CLK DA TE2 A = product version X = Load / Output version 2, 4, 6, 8 Y = year WW = week 5 (10) DA9279.003 13 July 2006 PACKAGE (QFN10 3X3) OUTLINE D E/2 L2 D/2 PIN 1 MARK TOP VIEW A2 A3 0-10 deg A SIDE VIEW E2/2 L A1 SEATING PLANE E2 D2 EXPOSED PAD b e BOTTOM VIEW Symbol Min Nom Max Unit A A1 A2 A3 b D D2 E E2 e L L2 0.8 0 0.65 0.15 0.200 0.9 0.025 0.70 0.20 0.250 3.00 BSC 2.02 3.00 BSC 1.70 0.50 BSC 0.400 - 1.0 0.05 0.75 0.25 0.300 mm mm mm mm mm mm mm mm mm mm mm mm 1.92 1.65 0.350 - 2.12 1.75 0.450 0.125 Dimensions do not include mold or interlead flash, protrusions or gate burrs. 6 (10) DA9279.003 13 July 2006 SOLDERING INFORMATION Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile According to RSH test IEC 68-2-58/20 260°C 3 Thermal profile parameters stated in JESD22-A113 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 µm, material Matte Tin Seating Plane Co-planarity Lead Finish EMBOSSED TAPE SPECIFICATIONS 4.0 +/- 0.1 3.17 +/- 0.1 8.0 +0.3,-0.1 1.37 +/- 0.1 ORIENTATION ON TAPE 0.254 +/-0.02 4.0 +/- 0.1 3.23 +/- 0.1 USER FEED DIRECTION 7 (10) DA9279.003 13 July 2006 REEL SPECIFICATIONS W2 A D C Tape Slot for Tape Start N B W1 Carrier Tape Cover Tape End Start Trailer Dimension A B C D N W1 (measured at hub) W2 (measured at hub) Trailer Leader Components Min 1.5 12.80 20.2 50 8.4 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape Leader Max Unit 178 mm mm mm mm mm mm mm mm mm 13.50 9.9 14.4 8 (10) DA9279.003 13 July 2006 ORDERING INFORMATION Product Code Product MAS9279A1TG00 IC FOR VCTCXO MAS9279A1HH06 IC FOR VCTCXO MAS9279A2TG00 IC FOR VCTCXO MAS9279A2HH06 IC FOR VCTCXO MAS9279A3TG00 IC FOR VCTCXO Frequency output f0/2 MAS9279A3HH06 TE OUTPUT In QFN10 Package Comments EWS Tested wafers 215 µm For 8pF Crystal load For 8pF Crystal load For 10pF Crystal load For 10pF Crystal load For 8pF Crystal load TE1 QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm TE2 QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm TE1 QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm TE2 MAS9279A5TG00 IC FOR VCTCXO Frequency output f0/2 IC FOR VCTCXO Frequency output f0/2 IC FOR VCTCXO Frequency output f0/2 IC FOR TCXO QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm MAS9279A5HH06 IC FOR TCXO TE1 MAS9279A6TG00 IC FOR TCXO QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm MAS9279A6HH06 IC FOR TCXO TE2 MAS9279A7TG00 IC FOR TCXO Frequency output f0/2 IC FOR TCXO Frequency output f0/2 IC FOR TCXO Frequency output f0/2 IC FOR TCXO Frequency output f0/2 QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm TE1 QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant EWS Tested wafers 215 µm TE2 QFN10, T&R, 3.000 pcs/reel; Pb free, RoHS compliant MAS9279A4TG00 MAS9279A4HH06 MAS9279A7HH06 MAS9279A8TG00 MAS9279A8HH06 For 8pF Crystal load For 10pF Crystal load For 10pF Crystal load For 8pF Crystal load For 8pF Crystal load For 10pF Crystal load For 10pF Crystal load For 8pF Crystal load For 8pF Crystal load For 10pF Crystal load For 10pF Crystal load Contact Micro Analog Systems Oy for other wafer thickness and bonding options LOCAL DISTRIBUTOR 9 (10) DA9279.003 13 July 2006 MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 10 (10)