Holtek HT9020B Call progress tone decoder & abr controller Datasheet

HT9020
Call Progress Tone Decoder & ABR Controller
Features
•
•
•
•
•
Low cost 32768Hz crystal
Low power consumption
Operating voltage: 2.5V to 5.5V (CPT mode)
2.0V to 5.5V (ABR mode)
Call progress tone decoder
– Fully decoded tristate call progress status
output
– Works with traditional precision or PBX call
progress tones
Busy redial controller
– Repeat times: 3, 10 or 15 times
( 2, 5, 15 times by mask option)
– 4.65, 32.6 and 62.8 sec break time
(16.3sec by mask option)
– Auto-terminate after 30 times (default)
ringback tone receipt
General Description
The HT9020 provides two modes; Call progress
tone decoder and Busy redial controller, to support the application fields.
Busy redial controller
This feature implements a busy redial function.
After decoding, if the line is busy, this device
forces the dialer to break for 62.8 sec, then
triggers the redial key after the dial tone receipt. If the receiver is still busy, the redial
sequence will be repeated 10 times. If the receiver is ringing, the redial sequence will be
terminated after 30 times of ringback tone receipt.
Standard call progress tone decoder
This feature detects a specified input signal and
then outputs relative envelopes during a 2.32sec
interval. Three tristate output pins (DIAL, RBK,
BUSY) indicate the presence of a dial tone, ringback tone or busy/reorder tone respectively, so it
provides information that enables the microprocessor to decide whether to initiate, continue or
terminate calls.
Selection Table
Function
Operating
Voltage
OSC
Frequency
CPT Decoder
ABR
Repeat Times
ABR
Break Time
Package
HT9020A
CPT mode
2.5V~5.5V
ABR mode
2.0V~5.5V
32768Hz
Full decoded
3/10/15 times
[2/5/15 by
metal option]
4.65/32.6/62.8 sec
[16.3 sec by
metal option]
18 DIP/SOP
HT9020B
CPT mode
2.5V~5.5V
32768Hz
CPT envelope only
Part No.
1
8 DIP
21st Aug ’98
HT9020
Block Diagram
Pin Assignment
Pin Description
Pin Name
DEC/ABRC
OE/HKOFF
I/O
I
I
Internal
Connection
Description
CMOS IN
When this pin is connected to VDD, the chip is in the call
progress tone decoder mode (CPTD mode)
When this pin is connected to VSS, the chip is in the auto busy
redial controller mode (ABRC mode)
CMOS IN
CPTD mode: DIAL, RBK, BUSY and ENV pin tristate output
control pin. OE=VDD: Tristate output selected
ABRC mode: Off hook sense pin
HKOFF=VDD: Reset controller and disable ABR operation
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HT9020
Internal
Connection
Description
CMOS OUT
CPTD mode: While an input signal is within specification,
this pin will output the envelope relative to the input signal
with a typical 40ms timing delay.
ABRC mode: This is an ABR finished indicating signal
output pin. When an ABR counter is full, this pin will output
a 100ms pulse.
CMOS OUT
CPTD mode: The call progress tone is decoded in this ready
output pin. This pin can be used to trigger a microcontroller to
read the latched data at DIAL, RBK and BUSY
ABRC mode: ABR indicating signal output. While ABR is
active, this pin will output a 0.86Hz, 25% duty cycle clock.
CMOS IN
CPTD mode: Output data return to zero select pin
RTZ=VDD; The outputs of DIAL, RBK and BUSY will be
cleared when the input signal is out of specification while in
the 2.32 sec time window.
RTZ=VSS; The outputs of DIAL, RBK and BUSY will be
latched until the next valid data is received.
ABRC mode: Numbers of the busy redial and time of break
selection pin.
I/O
CMOS I/O
(VREF:O
SEL2:I)
CPTD mode: 1/2 VDD reference voltage output pin
When EN=VDD, the device will be turned off and VREF
disabled. All outputs will be pulled low to reduce power
consumption.
ABRC mode: Number of the busy redial and time of break
selection pin.
I
CMOS IN
AC coupled analog signal input pin
I
CMOS IN
CPTD mode: Received busy tone pattern select pin
B3=VDD; BUSY will be set after three successive busy tones
are received.
B3=VSS; BUSY will be set immediately after a busy tone is
received.
ABRC mode: Ringer detection input pin
VSS
—
—
Negative power supply
2.5~5.5V for CPT mode operation
2.0~5.5V for ABR mode operation
VDD
—
—
Positive power supply, 2.5~5.5V for normal operation
Pin Name
ENV/END
DV/LED
RTZ/SEL1
VREF/SEL2
SIN
B3/RING
BUSY/
BREAK
I/O
O
O
I
O
CMOS OUT
CPTD mode: BUSY=HIGH: The detected input signal is a
busy or reorder tone
ABRC mode: When in ABR mode, the BREAK pin will be
high. After a busy tone is detected it will return low.
When the break timer has timed out, it will return high.
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HT9020
Pin Name
RBK/KEY2
DIAL/KEY1
I/O
O
O
Internal
Connection
Description
CMOS OUT
CPTD mode: RBK=HIGH: The detected input signal is a
ringback tone.
ABRC mode: Transmission gate input or output pin. Used to
trigger the row and column pin of the redial key when a dial
tone is received. It will output a 100ms pulse.
CMOS OUT
CPTD mode: DIAL=HIGH; The detected input signal is a
dial tone.
ABRC mode: Transmission gate input or output pin. Used to
trigger the row and column pin of the redial key when a dial
tone is received. It will output a 100ms pulse.
EN/KEY
I
CMOS IN
CPTD mode: EN=VSS; Normal operation mode
EN=VDD; Device disabled. The oscillator stops and all output
pins are pulled low or high impedance.
ABRC mode: The pin is schmitt trigger input structure.
Active low. Applying a negative going pulse to this pin can
toggle the auto-busy-redial function.
CLR
I
CMOS IN
When CLR is low and BREAK is high, the tone decoder is
reset. This pin can be connected to the mute pin of the dialer
IC for tone elimination.
X1
I
The system oscillator consists of an inverter, a bias resistor
OSCILLATOR and the necessary load capacitor on-chip. Connect a standard
32.768kHz crystal or ceramic resonator.
X2
O
X1 and X2 terminals implement the oscillator function.
OSCILLATOR The oscillator is turned off in the standby mode, and is
actuated whenever a keyboard entry is detected.
TEST
I
CMOS IN
Pull-low
For testing only, active high
Approximate internal connection circuits
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HT9020
Absolute Maximum Ratings*
Supply Voltage ............................... –0.3V to 6V
Storage Temperature................. –55°C to 150°C
Input Voltage ............... VSS–0.3V to VDD+0.3V
Operating Temperature .............. –20°C to 75°C
*Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this
device at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
Electrical Characteristics
Symbol
Parameter
VDD
Operating Voltage
IDD
Operating Current
Test Conditions
VDD
Conditions
Min. Typ. Max. Unit
CPT mode
2.5
—
5.5
V
ABR mode
2.0
—
5.5
V
Functions enabled
—
—
2
mA
2.5V No load
—
—
0.8
mA
Functions disabled or
2.5V
EN=1
—
—
1
µA
fIN=305~640Hz
–36
—
0
dBm
–42
—
–8
dBm
—
—
–50
dBm
—
5V
ISTB
Standby Current
GDV
Detection Level
GRL
Rejection Level
—
All frequency, ENV=0
fRL
fRH
Rejection Out-band
Frequency
—
V≤ 0 dBm, ENV=0
—
800
—
200
—
Hz
tDD
Detection Signal Time
—
In-band signal input,
ENV=1
40
—
—
ms
tRD
Rejection Noise Time
—
Any signal input,
ENV=0
—
—
20
ms
tDH
tDL
Envelope Output
Delay Time
—
Time to output high
Time to output low
—
40
—
ms
tDV
Data Valid Output Time
—
Time to output high/low
1.05
1.16
1.2
sec
tSU
Data Setup Time
—
3
4
5
ms
tI
Interval Time
—
Internal signal
—
2.32
—
sec
tIP
Interval Pause Time
—
Internal signal
8
—
ms
tCL
Clear Time
—
—
—
250
—
ns
tST
OSC Start Up Time
—
—
—
0.8
2
sec
ZI
Input Impedance
—
fIN=200~3.4kHz
1.0
—
—
MΩ
VREF
Reference Voltage
—
No load
2.4
2.5
2.6
V
5V
2.5V ENV=1
—
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HT9020
Symbol
Parameter
Test Conditions
VDD
Conditions
Min. Typ. Max. Unit
ZREF
Output Impedance
—
—
—
10
20
MΩ
VIH
Logic Input High Voltage
5V
—
3.5
—
—
V
VIL
Logic Input Low Voltage
5V
—
—
—
1.5
V
IIH
Logic Input High Current
5V
VIH=5.0V
—
—
0.1
µA
IIL
Logic Input Low Current
5V
VIL=0V
–0.1
—
—
IOH
Output High Current
5V
VOH=4.5V
—
—
–0.5
mA
IOL
Output Low Current
5V
VOL=0.5V
2.0
—
—
mA
ILKH
5V
VLKH=5.0V
—
—
0.1
µA
ILKL
Output Disable
Leakage Current
5V
VLKL=0V
–0.1
—
—
µA
ISO
Pull Down Current
5V
—
—
25
35
µA
IDR
Pull Up Current
5V
—
—
25
35
µA
GDL
Detection Level
–42
—
–8
dBm
–36
—
0
dBm
GRL
Rejection Level
5V
All frequency
—
—
–50
dBm
fROL
Rejection Out-band
Low Frequency
5V
V<0 dBm, ENV=0
—
—
200
Hz
fROH
Rejection Out-band
High Frequency
5V
V<0 dBm, ENV=0
800
—
—
Hz
tDD1
Detection Time
5V
In-band dial tone
2.1
3.32
3.0
sec
tDD2
Detection Time
5V
In-band dial tone
6.5
7.0
8.0
sec
tDB
Detection Busy Time
5V
In-band busy tone
6.8
7.5
8.2
sec
tDR
Detection Ringer Time
5V
30 Times ringback tone
(2 sec On/4 sec Off)
150
180
210
sec
tDN
Detection Time
5V
No signal
25
30.2
35
sec
tDE
Detection Enable Time
5V
—
0.2
30.2
35
sec
tTO
RELI, O Turn on Time
5V
—
80
100
120
ms
tO
ABREND Output Time
5V
—
80
100
120
ms
tB1
5V
After a busy tone is detected 60.0
62.8
65.0
sec
tB2
Break Time
(tB1+2.3sec)
5V
After no signal is detected
62.0
65.1
68.0
sec
RON
Transition on Resistor
5V
VRDLI=5.0V, VRDLO=0V
—
500
100
Ω
ROFF
Gate Output off Resistor
5V
VRDLI=0V, VRDLO=5.0V
10
—
—
MΩ
2.5V
5.0V
fIN=305~640Hz
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HT9020
Functional Description
Decoder
The HT9020 call progress tone decoder (DEC/ABRC=VDD) can be used in the U.S.A. and many other
countries in the world. The signal format, truth table and timing of the decoder are shown below.
The signal format of the call progress tone
Tone
Frequency
Condition
Precision Dial Tone
350Hz + 440Hz
Continuous
Old Dial Tone
120Hz(or 133Hz, ..) + 600Hz
Continuous
Precision Busy Tone
480Hz + 620Hz
0.5sec On and 0.5sec Off
Old Busy Tone
120Hz + 600Hz
0.5sec On and 0.5sec Off
Precision Reorder Tone
480Hz + 620Hz
0.3sec On and 0.2sec Off
Old Reorder Tone
120Hz + 600Hz
0.2sec On and 0.3sec Off or 0.25sec
On and 0.25sec Off
Precision Ring-back Tone
440Hz + 480Hz
2sec On and 4sec Off
Old Ring-back Tone
40Hz (or the others) + 420Hz
2sec On and 4sec Off
The truth table of the decoder
Tone
Transition No.
DIAL
RBK
BUSY
DV
OE/HKOFF
Initial
—
0
0
0
0
0
Dial
1
1
0
0
1
0
Ringback
2~4
0
1
0
1
0
Busy/Reorder
5~16
0
0
1
1
0
over 16
0
0
0
1
0
—
Hi-Z
Hi-Z
Hi-Z
*
1
Overflow
Output Disable
Notes: Hi-Z: Hi impedance
*: previous state
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HT9020
Decoder timing diagrams
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HT9020
After the break timer has timed-out, the redial
will be executed again. If the repeat-number
ends, the OVER pin will output a 100ms high
pulse to automatically reset to the initial state.
ABR controller
Initial state:
• RDLO=Hi-Impedance
• RDLI=Hi-Impedance
If the receiver does not answer within 30 cycles,
a ringback tone is produced, and the OVER pin
will output a 100ms high pulse to automatically
reset to the initial state.
• BREAK=Low
• ABRI=Low
The break time and repeat number setting
If a negative transition is received on the ABR
pin, then the Auto-busy-dial function will be
executed, and the LED pin will output a 0.86Hz
(duty=0.25) clock. If the device detects a dial
tone, KEY1 and KEY2 pins output a 100ms
pulse to trigger the redial key of the telephone
dialer. The dial tone will be ignored after the
redial key is triggered.
Repeat No.
SEL1 SEL2
(times)
If a busy/reorder tone for three successive windows is received or the line signal is off for
30.2secs or a dial tone appears again for more
than 7 secs after the number is dialed-out, the
device will turn on the internal register to implement the following control:
Break Time
(seconds)
tB1
tB2
0
0
10
62.8
84.9
0
1
10
32.6
34.9
1
0
3
62.8
64.9
1
1
15
4.65
6.97
• Turn off the filter
• BREAK pin output low for on-hook switch
control
• The on-hook timer starts counting the break
time
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HT9020
ABR controller timing diagrams
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HT9020
Application Circuits
Application Circuit 1
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HT9020
Application Circuit 2
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21st Aug ’98
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