LC87F7NC8A CMOS LSI 8-bit Microcontroller with LCD Controller Driver www.onsemi.com 128K-byte Flash ROM / 4K-byte RAM / 100-pin Features LCD Driver 4COM × 54SEG Infrared Remote Control Receiver Circuit × 2 Full duplex UART × 2 Performance Minimum Bus Cycle Time 56ns (CF=18MHz) Minimum Instruction Cycle Time (Tcyc) 167ns (CF=18MHz) Operating Supply Voltage 2.7V to 3.6V Operating Ambient Temperature 40°C to +85°C QIP100E(14X20) Function Descriptions V2/PL5/AN13/DBGP1 V1/PL4/AN12/DBGP0 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/INT4/T1IN/INT6/T0LCP1/PWM4/S48 P31/INT4/T1IN/PWM5/S49 VSS3 VDD3 P32/INT4/T1IN/UTX1/S50 P33/INT4/T1IN/URX1/S51 P34/INT5/T1IN/INT7/T0HCP1/UTX2/S52 P35/INT5/T1IN/URX2/S53 P00/DGBP0 P01/DGBP1 P02 /DGBP2 P03/INT6 P04/INT7 P05/CKO Application V3/PL6/AN14/DBGP2 S47/PF7/INT7 S46/PF6/INT6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 S23/PC7 S22/PC6 S21/PC5 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P06/T6O P07/T7O P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/NKIN P73/INT3/T0IN/RMIN S0/PA0 AV apparatus Household appliance mounted with LCD panel TQFP100(14X14) [ Under Development ] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1) Ports I/O Ports 29 LCD Common Ports 4 LCD Segment Ports 54 (I/O port combined use) Bias Power Source For LCD 3 Power Pins (VSS1, VDD1) 6 2) Timer × 8 Timer 0 : 16-bit timer/counter with capture registers Timer 1 : 16-bit timer that supports PWM/toggle outputs Timer 4 : 8-bit timer with a 6-bit prescaler Timer 5 : 8-bit timer with a 6-bit prescaler Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle output) Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle output) Timer 8 : 16-bit timer with an 8-bit prescaler Base timer 3) Full duplex UART × 2 4) Infrared Remote Control Receiver Circuit × 2 * This product is licensed from Silicon Storage Technology, Inc. (USA). ORDERING INFORMATION Pin Assignment : QIP100E(14x20) [ Top view ] See detailed ordering and shipping information on page 28 of this data sheet. © Semiconductor Components Industries, LLC, 2014 November 2014 - Rev. 1 1 Publication Order Number : LC87F7NC8A/D S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 LC87F7NC8A Function Details Ports Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units Normal withstand voltage input port LCD ports Segment output Common output Bias power sources for LCD driver Other functions Input/output ports Input ports Dedicated oscillator ports Reset pins Power pins : 29 (P0n, P1n, P70 to P73, P8n, XT2) : 1 (XT1) : 54 (S00 to S53) : 4 (COM0 to COM3) : 3 (V1 to V3) : 54 (P3n, PAn, PBn, PCn, PDn, PEn, PFn) : 7 (PLn) : 2 (CF1, CF2) : 1 (RES) : 6 (VSS1 to VSS3, VDD1 to VDD3) LCD Controller 1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty 1/2, 1/3 bias) 2) Segment output and common output can be switched to general-purpose input/output ports Small Signal Detection (MIC signals etc.) 1) Counts pulses with a level which is greater than a preset value 2) 2-bit counter Timers Timer 0: 16-bit timer/counter with two capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers) Timer1: 16-bit counter timer that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler 2 channels Mode 2: 16-bit counter timer with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) Timer4: 8-bit timer with a 6-bit prescaler Timer5: 8-bit timer with a 6-bit prescaler Timer6: 8-bit timer with a 6-bit prescaler (with toggle output) Timer7: 8-bit timer with a 6-bit prescaler (with toggle output) Timer8: 16-bit timer Mode 0: 8-bit timer with an 8-bit prescaler 2 channels Mode 1: 16-bit timer with an 8-bit prescaler Base Timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes Day and time counter 1) Used with a base timer, the day and time counter can be used as a 65000 day + minute + second counter. www.onsemi.com 2 LC87F7NC8A High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real-time. Serial Interfaces SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first made selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle 4/3tCYC) 3) Automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units) SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) UART1 Full duplex 7/8/9 bit data bits selectable 1 stop bit (2 bits in continuous data transmission) Built-in baudrate generator UART2 Full duplex 7/8/9 bit data bits selectable 1 stop bit (2 bits in continuous data transmission) Built-in baudrate generator AD Converter :12 bits 15 channels PWM :Multi frequency 12-bit PWM 2 channels Infrared Remote Control Receiver Circuit1 1) Noise reduction function (Time constant of noise reduction filter: approx. 120s, when selecting a 32.768kHz crystal oscillator as a reference clock) 2) Supporting reception formats with a guide-pulse of half-clock/clock/none. 3) Determines a end of reception by detecting a no-signal periods (No carrier). (Supports same reception format with a different bit length.) 4) X’tal HOLD mode cancellation function Infrared Remote Control Receiver Circuit2 1) Noise reduction function (Time constant of noise reduction filter: approx. 120μs, when selecting a 32.768kHz crystal oscillator as a reference clock.) 2) Supporting reception formats with a guide-pulse of half-clock/clock/none. 3) Determines a end of reception by detecting a no-signal periods (No carrier). (Supports same reception format with a different bit length.) 4) X’tal HOLD mode cancellation function Watchdog Timer 1) External RC watchdog timer 2) Interrupt and reset signals selectable Clock Output Function 1) Can output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 as a system clock. 2) Can output the source oscillation clock for the sub clock. www.onsemi.com 3 LC87F7NC8A Interrupt Source Flags 31 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4/remote control receiver1 4 0001BH H or L INT3/base timer/INT5/ remote control receiver2 5 00023H H or L T0H/INT6 6 0002BH H or L T1L/T1H/INT7 7 00033H H or L SIO0/UART1 receive/ UART2 receive/T8L/T8H 8 0003BH H or L SIO1/UART1 transmit/ UART2 transmit 9 00043H H or L ADC/MIC/T6/T7/PWM4/PWM5 10 0004BH H or L Port 0/T4/T5 Priority levels X > H > L Of interrupts of the same level, the one with the smallest vector address takes precedence. IFLG (List of interrupt source flag function) 1) Shows a list of interrupt source flags that caused a branching to a particular vector address. Subroutine Stack Levels 2048 levels maximum (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions 16 bits 8 bits (5 tCYC execution time) 24 bits 16 bits (12 tCYC execution time) 16 bits 8 bits (8 tCYC execution time) 24 bits 16 bits (12 tCYC execution time) Oscillation Circuits RC oscillation circuit (internal): For system clock CF oscillation circuit: For system clock, with internal Rf and external Rd Crystal oscillation circuit: For low-speed system clock, with internal Rf and external Rd Multifrequency RC oscillation circuit (internal): For system clock 1) Adjustable in ±4 (typ) increments from the selected center frequency. 2) Measures the frequency of the source oscillation clock using the input signal from XT1 as the reference. System Clock Divider Function Can run on low current. The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and 76.8s (at a main clock rate of 10MHz). www.onsemi.com 4 LC87F7NC8A Standby Function HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation (Some parts of the serial transfer function stop operation) . 1) Oscillation is not stopped automatically. 2) Canceled by a system reset or occurrence of an interrupt HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, X’tal, and multifrequency RC oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer and infrared remote controller circuit. 1) The CF, RC, and multifrequency RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an interrupt source established in the infrared remote control receiver circuit On-chip Debugger Function Supports software debugging with the IC mounted on the target board. Package Form QIP100E(1420) QFP100(14 : Pb-Free / Halogen Free type : Pb-Free / Halogen Free type [Under Development] Development Tools On-chip Debugger: TCB87 TypeB +LC87F7Nxx A or TCB87 TypeC (3Lines Cable) +LC87F7NxxA www.onsemi.com 5 LC87F7NC8A Flash ROM Programming boards Package Programming Boards QIP100E(1420) W87FQ100 TQFP100(1414) W87FSQ100 Flash ROM Programmer Model Maker Single Programmer Device LC87F7NP6A AF9709C (Note 2) LC87F7NJ2A LC87F7NC8A AF9723/AF9723B(main unit) Flash Support Group, Inc (FSG) Supported Version (including models manufactured by Gang Ando Electric Co., Ltd.) Programmer AF9833(unit) (including models manufactured by (Note 2) LC87F7NP6A LC87F7NJ2A (Note 2) LC87F7NC8A Ando Electric Co., Ltd.) Flash Support Group, Inc (FSG) +Our company (Note 1) Our company AF9101/AF9103(main unit) In-circuit (manufactured by FSG) Single/Gang SIB87 Type C Programmer (Interface Driver) LC87F7NP6A (Note 2) LC87F7NJ2A LC87F7NC8A (Our company model) Single/Gang SKK Type B / Type C Programmer (SanyoFWS) In-circuit Single/Gang Programmer Application Version 1.08or later SKK-DBG Type B /Type C Chip Data Version (SanyoFWS) 2.44 later LC87F7NP6A LC87F7NJ2A LC87F7NC8A Contact information about the AF series : Flash Support Group Company (TOA ELECTRONICS, Inc.) Phone : 81-53-428-8380 E-mail : [email protected] Note1 : On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from our company (SIB87) together can give a PC-less, standalone on-board-programming capabilities. Note2 : It needs a special programming devices and applications depending on the use of programming environment. Please ask FSG or our company for the information. www.onsemi.com 6 LC87F7NC8A Package Dimensions unit : mm PQFP100 14x20 / QIP100E CASE 122BV ISSUE A 0.8 0.2 23.2 0.2 17.2 0.2 100 14.0 0.1 20.0 0.1 12 0.65 0.3 0.05 0.15 0.13 0.1 0.1 (2.7) 3.0 MAX (0.58) 0 to 10 0.10 SOLDERING FOOTPRINT* 22.30 GENERIC MARKING DIAGRAM* 16.30 (Unit: mm) 0.43 XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data 1.30 0.65 XXXXXXXXX YMDDD NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 7 *This information is generic. Please refer to device data sheet for actual part marking. may or may not be present. LC87F7NC8A Package Dimensions unit : mm *Package TQFP100(1414) type is Under Development. TQFP100 14x14 / TQFP100 CASE 932AY ISSUE A 0.5 0.2 16.0 0.2 16.0 0.2 100 14.0 0.1 14.0 0.1 1 2 0.5 0.125 0.2 0.10 (1.0) 0 to 10 0.1 0.1 1.2 MAX (1.0) 0.10 SOLDERING FOOTPRINT* GENERIC MARKING DIAGRAM* 15.40 XXXXXXXX YMDDD 15.40 (Unit: mm) XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data *This information is generic. Please refer to device data sheet for actual part marking. 0.28 may or may not be present. 1.00 0.50 NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 8 V2/PL5/AN13/DBGP1 V1/PL4/AN12/DBGP0 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/INT4/T1IN/INT6/T0LCP1/PWM4/S48 P31/INT4/T1IN/PWM5/S49 VSS3 VDD3 P32/INT4/T1IN/UTX1/S50 P33/INT4/T1IN/URX1/S51 P34/INT5/T1IN/INT7/T0HCP1/UTX2/S52 P35/INT5/T1IN/URX2/S53 P00/DGBP0 P01/DGBP1 P02 /DGBP2 P03/INT6 P04/INT7 P05/CKO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P06/T6O P07/T7O P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/NKIN P73/INT3/T0IN/RMIN S0/PA0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 V3/PL6/AN14/DBGP2 S47/PF7/INT7 S46/PF6/INT6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 S23/PC7 S22/PC6 S21/PC5 LC87F7NC8A Pin Assignment QIP100E(1420), Pb-Free/Halogen Free type www.onsemi.com 9 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 LC87F7NC8A 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 TQFIP100(1414), Pb-Free/Halogen Free type [Under Development] 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 S23/PC7 S22/PC6 S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 S0/PA0 P73/INT3/T0IN/RMIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/NKIN S47/PF7 V3/PL6/AN14/DBGP2 V2/PL5/AN13/DBGP1 V1/PL4/AN12/DBGP0 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/INT4/T1IN/INT6/T0LCP1/PWM4/S48 P31/INT4/T1IN/PWM5/S49 VSS3 VDD3 P32/INT4/T1IN/UTX1/S50 P33/INT4/T1IN/URX1/S51 P34/INT5/T1IN/INT7/T0HCP1/S52 P35/INT5/T1IN/S52 P00/DGBP0 P01/DGBP1 P02/T8LO/DGBP2 P03/T8HO P04 P05/CKO P06/T6O P07/T7O P10/SO0 www.onsemi.com 10 Top view LC87F7NC8A System Block Diagram Interrupt control IR PLA Standby control Flash ROM RC VMRC Clock generator CF PC X’tal ACC B register C register ALU SIO0 Bus interface SIO1 Port 0 Timer 0 (High speed clock counter) Port 1 Timer 1 Port 3 PSW RAR Base timer Port 7 LCD Controller Port 8 INT0 to 7 Noise Rejection Filter ADC Timer 4 Small signal detector Timer 5 Timer 6 UART1 UART2 RAM Stack pointer Watchdog timer On-chip debugger PWM4/5 Timer 7 Remote control receiver circuit 1 Timer 8 Remote control receiver circuit 2 Day and time counter www.onsemi.com 11 LC87F7NC8A Pin Description Pin Name VSS1 VSS2 VSS3 VDD1 I/O Description Option - power supply pin No - + power supply pin No • 8-bit I/O port Yes VDD2 VDD3 Port 0 I/O • I/O specifiable in 1-bit units P00 to P07 • Pull-up resistors can be turned on and off in 1-bit units. • Input for HOLD release • Input for port 0 interrupt • Shared pins P03: INT6 input P04: INT7 input P05: Clock output (system clock/can selected from sub clock) P06: Timer 6 toggle output P07: Timer 7 toggle output On chip debugger pins: DBGP0 to DBGP2(P00 to P02) Port 1 I/O Yes • 8-bit I/O port • I/O specifiable in 1-bit units P10 to P17 • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output Port 3 P30 to P35 I/O • 6-bit I/O port Yes • Segment output for LCD • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P30 to P33: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P34 to P35: INT5 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P30: PWM4 output/INT6 input/timer 0L capture 1 input P31: PWM5 output P32: UART1 transmit P33: UART1 receive P34: UART2 transmit/INT7 input/timer 0H capture 1 input P35: UART2 receive Interrupt acknowledge type Rising Falling INT4 enable enable INT5 enable enable INT6 enable INT7 enable Rising & H level L level enable disable disable enable disable disable enable enable disable disable enable enable disable disable Falling Continued on next page. www.onsemi.com 12 LC87F7NC8A Continued from preceding page. Pin Name Port 7 I/O I/O Description Option No • 4-bit I/O port • I/O specifiable in 1-bit units P70 to P73 • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/ remote control receiver input AD converter input ports: AN8 (P70), AN9 (P71) Interrupt acknowledge type Port 8 I/O Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising & H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable Falling No • 8-bit I/O port • I/O specifiable in 1-bit units P80 to P87 • Shared pins AD converter input ports: AN0 to AN7 Small signal detector input port: MICIN (P87) S0/PA0 to I/O S7/PA7 S8/PB0 to I/O I/O I/O • Segment output for LCD No • Segment output for LCD No • Can be used as general-purpose I/O port (PD) I/O S39/PE7 S40/PF0 to No • Can be used as general-purpose I/O port (PC) S31/PD7 S32/PE0 to • Segment output for LCD • Can be used as general-purpose I/O port (PB) S23/PC7 S24/PD0 to No • Can be used as general-purpose I/O port (PA) S15/PB7 S16/PC0 to • Segment output for LCD • Segment output for LCD No • Can be used as general-purpose I/O port (PE) I/O S47/PF7 No • Segment output for LCD • Can be used as general-purpose I/O port (PF) PF6: INT6 input PF7: INT7 input COM0/PL0 to I/O COM3/PL3 V1/PL4 to • Common output for LCD No • Can be used as general-purpose input port (PL) I/O V3/PL6 • LCD output bias power supply No • Can be used as general-purpose input port (PL) • Shared pins AD converter input ports: AN12 (V1) to AN14 (V3) On-chip debugger pins: DBGP0 (V1) to DBGP2 (V3) RES Input XT1 Input Reset pin No • 32.768kHz crystal oscillator input pin No • Shared pins General-purpose input port Must be connected to VDD1 if not to be used. AD converter input port: AN10 XT2 I/O No • 32.768kHz crystal oscillator output pin • Shared pins General-purpose I/O port Must be set for oscillation and kept open if not to be used. AD converter input port: AN11 CF1 Input CF2 Output Ceramic resonator input pin No Ceramic resonator output pin No www.onsemi.com 13 LC87F7NC8A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode Port Name Option Selected in Units of P00 to P07 each bit P10 to P17 each bit P30 to P35 each bit Option Type Output Type Pull-up Resistor 1 CMOS Programmable (Note) 2 Nch-open drain Programmable 1 CMOS Programmable 2 Nch-open drain Programmable 1 CMOS Programmable 2 Nch-open drain Programmable Programmable P70 - No Nch-open drain P71 to P73 - No CMOS Programmable P80 to P87 - No Nch-open drain No S0/PA0 to S47/PF7 - No CMOS Programmable COM0/PL0 to - No Input only No COM3/PL3 V1/PL4 to V3/PL6 - No Input only No XT1 - No Input only No XT2 - No Output for 32.768kHz crystal oscillator (Nch-open drain when in general-purpose No output mode) User Option List Option Name Option Type P00 to P07 Mask Version Flash Version *1 Option Selected in Specified Item Units of CMOS each bit Nch-open drain Port output form P10 to P17 CMOS each bit Nch-open drain P30 to P35 CMOS each bit Nch-open drain Program start - address 00000H *2 1FF00H *1: Mask option selection - No change possible after the mask is completed. *2: Program start address of the mask version is 00000H. LSI VDD1 Power supply For backup *2 VDD2 VDD3 VSS1 VSS2 VSS3 *1: Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. *2: The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup mode. www.onsemi.com 14 LC87F7NC8A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Symbol Pin/Remarks Maximum supply voltage VDD max VDD1, VDD2, VDD3 VDD1=VDD2=VDD3 0.3 +4.6 supply voltage for VLCD V1/PL4, V2/PL5, VDD1=VDD2=VDD3 0.3 VDD 0.3 VDD+0.3 VSS VDD+0.1 0.3 VDD+0.3 LCD Conditions Specification Parameter V3/PL6 Input voltage VI(1) Port L XT1, CF1, RES VI(2) Input/output voltage VIO(1) VDD2, VDD3 VDD [V] min typ max unit V Ports 0, 1, 3, 7, 8 Ports A, B, C, D, E, F, XT2 Peak output IOPH(1) Ports 0, 1, 32 to 35 current • CMOS output selected • Current at each pin IOPH(2) Ports 30, 31 • CMOS output selected High level output current • Current at each pin Mean output 20 IOPH(3) Ports 71 to 73 Current at each pin 5 IOPH(4) Ports A, B, C, D, E, F Current at each pin 5 IOMH(1) Ports 0, 1, 32 to 35 • CMOS output selected • Current at each pin current (Note 1-1) 10 IOMH(2) Ports 30, 31 • CMOS output selected • Current at each pin 7.5 15 3 IOMH(3) Ports 71 to 73 Current at each pin IOMH(4) Ports A, B, C, D, E, F Current at each pin Total output IOAH(1) Ports 0, 1, 32 to 35 Total of all pins 25 current IOAH(2) Ports 30, 31 Total of all pins 25 IOAH(3) Ports 0, 1, 3 Total of all pins 45 IOAH(4) Ports 71 to 73 Total of all pins 5 IOAH(5) Ports A, B, C Total of all pins 25 IOAH(6) Ports D, E, F Total of all pins 25 IOAH(7) Ports A, B, C, D, E, F Total of all pins 45 Peak output IOPL(1) Ports 0, 1, 32 to 35 Current at each pin 20 current IOPL(2) Ports 30, 31 Current at each pin 30 IOPL(3) Ports 7, 8 Current at each pin 3 10 XT2 Low level output current mA IOPL(4) Ports A, B, C, D, E, F Current at each pin Mean output IOML(1) Ports 0, 1, 32 to 35 Current at each pin 15 current IOML(2) Ports 30, 31 Current at each pin 20 Ports 7, 8 Current at each pin (Note 1-1) IOML(3) 10 7.5 XT2 IOML(4) Ports A, B, C, D, E, F Current at each pin Total output OAL(1) Ports 0,1,32 to 35 Total of all pins 45 current IOAL(2) Ports 30, 31 Total of all pins 45 IOAL(3) Ports 0, 1, 3 Total of all pins 80 IOAL(4) Ports 7, 8 Total of all pins 7.5 20 XT2 Maximum power IOAL(5) Ports A, B, C Total of all pins 45 IOAL(6) Ports D, E, F Total of all pins 45 IOAL(7) Ports A, B, C, D, E, F Total of all pins Pd max QIP100E(1420) Ta=40 to +85C 215 TQFP100(1414) Ta=40 to +85C under dissipation Operating ambient Topr 40 +85 Tstg 55 +125 temperature Storage ambient 80 mW C temperature Note 1-1: The mean output current is a mean value measured over 100ms. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 15 LC87F7NC8A Allowable Operating Range at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD [V] Operating VDD(1) VDD1=VDD2=VDD3 min typ max unit 0.167stCYC200s 2.7 3.6 0.356stCYC200s 2.5 3.6 2.0 3.6 0.3VDD VDD supply voltage (Note 2-1) Memory VHD VDD1 sustaining RAM and register contents sustained in HOLD mode. supply voltage High level input VIH(1) voltage Ports 0, 3, 8 Output disabled Ports A, B, C, D, E, F 2.5 to 3.6 Port L VIH(2) Port 1 • Output disabled Ports 71 to 73 • When INT1VTSL=0 P70 port input/ (P71 only) 2.5 to 3.6 +0.7 0.3VDD VDD +0.7 interrupt side VIH(3) P71 interrupt side • Output disabled • When INT1VTSL=1 VIH(4) P87 small signal Output disabled input side VIH(5) P70 watchdog timer Output disabled side VIH(6) Low level input VIL(1) voltage XT1, XT2, CF1, RES Ports 0, 3, 8 2.5 to 3.6 0.85VDD VDD 2.5 to 3.6 0.75VDD VDD 2.5 to 3.6 0.9VDD VDD 2.5 to 3.6 0.75VDD 2.5 to 3.6 VSS 0.2VDD 2.5 to 3.6 VSS 0.2VDD 2.5 to 3.6 VSS 0.45VDD 2.5 to 3.6 VSS 0.25VDD 2.5 to 3.6 VSS V VDD Output disabled Ports A, B, C, D, E, F Port L VIL(2) Port 1 • Output disabled Ports 71 to 73 • When INT1VTSL=0 P70 port input/ (P71 only) interrupt side VIL(3) P71 interrupt side • Output disabled • When INT1VTSL=1 VIL(4) P87 small signal Output disabled input side VIL(5) P70 watchdog timer Output disabled side VIL(6) Instruction cycle XT1, XT2, CF1, RES tCYC 0.8VDD -1.0 0.25VDD 2.5 to 3.6 VSS 2.7 to 3.6 0.167 200 2.5 to 3.6 0.356 200 2.5 to 3.6 0.1 18 s time (Note 2-2) External system clock frequency FEXCF(1) CF1 • CF2 pin open • System clock frequency division ratio=1/1 • External system clock MHz duty=50±5% • CF2 pin open • System clock frequency 2.5 to 3.6 0.2 36 division ratio=1/2 Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Continued on next page. www.onsemi.com 16 LC87F7NC8A Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD [V] Oscillation FmCF(1) CF1, CF2 • See Fig. 1. frequency range (Note 2-3) • 18MHz ceramic oscillation FmCF(2) CF1, CF2 • 8MHz ceramic oscillation • See Fig. 1. FmRC Internal RC oscillation FmVMRC(1) • Frequency variable RC min typ max 2.7 to 3.6 18 2.5 to 3.6 8 2.5 to 3.6 0.3 1.0 unit 2.0 source oscillation • When VMRAJ2 to 0=4, 2.5 to 3.6 10 2.5 to 3.6 4 2.5 to 3.6 32.768 MHz VMFAJ2 to 0=0, VMSL4M=0 FmVMRC(2) • Frequency variable RC source oscillation • When VMRAJ2 to 0=4, VMFAJ2 to 0=0, VMSL4M=1 FsX’tal XT1, XT2 • 32.768kHz crystal oscillation • See Fig. 2. Frequency OpVMRC(1) When VMSL4M=0 variable RC OpVMRC(2) When VMSL4M=1 oscillation kHz 2.5 to 3.6 8 10 12 2.5 to 3.6 3.5 4 4.5 2.5 to 3.6 8 24 64 2.5 to 3.6 1 4 8 MHz usable range Frequency VmADJ(1) Each step of VMRAJn variable RC oscillation (Wide range) VmADJ(2) Each step of VMFAJn adjustment (Small range) range Note 2-3: See Tables 1 and 2 for the oscillation constants. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Electrical Characteristics at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD [V] High level input IIH(1) current Ports 0, 1, 3, 7, 8 • Output disabled Ports A, B, C, D, E, • Pull-up resistor off F • VIN=VDD (Including output Tr's Port L RES VIN=VDD IIH(3) XT1, XT2 • For input port specification • VIN=VDD IIH(5) Low level input IIL(1) current unit 1 2.5 to 3.6 1 2.5 to 3.6 1 15 VIN=VDD 2.5 to 3.6 P87 small signal input side VIN=VBIS+0.5V (VBIS: Bias voltage) 2.5 to 3.6 Ports 0, 1, 3, 7, 8 • Output disabled Ports A, B, C, D, E, • Pull-up resistor off F • VIN=VSS (Including output Tr's 1.5 5.5 10 A 2.5 to 3.6 1 2.5 to 3.6 1 2.5 to 3.6 1 off leakage current) IIL(2) RES VIN=VSS IIL(3) XT1, XT2 • For input port specification • VIN=VSS IIL(4) CF1 VIN=VSS 2.5 to 3.6 15 IIL(5) P87 small signal VIN=VBIS0.5V (VBIS: Bias voltage) 2.5 to 3.6 10 input side max 2.5 to 3.6 CF1 Port L typ off leakage current) IIH(2) IIH(4) min 5.5 1.5 Continued on next page. www.onsemi.com 17 LC87F7NC8A Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD [V] min High level output VOH(1) Ports 0, 1, 32 to 35 IOH=0.4mA 2.5 to 3.6 VDD0.4 voltage VOH(2) Ports 30, 31 IOH=1.6mA 2.5 to 3.6 VDD0.4 VOH(3) Ports 71 to 73 IOH=0.4mA 2.5 to 3.6 VDD0.4 VOH(4) Ports A, B, C IOH=0.4mA 2.5 to 3.6 VDD0.4 Ports D, E, F Low level output VOL(1) voltage Ports 0, 1, 32 to 35 typ max unit IOL=1.6mA Ports 30, 31 2.5 to 3.6 0.4 2.5 to 3.6 0.4 IOL=1.6mA 2.5 to 3.6 0.4 IOL=1.6mA 2.5 to 3.6 0.4 (PWM function output mode) VOL(2) Ports 30, 31 IOL=5mA (Port function output mode) VOL(3) Ports 7, 8 V XT2 VOL(4) Ports A, B, C Ports D, E, F LCD output voltage VODLS S0 to S53 regulation • IO=0mA • VLCD, 2/3VLCD, 1/3VLCD level output 2.5 to 3.6 0 ±0.2 2.5 to 3.6 0 ±0.2 • See Fig. 8. VODLC COM0 to COM3 • IO=0mA • VLCD, 2/3VLCD, 1/2VLCD, 1/3VLCD level output • See Fig. 8. LCD bias resistor RLCD(1) Resistance per See Fig. 8. one bias resister RLCD(2) Resistance per 2.5 to 3.6 60 2.5 to 3.6 30 See Fig. 8. one bias resister k 1/2R mode Resistance of Rpu(1) pull-up MOS Tr. Ports 0, 1, 3, 7 VOH=0.9VDD Ports A, B, C, D, E, 2.5 to 3.6 18 50 50 F Hysterisis voltage VHYS(1) Ports 1, 7 RES VHYS(2) P87 small signal CP All pins 0.1VDD 2.5 to 3.6 0.1VDD 2.5 to 3.6 10 V input side Pin capacitance 2.5 to 3.6 • For pins other than that under test: VIN=VSS • f=1MHz pF • Ta=25C Input sensitivity Vsen P87 small signal 2.5 to 3.6 input side 0.12VDD Vpp Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 18 LC87F7NC8A Serial I/O Characteristics at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V, 0.190μs tCYC 200μs SIO0 Serial I/O Characteristics (Note 4-1-1) at VDD = 2.7 V to 3.6V 0.190μs tCYC 200μs Specification Parameter Symbol Pin/Remarks Conditions Input clock VDD [V] Frequency tSCK(1) Low level tSCKL(1) SCK0(P12) See Fig. 6. tSCKH(1) 2.5 to 3.6 pulse width tSCKHA(1) tCYC 4 (Note 4-1-2) Frequency tSCK(2) SCK0(P12) • CMOS output selected 4/3 • See Fig. 6. Output clock Low level tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 2.5 to 3.6 pulse width tSCKHA(2) 1/2 • Continuous data tSCKH(2) transmission/reception mode +2tCYC • CMOS output selected • See Fig. 6. Data setup time Serial input unit 1 • Continuous data transmission/reception mode tsDI(1) SB0(P11), SI0(P11) Data hold time respect to rising edge of +(10/3) tCYC tCYC 0.03 2.5 to 3.6 • See Fig. 6. thDI(1) tSCKH(2) • Must be specified with SIOCLK. 0.03 Input clock Output tdD0(1) delay time SO0(P10), SB0(P11) • Continuous data (1/3)tCYC transmission/reception mode +0.05 (Note 4-1-3) tdD0(2) • Synchronous 8-bit mode 2.5 to 3.6 tdD0(3) s 1tCYC (Note 4-1-3) +0.05 (Note 4-1-3) Output clock Serial output max 1 • See Fig. 6. Serial clock typ 2 pulse width High level min (1/3)tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. www.onsemi.com 19 LC87F7NC8A SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin/Remarks Conditions Input clock Frequency tSCK(3) SCK1(P15) Low level tSCKL(3) See Fig. 6. Frequency SCK1(P15) • CMOS output selected tSCKL(4) 1 2 2.5 to 3.6 pulse width High level 1/2 tSCK tSCKH(4) 1/2 pulse width Serial input Data setup time tsDI(2) unit 1 • See Fig. 6. Low level max tCYC tSCKH(3) tSCK(4) typ 2 2.5 to 3.6 pulse width High level min pulse width Output clock Serial clock VDD [V] SB1(P14), SI1(P14) • Must be specified with respect to rising edge of 2.5 to 3.6 0.03 2.5 to 3.6 0.03 SIOCLK. Data hold time Output delay time • See Fig. 6. thDI(2) tdD0(4) SO1(P13), Serial output SB1(P14) • Must be specified with s respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of (1/3)tCYC 2.5 to 3.6 +0.05 output state change in open drain output mode. • See Fig. 6. Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD [V] High/low tPIH(1) INT0(P70), • Interrupt source flag can be set. level pulse tPIL(1) INT1(P71), • Event inputs for timer 0 or 1 are width INT2(P72), min typ max unit enabled. INT4(P30 to P33), 2.5 to 3.6 1 2.5 to 3.6 2 2.5 to 3.6 64 2.5 to 3.6 256 2.5 to 3.6 1 2.5 to 3.6 4 2.5 to 3.6 200 INT5(P34 to P35), INT6(P30), INT7(P34) tPIH(2) INT3(P73) when noise filter • Interrupt source flag can be set. tPIL(2) time constant is 1/1 • Event inputs for timer 0 are enabled. tPIH(3) INT3(P73) when noise filter • Interrupt source flag can be set. tPIL(3) time constant is 1/32 • Event inputs for timer 0 are enabled. tPIH(4) INT3(P73) when noise filter • Interrupt source flag can be set. tPIL(4) time constant is 1/128 • Event inputs for timer 0 are enabled. tPIH(5) MICIN(P87) tPIL(5) tPIH(6) RMIN(P73) tPIL(6) tPIL(7) Condition that signal is accepted to small signal detection counter. Condition that signal is accepted to remote control receiver circuit. RES Resetting is enabled. Note 5-1: RMCK is an unit for the base clock (40tCYC/50tCYC/Sub-Clock) of remote control receiver circuit. www.onsemi.com 20 tCYC RMCK (Note 5-1) s LC87F7NC8A AD Converter Characteristics at VSS1 = VSS2 = VSS3 = 0V <12bits AD Converter Mode at Ta =30 to +70C> Specification Parameter Symbol Pin/Remarks Conditions VDD [V] Resolution N AN0(P80) to Absolute ET AN7(P87), Conversion tCAD time Analog input 2.5 to 3.6 (Note 6-1) AN9(P71), • See Conversion time calculation AN10(XT1), formulas. AN11(XT2) (Note 6-2) typ max unit 12 2.5 to 3.6 AN8(P70), accuracy min bit ±16 3.0 to 3.6 64 115 2.7 to 3.6 128 230 2.5 to 3.6 256 460 VSS VDD VAIN voltage range Analog port IAINH VAIN=VDD 2.5 to 3.6 input current IAINL VAIN=VSS 2.5 to 3.6 1 1 LSB s V A <8bits AD Converter Mode at Ta =30 to +70C> Specification Parameter Symbol Pin/Remarks Conditions VDD [V] Resolution N AN0(P80) to Absolute ET AN7(P87), accuracy AN8(P70), Conversion AN9(P71), TCAD time Analog input min 2.5 to 3.6 (Note 6-1) formulas. AN11(XT2) (Note 6-2) max unit 8 bit 1.5 2.5 to 3.6 • See Conversion time calculation AN10(XT1), typ 3.0 to 3.6 39 71 2.7 to 3.6 79 140 2.5 to 3.6 157 280 VSS VDD VAIN voltage range Analog port IAINH VAIN=VDD 2.5 to 3.6 input current IAINL VAIN=VSS 2.5 to 3.6 1 1 LSB s V A <Conversion time calculation formulas> 12bits AD Converter Mode: tCAD(Conversion time)=((52/(division ratio)) + 2) (1/3) tCYC 8bits AD Converter Mode: tCAD(Conversion time)=((32/(division ratio)) + 2) (1/3) tCYC Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. www.onsemi.com 21 LC87F7NC8A Consumption Current Characteristics at Ta = 40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Normal mode Symbol IDDOP(1) Pin/ Remarks Specification Conditions VDD [V] • FmCF=18MHz ceramic oscillation mode consumption VDD1 =VDD2 current =VDD3 • System clock set to 12MHz side (Note 7-1) min typ max 2.7 to 3.6 6.1 15.6 2.5 to 3.6 3.9 8.8 2.5 to 3.6 0.4 1.7 2.5 to 3.6 4.3 12.0 2.5 to 3.6 2.1 6.6 2.5 to 3.6 19.3 73 unit • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDOP(2) • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDOP(3) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation mA • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDOP(4) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped. • System clock set to 10MHz with frequency variable RC oscillation • 1/1 frequency division ratio IDDOP(5) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped. • System clock set to 4MHz with frequency variable RC oscillation • 1/1 frequency division ratio IDDOP(6) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal RC oscillation stopped. A • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. www.onsemi.com 22 LC87F7NC8A Continued from preceding page. Parameter Symbol Specification Pin/ Conditions Remarks VDD [V] • HALT mode consumption VDD1 =VDD2 current =VDD3 • FmX’tal=32.768kHz crystal oscillation mode HALT mode IDDHALT(1) typ max 2.7 to 3.6 2.7 6.8 2.5 to 3.6 1.4 3.1 2.5 to 3.6 0.2 0.75 2.5 to 3.6 1.6 4.6 2.5 to 3.6 0.7 1.75 2.5 to 3.6 12.4 54.9 unit • FmCF=18MHz ceramic oscillation mode • System clock set to 12MHz side (Note 7-1) min • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(2) • HALT mode • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/1 frequency division ratio IDDHALT(3) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation mA • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio IDDHALT(4) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped. • System clock set to 10MHz with frequency variable RC oscillation • 1/1 frequency division ratio IDDHALT(5) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped. • System clock set to 4MHz with frequency variable RC oscillation • 1/1 frequency division ratio IDDHALT(6) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped. • 1/2 frequency division ratio HOLD mode IDDHOLD(1) consumption VDD1 A • HOLD mode • CF1=VDD or open (External clock mode) 2.5 to 3.6 0.08 18.4 2.5 to 3.6 10.14 34.4 current Timer HOLD IDDHOLD(2) • Timer HOLD mode mode • CF1=VDD or open (External clock mode) consumption • FmX’tal=32.768kHz crystal oscillation mode current Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. www.onsemi.com 23 LC87F7NC8A F-ROM Write Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD [V] Onboard IDDFW(1) VDD1 min typ max unit • Without CPU current programming 3.0 to 3.6 7 11 mA current Programming tFW(1) • 2K-byte erase operation 3.0 to 3.6 12 15 ms time tFW(2) • 2K-byte writing operation 3.0 to 3.6 35 45 s UART (Full Duplex) Operating Conditions at Ta = +40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD [V] Transfer rate UBR UTX(S32), 2.5 to 3.6 URX(S33) min typ 16/3 max unit 8192/3 tCYC Data length : 7/8/9 bits (LSB first) Stop bits : 1 bit (2-bit in continuous data transmission) Parity bits : None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H) Start bit Start of transmission Stop bit Transmit data (LSB first) End of transmission UBR Example of 8-bit Data Reception Mode Processing (Receive Data=55H) Stop bit Start bit Start of reception Receive data (LSB first) UBR www.onsemi.com 24 End of reception LC87F7NC8A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Vendor Frequency Name 18MHz 10MHz 8MHz Stabilization Voltage Oscillator Name CSTCE18M0V51-R0 Oscillation Operating Circuit Constant Time Range typ Remarks C1 C2 Rf1 Rd1 [pF] [pF] [] [] [ms] [ms] (5) (5) OPEN 150 2.7 to 3.6 0.05 0.15 [V] max Values shown in parentheses are capacitance included in the oscillator Values shown in parentheses are capacitance included in the oscillator Values shown in parentheses are capacitance included in the oscillator MURATA CSTLS18M0X51-B0 (5) (5) OPEN 0 2.7 to 3.6 0.11 0.33 CSTCE10M00G52-R0 (10) (10) OPEN 680 2.5 to 3.6 0.05 0.15 CSTLS10M00G53-B0 (15) (15) OPEN 1.5k 2.5 to 3.6 0.05 0.15 MURATA CSTCE8M00G52-R0 (10) (10) OPEN 680 2.5 to 3.6 0.05 0.15 CSTLS8M00G53-B0 (15) (15) OPEN 1.5k 2.5 to 3.6 0.05 0.15 MURATA The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillation Circuit with a Crystal Oscillation Nominal Frequency 32.768kHz Vendor Name EPSON TOYOCOM Circuit Constant Oscillator Name Operating Oscillation Voltage Stabilization Time C3 C4 Rf2 Rd2 Range typ max [pF] [pF] [] [] [V] [s] [s] 9 9 Open 330k 2.5 to 3.6 1.0 3.0 MC-306 Remarks CL=7.0pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Fig. 4). Caution: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 XT1 CF2 XT2 Rf2 Rf1 Rd1 C1 C3 C2 Rd2 C4 X’tal CF Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point www.onsemi.com 25 LC87F7NC8A VDD Operating VDD lower limit 0V Power supply Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD reset signal VALID Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times www.onsemi.com 26 LC87F7NC8A VDD Note : RRES Determine the value of CRES and RRES so that the reset signal is present for a period of 200s after the supply voltage goes beyond the lower limit of the IC's operating voltage. RES CRES Figure 5 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Data RAM transfer period (SIO0 only) tSCK tSCKH tSCKL SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKL tSCKHA SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 6 Serial I/O Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform www.onsemi.com 27 LC87F7NC8A VDD SW: ON/OFF (programmable) RLCD RLCD SW: On when VLCD=VDD RLCD RLCD VLCD RLCD RLCD 2/3 VLCD RLCD 1/2 VLCD RLCD 1/3 VLCD RLCD RLCD GND Figure 8 LCD bias resistor ORDERING INFORMATION LC87F7NC8AUEJ-2H Device Package QIP100E(1420) (Pb-Free / Halogen Free) LC87F7NC8AVUEJ-2H QIP100E(1420) (Pb-Free / Halogen Free) Shipping (Qty / Packing) 50 / Tray Foam 50 / Tray Foam ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. www.onsemi.com 28