ON FAN53526 3.0 a, 2.4 mhz, digitally programmable tinybuck regulator Datasheet

FAN53526
3.0 A, 2.4 MHz, Digitally
Programmable TinyBuck)
Regulator
Descriptions
The FAN53526 is a step−down switching voltage regulator that delivers a
digitally programmable output from an input voltage supply of 2.5 V to 5.5 V.
The output voltage is programmed through an I2C interface capable of
operating up to 3.4 MHz.
Using a proprietary architecture with synchronous rectification, the
FAN53526 is capable of delivering 3.0 A continuous at over 80% efficiency,
maintaining that efficiency at load currents as low as 10 mA. The regulator
operates at a nominal fixed frequency of 2.4 MHz, which reduces the value of
the external components. Additional output capacitance can be added to
improve regulation during load transients without affecting stability.
At moderate and light loads, Pulse Frequency Modulation (PFM) is used to
operate in Power−Save Mode with a typical quiescent current of 50 mA at
room temperature. Even with such a low quiescent current, the part exhibits
excellent transient response during large load swings. At higher loads, the
system automatically switches to fixed−frequency control, operating at
2.4 MHz. In Shutdown Mode, the supply current drops below 1 mA, reducing
power consumption. PFM Mode can be disabled if fixed frequency is desired.
The FAN53526 is available in a 15−bump, 1.310 mm x 2.015 mm, 0.4 mm
ball pitch WLCSP.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Fixed−Frequency Operation: 2.4 MHz
Best−in−Class Load Transient
Continuous Output Current Capability: 3.0 A
2.5 V to 5.5 V Input Voltage Range
Digitally Programmable Output Voltage:
♦ −0.600 V to 1.39375 V in 6.25 mV Steps
Programmable Slew Rate for Voltage Transitions
I2C−Compatible Interface Up to 3.4 Mbps
PFM Mode for High Efficiency in Light-Load
Quiescent Current in PFM Mode: 50 mA (Typical)
Input Under−Voltage Lockout (UVLO)
Thermal Shutdown and Overload Protection
15−Bump Wafer−Level Chip Scale Package (WLCSP)
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WLCSP−15
CASE 567QS
MARKING DIAGRAM
Pin−1
Mark
1, 2
KK
.
X
Y
Z
1
2
K
K
X
Y
Z
= Two Alphanumeric Characters for
Device Mark
= Two Alphanumeric Characters for
Lot Rune Code Mark
= Pin 1 Indicator
= Alphabetical Year Code
= 2−weeks Date Code
= Assembly Plant Code
PIN CONFIGURATION
VIN
A1
SW
A2
PGND
A3
B1
B2
B3
C1
PGND
C2
AGND
C3
VSEL
D1
EN
D2
SDA
D3
AGND
E1
SCL
E2
VOUT
E3
Applications
• Application, Graphic, and DSP Processors
ORDERING INFORMATION
ARMt, Tegrat, OMAPt, NovaThor,
ARMADAt, Kraitt, etc.
Hard Disk Drives, LPDDR3, LPDDR4
Tablets, Netbooks, Ultra−Mobile PCs
Smart Phones
Gaming Devices
See detailed ordering and shipping information on page 2 of
this data sheet.
♦
•
•
•
•
© Semiconductor Components Industries, LLC, 2006
December, 2017 − Rev. 4
1
Publication Order Number:
FAN53526/D
FAN53526
PVIN
CIN_LOAD
VOUT
SDA
SCL
C BY
C IN
EN
L1
SW
FAN 53526
VSEL
C OUT
PGND
LOAD
AGND
Figure 1. Typical Application
Table 1. ORDERING INFORMATION
Power−Up
Defaults
DVS Range
/ Step Size
I2C Slave
Address
Temperature
Range
Packing
Method
Device
Marking
Part Number
VSEL0
VSEL1
FAN53526UC84X
1.125
1.125
F7
FAN53526UC89X
1.15625
1.15625
CL
FAN53526UC100X
1.225
1.225
F9
FAN53526UC106X
1.2625
1.2625
Package
C7
C0
0.600 V to
1.39375 V /
6.25 mV
FAN53526UC128X
1.20
1.20
FAN53526UC00X
0.60
0.60
FAN53526UC64X
1.00
1.00
GG
FAN53526UC88X
1.15
1.15
LM
FAN53526UC288X
1.15
1.15
FAN53526UC168X
1.125
1.125
−40 to 85_C
WLCSP
F3
Tape & Reel
GA
LN
C2
FR
RECOMMENDED EXTERNAL COMPONENTS
Table 2. RECOMMENDED EXTERNAL COMPONENTS FOR 3.0 A MAXIMUM LOAD CURRENT
Component
Description
L1
330 nH, 2016 Case Size
Vendor
Parameter
Typ.
L1 Alternative (Note 1)
470 nH 2016 Case Size
COUT1, COUT2
47 mF, 6.3 V, X5R, 0603
GRM188R60J476ME15 (Murata)
C
47
COUT1, COUT2 Alternative
(Note 1)
22 mF, 10 V, X5R, 0603
CL10A226MP8NUNB (SAMSUNG)
C
22
CIN
1 Piece; 4.7 mF, 10 V, X5R, 0603
C1608X5R1A475K (TDK)
C
4.7
CBY
1 Piece; 100 nF, 6.3V, X5R, 0201
GRM033R60J104KE19D (Murata)
C
100
Unit
See Table 3
mF
nF
1. COUT Alternative and L1 Alternative can be used if not following reference design. CBY is recommended to reduce any high frequency
component on VIN bus. CBY is optional and used to filter any high frequency component on VIN bus.
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2
FAN53526
Table 3. RECOMMENDED INDUCTORS
Manufacturer
Part #
L (nH)
DCR
(mW Typ.)
ISAT
(Note 2)
L
W
H
Toko
DFE201612E−R33N
330
15
7.0
2.0
1.6
1.2
Toko
DFE201612E−R47N
470
21
6.1
2.0
1.6
1.2
Cyntek
PIFE20161B−R47MS−39
470
30
3.1
2.0
1.6
1.2
SEMCO
CIGT201610UMR47MNE
470
30
4.0
2.0
1.6
0.9
SEMCO
CIGT201610UMR47MNE
470
33
3.0
2.0
1.2
0.9
2. ISAT where the dc current drops the inductance by 30%.
PIN CONFIGURATION
VIN
A1
SW
A2
PGND
A3
A3
A2
A1
B1
B2
B3
B3
B2
B1
C1
PGND
C2
AGND
C3
C3
C2
C1
VSEL
D1
EN
D2
SDA
D3
D3
D2
D1
AGND
E1
SCL
E2
VOUT
E3
E3
E2
E1
Top View
Bottom View
Figure 2. Pin Configuration
Table 4. PIN DEFINITIONS
Pin #
Name
Description
D1
VSEL
Voltage Select. When this pin is LOW, VOUT is set by the VSEL0 register. When this pin is HIGH,
VOUT is set by the VSEL1 register. Polarity of pin in conjunction with the MODE bits in the Control
register 02h, will select Forced PWM or Auto PFM/PWM mode of operation. VSEL0=Auto PFM,
and VSEL1=FPWM. The VSEL pin has an internal pull−down resistor (250kW), which is only activated with a logic low.
D2
EN
Enable. The device is in Shutdown Mode when this pin is LOW. Device keeps register content
when EN pin is LOW. The EN Pin has an internal pull−down resistor (250kW), which is only activated with a logic low.
E2
SCL
I2C Serial Clock
D3
SDA
I2C Serial Data
E3
VOUT
VOUT. Sense pin for VOUT. Connect to COUT.
A3, B3, C2
PGND
Power Ground. The low−side MOSFET is referenced to this pin. CIN and COUT should be returned
with a minimal path to these pins.
C3, E1
AGND
Analog Ground. All signals are referenced to this pin. Avoid routing high dV/dt AC currents through
this pin.
A1, B1, C1
VIN
Power Input Voltage. Connect to the input power source. Connect to CIN with minimal path.
A2, B2
SW
Switching Node. Connect to the inductor.
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3
FAN53526
ABSOLUTE MAXIMUM RATINGS
Stresses exceeding the absolute maximum ratings may
damage the device. The device may not function or be
operable above the recommended operating conditions and
stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the
recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings
only.
Table 5. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VIN
Parameter
Voltage on SW, VIN Pins
Min
Max
Unit
IC Not Switching
−0.3
7.0
V
IC Switching
−0.3
6.5
−0.3
VIN
(Note 3)
−0.3
VIN
(Note 3)
−0.3
6.5
V
100
V/ms
Voltage on EN Pin
Voltage on All Other Pins
VOUT
IC Not Switching
Voltage on VOUT Pin
VINOV_SLEW
ESD
Maximum Slew Rate of VIN > 6.5V, PWM Switching
Human Body Model, ANSI/ESDA/JEDEC JS−001−2012
2000
Charged Device Model per JESD22−C101
1000
V
TJ
Junction Temperature
−40
+150
°C
TSTG
Storage Temperature
−65
+150
°C
+260
°C
TL
Lead Soldering Temperature, 10 Seconds
3. Lesser of 7V or VIN + 0.3 V.
RECOMMENDED OPERATING CONDITIONS
The Recommended Operating Conditions table defines
the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal
performance to the datasheet specifications. On
Semiconductor does not recommend exceeding them or
designing to Absolute Maximum Ratings.
Table 6. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VIN
Supply Voltage Range
IOUT
Output Current
Min.
Max.
Unit
2.5
Typ.
5.5
V
0
3.0
A
TA
Operating Ambient Temperature
−40
+85
°C
TJ
Operating Junction Temperature
−40
+125
°C
Max.
Unit
Table 7. THERMAL PROPERTIES
Symbol
Parameter
θJA
Junction−to−Ambient Thermal Resistance
(Note 4)
Min.
Typ.
42
°C/W
4. Junction−to−ambient thermal resistance is a function of application and board layout. This data is simulated with four−layer 2s2p boards with
vias in accordance to JESD51− JEDEC standard. Special attention must be paid not to exceed the junction temperature
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4
FAN53526
ELECTRICAL CHARACTERISTICS
Table 8. ELECTRICAL CHARACTERISTICS
Minimum and maximum values are at VIN=3.6 V, TA=-40°C to +85°C, unless otherwise noted. Typical values are at TA=25°C, VIN=3.6 V,
and EN=HIGH. VOUT = 1.15625 V.
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Power Supplies
ILOAD=0
50
mA
ILOAD=0, MODE Bit=1 (Forced PWM)
15
mA
H/W Shutdown Supply Current
EN=GND
0.1
3.0
mA
S/W Shutdown Supply Current
EN=VIN, BUCK_ENx=0,
2.5 V ≤ VIN ≤ 5.5 V
2
12
mA
VUVLO
Under−Voltage Lockout Threshold
VIN Rising
2.32
2.45
V
VUVHYST
Under−Voltage Lockout Hysteresis
IQ
I SD
Quiescent Current
350
mV
EN, VSEL, SDA, SCL
VIH
high−Level Input Voltage
2.5 V ≤ VIN ≤ 5.5 V
VIL
low−Level Input Voltage
2.5 V ≤ VIN ≤ 5.5 V
IIN
Input Bias Current
Input Tied to GND or VIN
1.1
V
0.01
0.4
V
1.00
mA
VOUT Regulation
VREG
VOUT DC Accuracy
2.5 V ≤ VIN ≤ 5.5 V, VOUT from Minimum to Maximum, IOUT(DC)=0 to
3.0 A, Auto PFM/PWM
−2.5
2.5
2.5 V ≤ VIN ≤ 5.5 V, VOUT from Minimum to Maximum, IOUT(DC)=0 to
3.0 A, Forced PWM
−1.5
1.5
−2.3
−0.5
−14
−3
VIN=3.8 V, VOUT=0.6 V,
IOUT(DC)=500 mA, Auto PFM/PWM
%
mV
DV OUT
DI LOAD
Load Regulation
IOUT(DC)=1 to 3 A
−0.01
%/A
DV OUT
DV IN
Line Regulation
2.5 V ≤ VIN ≤ 5.5 V, IOUT(DC)=1.5 A
0.01
%/A
ILOAD Step 0.01 A ⇔ 1.5 A,
tr=tf=200 ns, VOUT=1.15625 V
±50
ILOAD Step 0 A ⇔ 500 mA,
tr=tf=100 ns, VIN=3.8 V, VOUT=0.6 V
±16
VTRSP
Transient Response
mV
Power Switch / Protection
ILIMPK
P−MOS Peak Current Limit
4.00
TLIMIT
Thermal Shutdown
150
°C
THYST
Thermal Shutdown Hysteresis
17
°C
VSDWN
Input OVP Shutdown
Rising Threshold
Falling Threshold
4.75
5.50
6.15
5.50
5.73
2.05
2.40
A
V
Frequency Control
fSW
Oscillator Frequency
2.75
MHz
DAC
Resolution
Differential
7
Nonlinearity(5)
Bits
0.5
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5
LSB
FAN53526
Table 8. ELECTRICAL CHARACTERISTICS
Minimum and maximum values are at VIN=3.6 V, TA=-40°C to +85°C, unless otherwise noted. Typical values are at TA=25°C, VIN=3.6 V,
and EN=HIGH. VOUT = 1.15625 V.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Soft−Start
tSS
Regulator Enable to Regulated
VOUT
RLOAD > 5W, VOUT=1.15625V, From
EN Rising Edge to 95% VOUT
150
ms
5. Monotonicity assured by design.
Table 9. I2C TIMING SPECIFICATIONS
Minimum and maximum values are at VIN=3.6 V, TA=-40°C to +85°C, unless otherwise noted. Typical values are at TA=25°C, VIN=3.6 V,
and EN=HIGH. VOUT = 1.15625 V.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Power Supplies
fSCL
tBUF
tHD;STA
tLOW
SCL Clock Frequency
Bus−Free Time between STOP and
START Conditions
START or REPEATED START
Hold Time
SCL LOW Period
Standard Mode
100
Fast Mode
400
Fast Mode Plus
1000
High−Speed Mode, CB ≤ 100 pF
3400
High−Speed Mode, CB ≤ 400 pF
1700
Standard Mode
4.7
Fast Mode
1.3
Fast Mode Plus
0.5
Standard Mode
4
Fast Mode
600
Fast Mode Plus
260
High−Speed Mode
160
Standard Mode
4.7
Fast Mode
1.3
Fast Mode Plus
0.5
High−Speed Mode, CB ≤ 100 pF
160
High−Speed Mode, CB ≤ 400 pF
320
Standard Mode
tHIGH
tSU;STA
SCL HIGH Period
Repeated START Setup Time
4
Fast Mode
600
Fast Mode Plus
260
High−Speed Mode, CB ≤ 100 pF
60
High−Speed Mode, CB ≤ 400 pF
120
Standard Mode
4.7
Fast Mode
600
Fast Mode Plus
260
High−Speed Mode
160
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6
kHz
ms
ms
ns
ms
ns
ms
ns
ms
ns
FAN53526
Table 9. I2C TIMING SPECIFICATIONS
Minimum and maximum values are at VIN=3.6 V, TA=-40°C to +85°C, unless otherwise noted. Typical values are at TA=25°C, VIN=3.6 V,
and EN=HIGH. VOUT = 1.15625 V.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Power Supplies
tSU;DAT
tHD;DAT
tRCL
tFCL
tRCL1
tRDA
tFDA
tSU;STO
CB
Data Setup Time
Data Hold Time
SCL Rise Time
SCL Fall Time
Rise Time of SCL After a REPEATED START Condition and After ACK Bit
SDA Rise Time
SDA Fall Time
Stop Condition Setup Time
Standard Mode
250
Fast Mode
100
Fast Mode Plus
50
High−Speed Mode
10
ns
Standard Mode
0
3.45
Fast Mode
0
900
Fast Mode Plus
0
450
High−Speed Mode, CB ≤ 100 pF
0
70
High−Speed Mode, CB ≤ 400 pF
0
150
Standard Mode
20+0.1CB
1000
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
20+0.1CB
300
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
40
High−Speed Mode, CB ≤ 400 pF
20
80
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
20+0.1CB
1000
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
20+0.1CB
300
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
4
Fast Mode
600
Fast Mode Plus
120
High−Speed Mode
160
Capacitive Load for SDA and SCL
7
ns
ns
ns
ns
ns
ns
ms
ns
400
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ms
pF
FAN53526
Timing Diagrams
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÖÖ
ÖÖ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÑÑ
ÓÓÓ
ÓÓÓ
tF
SDA
SCL
tSU;STA
tR
TSU;DAT
tHIGH
tLOW
tHD;STA
tHD;DAT
tSU;STA
SCLH
tHD;STO
REPEATED
START
STOP
Figure 3. I2C Interface Timing for Fast Plus, Fast, and Slow Modes
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÛÛÛ
ÛÛÛ
tFDA
SDAH
tBUF
tHD;STA
START
tRDA
tFCL
REPEATED
START
REPEATED
START
tRCL
tSU;STO
tHIGH
tLOW
tHD;STA
START
ŠŠŠŠ
ÙÙ
ÜÜÜ
ŠŠŠŠÙÙ
ÕÕÜÜÜ
ÕÕ
ÕÕ
ÕÕ
ÕÕ
tSU;DAT
tRCL1
ÌÌ
ÌÌÎÎ
ÎÎ
ÌÌÎÎ
ÌÌÎÎ
ÌÌÎÎ
ÌÌÎÎ
ÒÒ
ÏÏ
ÒÒÏÏ
tHD;DAT
note A
= MCS Current Source Pull−up
= RP Resistor Pull−up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 4. I2C Interface Timing for High−Speed Mode
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STOP
FAN53526
TYPICAL CHARACTERISTICS
(Unless otherwise specified, Auto PFM/PWM Mode, VIN = 3.6 V, VOUT = 1.15625V, VSEL = EN = VIN, TA = 25°C; circuit and components
according to Figure 1 and Table 2. Efficiency test conditions; ILOAD: 1 mA to 3 A, L = 330 nH, DFE201612E−R33N (Toko). CIN = 4.7 mF,
0603, C1608X5R1A475K (TDK), COUT x 2 = 2X47 mF, 0603, GRM188R60J476ME (Murata).)
Figure 5. Efficiency vs. Load Current and Input
Voltage, VOUT=1.15625V
Figure 6. Efficiency vs. Load Current and
Temperature, VIN=3.6V, VOUT=1.15625V
Figure 7. Output Regulation vs. Load Current and
Input Voltage, VOUT=1.15625V
Figure 8. PWM Entry / Exit Level vs. Input Voltage,
VOUT=1.15625V
Figure 9. Output Ripple vs. Load Current, VIN=4.2V
and 3.6V, VOUT=1.15625V, Auto and Forced PWM
Figure 10. Frequency vs. Load Current, VIN=4.2V
and 3.6V, VOUT=1.15625V, Auto PWM
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FAN53526
TYPICAL CHARACTERISTICS (continued)
(Unless otherwise specified, Auto PFM/PWM Mode, VIN = 3.6 V, VOUT = 1.15625V, VSEL = EN = VIN, TA = 25°C; circuit and components
according to Figure 1 and Table 2. Efficiency test conditions; ILOAD: 1 mA to 3 A, L = 330 nH, DFE201612E−R33N (Toko). CIN = 4.7 mF,
0603, C1608X5R1A475K (TDK), COUT x 2 = 2X47 mF, 0603, GRM188R60J476ME (Murata).)
Figure 11. Quiescent Current vs. Input Voltage and
Temperature, Auto Mode, VOUT=1.15625V
Figure 12. Efficiency vs. Load Current and
Temperature, VIN=3.6V, VOUT=1.15625V
VIN
IOUT
VOUT
VOUT
Figure 13. Line Transient, 3.6−4.2 VIN, 1.15625
VOUT, 10 ms Edge at 1 A Load
Figure 14. Load Transient, 3.6 VIN, 1.15625 VOUT,
0.01−1.5 A, 120 ns Edge
IOUT
EN
VOUT
VOUT
Figure 15. Startup, 5 W Load, VOUT = 1.15625 V,
VIN = 3.6 V
Figure 16. Load Transient, 3.6 VIN, 1.15625 VOUT,
1.5−3 A, 120 ns Edge
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FAN53526
TYPICAL CHARACTERISTICS (continued)
(Unless otherwise specified, Auto PFM/PWM Mode, VIN = 3.6 V, VOUT = 1.15625V, VSEL = EN = VIN, TA = 25°C; circuit and components
according to Figure 1 and Table 2. Efficiency test conditions; ILOAD: 1 mA to 3 A, L = 330 nH, DFE201612E−R33N (Toko). CIN = 4.7 mF,
0603, C1608X5R1A475K (TDK), COUT x 2 = 2X47 mF, 0603, GRM188R60J476ME (Murata).)
IOUT (9500mA/div)
500mA
0mA
618mV
VOUT (10mV/div)
0.6V offset
+ 16mV
− 16mV
582mV
Figure 17. Load Transient, 3.8 VIN, 0.6 VOUT, 0−500
mA, 100 ns Edge, 47 mF COUT
Operating Description
For very light loads, the FAN53526 operates in
Discontinuous Current Mode (DCM) single−pulse PFM,
which produces low output ripple compared with other PFM
architectures. Transition between PWM and PFM is
relatively seamless, providing a smooth transition between
DCM and CCM Modes.
PFM can be disabled by programming the MODE bits in
the CONTROL register in combination with the state of the
VSEL pin. See table in the Control Register, 02h.
The FAN53526 is a step−down switching voltage
regulator that delivers a programmable output voltage from
an input voltage supply of 2.5 V to 5.5 V. Using a proprietary
architecture with synchronous rectification, the FAN53526
is capable of delivering 3.0 A at over 80% efficiency. The
regulator operates at a nominal frequency of 2.4 MHz at full
load, which reduces the value of the external components to
330 nH or 470 nH for the output inductor and 44 μF for the
output capacitor. High efficiency is maintained at light load
with single−pulse PFM.
An I2C−compatible interface allows transfers up to
3.4 Mbps. This communication interface can be used to:
• Dynamically re−program the output voltage in 6.25 mV
increments;
• Reprogram the mode to enable or disable PFM;
• Control voltage transition slew rate; or
• Enable / disable the regulator.
Enable and Soft−Start
When the EN pin is LOW; the IC is shut down, all internal
circuits are off, and the part draws very little current. In this
state, I2C can be written to or read from as long as input
voltage is above the UVLO. The registers keep the content
when the EN pin is LOW. The registers are reset to default
values during a Power On Reset (POR). When the
OUTPUT_DISCHARGE bit in the Control register is
enabled (logic HIGH) and the EN pin is LOW or the
BUCK_ENx bit is LOW, an 11 W load is connected from
VOUT to GND to discharge the output capacitors.
Raising EN while the BUCK_ENx bit is HIGH activates
the part and begins the soft−start cycle. During soft−start, the
modulator’s internal reference is ramped slowly to minimize
surge currents on the input and prevent overshoot of the
output voltage. Synchronous rectification is inhibited,
allowing the IC to start into a pre−charged capacitive load.
If large values of output capacitance are used, the
regulator may fail to start. The maximum COUT capacitance
for starting with a heavy constant−current load is
approximately:
Control Scheme
The FAN53526 uses a proprietary non−linear,
fixed−frequency PWM modulator to deliver a fast load
transient response, while maintaining a constant switching
frequency over a wide range of operating conditions. The
regulator performance is independent of the output
capacitor ESR, allowing for the use of ceramic output
capacitors. Although this type of operation normally results
in a switching frequency that varies with input voltage and
load current, an internal frequency loop holds the switching
frequency constant over a large range of input voltages and
load currents.
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11
FAN53526
C OUTMAX [ (I LMPK * I LOAD) @
320m
tri−state before reattempting soft−start 1700 ms later. This
limits the duty cycle of full output current during soft−start
to prevent excessive heating.
The IC allows for software enable of the regulator, when
EN is HIGH, through the BUCK_EN bits. BUCK_EN0 and
BUCK_EN1 are both initialized HIGH. These options start
after a POR, regardless of the state of the VSEL pin.
(eq. 1)
V OUT
where COUTMAX is expressed in μF and ILOAD is the
load current during soft−start, expressed in A.
If the regulator is at its current limit for 16 consecutive
current limit cycles, the regulator shuts down and enters
Table 10. HARDWARE AND SOFTWARE ENABLE
Pins
BITS
EN
VSEL
BUCK_EN0
BUCK_EN1
Output
Mode
0
X
X
X
OFF
Shutdown
1
0
0
X
OFF
Shutdown
1
0
1
X
ON
Auto
1
1
X
0
OFF
Shutdown
1
1
X
1
ON
FPWM
VSEL Pin and I2C Programming Output Voltage
VSEL0 and VSEL HIGH corresponds to VSEL1. Upon
POR, VSEL0 and VSEL1 are reset to their default voltages,
as shown in Table 8.
The output voltage is set by the NSELx control bits in
VSEL0 and VSEL1 registers. The output is given as:
V OUT + 0.600V ) NSELx @ 6.25mV
(eq. 2)
For example, if NSEL =1010000 (80 decimal), then VOUT
= 0.600 + 0.5 = 1.100 V.
Output voltage can also be controlled by toggling the
VSEL pin LOW or HIGH. VSEL LOW corresponds to
Transition Slew Rate Limiting
When transitioning from a low to high voltage, the IC can
be programmed for one of eight possible slew rates using the
SLEW bits in the Control register, as shown in Table 5.
Table 11. TRANSITION SLEW RATE
Decimal
Bin
Slew Rate
0
000
64.00
mV/ms
1
001
32.00
mV/ms
2
010
16.00
mV/ms
3
011
8.00
mV/ms
4
100
4.00
mV/ms
5
101
2.00
mV/ms
6
110
1.00
mV/ms
7
111
0.50
mV/ms
Input Over−Voltage Protection (OVP)
Transitions from high to low voltage rely on the output
load to discharge VOUT to the new set point. Once the
high−to−low transition begins, the IC stops switching until
VOUT has reached the new set point.
When VIN exceeds VSDWN (~ 6.2 V), the IC stops
switching to protect the circuitry from internal spikes above
6.5 V. An internal filter prevents the circuit from shutting
down due to noise spikes.
Under−Voltage Lockout (UVLO)
Current Limiting
When EN is HIGH, the under−voltage lockout keeps the
part from operating until the input supply voltage rises
HIGH enough to properly operate. This ensures proper
operation of the regulator during startup or shutdown.
A heavy load or short circuit on the output causes the
current in the inductor to increase until a maximum current
threshold is reached in the high−side switch. Upon reaching
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12
FAN53526
I2C Interface
this point, the high−side switch turns off, preventing high
currents from causing damage. 16 consecutive current limit
cycles in current limit, cause the regulator to shut down and
stay off for about 1700 ms before attempting a restart.
The serial interface is compatible with Standard, Fast,
Fast Plus, and HS Mode I2C BusR specifications. The SCL
line is an input and its SDA line is a bi−directional
open−drain output; it can only pull down the bus when
active. The SDA line only pulls LOW during data reads and
when signaling ACK. All data is shifted in MSB (bit 7) first.
Thermal Shutdown
When the die temperature increases, due to a high load
condition and/or high ambient temperature, the output
switching is disabled until the die temperature falls
sufficiently. The junction temperature at which the thermal
shutdown activates is nominally 150°C with a 17°C
hysteresis.
I2C Slave Address
In hex notation, the slave address assumes a 0 LS Bit. The
hex slave address is C0 for all options except
FAN53526UC168X, which has a hex slave address of C2.
Monitor Register (Reg05)
The Monitor register indicates of the regulation state of
the IC. If the IC is enabled and is regulating, its value is
(1000 0001).
Table 12. I2C SLAVE ADDRESS
Bits
Hex
7
6
5
4
3
2
1
C0
1
1
0
0
0
0
0
C2
1
1
0
0
0
0
1
Other slave addresses can be assigned. Contact an On
Semiconductor representative.
SDA
Bus Timing
tHD;STA
0
Slave Address
MS Bit
SCL
As shown in Figure 18 data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow sufficient time for the data to set up before
the next SCL rising edge.
Figure 19. START Bit
A transaction ends with a STOP condition, defined as
SDA transitioning from 0 to 1 with SCL high, as shown in
Figure 20.
Data change allowed
Slave Releases
SDA
SDA
tH
SCL
Master Drives
tHD;STO
ACK(0) or
NACK(1)
SCL
tSU
Figure 20. STOP Bit
During a read from the FAN53526, the master issues a
REPEATED START after sending the register address and
before resending the slave address. The REPEATED
START is a 1 to 0 transition on SDA while SCL is HIGH, as
shown in Figure 21.
Figure 18. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
is defined as SDA transitioning from 1 to 0 with SCL HIGH,
as shown in Figure 19.
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13
FAN53526
Slave Releases
tSU;STA
SDA
The master generates a REPEATED START condition
(Figure 21) that causes all slaves on the bus to switch to HS
Mode. The master then sends I2C packets, as described
above, using the HS Mode clock rate and timing.
The bus remains in HS Mode until a STOP bit (Figure 20)
is sent by the master. While in HS Mode, packets are
separated by REPEATED START conditions (Figure 21).
tHD;STA
ACK(0) or
NACK(1)
SLADDR
MS Bit
SCL
Figure 21. REPEATED START Timing
High−Speed (HS) Mode
Read and Write Transactions
The protocols for High−Speed (HS), Low−Speed (LS),
and Fast−Speed (FS) Modes are identical; except the bus
speed for HS Mode is 3.4 MHz. HS Mode is entered when
the bus master sends the HS master code 00001XXX after
a START condition (Figure 19). The master code is sent in
Fast or Fast−Plus Mode (less than 1 MHz clock); slaves do
not ACK this transmission.
The following figures outline the sequences for data read
and write. Bus control is signified by the shading of the
packet, defined as:
•
•
Master Drives Bus
and
Slave Drives Bus
All addresses and data are MSB first.
Table 13. I2C BIT DEFINITIONS FOR FIGURE 22 AND FIGURE 23
Symbol
Definition
S
START, see Figure 19
P
STOP, see Figure 20
R
REPEATED START, see Figure 21
A
ACK. The slave drives SDA to 0 acknowledge the preceding packet.
A
NACK. The slave sends a 1 to NACK the preceding packet.
7 bits
S
Slave Address
0
0
8 bits
0
8 bits
0
A
Reg Addr
A
Data
A
P
Figure 22. Write Transaction
7 bits
S
Slave Address
0
0
8 bits
0
A
Reg Addr
A
7 bits
R
Slave Address
1
0
8 bits
1
A
Data
A
Figure 23. Write Transaction Followed by a Read Transaction
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P
FAN53526
REGISTER DESCRIPTION
Table 14. REGISTER MAP
Hex
Address
Name
00
VSEL0
01
VSEL1
02
CONTROL
03
Function
Binary
Hex
Controls VOUT settings when VSEL pin = LOW
1XXXXXXX
XX
Controls VOUT settings when VSEL pin = HIGH
1XXXXXXX
XX
Determines whether VOUT output discharge is enabled and also the slew rate
of positive transitions
10000010
82
ID1
Read−only register identifies vendor and chip type
10000001
81
04
ID2
Read−only register identifies die revision
00001000
08
05
MONITOR
Indicates device status
00000000
00
Table 15. BIT DEFINITIONS
Bit
Name
Type
Value
VSEL0
Register Address: 00
Software buck enable. When EN pin is LOW, the regulator is
off. When EN pin is HIGH, BUCK_EN bit takes precedent.
7
BUCK_EN0
R/W
1
6:0
NSEL0
R/W
XXX XXXX
VSEL1
Sets VOUT value from 0.600 to 1.39375 V (see Eq.2).
Register Address: 01
Software buck enable. When EN pin is LOW, the regulator is
off. When EN pin is HIGH, BUCK_EN bit takes precedent.
7
BUCK_EN1
R/W
1
6:0
NSEL1
R/W
XXX XXXX
CONTROL
Sets VOUT value from 0.600 to 1.39375 V (see Eq.).
Register Address: 02
0
When the regulator is disabled, VOUT is not discharged.
When the regulator is disabled, VOUT discharges through an
internal pull−down.
7
OUTPUT_ DISCHARGE
R/W
1
6:4
SLEW
R/W
000 –111
3
Reserved
2
RESET
1:0
Description
MODE
R/W
R/W
Sets the slew rate for positive voltage transitions (see Table 4)
0
Always reads back 0.
0
Setting to 1 resets all registers to default values. Always reads
back 0.
In combination with the VSEL pin, these two bits set the operation of the buck to be either in Auto−PFM/PWM Mode during
light load or Forced PWM mode. See table below.
Mode of Operation
VSEL Pin Binary Operation
10
Low
Low
High
High
ID1
X0
X1
0X
1X
Auto PFM/PWM
Forced PWM
Auto PFM/PWM
Forced PWM
Register Address: 03
7:5
VENDOR
R
100
Signifies On Semiconductor as the IC vendor.
4
Reserved
R
0
3:0
DIE_ID
R
0001
Always reads back 0.
ID2
DIE ID − FAN53525/6.
Register Address: 04
7:4
Reserved
R
0000
Always reads back 0000.
3:0
DIE_REV
R
1000
FAN53526 Die Revision
MONITOR
7
Register Address: 05
PGOOD
R
1: Buck is enabled and soft−start is completed.
0
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15
FAN53526
Table 15. BIT DEFINITIONS
Bit
Name
Type
Value
Description
6
UVLO
R
0
1: Signifies the VIN is less than the UVLO threshold.
5
OVP
R
0
1: Signifies the VIN is greater than the OVP threshold.
4
POS
R
0
1: Signifies a positive voltage transition is in progress and the
output voltage has not yet reached its new setpoint.
3
NEG
R
0
1: Signifies a negative voltage transition is in progress and the
output voltage has not yet reached its new setpoint.
2
RESET−STAT
R
0
1: Indicates that a register reset was performed. This bit is
cleared after register 5 is read.
1
OT
R
0
1: Signifies the VIN is less than the UVLO threshold.
0
BUCK_STATUS
R
0
1: Signifies the VIN is greater than the OVP threshold.
APPLICATION INFORMATION
Selecting the Inductor
size typically decreases the DCR; but since ΔI increases, the
RMS current increases, as do core and skin−effect losses:
The output inductor must meet both the required
inductance and the energy−handling capability of the
application. The inductor value affects the average current
limit, the output voltage ripple, and the efficiency.
The ripple current (ΔI) of the regulator is:
DI [
V OUT
V IN
@
ǒ
V IN*V OUT
L @ f SW
Ǔ
I RMS +
DI
2
OUT(DC)
2
)
DI 2
12
(eq. 5)
The increased RMS current produces higher losses
through the RDS(ON) of the IC MOSFETs and the inductor
ESR.
Increasing the inductor value produces lower RMS
currents, but degrades transient response. For a given
physical inductor size, increased inductance usually results
in an inductor with lower saturation current.
The increased RMS current produces higher losses
through the RDS(ON) of the IC MOSFETs and the inductor
ESR.
Increasing the inductor value produces lower RMS
currents, but degrades transient response. For a given
physical inductor size, increased inductance usually results
in an inductor with lower saturation current.
(eq. 3)
The maximum average load current, IMAX(LOAD), is
related to the peak current limit, ILIM(PK), by the ripple
current such that:
I MAX(LOAD) + I LIM(PK)*
ǸI
(eq. 4)
The FAN53526 is optimized for operation with
L=330 nH, but is stable with inductances up to 1.0 μH
(nominal). The inductor should be rated to maintain at least
80% of its value at ILIM(PK). Failure to do so decreases the
amount of DC current the IC can deliver.
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
Table 16. EFFECTS OF INDUCTOR VALUE (FROM 330NH RECOMMENDED) ON REGULATOR
PERFORMANCE
IMAX(LOAD)
DVOUT(Eq.(7))
Transient Response
Increase
Decrease
Degraded
Inductor Current Rating
Output Capacitor and VOUT Ripple
The current-limit circuit can allow substantial peak
currents to flow through L1 under worst−case conditions. If
it is possible for the load to draw such currents, the inductor
should be capable of sustaining the current or failing in a safe
manner.
For space−constrained applications, a lower current rating
for L1 can be used. The FAN53526 may still protect these
inductors in the event of a short circuit, but may not be able
to protect the inductor from failure if the load is able to draw
higher currents than the DC rating of the inductor. Refer to
Table 2 for the recommended inductors.
If space is at a premium, 0603 capacitors may be used.
Increasing COUT has negligible effect on loop stability
and can be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, DVOUT,
is calculated by:
DV OUT + DI L
ƪ
f SW @ C OUT @ ESR 2
2 @ D @ (1 * D)
)
1
8 @ f SW @ C OUT
ƫ
where COUT is the effective output capacitance.
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16
(eq. 6)
FAN53526
copper weight, and trace width) and the temperature rise
from junction to ambient (ΔT).
For the FAN53526, θJA is 42°C/W when mounted on its
four−layer with vias evaluation board in still air with 2 oz.
outer layer copper weight and 1 oz. inner layer.
For long−term reliable operation, the junction
temperature (TJ) should be maintained below 125°C.
To calculate maximum operating temperature (<125°C)
for a specific application:
1. Use efficiency graphs to determine efficiency for
the desired VIN, VOUT, and load conditions.
2. Calculate total power dissipation using:
The capacitance of COUT decreases at higher output
voltages, which results in higher DVOUT. Equation 6 is only
valid for CCM operation, which occurs in PWM Mode.
The FAN53526 can be used with either 2 x 22 mF (0603)
or 2 x 47 mF (0603) output capacitor configuration. If a
tighter ripple and transient specification is need from the
FAN53526, then the 2 x 47 mF is recommended.
The lowest DVOUT is obtained when the IC is in PWM
Mode and, therefore, operating at 2.4 MHz. In PFM Mode,
fSW is reduced, causing DVOUT to increase.
ESL Effects
The Equivalent Series Inductance (ESL) of the output
capacitor network should be kept low to minimize the
square−wave component of output ripple that results from
the division ratio COUT ESL and the output inductor (LOUT).
The square−wave component due to the ESL can be
estimated as:
DV OUT(SQ) [ V IN @
ESL COUT
L1
ǒ
1
P T + V OUT @ I LOAD @ h * 1
Ǔ
(eq. 8)
3. Estimate inductor copper losses using:
2
P L + I LOAD @ DCR L
(eq. 9)
4. Determine IC losses by removing inductor losses
(step 3) from total dissipation:
P IC + P T * P L
(eq. 7)
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired COUT value. For
example, to obtain COUT=20 mF, a single 22 mF 0805 would
produce twice the square wave ripple as two x 10 F 0805.
To minimize ESL, try to use capacitors with the lowest
ratio of length to width. 0805 s have lower ESL than 1206 s.
If low output ripple is a chief concern, some vendors
produce 0508 capacitors with ultra−low ESL. Placing
additional small−value capacitors near the load also reduces
the high−frequency ripple components.
(eq. 10)
5. Determine device operating temperature:
DT + P IC @ Q JA
T IC + T A ) DT
(eq. 11)
and
Note that the RDS(ON) of the power MOSFETs increases
linearly with temperature at about 1.4%/°C. This causes the
efficiency (η) to degrade with increasing die temperature.
Layout Recommendations
1. The input capacitor (CIN) should be connected as
close as possible to the VIN and GND pins.
Connect to VIN and GND using only top metal.
Do not route through via (see Figure 24).
2. Place the inductor (L) as close as possible to the
IC. Use short wide traces for the main current
paths.
3. The output capacitor (COUT) should be as close as
possible to the IC. Connection to GND should
only be on top metal. Feedback signal connection
to VOUT should be routed away from noisy
components and traces (e.g. SW line)
(see Figure 26).
Input Capacitor
The ceramic input capacitors should be placed as close as
possible between the VIN and PGND pins to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or
tantalum) should be placed between CIN and the power
source lead to reduce under−damped ringing that can occur
between the inductance of the power source leads and CIN.
Thermal Considerations
Heat is removed from the IC through the solder bumps to
the PCB copper. The junction−to−ambient thermal
resistance (θJA) is largely a function of the PCB layout (size,
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17
FAN53526
Figure 24. Guidance for Layer 1
Figure 25. Layer 2
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18
FAN53526
Figure 26. Layer 3
Figure 27. Layer 4
Table 17. PRODUCT−SPECIFIC DIMENSIONS
D
E
X
Y
2.015 0 ± 03 mm
1.310 ± 0.03 mm
0.255 mm
0.2075 mm
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19
FAN53526
PVIN
EN
SDA
SCL
VSEL
CIN
CIN1
1. FB trace connects to “+” side of COUT cap.
2. Do not place COUT near FAN53526, place COUT near load.
VOUT
FAN53526
FAN5352
6
L1
SW
COUT
C
PGND
AGND
VDO
Core
Processor
(System Load)
GND
3. Maximum trace resistance between the inductor and the load should not exceed 30mΩ. For
a 20 mils wide PCB trace with 0.5mils thickness using 2oz. Copper, a length of 0.5 inches
gives a resistance of 24.3mΩ.
Figure 28. Remote Sensing Schematic
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FAN53526
WLCSP15 2.015x1.31x0.586
CASE 567QS
ISSUE O
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21
FAN53526
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FAN53526/D