APW7057 High Power Step-Down Synchronous DC/DC Controller Features General Description • • The APW7057 is a 300kHz constant frequency voltage mode synchronous switching controller that drives exter- Operates from +5V Input 0.8V Internal Reference Voltage nal N-channel MOSFETs. When the input supply drops close to output, the upper MOSFET remains on, achiev- - ±1.5% Accuracy Over Line, Load and Temperature • • ing 100% duty cycle. Internal loop compensation is optimized for fast transient response, eliminating external 0.8V to VCC Output Range compensation network. The precision 0.8V reference makes this part suitable for a wide variety of low voltage Full Duty Cycle Range - 0% to 100% • • applications. Soft-start is internally set to 2ms, limiting the input in-rush current and preventing the output from Internal Loop Compensation overshoot during powering up. The APW 7057 has over current and short circuit Internal Soft-Start - Typical 2ms • • • • • • Programmable Over-Current Protection protections. Over current protection is achieved by monitoring the voltage drop across the high side MOSFET, - Lossless Sensing Using MOSFET RDS (ON) eliminating the need for a current sensing resistor and short circuit condition is detected through the FB pin. If Under-Voltage Protection either fault conditions occur, the APW7057 would initiate the soft-start cycle. After three cycles and if the fault condi- Drives External N-Channel MOSFETs tion persists, the controller will be shut down. To restart the controller, either recycle the VCC supply or momen- Shutdown Control Small SOP-8 Package tarily pull the OSCSET pin below 1.25V. The APW7057 can be shutdown by pulling the OCSET Lead Free and Green Devices Avaliable (RoHS Compliant) pin below 1.25V. In shutdown, both gate drive signals will be low. The controller is available in a small SOP-8 Applications • • • • • • • package. Motherboard Pin Configuration Graphics Cards Cable or DSL Modems, Set Top Boxes DSP Supplies Memory Supplies 5V Input DC-DC Regulators Distributed Power Supplies BOOT 1 8 PHASE UGATE 2 7 OCSET GND 3 6 FB LGATE 4 5 VCC SOP-8 (Top View ) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 1 www.anpec.com.tw APW7057 Ordering and Marking Information Package Code K : SOP-8 Operating Junction Temperature Range APW7057 C : 0 to 70°C Handling Code Assembly Material TR : Tape & Reel Handling Code Temperature Range APW7057 K : Assembly Material L : Lead Free Device G : Halogen and Lead Free Device Package Code APW7057 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VCC VBOOT Parameter Rating Unit VCC Supply Voltage (VCC to GND) -0.3 ~ 7 V BOOT Supply Voltage (BOOT to GND) -0.3 ~ 15 V PHASE, OCSET to GND Input Voltage -0.3 ~ 12 V FB to GND Input Voltage -0.3 ~ VCC+0.3 Maximum Junction Temperature TSTG TSDR Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds V 125 o -65 ~ 150 o 260 o C C C Thermal Characteristics Symbol θJA Parameter Typical Value Junction-to-Ambient Resistance in Free Air Unit o SOP-8 160 C/W Recommended Operating Conditions Symbol VCC VOUT Parameter VCC Supply Voltage Output Voltage of the Switching Regulator VIN Input Voltage of the Switching Regulator TA Ambient Temperature TJ (Note) (Note) Junction Temperature Range Unit 5 ± 5% V 0.8 ~ VCC V 3.3 ~ VCC V 0 ~ 70 o 0 ~ 125 o C C Note : Refer to the typical application circuit Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 2 www.anpec.com.tw APW7057 Electrical Characteristics Unless otherwise specified, these specifications apply over VCC=5V, VBOOT=12V and TA= 0~70 oC. Typical values are at T =25oC. A APW7057 Symbol Parameter Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT IVCC VCC Nominal Supply Current UGATE and LGATE Open - 2.1 - mA IBOOT BOOT Nominal Supply Current UGATE Open - 2.1 - mA Rising VCC Threshold 4.0 4.2 4.4 V Falling VCC Threshold 3.8 4.0 4.2 V 250 300 340 kHz Ramp Upper Threshold - 2.85 - V Ramp Lower Threshold - 0.95 - V Ramp Amplitude - 1.9 - VP-P - 0.8 - V -1.5 - +1.5 % DC Gain - 75 - dB FP First Pole Frequency - 10 - Hz FZ First Zero Frequency - 1 - kHz UGATE Duty Range 0 - 100 % FB Input Current - - 0.1 µA UNDER VOLTAGE LOCKOUT (UVLO) OSCILLATOR FOSC ∆VOSC Free Running Frequency REFERENCE VOLTAGE VREF Reference Voltage Reference Voltage Accuracy ERROR AMPLIFIER PWM CONTROLLER GATE DRIVERS TD UGATE Source VUAGTE=1V - 0.6 - A UGATE Sink VUGATE=1V - 7.3 - Ω LGATE Source VLGATE=1V - 0.6 - A LGATE Sink VLGATE=1V - 1.8 - Ω - 50 - nS 34 40 46 µA - 0.5 - V - 15 - mV Dead Time PROTECTION IOCSET OCSET Sink Current VOCSET=4.5V UVFB FB Under-Voltage Level FB falling FB Under-Voltage Hysteresis Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 3 www.anpec.com.tw APW7057 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC=5V, VBOOT=12V and TA= 0~70 oC. Typical values are at T =25oC. A APW7057 Symbol Parameter Unit Test Conditions Min. Typ. Max. - 2 - mS - 1.25 - V - 20 - mV SOFT-START AND SHUTDOWN TSS Soft-Start Interval Shutdown Threshold VOCSET Falling OCSET Shutdown Hysteresis Function Pin Description BOOT (Pin 1) OCSET (Pin 7) This pin provides the supply voltage to the high side This pin serves two functions: as a shutdown control and for setting the over current limit threshold. Pulling this pin MOSFET driver. A voltage no greater than 13V can be connected to this pin as a supply to the driver. For driving below 1.25V shuts the controller down, forcing the UGATE and LGATE signals to be at 0V. A soft-start cycle will be logic level N-channel MOSEFT, a bootstrap circuit can be use to create a suitable driver’s supply. initiated upon the release of this pin. A resistor (Rocset) connected between this pin and the drain UGATE (Pin 2) of the high side MOSFET will determine the over current limit. An internally generated 40µA current source will flow This pin provides gate drive for the high-side MOSFET. through this resistor, creating a voltage drop. This voltage will be compared with the voltage across the high GND (Pin 3) Signal and power ground for the IC. All voltage levels are side MOSFET. The threshold of the over current limit is therefore given by: measured with respect to this pin. Tie this pin to the ground plane through the lowest impedance connection available. IOI = LGATE (Pin 4) This pin provides the gate drive signal for the low side MOSFET. 40uA x ROCSET RDS(ON) An over current condition will cycle the soft-start function. After three consecutive cycles and if the fault condition VCC (Pin 5) persists, the controller will be shut down. To restart the controller, either recycle the VCC supply or momentarily This is the main bias supply for the controller and its low side MOSFET driver. Must be closely decoupled to GND (Pin 3). DO NOT apply a voltage greater than 5.5V to this pull the OSCSET pin below 1.25V. pin. PHASE (Pin 8) This pin is connected to the source of the high-side FB (Pin 6) This pin is the inverting input of the error amplifier and it receives the feedback voltage from an external resistive MOSFET and is used to monitor the voltage drop across the high-side MOSFET for over-current protection. divider across the output (VOUT). The output voltage is determined by: VOUT = 0.8V(1+ ROUT ) RGND where ROUT is the resistor connected between VOUT and FB while RGND is the resistor connected from FB to GND. Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 4 www.anpec.com.tw APW7057 Block Diagram VCC BOOT Shutdown UnderVoltage Lockout OC Comparator UVLO Soft-Start and Fault Logic 0.5V OCSET IOCSET 40µA OCP PHASE UVP UGATE Inhibit Soft-Start PWM -+ FB VREF Gate Control COMP Error Amplifier VCC + - LGATE 0.8V Oscillator FOSC GND 300kHz Figure 1. Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 5 www.anpec.com.tw APW7057 Typical Application Circuit R3 C3 1uF 5 R4 8.2k C7 470pF BOOT UGATE Shutdown PHASE 6 U1 APW7057 LGATE FB C1 1uF + +5V C2 1000uF x2 1 OCSET Q3 VIN D1 1N4148 VCC 7 2.2 2 C4 0.1uF Q1 L1 3.3uH 8 VOUT + 4 +2.5V/10A C5 1000uF x2 Q2 GND R1 5.1k 3 R2 2.4k C6 0.1uF Q1: APM2014N UC Q2: APM2014N UC Q3: 2N7002 C2: 1000uF/10V, ESR = 25m Ω C5: 1000uF/6.3V, ESR = 25m Ω Figure 2. Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 6 www.anpec.com.tw APW7057 Typical Operating Characteristics Switching Frequency vs. Junction Temperature Reference Voltage vs. Junction Temperature 350 0.812 Switching Frequency, FOSC (kHz) Reference Voltage, VREF (V) 340 0.808 0.804 0.800 0.796 0.792 330 320 310 300 290 280 270 260 250 0.788 -50 -25 0 25 50 75 100 125 -50 150 -25 0 25 50 75 100 125 150 Junction Temperature (°C) Junction Temperature (oC) OCSET Current vs. Junction Temperature 46 OCSET Current , IOCSET (µA) 45 44 43 42 41 40 39 38 37 36 35 34 -50 -25 0 25 50 75 100 125 150 Junction Temperature (oC) Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 7 www.anpec.com.tw APW7057 Operating Waveforms (Refer to the typical application circuit) 1. Load Transient Response : IOUT = 0A -> 10A -> 0A - IOUT slew rate = ±10A/µS IOUT = 0A -> 10A IOUT = 10A -> 0A IOUT = 0A -> 10A -> 0A VOUT VOUT VOUT VUGATE VUGATE 10A IOUT Ch1 : VOUT, 100mV/Div, DC, Offset = 2.50V Ch2 : VUGATE, 10V/Div, DC Ax1 : IOUT, 5A/Div Time : 10µS/Div BW = 20MHz IOUT IOUT 0A Ch1 : VOUT, 100mV/Div, DC, Offset = 2.50V Ax1 : IOUT, 5A/Div Time : 100µS/Div BW = 20MHz Ch1 : VOUT, 100mV/Div, DC, Offset = 2.50V Ch2 : VUGATE, 10V/Div, DC Ax1 : IOUT, 5A/Div Time : 10µS/Div BW = 20MHz 2. UGATE and LGATE UGATE Rising UGATE Falling IOUT=10A IOUT=10A VUGATE VUGATE VLGATE Ch1 : VUGATE, 2V/Div, DC Time : 125nS/Div VLGATE Ch2 : VLGATE, 2V/Div, DC BW = 500MHz Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 Ch1 : VUGATE, 2V/Div, DC Time : 125nS/Div 8 Ch2 : VLGATE, 2V/Div, DC BW = 500MHz www.anpec.com.tw APW7057 Operating Waveforms (Cont.) (Refer to the typical application circuit) 3. Powering ON / OFF Soft-Start at Powering ON Ch1 : VIN, 2V/Div, DC Time : 1mS/Div Powering OFF VIN VIN VOUT VOUT Ch1 : VIN, 2V/Div, DC Time : 5mS/Div Ch2 : VOUT, 1V/Div, DC BW = 20MHz Ch2 : VOUT, 1V/Div, DC BW = 20MHz 4. Short-Circuit Protection Under-Voltage (UVP) UVP and Over-Current Protection (OCP) OCP OCP VOUT Ch1 : VOUT, 1V/Div, DC Ax1 : IOUT, 10A/Div Time : 1mS/Div BW = 20MHz IOUT Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 9 www.anpec.com.tw APW7057 Application Information Component Selection Guidelines The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple Output Capacitor Selection current to be approximately 30% of the maximum output current. The selection of COUT is determined by the required effective series resistance (ESR) and voltage rating rather than the actual capacitance requirement. Therefore, select high Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak cur- performance low ESR capacitors that are intended for switching regulator applications. In some applications, rent without going into saturation. In some types of inductors, especially core that is make of ferrite, the ripple multiple capacitors have to be paralled to achieve the desired ESR value. If tantalum capacitors are used, make current will increase abruptly when it saturates. This will result in a larger output ripple voltage. sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. MOSFET Selection Input Capacitor Selection The selection of the N-channel power MOSFETs are de- The input capacitor is chosen based on the voltage rating termined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum output current requirement.The losses in and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher the MOSFETs have two components: conduction loss and transition loss. For the upper and lower MOSFET, the than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2 , where losses are approximately given by the following equations: IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. If tanta- PUPPER = Iout (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS lum capacitors are used, make sure they are surge tested PLOWER = Iout (1+ TC)(RDS(ON))(1-D) 2 2 by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor be- where IOUT is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tween 0.1µF to 1µF can be connected between VCC and ground pin. tsw is the switching interval D is the duty cycle Inductor Selection The inductance of the inductor is determined by the output voltage requirement. The larger the inductance, the Note that both MOSFETs have conduction losses while the upper MOSFET includes an additional transition loss. lower the inductor’s current ripple. This will translate into lower output ripple voltage. The ripple current and ripple The switching internal, tsw, is the function of the reverse transfer capacitance CRSS. Figure 3 illustrates the switch- voltage can be approximated by: ing waveform internal of the MOSFET. IRIPPLE = VIN - VOUT Fs x L x V OUT VIN Layout Consideration In high power switching regulator, a correct layout is im- ∆VOUT = IRIPPLE x ESR portant to ensure proper operation of the regulator. In general, interconnecting impedances should be mini- where Fs is the switching frequency of the regulator. There is a tradeoff exists between the inductor’s ripple mized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally current and the regulator load transient response time. A smaller inductor will give the regulator a faster load tran- combined using ground plane construction or single point grounding. Figure 4 illustrates the layout, with bold lines sient response at the expense of higher ripple current and vice versa. indicating high current paths. Components along the bold lines should be placed close together. Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 10 www.anpec.com.tw APW7057 Application Information Layout Consideration (Cont.) Below is a checklist for your layout: C HF • Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep VCC traces to these nodes as short as possible. BOOT • Decoupling capacitor CIN provides the bulk capacitance and needs to be placed close to the IC since it will provide the MOSFET drivers transient current LGATE 5 1 VIN CIN + 4 APW7057 requirement. • The ground return of CIN must return to the combine COUT (-) terminal. • Capacitor CBOOT should be connected as close to the U 1 UGATE 2 PHASE 8 Q1 Q2 + L1 COUT VOUT Figure 4. Recommended Layout Diagram BOOT and PHASE pins as possible. • Capacitor CHF is to improve noise performance and a small 1µF ceramic capacitor will be sufficient. Voltage across drain and source of MOSFET V DS t sw Time Figure 3. Switching waveform across MOSFET Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 11 www.anpec.com.tw APW7057 Package Information SOP-8 D E E1 SEE VIEW A h X 45 ° c A 0.25 b GAUGE PLANE SEATING PLANE A1 A2 e L VIEW A S Y M B O L SOP-8 MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 1.75 0.069 0.004 0.25 0.010 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e 0.049 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0° 8° 0° 8° Note: 1. Follow JEDEC MS-012 AA. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 12 www.anpec.com.tw APW7057 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 A H 330.0± 2.00 50 MIN. P0 P1 P2 D0 D1 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. Application SOP-8 T1 C d D W E1 12.4+2.00 13.0+0.50 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 -0.00 -0.20 T A0 B0 F 5.5±0.05 K0 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 (mm) Devices Per Unit Package Type Unit Quantity SOP-8 Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 13 www.anpec.com.tw APW7057 Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat t 25°C to Peak 25 Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 14 www.anpec.com.tw APW7057 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 Package Thickness Volume mm <350 <2.5 mm 240 +0/-5°C ≥2.5 mm 225 +0/-5°C 3 Volume mm ≥350 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2008 15 www.anpec.com.tw