Hitachi HM658512ALRR-8 4 m psram (512-kword x 8-bit) 2 k refresh Datasheet

HM658512A Series
4 M PSRAM (512-kword × 8-bit)
2 k Refresh
ADE-203-218C(Z)
Rev. 3.0
Nov. 1997
Description
The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword × 8-bit. It realizes higher
density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process
technology.
It offers low power data retention by self refresh mode. It also offers easy non multiplexed address
interface and easy refresh functions. HM658512A is suitable for handy systems which work with battery
back-up systems.
The device is packaged in a small 525-mil SOP (460-mil body SOP) or a 8 × 20 mm TSOP with thickness
of 1.2 mm, or a 600-mil plastic DIP. High density custom cards made of Tape Carrier Packages are also
available.
Features
• Single 5 V (±10%)
• High speed
 Access time
CE access time: 70/80/100 ns (max)
 Cycle time
Random read/write cycle time:
115/130/160 ns (min)
• Low power
 Active: 250 mW (typ)
 Standby: 200 µW (typ)
• Directly TTL compatible
All inputs and outputs
• Simple address configuration
Non multiplexed address
• Refresh cycle
 2048 refresh cycles: 32 ms
HM658512A Series
• Easy refresh functions
Address refresh
Automatic refresh
Self refresh
Ordering Information
Type No.
Access time
Package
HM658512ALP-7
HM658512ALP-8
HM658512ALP-10
70 ns
80 ns
100 ns
600-mil 32-pin plastic DIP (DP-32)
HM658512ALP-7V
HM658512ALP-8V
HM658512ALP-10V
70 ns
80 ns
100 ns
HM658512ALFP-7
HM658512ALFP-8
HM658512ALFP-10
70 ns
80 ns
100 ns
HM658512ALFP-7V
HM658512ALFP-8V
HM658512ALFP-10V
70 ns
80 ns
100 ns
HM658512ALTT-7
HM658512ALTT-8
HM658512ALTT-10
70 ns
80 ns
100 ns
HM658512ALTT-7V
HM658512ALTT-8V
HM658512ALTT-10V
70 ns
80 ns
100 ns
HM658512ALRR-7
HM658512ALRR-8
HM658512ALRR-10
70 ns
80 ns
100 ns
HM658512ALRR-7V
HM658512ALRR-8V
HM658512ALRR-10V
70 ns
80 ns
100 ns
2
525-mil 32-pin plastic SOP (FP-32D)
400-mil 32-pin plastic TSOP (TTP-32D)
400-mil 32-pin plastic TSOP (TTP-32DR)
HM658512A Series
Pin Arrangement
HM658512ALP/ALFP Series
A18
1
32
VCC
A16
2
31
A15
A14
3
30
A17
A12
4
29
WE
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE/RFSH
A2
10
23
A10
A1
11
22
CE
A0
12
21
I/O7
I/O0
13
20
I/O6
I/O1
14
19
I/O5
I/O2
15
18
I/O4
VSS
16
17
I/O3
(Top view)
HM658512ALTT Series
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE/RFSH
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
(Top view)
3
HM658512A Series
Pin Arrangement (cont.)
HM658512ALRR Series
VCC
A15
A17
WE
A13
A8
A9
A11
OE/RFSH
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top view)
Pin Description
Pin name
Function
A0 to A18
Address
I/O0 to I/O7
Input/Output
CE
Chip enable
OE/RFSH
Output enable/Refresh
WE
Write enable
VCC
Power supply
VSS
Ground
4
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
HM658512A Series
Block Diagram
A0
Address
Latch
Control
Row
Decoder
Memory Matrix
(2048 × 256) × 8
A10
Column I/O
Input
Data
Control
I/O 0
I/O 7
Column Decoder
Address Latch Control
A11
A18
Refresh
Control
CE
OE/RFSH
WE
Timing Pulse Gen.
Read Write Control
5
HM658512A Series
Pin Functions
CE: Chip Enable (Input)
CE is a basic clock. RAM is active when CE is low, and is on standby when CE is high.
A0 to A18: Address Inputs (Input)
A0 to A10 are row addresses and A11 to A18 are column addresses. The entire addresses A0 to A18
are fetched into RAM by the falling edge of CE.
OE/RFSH: Output Enable/Refresh (Input)
This pin has two functions. Basically it works as OE when CE is low, and as RFSH when CE is high
(in standby mode). After a read or write cycle finishes, refresh does not start if CE goes high while
OE/RFSH is held low. In order to start a refresh in standby mode, OE/RFSH must go high to reset the
refresh circuits of the RAM. After the refresh circuits are reset, the refresh starts when OE/RFSH goes
low.
I/O0 to I/O7: Input/Output (Inputs and Outputs) These pins are data I/O pins.
WE: Write Enable (Input)
RAM is in write mode when WE is low, and is in read mode when WE is high. I/O data is fetched into
RAM by the rising edge of WE or CE (earlier timing) and the data is written into memory cells.
Refresh
There are three refresh modes : address refresh, automatic refresh and self refresh.
(1) Address refresh: Data is refreshed by accessing all 2048 row addresses every 32 ms. A read is one
method of accessing those addresses. Each row address (2048 addresses of A0 to A10)must be read at
least once every 32 ms. In address refresh mode, OE/RFSH can remain high. In this case, the I/O pins
remain at high impedance, but the refresh is done within RAM.
(2) Automatic refresh: Instead of address refresh, automatic refresh can be used. RAM goes to automatic
refresh mode if OE/RFSH falls while CE is high and it remains low for at least tFAP. One automatic
refresh cycle is executed by one low pulse of OE/RFSH. It is not necessary to input the refresh
address from outside since it is generated internally by an on-chip address counter. 2048 automatic
refresh cycles must be done every 32 ms.
(3) Self refresh: Self refresh mode is suitable for data retention by battery. In standby mode, a self refresh
starts automatically when OE/RFSH stays low for more than 8 µs. Refresh addresses are automatically
specified by the on-chip address counter, and the refresh period is determined by the on-chip timer.
Automatic refresh and self refresh are distinguished from each other by the width of the OE/RFSH low
pulse in standby mode. If the OE/RFSH low pulse is wider than 8 µs, RAM becomes into self refresh
mode; if the OE/RFSH low pulse is less than 8 µs, it is recognized as an automatic refresh instruction.
6
HM658512A Series
At the end of self refresh, refresh reset time (tRFS) is required to reset the internal self refresh operation of
the RAM. During tRFS, CE and OE/RFSH must be kept high. If auto refresh follows self refresh, low
transition of OE/RFSH at the beginning of automatic refresh must not occur during tRFS period.
Notes on Using the HM658512A
Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive
than conventional SRAM’s.
(1) If a short CE pulse of a width less than tCE min is applied to RAM, an incomplete read occurs and
stored data may be destroyed. Make sure that CE low pulses of less than tCE min are inhibited. Note
that a 10 ns CE low pulse may sometimes occur owing to the gate delay on the board if the CE signal is
generated by the decoding of higher address signals on the board. Avoid these short pulses.
(2) OE/RFSH works as refresh control in standby mode. A short OE/RFSH low pulse may cause an
incomplete refresh that will destroy data. Make sure that OE/RFSH low pulse of less than tFAP min are
also inhibited.
(3) tOHC and tOCD are the timing specs which distinguish the OE function of OE/RFSH from the RFSH
function. The t OHC and tOCD specs must be strictly maintained.
(4) Start the HM658512A operating by executing at least eight initial cycles (dummy cycles) at least 100
µs after the power voltage reaches 4.5 V-5.5 V after power-on.
Function Table
CE
OE/RFSH
WE
I/O pin
Mode
L
L
H
Dout
Read
L
X
L
High-Z
Write
L
H
H
High-Z
—
H
L
X
High-Z
Refresh
H
H
X
High-Z
Standby
Note: X means H or L.
7
HM658512A Series
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Terminal voltage with respect to V SS
VT
–1.0 to +7.0
V
1
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Storage temperature under bias
Tbias
–10 to +85
°C
Note:
1. With respect to V SS
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
VIH
2.4
—
6.0
V
VIL
–1.0
—
0.8
V
Input voltage
Note:
8
1. VIL min = –3.0 V for pulse width 30 ns
Notes
1
HM658512A Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10 %, VSS = 0 V)
Parameter
Symbol Min Typ
Max Unit Test conditions
Notes
Operating power supply current I CC1
—
—
75
mA
I I/O = 0 mA
t cyc = min
Standby power supply current
I SB1
—
1
2
mA
CE = VIH , Vin ≥ 0 V
OE/RFSH = VIH
I SB2
—
20
200
µA
CE ≥ VCC – 0.2 V, Vin ≥ 0 V, 1
OE/RFSH ≥ VCC – 0.2 V
100
µA
CE ≥ VCC – 0.2 V, Vin ≥ 0 V, 2
OE/RFSH ≥ VCC – 0.2 V
Operating power supply current I CC2
in self refresh mode
—
1
2
mA
CE = VIH , Vin ≥ 0 V,
OE/RFSH = VIL
I CC3
—
70
200
µA
CE ≥ VCC – 0.2 V, Vin ≥ 0 V, 1
OE/RFSH ≤ 0.2 V
40
100
µA
CE ≥ VCC – 0.2 V, Vin ≥ 0 V, 2
OE/RFSH ≤ 0.2 V
Input leakage current
I LI
–10 —
10
µA
VCC = 5.5 V, Vin = VSS to V CC
Output leakage current
I LO
–10 —
10
µA
OE/RFSH = VIH
VI/O = VSS to V CC
Output voltage
VOL
—
—
0.4
V
I OL = 2.1 mA
VOH
2.4
—
—
V
I OH = –1 mA
Notes: 1. Only for L-version.
2. Only for V-version.
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Typ
Max
Unit
Test conditions
Input capacitance
Cin
—
8
pF
Vin = 0 V
Input /output capacitance
CI/O
—
10
pF
VI/O = 0 V
Note : This parameter is sampled and not 100% tested.
9
HM658512A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
•
•
•
•
•
Input pulse levels: 0.4 V, 2.4 V
Input rise and fall time: 5 ns
Timing measurement level: 0.8 V, 2.2 V
Reference levels: VOH = 2.0 V, VOL = 0.8 V
Output load: 1 TTL Gate and C L (100 pF) (Including scope and jig)
HM658512A
-7
-8
-10
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit
Random read or write cycle time
t RC
115
—
130
—
160
—
ns
Chip enable access time
t CEA
—
70
—
80
—
100
ns
Read-modify- write cycle time
t RWC
160
—
180
—
220
—
ns
Output enable access time
t OEA
—
25
—
30
—
40
ns
Chip disable to output in high-Z
t CHZ
0
25
0
25
0
25
ns
1, 2
Chip enable to output in low-Z
t CLZ
20
—
20
—
20
—
ns
2
Output disable to output in high-Z
t OHZ
—
25
—
25
—
25
ns
1, 2
Output enable to output in low-Z
t OLZ
0
—
0
—
0
—
ns
2
Chip enable pulse width
t CE
70 n
10 µ
80 n
10 µ
100 n 10 µ
s
Chip enable precharge time
tP
35
—
40
—
50
—
ns
Address setup time
t AS
0
—
0
—
0
—
ns
Address hold time
t AH
20
—
20
—
25
—
ns
Read command setup time
t RCS
0
—
0
—
0
—
ns
Read command hold time
t RCH
0
—
0
—
0
—
ns
Write command pulse width
t WP
25
—
25
—
30
—
ns
Chip enable to end of write
t CW
70
—
80
—
100
—
ns
Chip enable to output enable delay t OCD
time
0
—
0
—
0
—
ns
Output enable hold time
0
—
0
—
0
—
ns
10
t OHC
Notes
HM658512A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.) (cont.)
HM658512A
-7
-8
-10
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit
Data in to end of write
t DW
20
—
20
—
25
—
ns
Data in hold time for write
t DH
0
—
0
—
0
—
ns
Output active from end of write
t OW
5
—
5
—
5
—
ns
2
Write to output in high-Z
t WHZ
—
20
—
20
—
25
ns
1, 2
Transition time (rise and fall)
tT
3
50
3
50
3
50
ns
6
Refresh command delay time
t RFD
35
—
40
—
50
—
ns
Refresh precharge time
t FP
35
—
40
—
40
—
ns
Refresh command pulse width for
automatic refresh
t FAP
70 n
8µ
80 n
8µ
80 n
8µ
s
Automatic refresh cycle time
t FC
115
—
130
—
160
—
ns
Refresh command pulse width for
self refresh
t FAS
8
—
8
—
8
—
µs
Refresh reset time from self refresh t RFS
600
—
600
—
600
—
ns
9
Refresh period
—
32
—
32
—
32
ms
2048
cycle
t REF
Notes
Notes: 1. tCHZ, tOHZ , t WHZ are defined as the time at which the output achieves the open circuit condition.
2. tCHZ, tCLZ, tOHZ , t OLZ , t WHZ and tOW are sampled under the condition of tT = 5 ns and not 100% tested.
3. A write occurs during the overlap of low CE and low WE. Write end is defined at the earlier of
WE going high or CE going high.
4. If the CE low transition occurs simultaneously with or from the WE low transition, the output
buffers remain in high impedance state.
5. In write cycle, OE or WE must disable output buffers prior to applying data to the device and at
the end of write cycle data inputs must be floated prior to OE or WE turning on output buffers.
During this period, I/O pins are in the output state, therefore the input signals of opposite phase
to the outputs must not be applied.
6. Transition time t T is measured between V IH (min) and VIL (max). VIH (min) and VIL (max) are
reference levels for measuring timing of input signals.
7. After power-up, pause for more than 100 µs and execute at least 8 initialization cycles.
8. 2048 cycles of burst refresh or the first cycle of distributed automatic refresh must be executed
within 15 µs after self refresh, in order to meet the refresh specification of 32 ms and 2048
cycles.
9. At the end of self refresh, refresh reset time (t RFS) is required to reset the internal self refresh
operation of the RAM. During t RFS, CE and OE/RFSH must be kept high. If automatic refresh
follows self refresh, low transition of OE/RFSH at the beginning of automatic refresh must not
occur during t RFS period.
11
HM658512A Series
Timing Waveform
Read Cycle
t RC
t CE
CE
tP
t AS
Address
A0 to A18
t AH
Valid
t OHC
WE
t CEA
t RCH
t RCS
OE/RFSH
t OEA
t CHZ
t OHZ
t OLZ
Dout
12
Valid data out
HM658512A Series
Write Cycle (1) (OE high)
t RC
t CE
CE
tP
t AS
Address
A0 to A18
t AH
Valid
t CW
t WP
WE
t OCD
OE/RFSH
t DW
t DH
Valid
Data in
Din
t WHZ
t CLZ
t OLZ
t OHZ
t OW
Dout
13
HM658512A Series
Write Cycle (2) (OE low)
t RC
t CE
CE
tP
t AS
Address
A0 to A18
t AH
Valid
t DH
t CW
t WP
WE
t OHC
OE/RFSH
t DW
Valid data in
Din
t WHZ
t CLZ
Dout
14
t DH
HM658512A Series
Read-Modify-Write Cycle
t RWC
t CE
CE
tP
t AS
Address
A0 to A18
t AH
Valid
t RCS
t RCH
t CW
t WP
t CEA
WE
t OHC
t OCD
OE/RFSH
t DW
t OEA
t DH
Valid data in
Din
t CHZ
t OLZ
t OHZ
t CLZ
t OW
Valid
data
out
Dout
Automatic Refresh Cycle
CE
t RFD
t FP
t FC
t FAP
t FC
t FP
t FAP
OE/RFSH
15
HM658512A Series
Self Refresh Cycle
CE
t RFS
t RFD
t FP
t FAS
OE/RFSH
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for V-version.
Parameter
Symbol
Min
Typ
Max
Unit
VCC for data retention
VDR
3.0
—
5.5
V
Self refresh current
I CCDR
—
—
50
µA
VCC = 3.0 V,
CE ≥ V CC – 0.2 V
OE/RFSH ≤ 0.2
Vin ≥ 0 V
—
—
100
µA
VCC = 5.5 V,
CE ≥ V CC – 0.2 V
OE/RFSH ≤ 0.2
Vin ≥ 0 V
Refresh setup time
t FS
0
—
—
ns
Operation recovery time
t FR
5
—
—
ms
16
Test conditions
HM658512A Series
Low V CC Data Retention Timing Waveform
Data Retention mode
VCC
4.5V
VDR
CE
Vcc-0.2V
2.4V
CE
0.8V
t RFD
t FP
OE/RFSH
t RFS
t FAS
2.4V
0.8V
Notes:
t FR
t FS
1.
2.
3.
4.
OE/RFSH
0.2V
Rise time and fall time of power supply voltage must be smaller than 0.05 V/ms.
Keep CE ≥ VCC – 0.2 V during data retention mode.
Regarding t RFD, tFP, tFAS and t RFS, refer to AC characteristics.
Input voltage should be lower than V CC +1.5 V in data retention mode.
17
HM658512A Series
Package Dimensions
HM658512ALP Series (DP-32)
Unit: mm
41.90
42.50 Max
17
13.4
13.7 Max
32
16
5.08 Max
1.20
2.30 Max
2.54 ± 0.25
0.48 ± 0.10
0.51 Min
2.54 Min
1
15.24
+ 0.11
0.25 – 0.05
0° – 15°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
18
DP-32
—
Conforms
5.1 g
HM658512A Series
HM658512ALFP Series (FP-32D)
Unit: mm
20.45
20.95 Max
17
11.30
32
1
1.27
0.40 ± 0.08
0.38 ± 0.06
0.10
0.15 M
Dimension including the plating thickness
Base material dimension
0.12
0.15 +– 0.10
1.00 Max
0.22 ± 0.05
0.20 ± 0.04
3.00 Max
16
14.14 ± 0.30
1.42
0° – 8°
0.80 ± 0.20
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-32D
Conforms
—
1.3 g
19
HM658512A Series
HM658512ALTT Series (TTP-32D)
Unit: mm
20.95
21.35 Max
17
10.16
32
1.27
0.42 ± 0.08
0.40 ± 0.06
0.21
16
M
0.80
11.76 ± 0.20
0.10
Dimension including the plating thickness
Base material dimension
20
0.17 ± 0.05
0.125 ± 0.04
1.20 Max
1.15 Max
0.13 ± 0.05
1
0° – 5° 0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TTP-32D
Conforms
—
0.51 g
HM658512A Series
HM658512ALRR Series (TTP-32DR)
Unit: mm
20.95
21.35 Max
16
10.16
1
1.27
0.42 ± 0.08
0.40 ± 0.06
0.21
17
M
0.80
11.76 ± 0.20
0.10
Dimension including the plating thickness
Base material dimension
0.17 ± 0.05
0.125 ± 0.04
1.20 Max
1.15 Max
0.13 ± 0.05
32
0° – 5° 0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TTP-32DR
Conforms
—
0.51 g
21
HM658512A Series
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herein.
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Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
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München
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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