ICS9248-112 Integrated Circuit Systems, Inc. Preliminary Product Preview Frequency Generator & Integrated Buffers for Celeron & PII/III™ Pin Configuration Recommended Application: 810/810E type chipset. Output Features: • 2- CPUs @2.5V, up to 150MHz. • 9 - SDRAM @ 3.3V, up to150MHz including 1 free running • 8 - PCICLK @ 3.3V • 1 - IOAPIC @ 2.5V, PCI or PCI/2 MHz • 2 - 3V66MHz @ 3.3V, 2X PCI MHz • 1- 48MHz, @3.3V fixed. • 1- 24MHz, @3.3V fixed • 1- REF @3.3V, 14.318MHz. Features: • Up to 166MHz frequency support • Support FS0-FS3 strapping status bit for I2C read back. • Support power management: Through Power down Mode from I2C programming. • Spread spectrum for EMI control ( ± 0.25% center). • Spread can be enabled or disabled to all 32 frequencies throuth I2C. • Uses external 14.318MHz crystal Skew Specifications: • CPU – CPU: <175ps • SDRAM - SDRAM: < 250ps • 3V66 – 3V66: <175ps • PCI – PCI: <500ps • CPU-SDRAM<500ps • For group skew specifications, please refer to group timing relationship. Block Diagram 48-Pin 300mil SSOP * These inputs have a 120K pull up to VDD. 1 These are double strength. Functionality FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) SDRAM (MHz) 3V66 (MHz) PCICLK (MHz) I OA P I C I OA P I C 1=PCICLK/2 0=PCICLK (MHz) (MHz) 66.80 68.00 100.30 103.00 133.73 145.00 133.73 137.33 140.00 140.00 118.00 124.00 133.70 137.00 150.00 72.50 100.20 102.00 100.30 103.00 100.30 108.75 100.30 103.00 105.00 140.00 118.00 124.00 133.70 137.00 112.50 108.75 66.80 68.00 66.87 68.67 66.87 72.50 66.87 68.67 70.00 93.33 78.67 82.67 89.13 91.33 75.00 72.50 33.40 34.00 33.43 34.33 33.43 36.25 33.43 34.33 35.00 46.67 39.33 41.33 44.57 45.67 37.50 36.25 16.70 17.00 16.72 17.17 16.72 18.13 16.72 17.17 17.50 23.33 19.67 20.67 22.28 22.83 18.75 18.13 33.40 34.00 33.43 34.33 33.43 36.25 33.43 34.33 35.00 46.67 39.33 41.33 44.57 45.67 37.50 36.25 Additional frequencies selectable through I2C programming. 9248- 112 Rev A 2/7/00 Third party brands and names are the property of their respective owners. PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICS9248-112 Preliminary Product Preview General Description Power Groups The ICS9248-112 is the single chip clock solution for designs using the 810/810E style chipset. It provides all necessary clock signals for such a system. GNDREF, VDDREF = REF0, X1, X2 GNDPCI , VDDPCI = PCICLK [9:0] GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F, supply for PLL core GND3V66 , VDD3V66 = 3V66 GND48 , VDD48 = 48MHz, 24_48MHz, VDDLAPIC = IOAPIC GNDLCPU , VDDLCPU = CPUCLK [1:0] Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-112 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. Pin Configuration PIN NUMBER 1 2, 9, 10, 18, 25, 29, 37 P I N NA M E TYPE DESCRIPTION REF1 OUT 3.3V, 14.318MHz reference clock output. VDD PWR 3.3V power supply 3 X1 IN 4 X2 OUT Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) PWR Ground pins for 3.3V supply 5, 6, 14, 21, 28, GND 33, 41 7, 8 3V66 (1:0) 11 12 13, 15, 16, 17, 19, 20 OUT 3.3V clock outputs for HUB running at 2XPCI MHz PCICLK01 FS0 OUT IN 3.3V PCI clock outputs, with Synchronous CPUCLKS Logic input frequency select bit. Input latched at power on. PCICLK11 OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS FS1 PCICLK (2:7) IN OUT Logic input frequency select bit. Input latched at power on. 3.3V PCI clock outputs, with Synchronous CPUCLKS 22 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 23 SCLK IN Clock input of I2C input 24 SDATA IN Data input for I2C serial input. 48MHz OUT 26 27 30 40, 39, 38, 36, 35, 34, 32, 31 42 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t f o r U S B FS3 IN Logic input frequency select bit. Input latched at power on. FS2 IN Logic input frequency select bit. Input latched at power on. 24MHz OUT 3.3V fixed 24MHz output SDRAM_F OUT 3.3V free running SDRAM not affected by I2C SDRAM (7:0) OUT 3.3V outputs GNDL PWR Ground for 2.5V power supply for CPU & APIC 43, 44 CPUCLK (1:0) OUT 2.5V Host bus clock output. 45, 47 46 VDDL IOAPIC REF01 PWR OUT OUT 2.5V power supply for CPU, IOAPIC 2.5V clock output 3.3V, 14.318MHz reference clock output. 48 FREQ_IOAPIC IN "If FREQ_APIC = 0, APIC Clock = PCICLK If FREQ_APIC = 1, APIC Clock = PCICLK/2 (default)" Third party brands and names are the property of their respective owners. 2 ICS9248-112 Preliminary Product Preview General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. Third party brands and names are the property of their respective owners. 3 ICS9248-112 Preliminary Product Preview Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) Bit Description Bit (2, 7:4) CPUCLK (MHz) SDRAM (MHz) 3V66 (MHz) 0 0 0 0 0 66.80 100.20 66.80 0 0 0 0 1 68.00 102.00 68.00 0 0 0 1 0 100.30 100.30 66.87 0 0 0 1 1 103.00 103.00 68.67 0 0 1 0 0 133.73 100.30 66.87 0 0 1 0 1 145.00 108.75 72.50 0 0 1 1 0 133.73 100.30 66.87 0 0 1 1 1 137.33 103.00 68.67 0 1 0 0 0 140.00 105.00 70.00 0 1 0 0 1 140.00 140.00 93.33 0 1 0 1 0 118.00 118.00 78.67 0 1 0 1 1 124.00 124.00 82.67 0 1 1 0 0 133.70 133.70 89.13 0 1 1 0 1 137.00 137.00 91.33 Bit 2, 0 1 1 1 0 150.00 112.50 75.00 Bit 7:4 0 1 1 1 1 72.50 108.75 72.50 1 0 0 0 0 75.00 112.50 75.00 1 0 0 0 1 83.00 83.00 27.67 1 0 0 1 0 110.00 110.00 73.33 1 0 0 1 1 120.00 120.00 80.00 1 0 1 0 0 125.00 125.00 83.33 1 0 1 0 1 69.25 103.88 69.25 1 0 1 1 0 70.00 105.00 70.00 1 0 1 1 1 76.67 115.00 76.67 1 1 0 0 0 145.00 145.00 96.67 1 1 0 0 1 66.50 99.75 66.50 1 1 0 1 0 150.00 150.00 100.00 1 1 0 1 1 99.75 99.75 66.50 1 1 1 0 0 155.00 155.00 103.33 1 1 1 0 1 166.50 166.50 111.00 1 1 1 1 0 153.33 115.00 76.67 1 1 1 1 1 133.00 99.75 66.50 0 - Frequency is selected by hardware select, Latched Inputs Bit 3 1 - Frequency is selected by Bit 2, 7:4 0 - Normal Bit 1 1 - Spread Spectrum Enabled ± 0.25% Center Spread 0 - Running Bit 0 1- Tristate all outputs PWD PCICLK (MHz) 33.40 34.00 33.43 34.33 33.43 36.25 33.43 34.33 35.00 46.67 39.33 41.33 44.57 45.67 37.50 36.25 37.50 13.83 36.67 40.00 41.67 34.63 35.00 38.33 48.33 33.25 50.00 33.25 51.67 55.50 38.33 33.25 FREQ_IOAPIC (MHz) 1 0 16.70 33.40 17.00 34.00 16.72 33.43 17.17 34.33 16.72 33.43 18.13 36.25 16.72 33.43 17.17 34.33 17.50 35.00 23.33 46.67 19.67 39.33 20.67 41.33 22.28 44.57 22.83 45.67 18.75 37.50 18.13 36.25 18.75 37.50 6.92 13.83 18.33 36.67 20.00 40.00 20.83 41.67 17.31 34.63 17.50 35.00 19.17 38.33 24.17 48.33 16.63 33.25 25.00 50.00 16.63 33.25 25.83 51.67 27.75 55.50 19.17 38.33 16.63 33.25 Spread Precentage +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center* +/- 0.25% Center* +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center* Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. * These frequencies with spread enabled are equal to original Intel defined frequency with -0.5% down spread. I2C is a trademark of Philips Corporation Third party brands and names are the property of their respective owners. 4 XXX Note1 0 1 0 ICS9248-112 Preliminary Product Preview Byte 1: Control Register (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 27 26 30 PWD X X X 1 1 1 1 1 Byte 2: SDRAM, Control Register (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DESCRIPTION FS3# FS0# FS2# 24MHz ( R e s e r ve d ) 48MHz ( R e s e r ve d ) SDRAM_F Byte 3: PCI, Control Register (1= enable, 0 = disable) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 20 19 17 16 15 13 12 11 PWD 1 1 1 1 1 1 1 1 PIN# - PWD 1 1 1 1 1 1 1 1 BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DESCRIPTION PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 DESCRIPTION SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 PIN# 8 7 46 43 44 PWD 0 1 1 X 1 X 1 1 DESCRIPTION ( R e s e r ve d ) 3V66_1 3V66_0 FREQ_IOAPIC# IOAPIC FS1# CPUCLK1 CPUCLK0 Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable) BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d Notes: PIN# - PWD 0 0 0 0 0 1 1 0 DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) Note: Dont write into this register, writing into this register can cause malfunction 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inferted logic load of the input frequency select pin conditions. Third party brands and names are the property of their respective owners. PWD 1 1 1 1 1 1 1 1 Byte 4: Control Register (1= enable, 0 = disable) Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable) BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PIN# 31 32 34 35 36 38 39 40 5 ICS9248-112 Preliminary Product Preview Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) on the ICS9248112 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 Third party brands and names are the property of their respective owners. 6 ICS9248-112 Preliminary Product Preview PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. Third party brands and names are the property of their respective owners. 7 ICS9248-112 Preliminary Product Preview Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Group Timing Relationship Table Group CPU 66MHz CPU 100MHz CPU 133MHz Offset Tolerance Offset Tolerance Offset Tolerance CPU to SDRAM CPU to 3V66 2.5ns 7.5ns 500ps 500ps 5.0ns 5.0ns 500ps 500ps 0.0ns 0.0ns 500ps 500ps SDRAM to 3V66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps 3V66 to PCI 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps PCI to PCI USB & DOT 0.0ns Asynch 1.0ns N/A 0.0ns Asynch 1.0ns N/A 0.0ns Asynch 1.0ns N/A Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance1 Transition Time IDD3.3PD CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M MIN 2 VSS-0.3 -5 -5 -200 CL = 0 pF; With input address to Vdd or GND Fi Lpin VDD = 3.3 V; CIN C out C INX Logic Inputs Out put pin capacitance X1 & X2 pins Ttrans TYP 2.0 -100 60 400 MAX UNITS VDD+0.3 V 0.8 V µA 5 µA µA 100 mA 600 µA 7 MHz nH 5 6 45 pF pF pF 14.318 27 To 1st crossing of target Freq. 3 mS Settling Time1 Ts From 1st crossing to 1% target Freq. 3 mS Clk Stabilization 1 TSTAB tPZH,tPZH tPLZ,tPZH From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs) 3 10 10 mS nS nS Delay 1 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP Guarenteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 8 1 1 ICS9248-112 Preliminary Product Preview Electrical Characteristics - CPU TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL Output Impedance RDSP2B1 RDSN2B1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current MIN TYP MAX UNITS VO = VDD*(0.5) 13.5 45 Ω VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V 13.5 2 45 -27 27 0.4 -27 30 Ω V V mA mA 1.6 ns 1.6 ns 55 % 250 ps 250 ps Rise Time tr2B1 VOL = 0.4 V, VOH = 2.0 V 0.4 Fall Time VOH = 0.4 V, VOL = 2.0 V 0.4 VT = 1.25 V 45 Skew tf2B1 dt2B1 tsk2B1 Jitter tjcyc-cyc1 Duty Cycle 1 VOH2B VOL2B IOH2B IOL2B CONDITIONS 50 VT = 1.25 V VT = 1.25 V Guarenteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RDSP1 1 VO = VDD*(0.5) 12 55 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN1 VOH1 VOL1 IOH1 IOL1 1 VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 55 0.55 -33 38 Ω V V mA mA Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns Fall Time 1 VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 VT = 1.5 V 45 55 % 1 VT = 1.5 V VT = 1.5 V 175 500 ps ps Output Impedance Duty Cycle Skew Jitter 1 tf1 dt1 tsk1 tjcyc-cyc Guarenteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 9 ICS9248-112 Preliminary Product Preview Electrical Characteristics - IOAPIC TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL Output Impedance RDSP4B1 RDSN4B1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current MIN TYP MAX UNITS VO = VDD*(0.5) 9 30 Ω VO = VDD*(0.5) IOH = -5.5 mA IOL = 9.0 mA VOH@ min = 1.0 V, VOH@ MAX = 2.375 V VOL@ MIN = 1.2 V, VOL@ MAX= 0.3 V 9 2 30 -27 27 0.4 -27 30 Ω V V mA mA Rise Time tr4B1 VOL = 0.4 V, VOH = 2.0 V 0.4 1.6 ns Fall Time tf4B1 dt4B1 VOH = 2.0 V, VOL = 0.4 V 0.4 1.6 ns VT = 1.25 V VT = 1.25 V 45 55 500 % ps 250 ps Duty Cycle Jitter Skew 1 VOH4\B VOL4B IOH4B IOL4B CONDITIONS tjcyc-cyc tsk41 Guarenteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RDSP3 1 VO = VDD*(0.5) 10 24 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN3 VOH3 VOL3 IOH3 IOL3 1 VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 2.0 V, VOH@ MAX=3.135 V VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V 10 2.4 24 -54 54 0.4 -46 53 Ω V V mA mA Rise Time Tr31 VOL = 0.4 V, VOH = 2.4 V 0.4 1.6 ns Fall Time Tf3 1 VOH = 2.4 V, VOL = 0.4 V 0.4 1.6 ns Dt3 1 VT = 1.5 V 45 55 % 250 250 ps ps Output Impedance Duty Cycle Skew Jitter 1 1 Tsk3 tj cyc-cyc VT = 1.5 V VT = 1.5 V Guarenteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 10 ICS9248-112 Preliminary Product Preview Electrical Characteristics - PCI TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RDSP1 1 VO = VDD*(0.5) 12 55 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN1 VOH1 VOL1 IOH1 IOL1 1 VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 55 0.55 -33 38 Ω V V mA mA Rise Time tr11 VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns Fall Time 1 VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 VT = 1.5 V 45 55 % 1 VT = 1.5 V VT = 1.5 V 500 500 ps ps Output Impedance Duty Cycle Skew Jitter 1 tf1 dt1 tsk1 tjcyc-cyc Guarenteed by design, not 100% tested in production. Electrical Characteristics - REF, 48MHz TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RDSP5 1 VO = VDD*(0.5) 20 60 Ω Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current RDSN5 VOH5 VOL5 IOH5 IOL5 1 VO = VDD*(0.5) IOH = 1 mA IOL = -1 mA VOH @MIN=1 V, VOH@MAX= 3.135 V VOL@MIN=1.95 V, VOL@MIN=0.4 V 20 2.4 60 0.4 -23 27 Ω V V mA mA Rise Time tr51 VOL = 0.4 V, VOH = 2.4 V 1.8 4 nS Fall Time 1 VOH = 2.4 V, VOL = 0.4 V 1.7 4 nS 1 VT = 1.5 V 55 % VT = 1.5 V; Fixed Clocks 500 pS VT = 1.5 V; Ref Clocks VT = 1.5 V 1000 250 pS pS Output Impedance Duty Cycle dt5 Jitter tjcyc-cyc1 tjcyc-cyc1 Skew 1 tf5 Tsk 45 Guarenteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. -29 29 11 ICS9248-112 Preliminary Product Preview Pin 1 Index Area .093 DIA. PIN (Optional) D/2 E/2 PARTING LINE H L DETAIL “A” TOP VIEW BOTTOM VIEW -eA2 c SEE DETAIL “A” A .004 C -E- A A1 A2 B c D E e H h L N µ SEATING PLANE -DEND VIEW SYMBOL B COMMON DIMENSIONS MIN. NOM. MAX. .095 .102 .110 .008 .012 .016 .087 .090 .094 .008 .0135 .005 .010 See Variations .291 .295 .299 0.025 BSC .395 .420 .010 .013 .016 .020 .040 See Variations 0° 8° SIDE VIEW VARIATIONS MIN. .620 AC A1 D NOM. .625 -C- N MAX. .630 48 “For current dimensional specifications, see JEDEC 95.” Dimensions in inches 48 Pin 300 mil SSOP Package Ordering Information ICS9248yF-112-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device Third party brands and names are the property of their respective owners. 12 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.