MOTOROLA MCM6341ZP15 128k x 24 bit static random access memory Datasheet

MOTOROLA
Order this document
by MCM6341/D
SEMICONDUCTOR TECHNICAL DATA
MCM6341
Advance Information
128K x 24 Bit Static Random
Access Memory
The MCM6341 is a 3,145,728–bit static random access memory organized as
131,072 words of 24 bits. Static design eliminates the need for external clocks
or timing strobes.
The MCM6341 is equipped with chip enable (E1, E2, E3) and output enable
(G) pins, allowing for greater system flexibility and eliminating bus contention
problems.
The MCM6341 is available in a 119–bump PBGA package.
•
•
•
•
•
•
•
Single 3.3 V ± 10% Power Supply
Fast Access Time: 10/11/12/15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Three–State Outputs
Power Operation: 280/275/270/260 mA Maximum, Active AC
Commercial Temperature (0°C to 70°C) and
Industrial Temperature (– 40°C to + 85°C) Options
ZP PACKAGE
PBGA
CASE 999–02
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . Output Enable
E1, E2, E3 . . . . . . . . . . . . . . . . Chip Enable
DQ . . . . . . . . . . . . . . . . . Data Input/Output
NC . . . . . . . . . . . . . . . . . . . . No Connection
VDD . . . . . . . . . . . . . + 3.3 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . Ground
BLOCK DIAGRAM
A
A
A
A
A
A
ROW
DECODER
MEMORY MATRIX
A
A
A
COLUMN I/O
DQ
INPUT
DATA
CONTROL
COLUMN DECODER
DQ
A
E1
E2
E3
W
G
A
A
A
A
A
A
A
DQ
DQ
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 2
2/18/98

Motorola, Inc. 1998
MOTOROLA
FAST SRAM
MCM6341
1
PIN ASSIGNMENT
A
B
C
D
1
2
3
4
5
6
7
NC
A
A
A
A
A
NC
NC
A
A
E1
A
A
NC
DQ
NC
E2
NC
E3
NC
DQ
DQ
VDD
VSS
VSS
VSS
VDD
DQ
DQ
VSS
VDD
VSS
VDD
VSS
DQ
DQ
VDD
VSS
VSS
VSS
VDD
DQ
DQ
VSS
VDD
VSS
VDD
VSS
DQ
DQ
VDD
VSS
VSS
VSS
VDD
DQ
VDD
VSS
VDD
VSS
VDD
VSS
VDD
DQ
VDD
VSS
VSS
VSS
VDD
DQ
DQ
VSS
VDD
VSS
VDD
VSS
DQ
DQ
VDD
VSS
VSS
VSS
VDD
DQ
DQ
VSS
VDD
VSS
VDD
VSS
DQ
DQ
VDD
VSS
VSS
VSS
VDD
DQ
DQ
NC
NC
NC
NC
NC
DQ
NC
A
A
W
A
A
NC
NC
A
A
G
A
A
NC
E
F
G
H
J
K
L
M
N
P
R
T
U
119–BUMP PBGA
TOP VIEW
MCM6341
2
MOTOROLA FAST SRAM
TRUTH TABLE (X = Don’t Care)
E1
E2
E3
G
W
Mode
I/O Pin
Cycle
Current
H
X
X
X
X
Not Selected
High–Z
—
ISB1, ISB2
X
L
X
X
X
Not Selected
High–Z
—
ISB1, ISB2
X
X
H
X
X
Not Selected
High–Z
—
ISB1, ISB2
L
H
L
H
H
Output Disabled
High–Z
—
IDDA
L
H
L
L
H
Read
Dout
Read
IDDA
L
H
L
X
L
Write
High–Z
Write
IDDA
ABSOLUTE MAXIMUM RATINGS (See Note)
Symbol
Value
Unit
VDD
– 0.5 to + 5.0
V
Vin, Vout
– 0.5 to VDD + 0.5
V
Output Current (per I/O)
Iout
± 20
mA
Power Dissipation
PD
1.0
W
Tbias
– 10 to + 85
– 45 to + 90
°C
Tstg
– 55 to + 150
°C
Rating
Power Supply Voltage Relative to VSS
Voltage Relative to VSS for Any Pin
Except VDD
Temperature Under Bias
Commercial
Industrial
Storage Temperature — Plastic
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to these high–impedance circuits.
This CMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MOTOROLA FAST SRAM
MCM6341
3
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
(TA = – 40 to + 85°C for Industrial Temperature Offering)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage (Operating Voltage Range)
VDD
3.0
3.3
3.6
V
Input High Voltage
VIH
2.2
—
VDD + 0.3**
V
Input Low Voltage
VIL
– 0.5*
—
0.8
V
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VDD)
Ilkg(I)
—
± 1.0
µA
Output Leakage Current (E = VIH, Vout = 0 to VDD)
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns).
** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width ≤ 2.0 ns).
DC CHARACTERISTICS (See Note)
Parameter
Ilkg(O)
—
± 1.0
µA
Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
—
V
Symbol
0 to 70°C
– 40 to
+ 85°C
Unit
NOTE: E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
POWER SUPPLY CURRENTS (See Note)
Parameter
AC Active Supply Current
(Iout = 0 mA, VDD = max)
MCM6341–10
MCM6341–11
MCM6341–12
MCM6341–15
IDD
280
275
270
260
290
285
280
270
mA
AC Standby Current (VDD = max, E = VIH,
No other restrictions on other inputs)
MCM6341–10
MCM6341–11
MCM6341–12
MCM6341–15
ISB1
50
50
50
45
55
55
55
50
mA
ISB2
20
20
mA
CMOS Standby Current (E ≥ VDD – 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)
(VDD = max, f = 0 MHz)
NOTE: E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance
Input/Output Capacitance
MCM6341
4
Symbol
Typ
Max
Unit
All Inputs Except Clocks and DQs
E, G, W
Cin
Cck
4
5
6
8
pF
DQ
CI/O
5
8
pF
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
(TA = – 40 to + 85°C for Industrial Temperature Offering)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING (See Notes 1, 2, and 3)
MCM6341–10
P
Parameter
MCM6341–11
MCM6341–12
MCM6341–15
S b l
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
U i
Unit
N
Notes
Read Cycle Time
tAVAV
10
—
11
—
12
—
15
—
ns
4
Address Access Time
tAVQV
—
10
—
11
—
12
—
15
ns
Enable Access Time
tELQV
—
10
—
11
—
12
—
15
ns
Output Enable Access Time
tGLQV
—
5
—
6
—
6
—
7
ns
Output Hold from Address Change
tAXQX
3
—
3
—
3
—
3
—
ns
Enable Low to Output Active
tELQX
3
—
3
—
3
—
3
—
ns
6, 7, 8
Output Enable Low to Output Active
tGLQX
0
—
0
—
0
—
0
—
ns
6, 7, 8
Enable High to Output High–Z
tEHQZ
0
5
0
6
0
6
0
7
ns
6, 7, 8
Output Enable High to Output High–Z
tGHQZ
0
5
0
6
0
6
0
7
ns
6, 7, 8
5
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
4. All read cycle timings are referenced from the last valid address to the first transitioning address.
5. Addresses valid prior to or coincident with E going low.
6. At any given voltage and temperature, tEHQZ max tELQX min, and tGHQZ max tGLQX min, both for a given device and from device
to device.
7. Transition is measured ± 200 mV from steady–state voltage.
8. This parameter is sampled and not 100% tested.
9. Device is continuously selected (E ≤ VIL, G ≤ VIL).
t
t
RL = 50 Ω
OUTPUT
Z0 = 50 Ω
VL = 1.5 V
Figure 1. AC Test Load
MOTOROLA FAST SRAM
MCM6341
5
READ CYCLE 1 (See Note 9)
tAVAV
A (ADDRESS)
tAXQX
Q (DATA OUT)
PREVIOUS DATA VALID
DATA VALID
tAVQV
READ CYCLE 2 (See Notes 3 and 5)
tAVAV
A (ADDRESS)
tELQV
E (CHIP ENABLE)
tEHQZ
tELQX
G (OUTPUT ENABLE)
tGLQV
tGHQZ
tGLQX
Q (DATA OUT)
HIGH–Z
DATA VALID
tAVQV
SUPPLY CURRENT
IDD
ISB
MCM6341
6
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled; See Notes 1, 2, 3, and 4)
MCM6341–10
P
Parameter
MCM6341–11
MCM6341–12
MCM6341–15
S b l
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
U i
Unit
N
Notes
Write Cycle Time
tAVAV
10
—
11
—
12
—
15
—
ns
5
Address Setup Time
tAVWL
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVWH
9
—
10
—
10
—
12
—
ns
Address Valid to End of Write (G
High)
tAVWH
8
—
9
—
9
—
10
—
ns
Write Pulse Width
tWLWH
tWLEH
9
—
10
—
10
—
12
—
ns
Write Pulse Width (G High)
tWLWH
tWLEH
8
—
9
—
9
—
10
—
ns
Data Valid to End of Write
tDVWH
4
—
5
—
5
—
6
—
ns
Data Hold Time
tWHDX
0
—
0
—
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
0
5
0
6
0
6
0
7
ns
6, 7, 8
Write High to Output Active
tWHQX
3
—
3
—
3
—
3
—
ns
6, 7, 8
Write Recovery Time
tWHAX
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
5. All write cycle timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured ± 200 mV from steady–state voltage.
7. This parameter is sampled and not 100% tested.
8. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
WRITE CYCLE 1 (W Controlled; See Notes 1, 2, 3, and 4)
tAVAV
A (ADDRESS)
tAVWH
tWHAX
E (CHIP ENABLE)
tWLWH
tWLEH
W (WRITE ENABLE)
tAVWL
tDVWH
DATA VALID
D (DATA IN)
tWLQZ
Q (DATA OUT)
MOTOROLA FAST SRAM
tWHDX
HIGH–Z
tWHQX
HIGH–Z
MCM6341
7
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, 3, and 4)
MCM6341–10
P
Parameter
MCM6341–11
MCM6341–12
MCM6341–15
S b l
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
U i
Unit
N
Notes
Write Cycle Time
tAVAV
10
—
11
—
12
—
15
—
ns
5
Address Setup Time
tAVEL
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVEH
9
—
10
—
10
—
12
—
ns
Address Valid to End of Write (G
High)
tAVEH
8
—
9
—
9
—
10
—
ns
Enable Pulse Width
tELEH,
tELWH
9
—
10
—
10
—
12
—
ns
6, 7
Enable Pulse Width (G High)
tELEH,
tELWH
8
—
9
—
9
—
10
—
ns
6, 7
Data Valid to End of Write
tDVEH
4
—
5
—
5
—
6
—
ns
Data Hold Time
tEHDX
0
—
0
—
0
—
0
—
ns
Write Recovery Time
tEHAX
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
5. All write cycle timing is referenced from the last valid address to the first transitioning address.
6. If E goes low coincident with or after W goes low, the output will remain in a high–impedance condition.
7. If E goes high coincident with or before W goes high, the output will remain in a high–impedance condition.
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, 3, and 4)
tAVAV
A (ADDRESS)
tAVEH
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
tEHAX
W (WRITE ENABLE)
tDVEH
DATA VALID
D (DATA IN)
tEHDX
Q (DATA OUT)
MCM6341
8
HIGH–Z
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
xCM
6341
XX XX
XX
Motorola Memory Prefix
Shipping Method (PBGA Standard)
Part Number
Speed (10 = 10 ns, 11 = 11 ns, 12 = 12 ns,
15 = 15 ns)
Package (ZP = PBGA)
Full Industrial Temperature Part Numbers — SCM6341ZP10A
SCM6341ZP12A
SCM6341ZP15A
Full Commercial Part Numbers — MCM6341ZP10
MCM6341ZP11
MCM6341ZP12
MCM6341ZP15
PACKAGE DIMENSIONS
ZP PACKAGE
119–PBGA
CASE 999–02
0.20
4X
119X
E
C
B
D
E2
e
6X
M
A B C
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
D1
16X
M
0.15
7 6 5 4 3 2 1
D2
b
0.3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. ALL DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
e
E1
TOP VIEW
BOTTOM VIEW
0.25 A
A3
0.35 A
0.20 A
A
A2
A1
MOTOROLA FAST SRAM
SIDE VIEW
SEATING
PLANE
DIM
A
A1
A2
A3
D
D1
D2
E
E1
E2
b
e
MILLIMETERS
MIN
MAX
–––
2.40
0.50
0.70
1.30
1.70
0.80
1.00
22.00 BSC
20.32 BSC
19.40
19.60
14.00 BSC
7.62 BSC
11.90
12.10
0.60
0.90
1.27 BSC
A
MCM6341
9
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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MCM6341
10
◊
MCM6341/D
MOTOROLA FAST
SRAM