LP61L1008A Preliminary 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM Features n Single 3.3V ± 10% power supply n Access times: 8/10/12 ns (max.) n Current: Operating: 160/155/150mA (max.) Standby: 5mA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Center Power/Ground Pin Configuration n Common I/O using three-state output n Output enable and one chip enable inputs for easy application n Data retention voltage: 2.0V (min.) n Available in 32-pin SOJ 300 mil package General Description The chip enable input is provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. The LP61L1008A is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Pin Configuration (August, 2001, Version 1.0) 1 32 A16 A1 2 31 A15 A2 3 30 A14 A3 4 29 A13 CE 5 28 OE I/O1 6 27 I/O8 I/O2 7 26 I/O7 VCC 8 25 GND GND 9 24 VCC I/O3 10 23 I/O6 I/O4 11 22 I/O5 WE 12 21 A12 A4 13 20 A11 A5 14 19 A10 A6 15 18 A9 A7 16 17 A8 LP61L1008AS PRELIMINARY A0 1 AMIC Technology, Inc. LP61L1008A Block Diagram VCC A0 GND 512 X 2048 DECODER MEMORY ARRAY INPUT DATA CIRCUIT COLUMN I/O A14 A15 A16 I/O 1 I/O8 CE OE WE CONTROL CIRCUIT Pin Description Pin No. Symbol 1 - 4, 13 - 21, 29- 32 A0 - A16 12 WE Write Enable 28 OE Output Enable 5 CE Chip Enable 6 –7, 10 - 11, 22 – 23, 26 - 27 I/O1 - I/O8 8, 24 VCC Power Supply 9, 25 GND Ground PRELIMINARY Description Address Inputs Data Input/Outputs (August, 2001, Version 1.0) 2 AMIC Technology, Inc. LP61L1008A Recommended DC Operating Conditions (TA = 0°C to + 70°C) Symbol Parameter VCC Supply Voltage GND Ground Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 V VIH Input High Voltage 2.2 - VCC + 0.3 V VIL Input Low Voltage -0.3 0 +0.8 V CL Output Load - - 30 pF TTL Output Load - - 1 - Absolute Maximum Ratings* *Comments VCC to GND .............................................. -0.5V to +4.6V IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V Operating Temperature, Topr ...................... 0°C to +70°C Storage Temperature, Tstg..................... -55°C to +125°C Power Dissipation, Pt................................................1.0W Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = 0°C to + 70°C, VCC = 3.3V ± 10%, GND = 0V) LP61L1008A- 8/10/12 Symbol Parameter Unit Min. Max. ILI Input Leakage Current - 2 µA ILO Output Leakage Current - 2 µA -8 - 160 -10 - 155 -12 - 150 - Conditions VIN = GND to VCC CE = VIH or ICC1 (1) Dynamic Operating Current ISB OE = VIH or WE = VIL VI/O = GND to VCC mA CE = VIL II/O = 0 mA 20 mA CE = VIH CE ≥ VCC - 0.2V, VIN ≤ 0.2V or VIN ≥ VCC - 0.2V ISB1 Standby Power Supply Current - 5 mA VOL Output Low Voltage - 0.4 V IOL = 8 mA VOH Output High Voltage 2.4 - V IOH = -4 mA Note: 1. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns PRELIMINARY (August, 2001, Version 1.0) 3 AMIC Technology, Inc. LP61L1008A Truth Table Mode I/O Operation Supply Current CE OE WE Standby H X X High Z ISB, ISB1 Output Disable L H H High Z ICC1 Read L L H DOUT ICC1 Write L X L DIN ICC1 Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF VIN = 0V CI/O* Input/Output Capacitance 8 pF VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V ± 10%, GND = 0V) Symbol LP61L1008A-8 Parameter LP61L1008A-10 LP61L1008A-12 Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 8 - 10 - 12 - ns tAA Address Access Time - 8 - 10 - 12 ns tACE Chip Enable Access Time - 8 - 10 - 12 ns tOE Output Enable to Output Valid - 4 - 5 - 6 ns tCLZ Chip Enable to Output in Low Z 3 - 3 - 5 - ns tOLZ Output Enable to Output in Low Z 0 - 0 - 2 - ns tCHZ Chip Disable to Output in High Z - 4 - 5 - 6 ns tOHZ Output Disable to Output in High Z 0 4 0 5 2 6 ns tOH Output Hold from Address Change 3 - 3 - 5 - ns PRELIMINARY (August, 2001, Version 1.0) CE CE CE 4 AMIC Technology, Inc. LP61L1008A AC Characteristics (continued) Symbol LP61L1008A-8 Parameter LP61L1008A-10 LP61L1008A-12 Min. Max. Min. Max. Min. Max. Unit Write Cycle tWC Write Cycle Time 8 - 10 - 12 - ns tCW Chip Enable to End of Write 6 - 7 - 10 - ns tAS Address Setup Time of Write 0 - 0 - 0 - ns tAW Address Valid to End of Write 6 - 7 - 10 - ns tWP Write Pulse Width 6 - 7 - 8 - ns tWR Write Recovery Time 0 - 0 - 0 - ns tWHZ Write to Output in High Z 0 4 0 5 0 5 ns tDW Data to Write Time Overlap 4 - 5 - 8 - ns tDH Data Hold from Write Time 0 - 0 - 0 - ns tOW Output Active from End of Write 3 - 3 - 5 - ns Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms (1, 2, 4) Read Cycle 1 tRC Address tAA tOH tOH DOUT PRELIMINARY (August, 2001, Version 1.0) 5 AMIC Technology, Inc. LP61L1008A Read Cycle 2 (1, 3, 4, 6) CE tACE tCLZ5 tCHZ5 DOUT Read Cycle 3 (1) tRC Address tAA OE tOE tOH tOLZ5 CE tACE tCHZ5 DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE = VI. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (August, 2001, Version 1.0) 6 AMIC Technology, Inc. LP61L1008A Timing Waveforms (continued) (6) Write Cycle 1 (Write Enable Controlled) tWC Address tAW tWR3 tCW CE 5 (4) tAS1 tWP2 WE tDW tDH DIN tWHZ tOW DOUT PRELIMINARY (August, 2001, Version 1.0) 7 AMIC Technology, Inc. LP61L1008A Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tWR3 tAW tCW5 CE tAS1 (4) tCW5 tWP2 WE tDW tDH DIN tWHZ7 DOUT Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP) of a low CE and a low WE . 3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle. 4. If the CE low transition with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (August, 2001, Version 1.0) 8 AMIC Technology, Inc. LP61L1008A AC Test Conditions Input Pulse Levels 0V to 3.0V Input Rise and Fall Time 3 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 +3.3V 320Ω Output I/O RL=50Ω ZO=50Ω 5pF* 350Ω VT=1.5V * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOHZ, tOLZ, tCHZ, tWHZ, and tOW Data Retention Characteristics (TA = 0°C to 70°C) Symbol VDR1 Parameter VCC for Data Retention Min. Max. Unit 2 3.6 V Conditions CE ≥ VCC - 0.2V VCC = 2V ICCDR1 Data Retention Current - 3 mA tCDR Chip Disable to Data Retention Time 0 - ns CE ≥ VCC - 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V See Retention Waveform tR Operation Recovery Time PRELIMINARY (August, 2001, Version 1.0) 5 - 9 ms AMIC Technology, Inc. LP61L1008A Low VCC Data Retention Waveform ( CE Controlled) DATA RETENTION MODE VCC 3.0V 3.0V tCDR tR VDR ≥ 2V VIH CE VIH CE ≥ VDR - 0.2V Ordering Information Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) LP61L1008AS-8 8 160 5 32L SOJ (300 mil) LP61L1008AS-10 10 155 5 32L SOJ (300 mil) LP61L1008AS-12 12 150 5 32L SOJ (300 mil) Part No. PRELIMINARY (August, 2001, Version 1.0) 10 Package AMIC Technology, Inc. LP61L1008A Package Information SOJ 32 (300mil BODY) Outline Dimensions unit: inches/mm b D 17 c 32 E F F BASE METAL WITH PLATING DETAIL "A" SECTION F-F 1 16 DETAIL "A" HE s b e D SEATING PLANE Symbol A1 y MIN 0.026" y A A2 b1 e1 0.004 y Dimensions in inches Dimensions in mm Min. Nom. Max. Min. Nom. Max. A 0128 0.132 0.140 3.25 3.35 3.56 A1 0.052 - - 2.08 - - A2 0.095 0.100 0.105 2.41 2.54 2.67 b 0.016 0.018 0.020 0.41 0.46 0.51 b1 0.026 0.028 0.032 0.66 0.71 0.81 c 0.006 0.008 0.012 0.15 0.20 0.30 D 0.820 0.825 0.830 20.83 20.96 21.08 HE 0.330 0.335 0.340 8.39 8.51 8.63 E 0.295 0.300 0.305 7.49 7.62 7.75 e1 0.260 0.267 0.274 6.61 6.78 6.96 e - 0.050 - - 1.27 - s - - 0.048 - - 1.22 y - - 0.004 - - 0.10 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E doesn't include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. PRELIMINARY (August, 2001, Version 1.0) 11 AMIC Technology, Inc.