M48Z35 M48Z35Y 256 Kbit (32 Kbit x 8) ZEROPOWER® SRAM FEATURES SUMMARY ■ INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ READ CYCLE TIME EQUALS WRITE CYCLE TIME ■ AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION ■ ■ WRITE PROTECT VOLTAGES: (VPFD = Power-fail Deselect Voltage) – M48Z35: VCC = 4.75 to 5.5V 4.5V ≤ VPFD ≤ 4.75V – M48Z35Y: 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V SELF-CONTAINED BATTERY IN THE CAPHAT™ DIP PACKAGE ■ PACKAGING INCLUDES A 28-LEAD SOIC and SNAPHAT® TOP (to be Ordered Separately) ■ PIN and FUNCTION COMPATIBLE WITH JEDEC STANDARD 32K x 8 SRAMs ■ SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY and CRYSTAL Figure 1. 28-pin CAPHAT™ DIP Package 28 1 PCDIP28 (PC) Battery CAPHAT Figure 2. 28-pin SOIC Package SNAPHAT (SH) Crystal / Battery 28 1 SOH28 (MH) May 2002 1/20 M48Z35, M48Z35Y TABLE OF CONTENTS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Logic Diagram (Figure 3.) . . . . . . . Signal Names (Table 1.) . . . . . . . . DIP Connections (Figure 4.) . . . . . SOIC Connections (Figure 5.) . . . . Block Diagram (Figure 6.) . . . . . . . ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... .....3 .....3 .....4 .....4 .....4 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AC Measurement Load Circuit (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating Modes (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 READ Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 READ Mode AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WRITE Enable Controlled, WRITE AC Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable Controlled, WRITE AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WRITE Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Down/Up Mode AC Waveforms (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Down/Up AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power Down/Up Trip Points DC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VCC Noise And Negative Going Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Supply Voltage Protection (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SNAPHAT Battery Table (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 M48Z35, M48Z35Y DESCRIPTION The M48Z35/Y ZEROPOWER® RAM is a 32 Kbit x 8, non-volatile static RAM that integrates powerfail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution. The M48Z35/Y is a non-volatile pin and function equivalent to any JEDEC standard 32K x8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 28 pin 600mil DIP CAPHAT™ houses the M48Z35/Y silicon with a long life lithium button cell in a single package. Figure 3. Logic Diagram The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28 lead SOIC, the battery package (i.e. SNAPHAT) part number is “M4Z28-BR00SH1.” Table 1. Signal Names VCC A0-A14 DQ0-DQ7 15 8 A0-A14 W Address Inputs Data Inputs / Outputs E Chip Enable Input G Output Enable Input W WRITE Enable Input DQ0-DQ7 M48Z35 M48Z35Y E G VSS VCC Supply Voltage VSS Ground AI01616D 3/20 M48Z35, M48Z35Y Figure 4. DIP Connections A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 5. SOIC Connections 28 1 27 2 26 3 25 4 24 5 23 6 7 M48Z35 22 8 M48Z35Y 21 20 9 19 10 18 11 17 12 13 16 14 15 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 27 2 26 3 25 4 24 5 23 6 22 7 M48Z35Y 21 8 20 9 19 10 18 11 17 12 16 13 15 14 AI01617D VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 AI02303C Figure 6. Block Diagram A0-A14 LITHIUM CELL POWER VOLTAGE SENSE AND SWITCHING CIRCUITRY 32K x 8 SRAM ARRAY DQ0-DQ7 E VPFD W G VCC 4/20 VSS AI01619B M48Z35, M48Z35Y MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol TA TSTG TSLD(1,2) Parameter Value Unit Grade 1 0 to 70 °C Grade 6 –40 to 85 °C SNAPHAT® –40 to 85 °C SOIC –55 to 125 °C 260 °C Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds VIO Input or Output Voltages –0.3 to 7.0 V VCC Supply Voltage –0.3 to 7.0 V IO Output Current 20 mA PD Power Dissipation 1 W Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). 2. For SO package: Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120 seconds). CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. 5/20 M48Z35, M48Z35Y DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. Operating and AC Measurement Conditions Parameter M48Z35 M48Z35Y Unit 4.75 to 5.5V 4.5 to 5.5 V Grade 1 0 to 70 0 to 70 °C Grade 6 –40 to 85 –40 to 85 °C Load Capacitance (CL) 100 100 pF Input Rise and Fall Times ≤5 ≤5 ns 0 to 3 0 to 3 V 1.5 1.5 V Supply Voltage (VCC) Ambient Operating Temperature (TA) Input Pulse Voltages Input and Output Timing Ref. Voltages Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 7. AC Measurement Load Circuit 645Ω DEVICE UNDER TEST CL = 100pF or 5pF CL includes JIG capacitance 1.75V AI03211 Table 4. Capacitance Symbol CIN CIO(3) Parameter(1,2) Min Max Unit Input Capacitance 10 pF Input / Output Capacitance 10 pF Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. 2. Outputs deselected. 3. At 25°C. 6/20 M48Z35, M48Z35Y Table 5. DC Characteristics Symbol Parameter ILI(2) Input Leakage Current ILO(2) Output Leakage Current Test Condition(1) Min Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±5 µA Outputs open 50 mA E = VIH 3 mA E = VCC – 0.2V 3 mA ICC Supply Current ICC1 Supply Current (Standby) TTL ICC2 Supply Current (Standby) CMOS VIL(3) Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2.2 VCC + 0.3 V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage IOH = –1mA 2.4 V Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. Outputs deselected. 3. Negative spikes of –1V allowed for up to 10ns once per cycle. OPERATING MODES The M48Z35/Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data until valid power returns. Table 6. Operating Modes Mode VCC Deselect WRITE READ 4.75 to 5.5V or 4.5 to 5.5V READ E G W DQ0-DQ7 Power VIH X X High Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT Active VIL VIH VIH High Z Active Deselect VSO to VPFD (min)(1) X X X High Z CMOS Standby Deselect ≤ VSO(1) X X X High Z Battery Back-up Mode Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10, page 13 for details. 7/20 M48Z35, M48Z35Y READ Mode The M48Z35/Y is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 264,144 locations in the static storage array. Thus, the unique address specified by the 15 Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. Figure 8. READ Mode AC Waveforms tAVAV VALID A0-A14 tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI00925 Note: WRITE Enable (W) = High. 8/20 M48Z35, M48Z35Y Table 7. READ Mode AC Characteristics M48Z35/Y Symbol Parameter (1) –70 Min tAVAV READ Cycle Time Unit Max 70 ns tAVQV(2) Address Valid to Output Valid 70 ns tELQV(2) Chip Enable Low to Output Valid 70 ns tGLQV(2) Output Enable Low to Output Valid 35 ns tELQX(3) Chip Enable Low to Output Transition 5 ns tGLQX(3) Output Enable Low to Output Transition 5 ns tEHQZ(3) Chip Enable High to Output Hi-Z 25 ns tGHQZ(3) Output Enable High to Output Hi-Z 25 ns tAXQX(2) Address Transition to Output Transition 10 ns Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 100pF. 3. CL = 5pF. 9/20 M48Z35, M48Z35Y WRITE Mode The M48Z35/Y is in the WRITE Mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. Figure 9. WRITE Enable Controlled, WRITE AC Waveforms tAVAV VALID A0-A14 tAVWH tWHAX tAVEL E tWLWH tAVWL W tWHQX tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH AI00926 Figure 10. Chip Enable Controlled, WRITE AC Waveforms tAVAV A0-A14 VALID tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI00927 10/20 M48Z35, M48Z35Y Table 8. WRITE Mode AC Characteristics M48Z35/Y (1) Symbol –70 Parameter Min Unit Max tAVAV WRITE Cycle Time 70 ns tAVWL Address Valid to WRITE Enable Low 0 ns tAVEL Address Valid to Chip Enable Low 0 ns tWLWH WRITE Enable Pulse Width 50 ns tELEH Chip Enable Low to Chip Enable High 55 ns tWHAX WRITE Enable High to Address Transition 0 ns tEHAX Chip Enable High to Address Transition 0 ns tDVWH Input Valid to WRITE Enable High 30 ns tDVEH Input Valid to Chip Enable High 30 ns tWHDX WRITE Enable High to Input Transition 5 ns tEHDX Chip Enable High to Input Transition 5 ns tWLQZ(2,3) WRITE Enable Low to Output Hi-Z 25 ns tAVWH Address Valid to WRITE Enable High 60 ns tAVEH Address Valid to Chip Enable High 60 ns WRITE Enable High to Output Transition 5 ns tWHQX(2,3) Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 5pF (see Figure 7, page 6). 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. 11/20 M48Z35, M48Z35Y Data Retention Mode With valid VCC applied, the M48Z35/Y operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD(max), VPFD(min) window. All outputs become high impedance, and all inputs are treated as “don't care.” Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z35/Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. There- fore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data. The internal button cell will maintain data in the M48Z35/Y for an accumulated period of at least 10 years (at 25°C) when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD(min) plus tREC(min). Normal RAM operation can resume tREC after VCC exceeds VPFD(max). For more information on Battery Storage Life refer to the Application Note AN1012. Figure 11. Power Down/Up Mode AC Waveforms VCC VPFD (max) VPFD (min) VSO tF tR tFB tDR tPD INPUTS tRB RECOGNIZED tREC DON'T CARE RECOGNIZED HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI01168C Table 9. Power Down/Up AC Characteristics Symbol Parameter(1) tPD E or W at VIH before Power Down tF(2) VPFD (max) to VPFD (min) VCC Fall Time tFB(3) Min Max Unit 0 µs 300 µs VPFD (min) to VSS VCC Fall Time 10 µs tR VPFD (min) to VPFD (max) VCC Rise Time 10 µs tRB VSS to VPFD (min) VCC Rise Time 1 µs tREC(4) VPFD (max) to Inputs Recognized 40 200 ms Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 4. tREC (min) = 20ms for industrial temperature Grade (6) device. 12/20 M48Z35, M48Z35Y Table 10. Power Down/Up Trip Points DC Characteristics Symbol Parameter(1) VPFD Power-fail Deselect Voltage VSO Battery Back-up Switchover Voltage tDR(2) Expected Data Retention Time Min Typ Max Unit M48Z35 4.5 4.6 4.75 V M48Z35Y 4.2 4.35 4.5 V M48Z35/Y 3.0 V 10 YEARS Note: All voltages referenced to VSS. 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. At 25°C. VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (see Figure 12) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount). Figure 12. Supply Voltage Protection VCC VCC 0.1µF DEVICE VSS AI02169 13/20 M48Z35, M48Z35Y PART NUMBERING Table 11. Ordering Information Scheme Example: M48Z 35Y –70 MH 1 TR Device Type M48Z Supply Voltage and Write Protect Voltage 35(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 35Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V Speed –70 = 70ns Package PC = PCDIP28 MH(2) = SOH28 Temperature Range 1 = 0 to 70°C 6(3) = –40 to 85°C Shipping Method for SOIC blank = Tubes TR = Tape & Reel Note: 1. The M48Z35 part is offered with the PCDIP28 (CAPHAT) package only. 2. The SOIC package (SOH28) requires the battery package (SNAPHAT ®) which is ordered separately under the part number “M4Zxx-BR00SH” in plastic tube or “M4Zxx-BR00SHTR” in Tape & Reel form. 3. Industrial temperature grade available in SOIC package (SOH28) only. Caution: Do not place the SNAPHAT battery package “M4Zxx-BR00SH” in conductive foam as it will drain the lithium button-cell battery. For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 12. SNAPHAT Battery Table Part Number 14/20 Description Package M4Z28-BR00SH Lithium Battery (48mAh) SNAPHAT SH M4Z32-BR00SH Lithium Battery (120mAh) SNAPHAT SH M48Z35, M48Z35Y PACKAGE MECHANICAL INFORMATION Figure 13. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Outline A2 A1 B1 B A L C e1 eA e3 D N E 1 PCDIP Note: Drawing is not to scale. Table 13. PMDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mechanical Data mm inches Symb Typ Min Max A 8.89 A1 Typ Min Max 9.65 0.350 0.380 0.38 0.76 0.015 0.030 A2 8.38 8.89 0.330 0.350 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.31 0.008 0.012 D 39.37 39.88 1.550 1.570 E 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 eA 15.24 16.00 0.600 0.630 L 3.05 3.81 0.120 0.150 N 28 28 15/20 M48Z35, M48Z35Y Figure 14. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline A2 A C B eB e CP D N E H A1 α L 1 SOH-A Note: Drawing is not to scale. Table 14. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data mm inch Symbol Typ Min A Typ Min 3.05 Max 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 – – – – eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 α 0° 8° 0° 8° N 28 e CP 16/20 Max 1.27 0.050 28 0.10 0.004 M48Z35, M48Z35Y Figure 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline A1 eA A2 A A3 B L eB D E SHZP-A Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data mm inches Symb Typ Min A Max Typ Min 9.78 Max 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 17/20 M48Z35, M48Z35Y Figure 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline A1 eA A2 A A3 B L eB D E SHZP-A Note: Drawing is not to scale. Table 16. SH – 4-pin SNAPHAT Housing for 120 mAh Battery, Package Mechanical Data mm inches Symb Typ Min A Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 18/20 Max 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 0.710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 M48Z35, M48Z35Y REVISION HISTORY Table 17. Revision History Date August 1999 Revision Details First Issue 04/21/00 SH and SH28 packages for 2-pin and 2-socket removed 05/10/01 Reformatted; added temperature information (Table 4, 5, 7, 8, 9, 10) 05/29/02 Modified reflow time and temperature footnotes (Table 2) 19/20 M48Z35, M48Z35Y Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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