OPA857 www.ti.com SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 Ultralow-Noise, Wideband, Selectable Feedback Resistance Transimpedance Amplifier Check for Samples: OPA857 FEATURES APPLICATIONS • • • • • • • • 1 2 • • • • • Internal Mid-Reference Voltage Pseudo-Differential Output Wide Dynamic Range Bandwidth: – 115 MHz (4.5-kΩ Transimpedance, 1.5-pF External Parasitic Capacitance) – 130 MHz (18.2-kΩ Transimpedance, 1.5-pF External Parasitic Capacitance) Ultralow Voltage Noise Density: 14.7 nARMS (NPBW = 85.7 MHz) Very Fast Overload Recovery Time: < 15 ns Internal Input Protection Diode Power Supply: – Voltage: +2.6 V to +3.6 V – Current: 23.4 mA Extended Temperature Range: –40°C to +85°C Photodiode Monitoring Precision I/V Conversion Optical Amplifiers CAT-Scanner Front-Ends DESCRIPTION The OPA857 is a wideband, fast overdrive recovery, fast-settling, ultralow-noise transimpedance amplifier targeted at photodiode monitoring applications. With selectable feedback resistance, the OPA857 simplifies the design of high-performance optical systems. Very fast overload recovery time and internal input protection provide the best combination to protect the remainder of the signal chain from overdrive while minimizing recovery time. The two selectable transimpedance gain configurations allow high dynamic range and flexibility required in today's transimpedance amplifier applications. The OPA857 is available in a 3-mm x 3-mm QFN package. The device is characterized for operation over the full industrial temperature range from –40°C to +85°C. +VS CTRL GND RF2 RF1 25 W OUT 25 W OUTN IN Test_SD Text Test_IN 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013–2014, Texas Instruments Incorporated OPA857 SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE AND ORDERING INFORMATION (1) (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see visit the device product folders at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Supply voltage VS– to VS+ Input and output voltage, VI VIN, VOUT pins VALUE UNIT 3.8 V (VS–) – 0.7 to (VS+) + 0.7 V Differential input voltage, VID 1 V Output current, IO 50 mA 10 mA Input current, II VIN pin Continuous power dissipation Maximum junction temperature Temperature range Electrostatic discharge (ESD) ratings (1) See Thermal Information table TJ +150 °C TJ (continuous operation, long-term reliability) +140 °C Operating free-air, TA –40 to +85 °C Storage, Tstg –65 to +150 °C Human body model (HBM) 2000 V Charge device model (CDM) 500 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION OPA857 THERMAL METRIC (1) RGT (QFN) UNITS 16 PINS θJA Junction-to-ambient thermal resistance 67.1 θJC(top) Junction-to-case(top) thermal resistance 91.6 θJB Junction-to-board thermal resistance 41.6 ψJT Junction-to-top characterization parameter 7.1 ψJB Junction-to-board characterization parameter 41.7 θJC(bottom) Junction-to-case(bottom) thermal resistance 23.1 (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 OPA857 www.ti.com SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS: VS+ – VS– = +3.3 V At TA = +25°C (1), VS = +3.3 V, CSource = 1.5 pF, VOUT = 0.5 VP (differential), RL = 500 Ω differential, single-ended input, pseudo-differential output, and input and output referenced to midsupply, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (2) AC PERFORMANCE Small-signal bandwidth SR Slew rate (differential) Settling time to 1% tS CTRL = 1, TA = –40°C to +85°C 130 MHz C CTRL = 0, TA = –40°C to +85°C 115 MHz C VOUT = 1-V step 220 V/μs C VOUT = 0.5-V step, CTRL = 0, TA = +25°C 7.2 8.1 ns B 8.2 ns B 8.8 ns B 9.1 ns B ns C VOUT = 0.5-V step, CTRL = 0, TA = –40°C to +85°C VOUT = 0.5-V step, CTRL = 1, TA = +25°C 7.7 VOUT = 0.5-V step, CTRL = 1, TA = –40°C to +85°C VOUT = 0.5-V step, CTRL = 0 152 VOUT = 0.5-V step, CTRL = 1 165 ns C VOUT = 0.5 VPP, f = 10 MHz, RF = 5 kΩ, TA = +25°C –94 dBc C VOUT = 0.5 VPP, f = 10 MHz, RF = 20 kΩ, TA = +25°C –81 dBc C VOUT = 0.5 VPP, f = 10 MHz, RF = 5 kΩ, TA = +25°C –97 dBc C VOUT = 0.5 VPP, f = 10 MHz, RF = 20 kΩ, TA = +25°C –101 dBc C CTRL = 0, NPBW = 85.7 MHz, with 120-MHz, firstorder, antialias filter 24.9 nARMS C CTRL = 1, NPBW = 85.7 MHz, with 120-MHz, firstorder, antialias filter 14.7 nARMS C ns B 50 Ω C CTRL = 1 into 500 Ω (3) (4) 18.2 kΩ C CTRL = 0 into 500 Ω (3) (4) 4.5 kΩ C TA = +25°C, RF = 20 kΩ and RF = 5 kΩ ±1 ±15 % A TA = +25°C ±1 ±5 mV A TA = –40°C to +85°C (5) ±6 mV B Output offset voltage drift TA = –40°C to +85°C (5) ±15 μV/°C C Common-mode voltage TA = +25°C, OUTN 1.88 V A pF C 1.9 V A 1.9 V B +5 mA C –20 mA C Settling time to 0.001% HD2 Second-harmonic distortion HD3 Third-harmonic distortion ieq_RMS Equivalent input-referred current noise Overdrive recovery time IIN = 100 µA, CTRL = 1, settling to 1% of final value with 120-MHz, first-order, antialias filter Closed-loop output impedance f = 1 MHz (differential) 15 DC PERFORMANCE Transimpedance gain Transimpedance gain error VOSO VCM Output offset voltage 1.78 1.83 INPUT Input pin capacitance 2 OUTPUT Output voltage swing Output current drive (for linear operation) (1) (2) (3) (4) (5) OUTN, TA = +25°C 0.6 TA = –40°C to +85°C (5) OUT, differential 50-Ω between OUT and OUTN Junction temperature = ambient for +70°C specifications. Test levels: (A) 100% tested at +25°C. Overtemperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. See the Application Information section for details on loading and effective transimpedance gain. Note that the effective transimpedance gain is reduced to 18.2 kΩ and 4.5 kΩ, respectively, with a 500-Ω load resulting from the internal series resistance on OUT and OUTN. Junction temperature = ambient at low temperature; junction temperature = ambient +3.5°C for overtemperature specifications. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 3 OPA857 SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS: VS+ – VS– = +3.3 V (continued) At TA = +25°C(1), VS = +3.3 V, CSource = 1.5 pF, VOUT = 0.5 VP (differential), RL = 500 Ω differential, single-ended input, pseudo-differential output, and input and output referenced to midsupply, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL (2) POWER SUPPLY Specified operating voltage Quiescent operating current +PSRR Power-supply rejection ratio 2.6 3.3 3.6 V B CTRL = 0, TA = +25°C 20.5 23.4 26.3 mA A CTRL = 0, TA = –40°C to +85°C (6) 20.0 26.8 mA B CTRL = 1, TA = +25°C 20.5 26.3 mA A CTRL = 1, TA = –40°C to +85°C (6) 20.0 26.8 mA B 23.4 At dc, TA = +25°C 70 80 dB A f = 10 MHz, TA = –40°C to +85°C (6) 15 18 dB B LOGIC LEVEL (CTRL) VIH High-level input voltage VIL Low-level input voltage 2 V A 0.8 V A High-level control pin input bias current 1 µA A Low-level control pin input bias current 1 µA A +85 °C C TEMPERATURE Specified operating range (6) 4 –40 Junction temperature = ambient at low temperature; junction temperature = ambient +3.5°C for overtemperature specifications. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 OPA857 www.ti.com SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 PIN CONFIGURATIONS 13 Test_SD/GND 14 Test_IN/+VS 15 IN 16 NC RGT PACKAGE QFN-16 (TOP VIEW) GND 3 10 +VS GND 4 9 +VS 8 +VS OUT 11 7 2 GND CTRL 6 GND GND 12 5 1 OUTN GND PIN DESCRIPTIONS PIN I/O DESCRIPTION NAME NO. CTRL 2 I Control pin for transimpedance gain 0 = 5-kΩ internal resistance, 1 = 20-kΩ internal resistance GND 1, 3, 4, 6, 7, 12 I Ground IN 15 I Input NC 16 — Not connected OUT 8 O Signal output OUTN 5 O Common-mode voltage output reference Test_IN/+VS 14 I Must be left floating or connected to +VS for normal operation 13 I Must be left floating or connected to GND for normal operation 9-11 I Supply voltage Test_SD/GND +VS Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 5 OPA857 SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, CS = 1.5 pF, and RL = 500 Ω differential between OUT and OUTN, unless otherwise noted. 3 0.5 0 Normalized Gain (dB -1 -1.5 -2 -2.5 -3 RLOAD ==11k RLOAD k -4 0 50 ±6 ±9 ±18 100 1 150 Frequency (MHz) 100 1000 Frequency (MHz) C001 Figure 2. 18.2-kΩ GAIN FREQUENCY RESPONSE vs TEMPERATURE 3 0.5 0 0 -0.5 Normalized Gain (dB Normalized Gain (dB 10 C000 Figure 1. 18.2-kΩ GAIN FREQUENCY RESPONSE -1 -1.5 -2 -2.5 -3 RLOAD k RLOAD ==11k -4 0 50 ±3 ±6 ±9 +0C -40C +25C +70C +105C ±12 ±15 RLOAD 500 RLOAD ==500 RLOAD ==100 RLOAD 100 -3.5 ±18 100 1 150 Frequency (MHz) 10 100 1000 Frequency (MHz) C002 Figure 3. 4.5-kΩ GAIN FREQUENCY RESPONSE C003 Figure 4. 4.5-kΩ GAIN FREQUENCY RESPONSE vs TEMPERATURE 2 200 2 45 1.8 180 1.8 40 1.6 160 1.6 35 1.4 140 1.4 30 1.2 25 1 20 0.8 15 0.6 10 0.4 40 0.2 20 5 0 IIN Iin VOUT Vout Time (250 ns/div) Input Current (uA) 50 Output Voltage (V) Input Current (uA) +0C -40C +25C +70C +105C ±12 ±15 RLOAD ==500 RLOAD 500 RLOAD ==100 RLOAD 100 -3.5 ±3 120 1.2 100 1 80 0.8 60 0.6 0 0 0.4 IinIIN VOUT Vout Time (250 ns/div) C004 Figure 5. 18.2-kΩ GAIN PULSE RESPONSE 6 Submit Documentation Feedback Output Voltage (V) Normalized Gain (dB 0 -0.5 0.2 0 C005 Figure 6. 4.5-kΩ GAIN PULSE RESPONSE Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 OPA857 www.ti.com SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, CS = 1.5 pF, and RL = 500 Ω differential between OUT and OUTN, unless otherwise noted. 30 Tz Gain: 4.5 k Input-Referred Current Noise (nArms) Input-Referred Current Noise (nArms) 30 Tz Gain: 18.2 k 25 20 15 10 Tz Gain: 18.2 k 25 20 15 10 -50 0 50 100 2.1 Temperature (C) 2.7 3 3.3 3.6 Supply Voltage (V) C007 Figure 8. RMS INPUT-REFERRED CURRENT NOISE vs SUPPLY VOLTAGE 100 140 Input-Referred Current Noise (nArms) Tz Gain: 18.2 k 90 80 70 60 50 40 30 20 10 Tz Gain: 4.5 k 120 100 80 60 40 20 0 0 0 5 10 15 20 0 Source Capacitance (pF) 3 0 0 Normalized Gain (dB 3 ±3 ±6 ±9 1.5 pF Parasitic 5 pF 10 pF 20 pF ±18 1 Frequency (MHz) C009 ±6 ±9 1.5 pF Parasitic 5 pF 10 pF 20 pF ±12 ±18 100 20 ±3 ±15 10 15 Figure 10. 4.5-kΩ GAIN RMS INPUT-REFERRED CURRENT NOISE vs INPUT CAPACITANCE 6 ±15 10 Source Capacitance (pF) 6 ±12 5 C008 Figure 9. 18.2-kΩ GAIN RMS INPUT-REFERRED CURRENT NOISE vs CAPACITANCE Normalized Gain (dB 2.4 C006 Figure 7. RMS INPUT-REFERRED CURRENT NOISE vs TEMPERATURE Input-Referred Current Noise (nArms) Tz Gain: 4.5 k 1000 1 Figure 11. 18.2-kΩ GAIN FREQUENCY RESPONSE vs INPUT CAPACITANCE 10 100 Frequency (MHz) C010 1000 C011 Figure 12. 4.5-kΩ GAIN FREQUENCY RESPONSE vs INPUT CAPACITANCE Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 7 OPA857 SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) 2 2 1.8 1.8 1.6 1.6 Output Voltage (V) Output Voltage (V) At TA = +25°C, CS = 1.5 pF, and RL = 500 Ω differential between OUT and OUTN, unless otherwise noted. 1.4 1.2 1 0.8 0.6 0.4 1.4 1.2 1 0.8 0.6 0.4 0.2 0.2 Vout 0 Vout 0 Time (250 ns/div) Time (250 ns/div) C012 C013 Figure 14. 4.5-kΩ GAIN OVERDRIVE RECOVERY 0 0 ±10 ±10 ±20 ±20 ±30 ±30 PSRR (dB) PSRR (dB) Figure 13. 18.2-kΩ GAIN OVERDRIVE RECOVERY ±40 ±50 ±60 -40C +0C +25C +70C +105C ±70 ±80 ±90 ±100 0.001 0.01 0.1 1 10 100 ±50 ±60 ±80 ±90 ±100 0.001 Harmonic Distortion (dBc) 5 1000 C015 ±85 ±90 ±95 ±100 Tz Gain: 4.5 k: RLOAD = 5 k: ±110 -50 -25 0 25 50 75 100 125 Temperature (C) 0 20 40 60 80 Frequency (MHz) C016 Figure 17. OUTPUT CURRENT vs TEMPERATURE 8 100 ±80 ±105 0 10 HD2 HD3 ±75 10 1 Figure 16. 4.5-kΩ GAIN POWER-SUPPLY REJECTION RATIO vs FREQUENCY ±70 15 0.1 Frequency (MHz) Source Sink 20 Output Current (mA) 0.01 C014 Figure 15. 18.2-kΩ GAIN POWER-SUPPLY REJECTION RATIO vs FREQUENCY 25 -40C +0C +25C +70C +105C ±70 1000 Frequency (MHz) ±40 C017 Figure 18. HARMONIC DISTORTION vs FREQUENCY Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 OPA857 www.ti.com SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, CS = 1.5 pF, and RL = 500 Ω differential between OUT and OUTN, unless otherwise noted. ±50 ±60 ±65 ±70 ±75 ±80 ±85 ±90 ±95 ±100 ±50 ±55 ±60 ±65 ±70 ±75 ±80 ±85 Tz Gain: 4.5 k: f = 50 MHz RLOAD = 5 k: ±90 Tz Gain: 18.2 k: RLOAD = 5 k: ±105 ±95 ±110 ±100 0 20 40 60 80 Frequency (MHz) 0 ±40 HD2 HD3 ±65 Harmonic Distortion (dBc) ±50 ±55 ±60 ±65 ±70 ±75 ±80 Tz Gain: 4.5 k: f = 50 MHz RL = 5 k: ±90 ±95 C019 Tz Gain: 4.5 k: f = 50 MHz ±70 ±75 ±80 ±85 ±90 ±95 ±100 ±100 0 0.5 1 1.5 Output Voltage (Vpp) 0 ±40 Harmonic Distortion (dBc) ±60 ±65 ±70 ±75 ±80 ±85 Tz Gain: 4.5 k: f = 50 MHz ±90 4000 HD2 HD3 ±65 ±55 3000 5000 6000 C021 Figure 22. HARMONIC DISTORTION vs RLOAD ±60 ±50 2000 Load Resistance ( HD2 HD3 ±45 1000 C020 Figure 21. HARMONIC DISTORTION vs OUTPUT VOLTAGE Harmonic Distortion (dBc) 1.5 Figure 20. HARMONIC DISTORTION vs OUTPUT VOLTAGE ±60 ±85 1 Output Voltage (Vpp) HD2 HD3 ±45 0.5 C018 Figure 19. HARMONIC DISTORTION vs FREQUENCY Harmonic Distortion (dBc) HD2 HD3 ±45 Harmonic Distortion (dBc) Harmonic Distortion (dBc) ±40 HD2 HD3 ±55 Tz Gain: 4.5 k RLOAD = 5 kQ f = 50 MHz TA = +25°C ±70 ±75 ±80 ±85 ±90 ±95 ±95 ±100 ±100 0 1000 2000 3000 4000 5000 6000 Load Resistance ( 2.1 Figure 23. HARMONIC DISTORTION vs RLOAD 2.4 2.7 3 3.3 3.6 Supply Voltage (V) C022 C023 Figure 24. HARMONIC DISTORTION vs SUPPLY VOLTAGE Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 9 OPA857 SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, CS = 1.5 pF, and RL = 500 Ω differential between OUT and OUTN, unless otherwise noted. ±40 ±50 ±55 ±60 ±65 ±70 Tz Gain: 18.5 k RLOAD = 5 kQ ±75 ±80 f = 50 MHz TA = +25°C ±85 ±55 f = 50 MHz ±60 ±65 ±70 ±75 ±80 ±85 HD2 HD3 ±90 ±90 ±95 2.1 2.4 2.7 3 3.3 3.6 -50 Supply Voltage (V) -25 0 Tz Gain: 4.5 k RLOAD = 5 kQ ±55 f = 50 MHz 50 75 100 125 C025 Figure 26. HARMONIC DISTORTION vs TEMPERATURE ±45 ±50 25 Temperature (C) C024 Figure 25. HARMONIC DISTORTION vs SUPPLY VOLTAGE 2500 2000 ±60 ±65 Count ±70 ±75 1500 1000 ±80 ±85 500 HD2 HD3 ±90 ±95 -50 -25 0 25 50 75 100 0 125 Temperature (C) C026 <21.9 22.2 22.5 22.8 23.1 23.4 23.8 24.1 24.4 24.7 25.0 25.3 25.7 26.0 26.3 26.6 26.9 >27.2 Harmonic Distortion (dBc) Tz Gain: 4.5 k RLOAD = 5 kQ ±50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) ±45 HD2 HD3 ±45 Quiescent Current (mA) Figure 27. HARMONIC DISTORTION vs TEMPERATURE C027 Figure 28. 18.2-kΩ IQ HISTOGRAM 2500 23.6 23.5 Quiescent Current (mA) Count 2000 1500 1000 500 23.4 23.3 23.2 23.1 0 <21.7 22.0 22.3 22.7 23.0 23.4 23.7 24.0 24.4 24.7 25.1 25.4 25.7 26.1 26.4 26.8 27.1 >27.4 23 Quiescent Current (mA) 22.9 ±50 ±25 0 25 50 Temperature (C) 75 100 125 C029 C028 Figure 29. 4.5-kΩ IQ HISTOGRAM 10 4.5 k 18.2 k Figure 30. QUIESCENT CURRENT vs TEMPERATURE Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 OPA857 www.ti.com SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, CS = 1.5 pF, and RL = 500 Ω differential between OUT and OUTN, unless otherwise noted. 3000 26 Tz Gain: 4.5 k 2500 22 2000 20 Count 18 16 1500 1000 14 500 12 4.5 k 18.2 k 0 10 2 2.2 2.4 2.6 2.8 3 3.2 3.4 Supply Voltage (V) 3.6 <-5 -4.5 -3.9 -3.3 -2.7 -2.1 -1.5 -0.9 -0.3 0.3 0.9 1.5 2.1 2.7 3.3 3.9 4.5 >5 Quiescent Current (mA) 24 Output Offset Voltage (mV) C030 C031 Figure 31. QUIESCENT CURRENT vs SUPPLY VOLTAGE Figure 32. 5-kΩ DIFFERENTIAL VOSO 3500 0.6 4.5 k Tz Gain: 18.2 k Output Offset Voltage (mV) 3000 Count 2500 2000 1500 1000 0 Same characteristic unit 0.2 0 -0.2 -0.4 -0.6 <-6 -5.4 -4.7 -4.0 -3.2 -2.5 -1.8 -1.1 -0.4 0.4 1.1 1.8 2.5 3.2 4.0 4.7 5.4 >6 500 18.2 k 0.4 ±50 ±25 0 25 50 75 100 Temperature (C) Output Offset Voltage (mV) 125 C033 C032 Figure 33. 20-kΩ DIFFERENTIAL VOSO Figure 34. OUTPUT VOLTAGE vs TEMPERATURE 4500 1.89 Reference Voltage (mV) 4000 3500 Count 3000 2500 2000 1500 1000 1.85 1.83 1.81 1.79 1.77 0 1.75 <1.76 1.767 1.775 1.784 1.792 1.801 1.809 1.817 1.826 1.834 1.843 1.851 1.859 1.868 1.876 1.885 1.893 >1.9 500 Reference Voltage (mV) Characteristic unit 1.87 ±50 ±25 0 25 50 75 100 Temperature (C) 125 C035 C034 Figure 35. REFERENCE VOLTAGE (VOUTN) DISTRIBUTION Figure 36. REFERENCE VOLTAGE (VOUTN) vs TEMPERATURE Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 11 OPA857 SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com APPLICATION INFORMATION TRANSIMPEDANCE AMPLIFIER OPERATION The OPA857 provides a unique combination of low-noise, high-bandwidth, and high-transimpedance gain. The amplifier is optimized to achieve greater than 100-MHz bandwidth on either the 4.5-kΩ or 18.2-kΩ transimpedance gain for the lowest possible RMS noise on the output for a targeted low input capacitance of 1.5 pF. Note that this 1.5-pF capacitance includes the board parasitic; thus, great attention must be placed on minimizing stray capacitance in the layout. This value is selected because the device is expected to be driven by a photodiode with biasing high enough to include the photodiode capacitance contribution between approximately 0.5 pF and 0.7 pF, leaving between 0.8 pF to 1 pF for the external parasitic. The device is a dedicated transimpedance amplifier with a pseudo-differential output. A block diagram is provided in Figure 37. +VS CTRL GND RF2 RF1 25 W OUT 25 W OUTN IN Test_SD Text Test_IN Figure 37. Block Diagram There are four distinct sections in this diagram: a transimpedance amplifier (TIA) block, a reference voltage block, a test structure, and an internal clamping circuit. The transimpedance section of Figure 37 includes two selectable gain configurations: RF1 and RF2. For a 500-Ω load, including the GND alternatives resulting from the internal 25-Ω series resistor on each output, the resulting gain is 4.5 kΩ or 18.2 kΩ. The transimpedance section is designed to provide excellent bandwidth (> 100 MHz) in both gain configurations with the lowest possible RMS noise over the entire bandwidth. This level of performance is achieved by minimizing the noise gain peaking at higher frequencies. The noise gain peaking resulting from feedback and source capacitance is the main noise contributor in high-speed transimpedance amplifiers. The reference voltage section of Figure 37 has several purposes: this section provides an adequate dc-reference voltage to the input and provides a dc reference at the output (thus allowing the dc-coupled solution to interface to a fully-differential signal chain). The CMRR provided by the fully-differential signal chain reduces any feedthrough from the OPA857 power supply, thereby increasing the PSRR of the amplifier. The test structure section is available on the pinout, but the main purpose of this section is to allow the device characterization to proceed as smoothly as possible. The internal clamping and ESD section is used for internal protection and to ensure that the amplifier can recover quickly after saturation. These sections are each described in further detail in the Operating Suggestions section. 12 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 OPA857 www.ti.com SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 DESIGNING THE SIGNAL CHAIN TI recommends maintaining a 200-Ω differential minimum load to ensure that the device bandwidth is not reduced because the open-loop gain of the OPA857 varies with loading; refer to Figure 1 and Figure 3 in the Typical Characteristics section. At a 100-Ω differential load, the OPA857 has an 87-MHz bandwidth instead of 130 MHz. In the high-gain configuration, heavier loading also has higher attenuation which further reduces the amplifier gain for a 500-Ω load resistance. Suitable fully-differential amplifiers for the signal chain have a sufficient 0.1-dB to 100-MHz bandwidth to ensure that the overall system performance is not reduced. Figure 38 shows a diagram of an associated signal chain. VS Device - RG RF + -VS 25 W - OUTN VCM + + 25 W IN VOCM +VS OUT - + +- RG RF Figure 38. TIA with Associated Signal Chain For a system composed of two first-order elements with a –3-dB bandwidth of f0 and f1, the resulting bandwidth is set by Equation 1 and Equation 2: fresulting = Q= f0 ´ f1 (1) f0 ´ f1 f0 + f1 (2) The resulting NPBW (noise power bandwidth) is given by Equation 3: NPBW = p 2 ´ Q ´ fresulting (3) A short list of suitable fully-differential amplifiers is provided in Table 1. Table 1. Fully-Differential Amplifier Selection AMPLIFIER QUIESCENT CURRENT (mA) -3-dB BANDWIDTH FEEDBACK RESISTOR (Ω) THS4520 13 600 499 Rail-to-rail output THS4521 1 135 1000 RRO, low IQ, limited bandwidth DESCRIPTION The fully-differential amplifiers selected in Table 1 offer a good compromise between the OPA857 loading while maintaining good gain and bandwidth. Note that the noise of the second stage in a high-speed transimpedance amplifier signal chain is not critical because the noise is dominated by the input stage. Also, the THS4521 is selected for its low quiescent current and may not prove sufficient for higher bandwidth systems. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 13 OPA857 SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 A • • • • • • • 14 www.ti.com summary of the recommended OPA857 implementation followed by a fully-differential amplifier is: Trace length between the OPA857 and the fully-differential amplifier must be kept low to minimize reflection. For optimum bandwidth, the differential load detected by the OPA857 should be kept above 500 Ω. Ideally, the fully-differential amplifier selected should have 0.1-dB flatness in excess of 100 MHz to ensure that the overall frequency response is not affected. Gain can be added after the device without affecting SNR because the noise is dominated by the device stage. The common-mode output voltage of 5/9th × VS of the OPA857 must be within the acceptable CMIR of the selected fully-differential amplifier. Although single-ended to differential conversions for connecting the device to the fully-differential amplifier is acceptable, best noise performance is achieved with the fully-differential connection described in Figure 38. The fully-differential connection has the advantage of reducing any common-mode signal. This reduction includes device power-supply variation, thus enhancing the PSRR capability of the circuit. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 OPA857 www.ti.com SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 DESIGN-IN TOOLS DEMONSTRATION FIXTURES An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the OPA857. The summary information for this fixture is shown in Table 2. Table 2. Demonstration Fixture PRODUCT PACKAGE ORDERING NUMBER LITERATURE NUMBER OPA857IRGT RGT OPA857EVM SBOU138 The demonstration fixture can be requested at the Texas Instruments web site (www.ti.com) through the OPA857 product folder. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. The previous statement is particularly true for transimpedance applications where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA857 is available through the OPA857 product folder under simulation models. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. These models, however, do not do as well in predicting harmonic distortion. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 15 OPA857 SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com OPERATING SUGGESTIONS REFERENCE SECTION The reference output voltage is set to be 5/9th of the power supply. Thus, for a single +3.3-V supply, the reference voltage is 1.83 V. The amplifier in the reference section is a high bandwidth while maintaining low output impedance to high frequencies. After the amplifier, the reference voltage is provided to two paths: one path leads to the output (OUTN) through a 25-Ω series resistor. The other path goes to the noninverting input of the TIA section through an RC filter to minimize noise. TRANSIMPEDANCE AMPLIFIER SECTION The amplifier of the TIA block has a class-A output stage, which limits its usable swing from the common-mode voltage of 1.83 V to the negative rail. Because the internal protection allows excellent overdrive recovery, the negative swing cannot go closer than 0.6 V to the rail. The resulting output dynamic range of the OPA857 on a +3.3-V supply is 1.2 V. This 1.2-V swing corresponds to a maximum input current of 60 µA in the high-gain configuration and 240 µA in the low-gain configuration. A 25-Ω series resistance can also be found on OUT, which limits the loading the amplifier experiences providing protection against short-circuit conditions. These internal resistances on the output also reduces the overall gain. With a 500-Ω differential load, the attenuation resulting from the load is 0.83 dB, which affects the overall transimpedance gain. Because of the load attenuation, the 20-kΩ transimpedance gain is reduced to an effective 18.2 kΩ while the 5-kΩ internal resistor gain is reduced to an effective 4.5-kΩ internal resistor. USING THE INTEGRATED TEST STRUCTURE In order to evaluate the low input capacitance condition on the input of the OPA857, simply evaluate the OPA857 performance without the photodiode. An integrated voltage-to-current conversion is implemented and can be accessed with the use of pins 13 and 14. This V-to-I converter structure is represented in Figure 39. If required, a capacitor can be added on the IN pin to match the desired operating conditions. This simple structure allows the emulation of a low capacitance photodiode with minimum test equipment. +VS Test_SD IN +VS Test_IN 2 kW Figure 39. Internal V-to-I Converter When using a photodiode, ensure that this source is turned off completely. This test structure is not intended to be used as a output dc-control voltage. To eliminate any possible interaction between the internal current source and the photodiode, connect the Test_In and Test_SD pins as described in Equation 4. To eliminate the current source from the schematic, Test_SD and Test_In need to be at Equation 4: Test_SD = GND or floating and Test_In = floating or +VS 16 Submit Documentation Feedback (4) Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 OPA857 www.ti.com SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 When the internal V-to-I converter needs to be operated, set Test_SD to logic 1, turn on the internal current source, and set a voltage on Test_IN. An adequate dc voltage must be set at the input to ensure that the output is operating within normal operation. At minimum, the output of the TIA section must be set to 5/9th of the supply voltage in preparation for a pulse configuration. For a sine-wave operation, as required when measuring a frequency response, the dc voltage on the OUT pin must be set to allow the full sine-wave amplitude and avoid clipping. In such a case, the OUT pin voltage is set lower than 5/9th of the supply voltage. Note that the 2-kΩ internal resistance used for the V-to-I conversion is not trimmed and can vary ±15% with process. As such, the source must be capable of sourcing both dc and ac voltages to ensure that the output voltage swing is compliant with the class-A output stage of the TIA section. Any change in the test circuit configuration (such as gain change) requires a new calibration of the internal V-to-I converter. Again if a photodiode is used, the internal V-to-I converter must be shut-off completely. Failure to do so results in degraded performance and higher than normal quiescent current. NOISE, BANDWIDTH, AND INPUT CAPACITANCE CONSIDERATION In a dedicated device such as a fixed gain transimpedance amplifier, where the input capacitance and load are carefully weighted and traded upon one another, understanding how the input capacitance specification, bandwidth, and the resulting noise relate to one another is important. The source input capacitance must stay low as stated earlier because of the fixed transimpedance configuration and associated internal compensation. The nominal design target is 1.5 pF, which includes board parasitic. Having an input capacitance in excess of 5 pF for maximum flatness in the low-gain configuration is not recommended. At a 5-pF input capacitance, the OPA857 in the high-gain configuration peaks at 1.5 dB, as shown in Figure 40 and Figure 41. This frequency peaking is expressed as overshoot in the time domain. 6 6 3 Normalized Gain (dB Normalized Gain (dB 3 0 ±3 ±6 ±9 1.5 pF Parasitic 5 pF 10 pF 20 pF ±12 ±15 ±18 1 0 ±3 ±6 ±9 1.5 pF Parasitic 5 pF 10 pF 20 pF ±12 ±15 10 100 Frequency (MHz) 1000 C010 ±18 1 10 100 Frequency (MHz) Figure 40. 18.2-kΩ Gain Frequency Response versus Input Capacitance 1000 C011 Figure 41. 4.5-kΩ Gain Frequency Response versus Input Capacitance Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 17 OPA857 SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com The internal compensation also affects the open-loop gain of the amplifier and is normally designed for one value, with an allowable range of operation. This loop-gain variation with the load resistance results in bandwidth variation with load resistance. This effect is normally small for a heavy-duty line driver, but may be more visible for receiver amplifiers such as the OPA857. The heavier the load, the lower the bandwidth is going to be, as shown in Figure 42 through Figure 45. Note that the high-gain configuration is more sensitive than the low-gain configuration for heavier loads. Unless high-impedance buffers are decided to be used (one for each output immediately after the OPA857), the loading is normally the gain resistor of a fully-differential amplifier. A programmable gain amplifier can also be used here, but because these amplifiers are generally intended for wireless infrastructure applications, the differential input impedance of the PGA is typically 150 Ω. 0.5 100 Input-Referred Current Noise (nArms) Normalized Gain (dB 0 -0.5 -1 -1.5 -2 -2.5 -3 RLOAD ==11k RLOAD k RLOAD ==500 RLOAD 500 RLOAD ==100 RLOAD 100 -3.5 -4 0 50 70 60 50 40 30 20 10 0 150 5 10 15 20 Source Capacitance (pF) C008 C000 Figure 42. 18.2-kΩ Gain Frequency Response Figure 44. 18.2-kΩ Gain RMS Input-Referred Current Noise versus Capacitance 3 Input-Referred Current Noise (nArms) 140 0 Normalized Gain (dB 80 0 100 Frequency (MHz) ±3 ±6 ±9 +0C -40C +25C +70C +105C ±12 ±15 ±18 1 Tz Gain: 4.5 k 120 100 80 60 40 20 0 0 10 100 Frequency (MHz) 1000 5 10 15 20 Source Capacitance (pF) C009 C001 Figure 43. 18.2-kΩ Gain Frequency Response versus Temperature 18 Tz Gain: 18.2 k 90 Figure 45. 4.5-kΩ Gain RMS Input-Referred Current Noise versus Capacitance Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 OPA857 www.ti.com SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 The source input capacitance must stay low as stated earlier because of the fixed transimpedance configuration and associated internal compensation. The nominal design target is 1.5 pF, which includes board parasitic. Having an input capacitance in excess of 5 pF for maximum flatness in the low-gain setting is not recommended. At a 5-pF input capacitance, the OPA857 in the high-gain setting peaks at 1.5 dB, as shown in Figure 46 and Figure 47. 6 6 3 Normalized Gain (dB Normalized Gain (dB 3 0 ±3 ±6 ±9 1.5 pF Parasitic 5 pF 10 pF 20 pF ±12 ±15 ±18 1 0 ±3 ±6 ±9 1.5 pF Parasitic 5 pF 10 pF 20 pF ±12 ±15 10 100 1000 Frequency (MHz) C010 ±18 1 10 100 Frequency (MHz) Figure 46. 18.2-kΩ Gain Frequency Response versus Input Capacitance 1000 C011 Figure 47. 4.5-kΩ Gain Frequency Response versus Input Capacitance GAIN CONTROL The device transimpedance gain is controlled with the CTRL pin. Setting the CTRL pin high results in selecting the high-gain configuration. Setting the CTRL pin low results in selecting the low-gain configuration, as described in Table 3. Table 3. Gain Control Logic Table GAIN CTRL (Pin 2) 4.5 kΩ 0 18.2 kΩ 1 THERMAL ANALYSIS Maximum-desired junction temperature sets the maximum allowed internal power dissipation, as described in this section. In no case should the maximum junction temperature be allowed to exceed 150°C. Operating junction temperature (TJ) is given by Equation 5: TA + PD × θ JA (5) The total internal power dissipation (PD) is the sum of the quiescent power (PDQ) and any additional power dissipated in the output stage (PDL) to deliver the output current. In the case of the OPA857, because the device has a low drive capability, consider the output current induced PDL to be negligible compared to the quiescent power induced PDQ. As a worst-case example, compute the maximum TJ using an OPA857 in the circuit of Figure 38 operating at the maximum specified ambient temperature of +95°C. Equation 6 and Equation 7 calculate PD and maximum TJ, respectively. PD = 3.3 V × 26.8 mA = 88.5 mW Maximum TJ = +95°C + (0.09 W × 39.5°C/W) = 98.5°C (6) (7) Although this result is still well below the specified maximum junction temperature, system reliability considerations may require lower tested junction temperatures. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 19 OPA857 SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com BOARD LAYOUT GUIDELINE Achieving optimum performance with a high-frequency amplifier such as the OPA857 requires careful attention to board layout parasitics and external component types. Recommendations that optimize performance include: a) Minimize parasitic capacitance to any ac ground for all signal I/O pins. Parasitic capacitance on the inverting input pin can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1-µF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. An optional supply decoupling capacitor (0.1 µF) across the two power supplies (for bipolar operation) improves second-harmonic distortion performance. Larger (2.2 µF to 6.8 µF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These capacitors may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components preserves the high-frequency performance of the OPA857. Resistors should be a very low reactance type. Surface-mount resistors function best and allow a tighter overall layout. Metal-film or carbon composition, axially-leaded resistors can also provide good highfrequency performance. Again, keep the leads and PC board traces as short as possible. Never use wirewound type resistors in a high-frequency application. d) Connections to other wideband devices on the board may be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. e) Socketing a high-speed part such as the OPA857 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network that makes achieving a smooth, stable frequency response almost impossible. Best results are obtained by soldering the OPA857 onto the board. INPUT AND ESD PROTECTION The OPA857 is built using a very high-speed, complementary, BICMOS process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 48. +VCC External Pin Internal Circuitry −VCC Figure 48. Internal ESD Protection These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30-mA continuous current. Where higher currents are possible, external lowcapacitance protection may be required. 20 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 OPA857 www.ti.com SBOS630B – DECEMBER 2013 – REVISED JANUARY 2014 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2013) to Revision B Page • Changed document status to Production Data ..................................................................................................................... 1 • Changed transimpedance value in both sub-bullets of Bandwidth Features bullet .............................................................. 1 • Changed Extended Temperature Range Features bullet to a range of –40°C to +85°C ..................................................... 1 • Changed first sentence of Description section: added "targeted at photodiode monitoring applications" ........................... 1 • Changed temperature range to –40°C to +85°C in last sentence of Description section .................................................... 1 • Changed front-page graphic ................................................................................................................................................. 1 • Added pages 2 through end of document ............................................................................................................................ 1 Changes from Original (December 2013) to Revision A Page • Changed document status to Product Preview .................................................................................................................... 1 • Deleted all pages past page 1 .............................................................................................................................................. 1 • Deleted fourth Applications bullet ......................................................................................................................................... 1 • Changed first sentence of Description section ..................................................................................................................... 1 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: OPA857 21 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA857IRGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 95 OPA857 OPA857IRGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 95 OPA857 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jan-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant OPA857IRGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 OPA857IRGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jan-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA857IRGTR QFN RGT 16 3000 367.0 367.0 35.0 OPA857IRGTT QFN RGT 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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