Revised March 2000 DM74LS533 Octal Transparent Latch with 3-STATE Outputs General Description Features The DM74LS533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flipflops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The DM74LS533 is the same as the DM74LS373, except that the outputs are inverted. For detailed specifications please see the DM74LS373 data sheet, but note that the propagation delays from data to output are 5.0 ns longer for the DM74LS533 than for the DM74LS373. ■ Eight latches in a single package ■ 3-STATE outputs for bus interfacing Ordering Code: Order Number Package Number Package Description DM74LS533WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS533N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Symbol VCC = Pin 20 GND = Pin 10 Pin Descriptions Pin Names Function Table Description OUTPUT Latch Enable Enable Latch Enable Input (Active HIGH) L H H L OE Output Enable Input (Active LOW) L H L H O0–O7 Complementary 3-STATE Outputs D0, D7 Data Inputs LE D Output O L L X QO H X X Z L = LOW State H = HIGH State X = Don't Care Z = High Impedance State QO = Previous Condition of O © 2000 Fairchild Semiconductor Corporation DS009811 www.fairchildsemi.com DM74LS533 Octal Transparent Latch with 3-STATE Outputs October 1988 DM74LS533 Absolute Maximum Ratings(Note 1) Supply Voltage Note 1: The “Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max Units 4.75 5 5.25 V VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage 0.8 V IOH High Level Output Current −2.6 mA IOL Low Level Output Current 24 mA TA Free Air Operating Temperature 70 °C 2 V 0 Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max, Output Voltage VIL = Max VOL LOW Level VCC = Min, IOL = Max, Output Voltage VIH = Min Min 2.4 Typ (Note 2) Max Units −1.5 V 3.4 V 0.35 0.5 IOL = 12 mA, VCC = Min 0.4 V II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA −100 mA 46 mA −20.0 µA 20.0 µA Short Circuit VCC = Max Output Current (Note 3) ICCZ Supply Current VCC = Max IOZL 3-STATE Output Off VCC = VCCH Current LOW VOZL = 0.4V IOS IOZH 3-STATE Output Off VCC = VCCH Current HIGH VOZH = 2.7V −20 mA Note 2: All typicals are at VCC = 5V, TA = 25°C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics VCC = +5.0V, TA = +25°C CL = 50 pF Symbol RL = 2 kΩ Parameter Min Units Max tPLH Propagation Delay 23 tPHL Data to Qx 23 tPLH Propagation Delay 30 tPHL LE to Qx 25 tPZL Output Enable Time 22 tPZH OE to Qx 20 tPHZ Output Enable Time 20 tPLZ OE to Qx 25 www.fairchildsemi.com 2 ns ns ns ns DM74LS533 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 3 www.fairchildsemi.com DM74LS533 Octal Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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