AD AD743JN Ultralow noise bifet op amp Datasheet

a
EXCELLENT DC PERFORMANCE
0.5 mV max Offset Voltage
250 pA max Input Bias Current
1000 V/mV min Open-Loop Gain
AC PERFORMANCE
2.8 V/ms Slew Rate
4.5 MHz Unity-Gain Bandwidth
THD = 0.0003% @ 1 kHz
Available in Tape and Reel in Accordance with
EIA-481A Standard
APPLICATIONS
Sonar Preamplifiers
High Dynamic Range Filters (>140 dB)
Photodiode and IR Detector Amplifiers
Accelerometers
PRODUCT DESCRIPTION
The AD743 is an ultralow noise precision, FET input,
monolithic operational amplifier. It offers a combination of the
ultralow voltage noise generally associated with bipolar input op
amps and the very low input current of a FET-input device.
Furthermore, the AD743 does not exhibit an output phase
reversal when the negative common-mode voltage limit is
exceeded.
The AD743’s guaranteed, maximum input voltage noise of
4.0 nV/√Hz at 10 kHz is unsurpassed for a FET-input
monolithic op amp, as is the maximum 1.0 µV p-p, 0.1 Hz to
10 Hz noise. The AD743 also has excellent dc performance with
250 pA maximum input bias current and 0.5 mV maximum
offset voltage.
The AD743 is specifically designed for use as a preamp in
capacitive sensors, such as ceramic hydrophones. It is available
in five performance grades. The AD743J and AD743K are rated
over the commercial temperature range of 0°C to +70°C. The
AD743A and AD743B are rated over the industrial temperature
range of –40°C to +85°C. The AD743S is rated over the
military temperature range of –55°C to +125°C and is available
processed to MIL-STD-883B, Rev. C.
The AD743 is available in 8-pin plastic mini-DIP, 8-pin cerdip,
16-pin SOIC, or in chip form.
CONNECTION DIAGRAMS
8-Pin Plastic Mini-DIP (N)
and
8-Pin Cerdip (Q) Packages
NULL
1
AD743
16-Pin SOIC (R) Package
8
NC
NC
1
2
8
16
NC
15
NC
–IN
2
7
OFFSET
+V S
NULL
+IN
3
6
OUT
–IN
3
–V S
4
5
NULL
NC
4
13
+VS
OUTPUT
TOP VIEW
NC = NO CONNECT
AD743
14 NC
+IN
5
12
–V S
6
11
OFFSET
NULL
NC
7
10
NC
NC
8
9
NC
NC = NO CONNECT
PRODUCT HIGHLIGHTS
1. The low offset voltage and low input offset voltage drift of
the AD743 coupled with its ultralow noise performance
mean that the AD743 can be used for upgrading many
applications now using bipolar amplifiers.
2. The combination of low voltage and low current noise make
the AD743 ideal for charge sensitive applications such as
accelerometers and hydrophones.
3. The low input offset voltage and low noise level of the
AD743 provide >140 dB dynamic range.
4. The typical 10 kHz noise level of 2.9 nV/√Hz permits a three
op amp instrumentation amplifier, using three AD743s, to be
built which exhibits less than 4.2 nV/√Hz noise at 10 kHz
and which has low input bias currents.
1000
OP27 &
RESISTOR
(—)
R SOURCE
INPUT NOISE VOLTAGE – nV/ Hz
FEATURES
ULTRALOW NOISE PERFORMANCE
2.9 nV/√Hz at 10 kHz
0.38 mV p-p, 0.1 Hz to 10 Hz
6.9 fA/√Hz Current Noise at 1 kHz
Ultralow Noise
BiFET Op Amp
AD743
EO
R SOURCE
100
AD743 + RESISTOR
)
(
AD743 & RESISTOR
OR
OP27 & RESISTOR
10
RESISTOR NOISE ONLY
(– – –)
1
100
1k
10k
100k
1M
10M
SOURCE RESISTANCE – Ω
Input Noise Voltage vs. Source Resistance
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD743–SPECIFICATIONS (@ +258C and 615 V dc, unless otherwise noted)
Model
Conditions
INPUT OFFSET VOLTAGE1
Initial Offset
Initial Offset
vs. Temp.
vs. Supply (PSRR)
vs. Supply (PSRR)
TMIN to TMAX
TMIN to TMAX
12 V to 18 V2
TMIN to TMAX
INPUT BIAS CURRENT3
Either Input
Either Input
@ TMAX
Either Input
Either Input, VS = ± 5 V
INPUT OFFSET CURRENT
Offset Current
@ TMAX
FREQUENCY RESPONSE
Gain BW, Small Signal
Full Power Response
Slew Rate, Unity Gain
Settling Time to 0.01%
Total Harmonic
Distortion4 (Figure 16)
Min
AD743J
Typ
0.25
90
88
INPUT VOLTAGE NOISE
AD743K/B
Typ
1.0/0.8
1.5
2
96
0.1
100
98
Max
Min
AD743S
Typ
0.5/0.25
1.0/0.50
1
106
100
0.25
90
88
Max
Units
1.0
2.0
mV
mV
µV/°C
dB
dB
2
96
150
400
150
250
150
400
pA
VCM = 0 V
VCM = +10 V
VCM = 0 V
250
30
8.8/25.6
600
200
250
30
5.5/16
400
125
300
30
413
600
200
nA
pA
pA
VCM = 0 V
40
150
30
75
40
150
pA
102
nA
VCM = 0 V
2.2/6.4
G = –1
VO = 20 V p-p
G = –1
f = 1 kHz
G = –1
–10
VCM = ± 10 V
TMIN to TMAX
80
78
4.5
25
2.8
6
4.5
25
2.8
6
MHz
kHz
V/µs
µs
0.0003
0.0003
0.0003
%
1 3 1010||20
3 3 1011||18
1 3 1010||20
3 3 1011||18
1 3 1010||20
3 3 1011||18
Ω||pF
Ω||pF
± 20
+13.3, –10.7
+12
± 20
+13.3, –10.7
+12
± 20
+13.3, –10.7
+12
V
V
V
95
dB
dB
0.38
5.5
3.6
3.2
2.9
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
95
0.38
5.5
3.6
3.2
2.9
INPUT CURRENT NOISE
f = 1 kHz
6.9
OPEN LOOP GAIN
VO = ± 10 V
RLOAD ≥ 2 kΩ
TMIN to TMAX
RLOAD = 600 Ω
OUTPUT CHARACTERISTICS
Voltage
RLOAD ≥ 600 Ω
RLOAD ≥ 600 Ω
TMIN to TMAX
RLOAD ≥ 2 kΩ
Current
Short Circuit
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
1000
800
–10
90
88
102
0.38
5.5
3.6
3.2
2.9
5.0
4.0
–10
80
78
1.0
10.0
6.0
5.0
4.0
6.9
4000
2000
1800
1200
4000
1000
800
1200
+13, –12
5.0
4.0
6.9
fA/√Hz
4000
V/mV
V/mV
V/mV
1200
+13, –12
+13, –12
+13.6, –12.6
+13.6, –12.6
+13.6, –12.6
+12, –10
± 12
+13.8, –13.1
20
40
+12, –10
± 12
+13.8, –13.1
20
40
+12, –10
± 12
+13.8, –13.1
20
40
± 4.8
± 15
8.1
# of Transistors
1.1/3.2
4.5
25
2.8
6
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
TRANSISTOR COUNT
Min
VCM = 0 V
INPUT IMPEDANCE
Differential
Common Mode
INPUT VOLTAGE RANGE
Differential5
Common-Mode Voltage
Over Max Operating Range6
Common-Mode
Rejection Ratio
Max
± 18
10.0
50
± 4.8
± 15
8.1
50
± 18
10.0
± 4.8
± 15
8.1
± 18
10.0
V
V
V
V
mA
V
V
mA
50
NOTES
1
Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = +25°C.
2
Test conditions: +VS = 15 V, –VS = 12 V to 18 V and +VS = 12 V to +18 V, –VS = 15 V.
3
Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperature, the current doubles every 10°C.
4
Gain = –1, RL = 2 kΩ, CL = 10 pF.
5
Defined as voltage between inputs, such that neither exceeds ± 10 V from common.
6
Thc AD743 does not exhibit an output phase reversal when the negative common-mode limit is exceeded.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
–2–
REV. C
AD743
ABSOLUTE MAXIMUM RATINGS 1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage Temperature Range (Q) . . . . . . . . . . –65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD743J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD743A/B . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD743S . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 60 seconds) . . . . . 300°C
Model
Temperature Range
Package
Option*
AD743JN
AD743KN
AD743JR-16
AD743KR-16
AD743BQ
AD743SQ/883B
AD743JR-16-REEL
AD743KR-16-REEL
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
0°C to +70°C
0°C to +70°C
N-8
N-8
R-16
R-16
Q-8
Q-8
Tape & Reel
Tape & Reel
*N = Plastic DIP; R = Small Outline IC; Q = Cerdip.
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
8-pin plastic package:
θJA = 100°C/Watt, θJC = 50°C/Watt
8-pin cerdip package:
θJA = 110°C/Watt, θJC = 30°C/Watt
16-pin plastic SOIC package: θJA = 100°C/Watt, θJC = 30°C/Watt
ESD SUSCEPTIBILITY
An ESD classification per method 3015.6 of MIL-STD-883C
has been performed on the AD743. The AD743 is a class 1
device, passing at 1000 V and failing at 1500 V on null pins 1
and 5, when tested, using an IMCS 5000 automated ESD
tester. Pins other than null pins fail at greater than 2500 V.
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
REV. C
–3–
AD743 –Typical Characteristics (@ +258C, V = +15 V)
S
20
20
35
OUTPUT VOLTAGE SWING – Volts
INPUT VOLTAGE SWING – Volts
R LOAD = 10kΩ
15
+VIN
10
–VIN
5
OUTPUT VOLTAGE SWING – Volts p-p
R LOAD = 10kΩ
15
POSITIVE
SUPPLY
10
NEGATIVE
SUPPLY
5
0
5
10
0
20
15
5
10
15
10
5
10
Figure 2. Output Voltage Swing vs.
Supply Voltage
–6
12
20
20
15
SUPPLY VOLTAGE ± VOLTS
SUPPLY VOLTAGE ± VOLTS
Figure 1. Input Voltage Swing
vs. Supply Voltage
25
0
0
0
30
100
1k
LOAD RESISTANCE – Ω
10k
Figure 3. Output Voltage Swing vs.
Load Resistance
200
10
100
–7
9
6
3
OUTPUT IMPEDANCE – Ω
INPUT BIAS CURRENT – Amps
QUIESCENT CURRENT– mA
10
–8
10
–9
10
–10
10
10
1
0.1
–11
10
–12
0.01
10
0
0
5
10
15
–60 –40
20
–20
SUPPLY VOLTAGE ± VOLTS
0
20
40
60
80 100
120
10k
140
100k
TEMPERATURE – °C
7.0
80
300
100M
10M
Figure 6. Output Impedance vs.
Frequency (Closed Loop Gain = –1)
Figure 5. Input Bias Current vs.
Temperature
Figure 4. Quiescent Current vs.
Supply Voltage
1M
FREQUENCY – Hz
200
100
GAIN BANDWIDTH PRODUCT – MHz
60
CURRENT LIMIT – mA
INPUT BIAS CURRENT – pA
70
+ OUTPUT
CURRENT
50
40
30
– OUTPUT
CURRENT
20
6.0
5.0
4.0
3.0
10
0
–12
0
–9
–6
–3
0
3
6
9
COMMON MODE VOLTAGE – Volts
Figure 7. Input Bias Current vs.
Common-Mode Voltage
12
–60
–40
–20
0
20
40
60
80
100 120
TEMPERATURE – °C
Figure 8. Short Circuit Current
Limit vs. Temperature
–4–
140
2.0
–60 –40
–20
0
20
40
60
80 100 120
140
TEMPERATURE – °C
Figure 9. Gain Bandwidth Product
vs. Temperature
REV. C
AD743
100
100
80
150
3.5
80
GAIN
40
40
20
20
0
0
1M
10k
100k
FREQUENCY – Hz
1k
10M
3.0
–20
0
0
20 40 60 80 100 120 140
TEMPERATURE – °C
POWER SUPPLY REJECTION – dB
60
40
20
15
20
Figure 12. Open-Loop Gain vs.
Supply Voltage, RLOAD = 2K
120
80
10
5
SUPPLY VOLTAGE ± VOLTS
Figure 11. Slew Rate vs.
Temperature (Gain = –1)
120
COMMON-MODE REJECTION – dB
80
2.0
–60 –40
Figure 10. Open-Loop Gain and
Phase vs. Frequency
VCM = ±10V
120
100
–20
100M
100
130
2.5
35
30
100
+ SUPPLY
OUTPUT VOLTAGE – Volts p-p
–20
100
OPEN-LOOP GAIN – dB
60
SLEW RATE – Volts/µs
140
60
PHASE MARGIN – Degrees
OPEN-LOOP GAIN – dB
PHASE
80
60
40
– SUPPLY
20
25
20
15
R L= 2kΩ
10
5
1k
10k
100k
FREQUENCY – Hz
0
100
1M
–100
GAIN = +10
–120
GAIN = –1
–130
100
1k
FREQUENCY – Hz
10k
100k
Figure 16. Total Harmonic Distortion vs. Frequency
NOISE VOLTAGE (REFERRED TO INPUT) – nV Hz
–90
THD – dB
1M
10M
0
100M
1k
10k
CLOSED-LOOP GAIN = 1
10
1.0
CLOSED-LOOP GAIN = 10
0.1
1
10
100
1k
10k
100k
FREQUENCY – Hz
1M
Figure 17. Input Noise Voltage
Spectral Density
–5–
100k
1M
FREQUENCY – Hz
100
–80
REV. C
100k
Figure 14. Power Supply Rejection
vs. Frequency
–70
–140
10
10k
FREQUENCY – Hz
Figure 13. Common-Mode Rejection vs. Frequency
–110
1k
Figure 15. Large Signal Frequency
Response
CURRENT NOISE SPECTRAL DENSITY – fA/ Hz
0
100
10M
1k
100
10
1.0
1
10
1k
100
FREQUENCY – Hz
10k
Figure 18. Input Noise Current
Spectral Density
100k
AD743 –Typical Characteristics (@ +25°C, V = +15 V)
S
69
63
NUMBER OF UNITS
57
51
45
39
33
27
21
15
9
3
2.5
2.7
3.3
2.9
3.1
INPUT VOLTAGE NOISE – nV Hz
3.5
3.8
Figure 22b. Unity-Gain Follower
Small Signal Pulse Response
Figure 19. Typical Noise Distribution
@ 10 kHz (602 Units)
100pF
2kΩ
+V S
2kΩ
VIN
7
0.1µF
1µF
2
VOUT
6
AD743
CL
100pF
3
SQUARE WAVE
INPUT
4
–VS
1µF
0.1µF
Figure 23a. Unity-Gain Inverter
Figure 20. Offset Null Configuration
Figure 23b. Unity-Gain Inverter
Large Signal Pulse Response
Figure 21. Unity-Gain Follower
Figure 22a. Unity-Gain Follower
Large Signal Pulse Response
Figure 23c. Unity-Gain Inverter
Small Signal Pulse Response
–6–
REV. C
AD743
OP AMP PERFORMANCE: JFET VS. BIPOLAR
DESIGNING CIRCUITS FOR LOW NOISE
The AD743 is the first monolithic JFET op amp to offer the low
input voltage noise of an industry-standard bipolar op amp
without its inherent input current errors. This is demonstrated
in Figure 24, which compares input voltage noise vs. input
source resistance of the OP27 and the AD743 op amps. From
this figure, it is clear that at high source impedance the low
current noise of the AD743 also provides lower total noise. It is
also important to note that with the AD743 this noise reduction
extends all the way down to low source impedances. The lower
dc current errors of the AD743 also reduce errors due to offset
and drift at high source impedances (Figure 25).
An op amp’s input voltage noise performance is typicaly divided
into two regions: flatband and low frequency noise. The AD743
offers excellent performance with respect to both. The figure of
2.9 nV/√Hz @ 10 kHz is excellent for JFET input amplifier.
The 0.1 Hz to 10 Hz noise is typically 0.38 µV p-p. The user
should pay careful attention to several design details in order to
optimize low frequency noise performance. Random air currents
can generate varying thermocouple voltages that appear as low
frequency noise: therefore sensitive circuitry should be well
shielded from air flow. Keeping absolute chip temperature low
also reduces low frequency noise in two ways: first, the low
frequency noise is strongly dependent on the ambient
temperature and increases above +25°C. Secondly, since the
gradient of temperature from the IC package to ambient is
greater, the noise generated by random air currents, as
previously mentioned, will be larger in magnitude. Chip
temperature can be reduced both by operation at reduced
supply voltages and by the use of a suitable clip-on heat sink, if
possible.
1000
OP27 &
RESISTOR
(—)
INPUT NOISE VOLTAGE – nV/ Hz
R SOURCE
EO
R SOURCE
100
AD743 + RESISTOR
)
(
AD743 & RESISTOR
OR
OP27 & RESISTOR
Low frequency current noise can be computed from the
~
magnitude of the dc bias current ( In = 2qI B ∆f ) and increases
below approximately 100 Hz with a 1/f power spectral density.
For the AD743 the typical value of current noise is 6.9 fA/√Hz
~
at 1 kHz. Using the formula, In = 4kT /R∆f , to compute the
Johnson noise of a resistor, expressed as a current, one can see
that the current noise of the AD743 is equivalent to that of a
3.45 3 108 Ω source resistance.
10
RESISTOR NOISE ONLY
(– – –)
1
100
1k
10k
100k
1M
10M
SOURCE RESISTANCE – Ω
At high frequencies, the current noise of a FET increases
proportionately to frequency. This noise is due to the “real” part
of the gate input impedance, which decreases with frequency.
This noise component usually is not important, since the voltage
noise of the amplifier impressed upon its input capacitance is an
apparent current noise of approximately the same magnitude.
Figure 24. Total Input Noise Spectral Density @ 1 kHz vs.
Source Resistance
INPUT OFFSET VOLTAGE – mV
100
ADOP27G
In any FET input amplifier, the current noise of the internal
bias circuitry can be coupled externally via the gate-to-source
capacitances and appears as input current noise. This noise is
totally correlated at the inputs, so source impedance matching
will tend to cancel out its effect. Both input resistance and input
capacitance should be balanced whenever dealing with source
capacitances of less than 300 pF in value.
10
1.0
AD743 KN
LOW NOISE CHARGE AMPLIFIERS
As stated, the AD743 provides both low voltage and low current
noise. This combination makes this device particularly suitable
in applications requiring very high charge sensitivity, such as
capacitive accelerometers and hydrophones. When dealing with
a high source capacitance, it is useful to consider the total input
charge uncertainty as a measure of system noise.
0.1
100
1k
10k
100k
1M
10M
SOURCE RESISTANCE – Ω
Figure 25. Input Offset Voltage vs. Source Resistance
Charge (Q) is related to voltage and current by the simply stated
fundamental relationships:
Q = CV and I =
dQ
dt
As shown, voltage, current and charge noise can all be directly
related. The change in open circuit voltage (∆V) on a capacitor
will equal the combination of the change in charge (∆Q/C) and
the change in capacitance with a built in charge (Q/∆C).
REV. C
–7–
AD743
Figure 28 shows that these two circuits have an identical
frequency response and the same noise performance (provided
that CS/CF = R1/ R2). One feature of the first circuit is that a
“T” network is used to increase the effective resistance of RB
and improve the low frequency cutoff point by the same factor.
Figures 26 and 27 show two ways to buffer and amplify the
output of a charge output transducer. Both require using an
amplifier which has a very high input impedance, such as the
AD743. Figure 26 shows a model of a charge amplifier circuit.
Here, amplification depends on the principle of conservation of
charge at the input of amplifier A1, which requires that the
charge on capacitor CS be transferred to capacitor CF, thus
yielding an output voltage of ∆Q/CF. The amplifiers input
voltage noise will appear at the output amplified by the noise
gain (1 + (CS/CF)) of the circuit.
–100
DECIBELS REFERENCED TO 1V/ Hz
–110
–120
–130
–140
TOTAL OUTPUT
NOISE
–150
–160
–170
–180
–190
NOISE DUE TO
R B ALONE
–200
NOISE DUE TO
I B ALONE
–210
–220
10M
1
100M
10
100
FREQUENCY – Hz
1k
10k
100k
Figure 28. Noise at the Outputs of the Circuits of Figures
26 and 27. Gain = 10, CS = 3000 pF, RB = 22 MΩ
However, this does not change the noise contribution of RB
which, in this example, dominates at low frequencies. The graph
of Figure 29 shows how to select an RB large enough to minimize
this resistor’s contribution to overall circuit noise. When the
equivalent current noise of RB ((√4kT)/R) equals the noise of IB
Figure 26. A Charge Amplifier Circuit
( 2qIB ), there is diminishing return in making RB larger.
RESISTANCE IN Ω
5.2 x 10
Figure 27. Model for a High Z Follower with Gain
The second circuit, Figure 27, is simply a high impedance
follower with gain. Here the noise gain (1 + (R1/R2)) is the
same as the gain from the transducer to the output. Resistor RB,
in both circuits, is required as a dc bias current return.
10
5.2 x 10 9
5.2 x 10
8
5.2 x 10
7
5.2 x 10 6
1pA
There are three important sources of noise in these circuits.
Amplifiers A1 and A2 contribute both voltage and current noise,
while resistor RB contributes a current noise of:
10pA
100pA
1nA
INPUT BIAS CURRENT
10nA
Figure 29. Graph of Resistance vs. Input Bias Current
where the Equivalent Noise √4kT/R, Equals the Noise
of the Bias Current 2qIB
T
~
∆f
N = 4k
To maximize dc performance over temperature, the source
resistances should be balanced on each input of the amplifier.
This is represented by the optional resistor RB in Figures 26 and
27. As previously mentioned, for best noise performance care
should be taken to also balance the source capacitance designated
by CB. The value for CB in Figure 26 would be equal to CS, in
Figure 27. At values of CB over 300 pF, there is a diminishing
impact on noise; capacitor CB can then be simply a large bypass
of 0.01 µF or greater.
RB
where:
k = Boltzman’s Constant = 1.381 x 10–23 Joules/Kelvin
T = Absolute Temperature, Kelvin (0°C = +273.2 Kelvin)
∆f = Bandwidth – in Hz (Assuming an Ideal “Brick Wall”
Filter)
This must be root-sum-squared with the amplifier’s own current
noise.
–8–
REV. C
AD743
HOW CHIP PACKAGE TYPE AND POWER DISSIPATION
AFFECT INPUT BIAS CURRENT
As with all JFET input amplifiers, the input bias current of the
AD743 is a direct function of device junction temperature, IB
approximately doubling every 10°C. Figure 30 shows the
relationship between bias current and junction temperature for
the AD743. This graph shows that lowering the junction
temperature will dramatically improve IB.
300
TA = +25°C
–6
10
θJ A = 165°C/W
200
100
θJ A = 115°C/W
θ J A = 0°C/W
10–7
VS = ±15V
TA = + 25°C
–8
10
0
5
10–9
10
SUPPLY VOLTAGE – ±Volts
15
Figure 32. Input Bias Current vs. Supply Voltage for
Various Values of θJA
–10
10
–11
10
–12
10
–60 –40
–20 0
20
40 60
80 100 120 140
JUNCTION TEMPERATURE – °C
Figure 30. Input Bias Current vs. Junction Temperature
The dc thermal properties of an IC can be closely approximated
by using the simple model of Figure 31 where current represents
power dissipation, voltage represents temperature, and resistors
represent thermal resistance (θ in °C/Watt).
θJC
TJ
PIN
θCA
θJA
Figure 33. A Breakdown of Various Package Thermal
Resistances
TA
WHERE:
PIN = DEVICE DISSIPATION
TA = AMBIENT TEMPERATURE
TJ = JUNCTION TEMPERATURE
θJC = THERMAL RESISTANCE – JUNCTION TO CASE
θCA = THERMAL RESISTANCE – CASE TO AMBIENT
Figure 31. A Device Thermal Model
REDUCED POWER SUPPLY OPERATION FOR
LOWER IB
Reduced power supply operation lowers IB in two ways: first, by
lowering both the total power dissipation and second, by
reducing the basic gate-to-junction leakage (Figure 32). Figure
34 shows a 40 dB gain piezoelectric transducer amplifier, which
operates without an ac coupling capacitor, over the –40°C to
+85°C temperature range. If the optional coupling capacitor is
used, this circuit will operate over the entire –55°C to +125°C
military temperature range.
From this model TJ = TA + θJA Pin. Therefore, IB can be
determined in a particular application by using Figure 30
together with the published data for θJA and power dissipation.
The user can modify θJA by use of an appropriate clip-on heat
sink such as the Aavid #5801. θJA is also a variable when using
the AD743 in chip form. Figure 32 shows bias current vs.
supply voltage with θJA as the third variable. This graph can be
used to predict bias current after θJA has been computed. Again
bias current will double for every 10°C. The designer using the
AD743 in chip form (Figure 33) must also be concerned with
both θJC and θCA, since θJC can be affected by the type of die
mount technology used.
Typically, θJC’s will be in the 3°C to 5°C/watt range; therefore,
for normal packages, this small power dissipation level may be
ignored. But, with a large hybrid substrate, θJC will dominate
proportionately more of the total θJA.
Figure 34. A Piezoelectric Transducer
AD743
AN INPUT-IMPEDANCE-COMPENSATED,
SALLEN-KEY FILTER
The simple high pass filter of Figure 35 has an important source
of error which is often overlooked. Even 5 pF of input capacitance
in amplifier “A” will contribute an additional 1% of passband
amplitude error, as well as distortion, proportional to the C/V
characteristics of the input junction capacitance. The addition
of the network designated “Z” will balance the source
impedance–as seen by “A”–and thus eliminate these errors.
Figure 36b. An Accelerometer Circuit Employing a
DC Servo Amplifier
A dc servo-loop (Figure 36b) can be used to assure a dc output
which is <10 mV, without the need for a large compensating
resistor when dealing with bias currents as large as 100 nA. For
optimal low frequency performance, the time constant of the
servo loop (R4C2 = R5C3) should be:
Figure 35. An Input Impedance Compensated
Sallen-Key Filter
TWO HIGH PERFORMANCE
ACCELEROMETER AMPLIFIERS

R2 
Time Constant ≥ 10 R11 +
 C1

R3 
Two of the most popular charge-out transducers are hydrophones
and accelerometers. Precision accelerometers are typically
calibrated for a charge output (pC/g).* Figures 36a and 36b
show two ways in which to configure the AD743 as a low noise
charge amplifier for use with a wide variety of piezoelectric
accelerometers. The input sensitivity of these circuits will be
determined by the value of capacitor C1 and is equal to:
∆V OUT =
A LOW NOISE HYDROPHONE AMPLIFIER
∆QOUT
C1
The ratio of capacitor C1 to the internal capacitance (CT) of the
transducer determines the noise gain of this circuit (1 + CT/C1).
The amplifiers voltage noise will appear at its output amplified
by this amount. The low frequency bandwidth of these circuits
will be dependent on the value of resistor R1. If a “T” network
is used, the effective value is: R1 (1 + R2/R3).
Hydrophones are usually calibrated in the voltage-out mode.
The circuits of Figures 37a and 37b can be used to amplify the
output of a typical hydrophone. Figure 37a shows a typical dc
coupled circuit. The optional resistor and capacitor serve to
counteract the dc offset caused by bias currents flowing through
resistor R1. Figure 37b, a variation of the original circuit, has a
low frequency cutoff determined by an RC time constant equal
to:
Time Constant =
1
2π × CC × 100Ω
Figure 36a. A Basic Accelerometer Circuit
*pC = Picocoulombs
g = Earth's Gravitational Constant
Figure 37a. A Basic Hydrophone Amplifier
–10–
REV. C
AD743
Where the dc gain is 1 and the gain above the low frequency
cutoff (1/(2πCC(100 Ω))) is the same as the circuit of Figure
37a. The circuit of Figure 37c uses a dc servo loop to keep the
dc output at 0 V and to maintain full dynamic range for IB’s up
to 100 nA. The time constant of R7 and C2 should be larger
than that of R1 and CT for a smooth low frequency response.
The transducer shown has a source capacitance of 7500 pF. For
smaller transducer capacitances (≤300 pF), lowest noise can be
achieved by adding a parallel RC network (R4 = R1, C1 = CT)
in series with the inverting input of the AD743.
BALANCING SOURCE IMPEDANCES
Figure 37b. An AC-Coupled, Low Noise
Hydrophone Amplifier
As mentioned previously, it is good practice to balance the
source impedances (both resistive and reactive) as seen by the
inputs of the AD743. Balancing the resistive components will
optimize dc performance over temperature because balancing
will mitigate the effects of any bias current errors. Balancing
input capacitance will minimize ac response errors due to the
amplifier’s input capacitance and, as shown in Figure 38, noise
performance will be optimized. Figure 39 shows the required
external components for noninverting (A) and inverting (B)
configurations.
Figure 38. RTI Voltage Noise vs. Input Capacitance
Figure 37c. A Hydrophone Amplifier Incorporating a
DC Servo Loop
Figure 39. Optional External Components for Balancing Source Impedances
REV. C
–11–
AD743
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C1433–24–10/90
8-Pin Plastic Mini-DIP (N)
8-Pin Cerdip (Q) Packages
PRINTED IN U.S.A.
16-Pin SOIC (R) Package
–12–
REV. C