NCV7381 FlexRay) Bus Driver NCV7381 is a single−channel FlexRay bus driver compliant with the FlexRay Electrical Physical Layer Specification Rev. 3.0.1, capable of communicating at speeds of up to 10 Mbit/s. It provides differential transmit and receive capability between a wired FlexRay communication medium on one side and a protocol controller and a host on the other side. NCV7381 mode control functionality is optimized for nodes permanently connected to car battery. It offers excellent EMC and ESD performance. http://onsemi.com KEY FEATURES General SSOP−16 DP SUFFIX CASE 565AE • Compliant with FlexRay Electrical Physical Layer Specification Rev 3.0.1 • FlexRay Transmitter and Receiver in Normal−power Modes for • • • • Communication up to 10 Mbit/s Support of 60 ns Bit Time FlexRay Low−power Mode Receiver for Remote Wakeup Detection Excellent Electromagnetic Susceptibility (EMS) Level over Full Frequency Range. Very Low Electromagnetic Emissions (EME) Bus Pins Protected against >10 kV System ESD Pulses Safe Behavior under Missing Supply or No Supply Conditions Interface Pins for a Protocol Controller and a Host (TxD, RxD, TxEN, RxEN, STBN, BGE, EN, ERRN) INH Output for Control of External Regulators Local Wakeup Pin WAKE TxEN Time−out BGE Feedback Supply Pins VBAT, VCC, VIO with Independent Voltage Ramp Up: ♦ VBAT Supply Parametrical Range from 5.5 V to 50 V ♦ VCC Supply Parametrical Range from 4.75 V to 5.25 V ♦ VIO Supply Parametrical Range from 2.3 V to 5.25 V Compatible with 14 V and 28 V Systems Operating Ambient Temperature −40°C to +125°C (TAMB_Class1) Junction Temperature Monitoring with Two Levels SSOP−16 Package • • • • Bus Driver Voltage Regulator Control Bus Driver – Bus Guardian Interface Bus Driver Logic Level Adaptation Bus Driver Remote Wakeup • • • • • • • • • • • FlexRay Functional Classes MARKING DIAGRAM 16 NV7381−0 AWLYYWW G 1 A = Assembly Location WL = Wafer Lot YYWW = Year / Work Week G = Pb−Free Package PIN CONNECTIONS INH EN VIO TxD TxEN RxD BGE STBN 1 VCC BP BM GND WAKE VBAT ERRN RxEN (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 23 of this data sheet. Quality • Automotive Qualification According to AEC−Q100 (Rev. F) © Semiconductor Components Industries, LLC, 2012 May, 2012 − Rev. 0 1 Publication Order Number: NCV7381/D NCV7381 VIO VCC Voltage Monitoring VBAT Thermal Shutdown TxD INH CC Module TxEN RxD Transmitter RxEN BGE Module BGE BP STBN CONTROL LOGIC Host Module ERRN Bus Error Detection BM EN Receiver VBAT Wakeup Detection WAKE (Normal mode / Low−power mode) NCV7381 GND Figure 1. Block Diagram Table 1. PIN DESCRIPTION Pin Number Pin Name Pin Type 1 INH high−voltage analog output 2 EN digital input Mode control input; internal pull−down resistor 3 VIO supply Supply voltage for digital pins level adaptation 4 TxD digital input Data to be transmitted; internal pull−down resistor 5 TxEN digital input Transmitter enable input; when High transmitter disabled; internal pull−up resistor 6 RxD digital output 7 BGE digital input Bus guardian enable input; when Low transmitter disabled; internal pull−down resistor 8 STBN digital input Mode control input; internal pull−down resistor 9 RxEN digital output Bus activity detection output; when Low bus activity detected 10 ERRN digital output Error diagnosis and status output 11 VBAT supply 12 WAKE high−voltage analog input 13 GND ground 14 BM high−voltage analog input/output Bus line minus 15 BP high−voltage analog input/output Bus line plus 16 VCC supply Pin Function External regulator control output Receive data output Battery supply voltage Local wake up input; internal pull up or pull down (depends on voltage at pin WAKE) Ground connection Bus driver core supply voltage; 5 V nominal http://onsemi.com 2 NCV7381 APPLICATION INFORMATION ECU INH VIO reg. OUT CVCC CVIO FlexRay Communication Controller Bus Guardian INH VCC reg. OUT MCU VBAT IN IN VIO VCC CVBAT RWAKE2 TxD WAKE WAKE TxEN RxD NCV7381 RxEN BGE STBN Host Interface RWAKE1 INH VBAT CMC BP BP BM BM RBUS1 EN ERRN GND RBUS2 CBUS GND Figure 2. Application Diagram Table 2. RECOMMENDED EXTERNAL COMPONENTS FOR THE APPLICATION DIAGRAM Component Function Min Typ Max Unit CVBAT Decoupling capacitor on battery line, ceramic 100 nF CVCC Decoupling capacitor on VCC supply line, ceramic 100 nF CVIO Decoupling capacitor on VIO supply line, ceramic 100 nF RWAKE1 Pull−up resistor on WAKE pin 33 kW RWAKE2 Serial protection resistor on WAKE pin 3.3 kW RBUS1 Bus termination resistor (Note 1) 47.5 W RBUS2 Bus termination resistor (Note 1) 47.5 W CBUS Common−mode stabilizing capacitor, ceramic (Note 2) 4.7 nF CMC Common−mode choke 100 mH 1. Tolerance ±1%, type 0805 2. Tolerance ±20%, type 0805 http://onsemi.com 3 NCV7381 FUNCTIONAL DESCRIPTION Operating Modes correct transition between any mode and the Sleep mode. All three modes – Standby, Sleep and Go−to−sleep – are referred to as low−power modes. The operating mode selected is a function of the host signals STBN and EN, the state of the supply voltages and the wakeup detection. As long as all three supplies (VBAT, VCC, VIO) remain above their respective under−voltage detection levels, the logical control by EN and STBN pins shown in Figure 3 applies. Influence of the power−supplies and of the wakeup detection on the operating modes is described in subsequent paragraphs. NCV7381 can switch between several operating modes depicted in Figure 3. In Normal and Receive−only modes, the chip interconnects a FlexRay communication controller with the bus medium for full−speed communication. These two modes are also referred to as normal−power modes. In Standby and Sleep modes, the communication is suspended and the power consumption is substantially reduced. A wakeup on the bus or through a locally monitored signal on pin WAKE can be detected and signaled to the host. Go−to−sleep mode is a temporary mode ensuring Normal Mode STBN=H EN=H Receive−only Mode Transmitter: on Receiver: on INH: High Power cons.: normal EN=H EN=L STBN=H STBN=H EN=H EN=L STBN=L STBN=L STBN=H EN=H STBN=L EN=L Transmitter: off Receiver: on INH: High Power cons.: normal STBN=H STBN=H Standby Mode Transmitter: off Receiver: wakeup−detection INH: High Power cons.: low EN=H EN=L STBN=L EN=H STBN=L EN=L STBN=H EN=L STBN=L EN=H Go−to−sleep Mode Transmitter: off Receiver: wakeup−detection INH: High Power cons.: low Power−up STBN=L, EN=H for >dGo−to−Sleep STBN=L, EN=H for <dGo−to−Sleep Sleep Mode Transmitter: off Receiver: wakeup−detection INH: floating Power cons.: low Figure 3. Operating Modes and their Control by the STBN and EN Pins http://onsemi.com 4 STBN=H EN=L NCV7381 Normal Mode Receive−Only Mode Standby Mode Go−to−sleep Mode Sleep Mode Normal Mode STBN EN ERRN Error Flag Error Flag Wake Flag Wake Flag Error Flag dGo−to−sleep dBDModeChange dBDModeChange dBDModeChange dBDModeChange Figure 4. Timing Diagram of Operating Modes Control by the STBN and EN Pins Power Supplies and Power Supply Monitoring All three supplies are monitored by under−voltage detectors with individual thresholds and filtering times both for under−voltage detection and recovery – see Table 18. NCV7381 is supplied by three pins. VBAT is the main supply both for NCV7381 and the full electronic module. VBAT will be typically connected to the automobile battery through a reverse−polarity protection. VCC is a 5 V low−voltage supply primarily powering the FlexRay bus driver core in a normal−power mode. VIO supply serves to adapt the logical levels of NCV7381 to the host and/or the FlexRay communication controller digital signal levels. All supplies should be properly decoupled by filtering capacitors − see Figure 2 and Table 2. Logic Level Adaptation Level shift input VIO is used to apply a reference voltage uVDIG = uVIO to all digital inputs and outputs in order to adapt the logical levels of NCV7381 to the host and/or the FlexRay communication controller digital signal levels http://onsemi.com 5 NCV7381 Internal Flags The NCV7381 control logic uses a number of internal flags (i.e. one−bit memories) reflecting important conditions or events. Table 3 summarizes the individual flags and the conditions that lead to a set or reset of the flags. Table 3. INTERNAL FLAGS Flag Set Condition Reset Condition Comment Local Wakeup Low level detected on WAKE pin in a low− power mode Low−power mode is entered Remote Wakeup Remote wakeup detected on the bus in a low−power mode Low−power mode is entered Wakeup Local Wakeup flag changes to set or Remote Wakeup flag changes to set Normal mode is entered or Low−power mode is entered or Any under−voltage flag becomes set Power−on Internal power supply of the chip becomes sufficient for the operation of the control logic Normal mode is entered Thermal Warning Junction temperature is higher than Tjw (typ. 140°C) in a normal−power mode and VBAT is not in under−voltage (Junction temperature is below Tjw in a normal−power mode or the status register is read in a low−power mode) and VBAT is not in under−voltage The thermal warning flag has no influence on the bus driver function Thermal Shutdown Junction temperature is higher than Tjsd (typ. 165°C) in a normal−power mode and VBAT is not in under−voltage Junction temperature is below Tjsd in a normal−power mode and falling edge on TxEN and VBAT is not in under−voltage The transmitter is disabled as long as the thermal shutdown flag is set TxEN Timeout TxEN is Low for longer than dBDTxActiveMax (typ. 1.5 ms) and bus driver is in Normal mode TxEN is High or Normal mode is left The transmitter is disabled as long as the timeout flag is set Bus Error Transmitter is enabled and Data on bus are different from TxD signal (sampled after each TXD edge) (Transmitter is enabled and Data on bus are identical to TxD signal) or Transmitter is disabled The bus error flag has no influence on the bus driver function VBAT Under− voltage VBAT is below the under−voltage threshold for longer than dBDUVVBAT VBAT is above the under−voltage threshold for longer than dBDRVBAT or Wake flag becomes set VCC Under− voltage VCC is below the under−voltage threshold for longer than dBDUVVCC VCC is above the under−voltage threshold for longer than dBDRVCC or Wake flag becomes set VIO Under− voltage VIO is below the under−voltage threshold for longer than dUVIO VIO is above the under−voltage threshold for longer than dBDRVIO or Wake flag becomes set Error Any of the following status bits is set: • Bus error • Thermal Warning • Thermal Shutdown • TxEN Timeout • VBAT Under−voltage • VCC Under−voltage • VIO Under−voltage All of the following status bits are reset: • Bus error • Thermal Warning • Thermal Shutdown • TxEN Timeout • VBAT Under−voltage • VCC Under−voltage • VIO Under−voltage http://onsemi.com 6 NCV7381 Operating Mode Changes Caused by Internal Flags FlexRay Bus Driver Changes of some internal flags described in Table 3 can force an operating mode transition complementing or overruling the operating mode control by the digital inputs STBN and EN which is shown in Figure 3: • Setting the VBAT or VIO under−voltage flag causes a transition to the Sleep mode • Setting the VCC under−voltage flag, while the bus driver is not in Sleep, causes a transition to the Standby mode • Reset of the Under−voltage flag (i.e. recovery from under−voltage) re−enables the control of the chip by digital inputs STBN and EN. • Setting of the Wake flag causes the reset of all under−voltage flags and the NCV7381 transitions to the Standby mode. The reset of the under−voltage flags allows the external power supplies to stabilize properly if, for example, they were previously switched off during Sleep mode. NCV7381 contains a fully−featured FlexRay bus driver compliant with Electrical Physical Layer Specification Rev. 3.0.1. The transmitter part translates logical signals on digital inputs TxEN, BGE and TxD into appropriate bus levels on pins BP and BM. A transmission cannot be started with Data_1. In case the transmitter is enabled for longer than dBDTxActiveMax, the TxEN Timeout flag is set and the current transmission is disabled. The receiver part monitors bus pins BP and BM and signals the detected levels on digital outputs RxD and RxEN. The different bus levels are defined in Figure 5. The function of the bus driver and the related digital pins in different operating modes is detailed in Table 4 and Table 5. • The transmitter can only be enabled if the activation of the transmitter is initiated in Normal mode. • The receiver function is enabled by entering a normal−power mode. uBus BP VCC/2 BM Idle_LP Idle Data_0 Data_1 Figure 5. FlexRay Bus Signals Table 4. TRANSMITTER FUNCTION AND TRANSMITTER−RELATED PINS Operating Mode BGE TxEN TxD Transmitted Bus Signal Standby, Go−to−sleep, Sleep x x x Idle_LP Receive−only x x x Idle Normal 0 x x Idle 1 1 x Idle 1 0 0 Data_0 1 0 1 Data_1 Table 5. RECEIVER FUNCTION AND RECEIVER−RELATED PINS Operating Mode Signal on Bus Wake flag RxD RxEN Standby, Go−to−sleep, Sleep x not set High High x set Low Low Idle x High High Data_0 x Low Low Data_1 x High Low Normal, Receive−only http://onsemi.com 7 NCV7381 Bus Guardian Interface Bus Driver Remote Wakeup Detection The interface consists of the BGE digital input signal allowing a Bus Guardian unit to disable the transmitter and of the RxEN digital output signal used to signal whether the communication signal is Idle or not. During a low−power mode and under the presence of VBAT voltage, a low−power receiver constantly monitors the activity on bus pins BP and BM. A valid remote wake−up is detected when either a wakeup pattern or a dedicated wakeup frame is received. A valid remote wake−up is also detected when wake−up pattern has been started in normal−power mode already. A wakeup pattern is composed of two Data_0 symbols separated by Data_1 or Idle symbols. The basic wakeup pattern composed of Data_0 and Idle symbols is shown in Figure 6; the wakeup pattern composed of Data_0 and Data_1 symbols – referred to as “alternative wakeup pattern” − is depicted in Figure 7. Bus Driver Voltage Regulator Control NCV7381 provides a high−voltage output pin INH which can be used to control an external voltage regulator (see Figure 2). The pin INH is driven by a switch to VBAT supply. In Normal, Receive−only, Standby and Go−to−Sleep modes, the switch is activated thus forcing a High level on pin INH. In the Sleep mode, the switch is open and INH pin remains floating. If a regulator is directly controlled by INH, it is then active in all operating modes with the exception of the Sleep mode. uBus <dWUTimeout >dWU0Detect Data_0 Idle(_LP) Data_0 >dWUIdleDetect 0 uData0_LP Idle(_LP) Idle(_LP) detected >dWUIdleDetect Remote wakeup >dWU0Detect Figure 6. Valid Remote Wakeup Pattern <dWUTimeout >dWUIdleDetect Data_0 Data_1 >dWU0Detect >dWUIdleDetect 0 uData0_LP Idle(_LP) Data_0 Figure 7. Valid Alternative Remote Wakeup Pattern Data_1 detected >dWU0Detect Remote wakeup uBus A remote wakeup will be also detected if NCV7381 receives a full FlexRay frame at 10 Mbit/s with the following payload data: 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF The wakeup pattern, the alternative wakeup pattern and the wakeup frame lead to identical wakeup treatment and signaling. Local Wakeup Detection Internal pull−up and pull−down current sources are connected to WAKE pin in order to minimize the risk of parasitic toggling. The current source polarity is automatically selected based on the WAKE input signal polarity – when the voltage on WAKE stays stable High (Low) for longer than dWakePulseFilter, the internal current source is switched to pull−up (pull−down). The high−voltage input WAKE is monitored in low−power modes and under the condition of sufficient VBAT supply level. If a falling edge is recognized on WAKE pin, a local wakeup is detected. In order to avoid false wakeups, the Low level after the falling edge must be longer than dWakePulseFilter in order for the wakeup to be valid. The WAKE pin can be used, for example, for switch or contact monitoring. http://onsemi.com 8 NCV7381 ERRN Pin and Status Register state of the internal “Error” or the wakeup source (See Table 6). The polarity of the indication is reversed – ERRN pin is pulled Low when the “Error” flag is set. The signaling on pin ERRN functions in all operating modes. Provided VIO supply is present together with either VBAT or VCC, the digital output ERRN indicates the state of the internal “Error” flag when in Normal mode and the state of the internal “Wake” flag when in Standby, Go−to−Sleep or Sleep. In Receive−only mode ERRN indicates either the Table 6. SIGNALING ON ERRN PIN STBN EN Conditions Error flag Wake flag ERRN High High − not set x High set x Low not set x High set x Low x Set local High x Set remote Low x not set High x set Low High Low EN has been set to High after previous wakeup EN has not been set to High after previous wakeup Low x − read−out continues. As soon as the EN level is stable for more than dBDModeChange, the read−out is considered as finished and the operating mode is changed according the current EN value. At the same time, the status register bits S4 to S10 are reset provided the particular bits have been read−out and the corresponding flags are not set any more – see Table 7. The status register read−out always starts with bit S0 and the exact number of bits shifted to ERRN during the read−out is not relevant. Additionally, a full set of internal bits referred to as status register can be read through ERRN pin with EN pin used as a clock signal – the status register content is described in Table 7 while an example of the read−out waveforms is shown in Figure 8 and Figure 9. The individual status bits are channeled to ERRN pin with reversed polarity (if a status bit is set, ERRN is pulled Low) at the falling edge on EN pin (the status register starts to be shifted only at the second falling edge). As long as the EN pin toggling period falls in the dENSTAT range, the operating mode is not changed and the Table 7. STATUS REGISTER Bit Number Status Bit Content Note Reset after Finished Read−out S0 Local wakeup flag reflects directly the corresponding flag no S1 Remote wakeup flag S2 not used; always High S3 Power−on status S4 Bus error status the status bit is set if the corresponding flag was set previously (the respective High level of the flag is latched in its status counter−part) S5 Thermal shutdown status yes, if the corresponding flag is reset and the bit was read−out S6 Thermal warning status S7 TxEN Timeout status S8 VBAT Under−voltage status S9 VCC Under−voltage status S10 VIO Under−voltage status S11 BGE Feedback Normal mode: BGE pin logical state (Note 3) Other modes: Low − S12−S15 not used; always Low S16−S23 Version of the NCV7381 analog part S24−S31 Version of the NCV7381 digital part no no fixed values identifying the production masks version 3. The BGE pin state is latched during status register read−out at rising edge of the EN pin. http://onsemi.com 9 no NCV7381 Receive−Only Normal Mode Mode STBN dENSTAT_L dENSTAT_H EN Error Flag S0 S1 dBDModeChange Sx Figure 8. Example of the Status Register Read−out (Started with EN High) Error Flag reset ERRN dEN_ERRN Status register dENSTAT Receive−Only Mode STBN dENSTAT_L dENSTAT_H EN Error Flag S0 S1 dBDModeChange Sx Figure 9. Example of the Status Register Read−out (Started with EN Low) http://onsemi.com 10 Error Flag reset ERRN dEN_ERRN Status register dENSTAT NCV7381 Table 8. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Units uVBAT−MAX Battery voltage power supply −0.3 50 V uVCC−MAX 5 V Supply voltage −0.3 5.5 V uVIO−MAX Supply voltage for VIO voltage level adaptation −0.3 5.5 V uDigInMAX DC voltage at digital inputs (BGE, EN, STBN, TXD, TXEN) −0.3 5.5 V DC voltage at digital outputs (ERRN, RxD, RxEN) −0.3 VIO+0.3 V Digital output pins input current (VIO = 0 V) −10 +10 mA uBMMAX DC voltage at pin BM −50 50 V uBPMAX DC voltage at pin BP −50 50 V uINHMAX DC voltage at pin INH −0.3 VBAT+0.3 V iINHMAX INH pin maximum load current −10 − mA DC voltage at WAKE pin −0.3 VBAT+0.3 V Junction temperature −40 175 °C Storage Temperature Range −55 150 °C uESDIEC System HBM on pins BP and BM (as per IEC 61000−4−2; 150 pF / 330 W) −10 +10 kV uESDEXT Component HBM on pins BP, BM, VBAT and WAKE (as per EIA−JESD22−A114−B; 100 pF / 1500 W) −6 +6 kV uESDINT Component HBM on all other pins (as per EIA−JESD22−A114−B; 100 pF / 1500 W) −4 +4 kV uVTRAN Voltage transients, pins BP, BM, VBAT and WAKE. According to ISO7637−2, Class C (Note 4) −100 − V test pulses 2a − +75 V test pulses 3a −150 − V test pulses 3b − +100 V Voltage transients, pin VBAT. According to ISO7637−2 test pulse 5 Load Dump − 50 V Overvoltage, pin VBAT, according to ISO16750−2 Jump Start − 50 V uDigOutMAX iDigOutIN−MAX uWAKEMAX TJ_MAX TSTG test pulses 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. Test is carried out according to setup in FlexRay Physical Layer EMC Measurement Specification, Version 3.0. This specification is referring to ISO7637. Test for higher voltages is planned. Table 9. OPERATING RANGES Symbol Parameter Min Max Units uVBAT−OP Battery voltage power supply 5.5 50 V uVCC−OP Supply voltage 5 V 4.75 5.25 V uVIO−OP Supply voltage for VIO voltage level adaptation 2.3 5.25 V 0 VBAT V uWAKEOP DC voltage at WAKE pin uDigIOOP DC voltage at digital pins (EN, TXD, TXEN, RXD, RXEN, BGE, STBN, ERRN) 0 VIO V uBMOP DC voltage at pin BM −50 50 V uBPOP DC voltage at pin BP −50 50 V uINHOP DC voltage at pin INH 0 VBAT V TAMB Ambient temperature (Note 5) −40 125 °C TJ_OP Junction temperature −40 150 °C 5. The specified range corresponds to TAMB_Class1 http://onsemi.com 11 NCV7381 THERMAL CHARACTERISTICS Table 10. PACKAGE THERMAL RESISTANCE Symbol Rating Value Unit RθJA_1 Thermal Resistance Junction−to−Air, JEDEC 1S0P PCB 78 °C/W RθJA_2 Thermal Resistance Junction−to−Air, JEDEC 2S2P PCB 69 °C/W ELECTRICAL CHARACTERISTICS The characteristics defined in this section are guaranteed within the operating ranges listed in Table 9, unless otherwise specified. Positive currents flow into the respective pin. Table 11. CURRENT CONSUMPTION Symbol Parameter Conditions iVBAT−NORM Current consumption from VBAT normal−power modes Typ Max Unit 0.65 1 mA low−power modes; TAMB=125°C 75 mA Sleep mode, VIO = VCC = 0 V; TAMB = 125°C 80 mA low−power modes, VIO = VCC = 0 V, VBAT = 12 V, TJ < 85°C (Note 6) 55 mA Normal mode – bus signals Idle 15 mA iVCC−NORM−ACTIVE Normal mode – bus signals Data_0/1 RBUS = 40−55 W 37 mA iVCC−REC Receive−only mode 15 mA iVCC−LP low−power modes, TJ < 85°C (Note 6) 8 mA normal−power modes 1 mA low−power modes, TJ < 85°C (Note 6) 6 mA low−power modes; TAMB = 125°C 95 mA Sleep mode, VIO = VCC = 5 V, VBAT = 12 V, TJ < 85°C (Note 6) 65 mA Sleep mode, VIO = VCC = 5 V, VBAT = 12 V, TJ < 25°C (Note 6) 55 mA iVBAT−LP iVCC−NORM−IDLE iVIO−NORM Current consumption from VCC Current consumption from VIO iVIO−LP iTot−LP Total current consumption – Sum from all supply pins 6. Values based on design and characterization, not tested in production http://onsemi.com 12 Min NCV7381 Table 12. TRANSMISSION PARAMETERS Symbol Parameter Conditions Min uBDTxactive Differential voltage |uBP−uBM| when sending symbol “Data_0” or “Data_1” uBDTxIdle Differential voltage |uBP−uBM| when driving signal “Idle” RBUS = 40−55 W; CBUS = 100 pF Parameters defined in Figure 10. dBDTx10 Transmitter delay, negative edge dBDTx01 Transmitter delay, positive edge dBDTxAsym Transmitter delay mismatch, |dBDTx10−dBDTx01| (Note 7) dBusTx10 Fall time of the differential bus voltage from 80% to 20% dBusTx01 Rise time of the differential bus voltage from 20% to 80% dBusTxDif Differential bus voltage fall and rise time mismatch |dBusTx10−dBusTx01| dBDTxia Transmitter delay idle −> active dBDTxai Transmitter delay active −> idle dBDTxDM Idle−active transmitter delay mismatch | dBDTxia − dBDTxai | dBusTxia Transition time idle −> active dBusTxai Transition time active −> idle dTxENLOW dBDTxActiveMax iBPBMShortMax iBMBPShortMax Test setup as per Figure 17 with RBUS = 40 W; CBUS = 100 pF Sum of TXD signal rise and fall time (20%−80% VIO) of up to 9 ns Parameters defined in Figure 10. Typ Max Unit 600 2000 mV 0 30 mV 75 ns 75 ns 4 ns 6 18.75 ns 6 18.75 ns 3 ns 75 ns 75 ns 50 ns 30 ns 30 ns Test setup as per Figure 17 with RBUS = 40 W; CBUS = 100 pF Parameters defined in Figure 11. Time span of bus activity 550 650 ns Maximum length of transmitter activation 650 2600 ms Absolute maximum output current when BP shorted to BM – no time limit RShortCircuit ≤ 1 W 60 mA iBPGNDShortMax iBMGNDShortMax Absolute maximum output current when shorted to GND – no time limit RShortCircuit ≤ 1 W 60 mA iBP−5VShortMax iBM−5VShortMax Absolute maximum output current when shorted to VBAT = −5 V – no time limit RShortCircuit ≤ 1 W 60 mA iBPBAT27ShortMax iBMBAT27ShortMax Absolute maximum output current when shorted to VBAT = 27 V – no time limit RShortCircuit ≤ 1 W 60 mA iBPBAT48ShortMax iBMBAT48ShortMax Absolute maximum output current when shorted to VBAT = 48 V – no time limit RShortCircuit ≤ 1 W 72 mA 500 W RBDTransmitter Bus interface equivalent output impedance (Bus driver simulation model parameter) 31 7. Guaranteed for ±300 mV and ±150 mV level of uBus http://onsemi.com 13 105 NCV7381 uTxD 100...4400 ns 100% VIO 50% VIO 0% VIO dBDTx01 dBDTx10 uBus uBDTxActive 100% 80% 300 mV −300 mV 20% −uBDTxActive 0% dBusTx01 dBusTx 10 Figure 10. Transmission Parameters (TxEN is Low and BGE is High) NOTE: TXD signal is constant for 100..4400 ns before the first edge. All parameters values are valid even if the test is performed with opposite polarity. uTxEN dTxENLOW 100% VIO 50% VIO 0% VIO dBDTxia dBDTxai uBus −30 mV −300 mV −uBDTx dBusTxai dBusTxia Figure 11. Transmission Parameters for Transitions between Idle and Active (TXD is Low) http://onsemi.com 14 NCV7381 Table 13. RECEPTION PARAMETERS Symbol Parameter uData0 Receiver threshold for detecting Data_0 uData1 Receiver threshold for detecting Data_1 |uData1|−|uData0| uData0_LP Mismatch of receiver thresholds Low power receiver threshold for detecting Data_0 uCM Common mode voltage range (with respect to GND) that does not disturb the receiver function and reception level parameters uBias Bus bias voltage during bus state Idle in normal−power modes Bus bias voltage during bus state Idle in low−power modes RCM1, RCM2 Receiver common mode resistance C_BP, C_BM Conditions Min Activity detected previously. |uBP−uBM| ≤ 3 V Typ Max Unit −300 −150 mV 150 300 mV (uBP+uBM)/2 = 2.5 V −30 30 mV uVBAT ≥ 7 V −400 −100 mV uBP = (uBP+uBM)/2 (Note 8) −10 15 V RBUS = 40−55 W; CBUS = 100 pF (Note 9) 1800 2500 3200 mV −200 0 200 mV (Note 9) 10 40 kW Input capacitance on BP and BM pin (Note 10) f = 5 MHz 20 pF C_BusDIF Bus differential input capacitance (Note 10) f = 5 MHz 5 pF iBPLEAK iBMLEAK Absolute leakage current when driver is off uBP = uBM = 5 V All other pins = 0 V 25 mA iBPLEAKGND iBMLEAKGND Absolute leakage current, in case of loss of GND uBP = uBM = 0 V All other pins = 16 V 1600 mA uBusRxData Test signal parameters for reception of Data_0 and Data_1 symbols 400 3000 mV 60 4330 ns 60 4330 ns 22.5 ns dBusRx0BD Test signal and parameters defined in Figure 12 and Figure 13. dBusRx1BD dBusRx10 RxD pin loaded with 25 pF capacitor. dBusRx01 22.5 ns dBDRx10 Receiver delay, negative edge (Note 11) 75 ns dBDRx01 Receiver delay, positive edge (Note 11) 75 ns Receiver delay mismatch | dBDRx10− dBDRx01| (Note 11) 5 ns 400 3000 mV 590 610 ns dBusIdle 590 610 ns dBusRxia 18 22 ns dBDRxAsym uBusRx dBusActive Test signal parameters for bus activity detection dBusRxai 18 22 ns Bus driver filter−time for idle detection 50 200 ns Bus driver filter−time for activity detection 100 250 ns dBDRxai Bus driver idle reaction time 50 275 ns dBDRxia Bus driver activity reaction time 100 325 ns 325 ns dBDIdleDetection dBDActivityDetection dBDTxRxai Idle−Loopdelay 8. Tested on a receiving bus driver. Sending bus driver has a ground offset voltage in the range of [−12.5 V to +12.5 V] and sends a 50/50 pattern. 9. Bus driver is connected to GND and uVCC = 5 V and uVBAT ≥ 7 V. 10. Values based on design and characterization, not tested in production. 11. Guaranteed for ±300 mV and ±150 mV level of uBus. http://onsemi.com 15 NCV7381 Table 14. REMOTE WAKEUP DETECTION PARAMETERS Symbol Parameter dWU0Detect Conditions Min Typ Max Unit Detection time for Wakeup Data_0 symbol 1 4 ms Detection time for Wakeup Idle/Data_1 symbol 1 4 ms dWUTimeout Maximum accepted Wakeup pattern duration 48 140 ms dWUInterrupt Acceptance timeout for interruptions 0.13 1 ms uVBAT−WAKE Minimum supply voltage VBAT for remote wakeup events detection − 5.5 V Reaction time after remote wakeup event 7 35 ms dWUIdleDetect dBDWakeup Reactionremote (Note 12) 12. The minimum value is only guaranteed, when the phase that is interrupted was continuously present for at least 870 ns. Table 15. TEMPERATURE MONITORING PARAMETERS Symbol Parameter Conditions Min Typ Max Unit Tjw Thermal warning level 125 140 150 °C Tjsd Thermal shut−down level 150 165 180 °C dBusRx10 uBus dBusRx01 uBusRxData 300 mV 150 mV −150 mV −300 mV −uBusRxData dBusRx0BD dBusRx1BD uRxD 100% VIO dBDRx10 dBDRx01 50% VIO 0% VIO Figure 12. Reception Parameters http://onsemi.com 16 NCV7381 dBusRxia uBus dBusRxai −30 mV −150 mV −300 mV −uBusRx dBusActive uRxD dBusIdle dBDRxia dBDRxai 100% VIO 50% VIO 0% VIO uRxEN 100% VIO 50% VIO 0% VIO Figure 13. Parameters of Bus Activity Detection Table 16. WAKE PIN PARAMETERS Symbol uVBAT−WAKE uWAKETH Parameter Conditions Min Typ Minimum supply voltage VBAT for local wakeup events detection Threshold of wake comparator Max Unit 7 V VBAT/2 V dBDWakePulseFilter Wake pulse filter time (spike rejection) 1 500 ms dBDWakeup Reactionlocal Reaction time after local wakeup event 14 50 ms uWAKE = 0 V for longer than dWakePulseFilter 3 11 mA uWAKE = VBAT for longer than dWakePulseFilter −11 −3 mA iWAKEPD Internal pull−down current iWAKEPU Internal pull−up current Table 17. INH PIN PARAMETERS Symbol uINH1Not_Sleep iINH1LEAK Parameter Voltage on INH pin, when signaling Not_Sleep Conditions Min Typ Max Unit iINH = −5 mA uVBAT > 5.5 V uVBAT − 0.6 uVBAT −0.27 uVBAT −0.1 V 5 mA Max Unit Leakage current while signaling Sleep −5 Table 18. POWER SUPPLY MONITORING PARAMETERS Symbol Parameter Conditions Min Typ uBDUVVBAT VBAT under−voltage threshold 4 5.5 V uBDUVVCC VCC under−voltage threshold 4 4.5 V uUVIO VIO under−voltage threshold 2 2.3 V uBDUVVBAT−WAKE VBAT under−voltage threshold for correct detection of the local wakeup 5 7 V uUV_HYST Hysteresis of the under−voltage detectors 20 200 mV http://onsemi.com 17 100 NCV7381 Table 18. POWER SUPPLY MONITORING PARAMETERS Symbol Parameter Conditions Min Typ Max Unit dBDUVVCC VCC Undervoltage detection time 150 350 750 ms dBDUVVIO VIO Undervoltage detection time 150 350 750 ms dBDUVVBAT VBAT Undervoltage detection time 350 750 1500 ms dBDRVCC VCC Undervoltage recovery time 1.5 4.5 ms dBDRVIO VIO Undervoltage recovery time 1 ms VBAT Undervoltage recovery time 1 ms dBDRVBAT Table 19. HOST INTERFACE PARAMETERS Symbol dBDModeChange dGo−to−Sleep dReactionTimeERRN Parameter Conditions Min Typ Max Unit EN and STBN level filtering time for operating mode transition 21 65 ms Go to Sleep mode timeout 14 33 ms Error detected 33 ms Wakeup detected or Mode changed 1 ms Reaction time on ERRN pin Digital Input Signals Table 20. DIGITAL INPUT SIGNALS VOLTAGE THRESHOLDS (Pins EN, STBN, BGE, TxEN) Symbol Parameter uVDIG−IN−LOW Low level input voltage uVDIG−IN−HIGH High level input voltage Conditions Min uVDIG = uVIO Typ Max Unit −0.3 0.3*VIO V 0.7*VIO 5.5 V Table 21. EN PIN PARAMETERS Symbol Parameter RPD_EN Pull−down resistance iENIL Low level input current Conditions uEN = 0 V Min Typ Max Unit 50 110 200 kW −1 0 1 mA 20 ms dENSTAT EN toggling period for status register read−out 2 dENSTAT_L, dENSTAT_H Duration of EN Low and High level for status register read−out 1 dEN_ERRN Delay from EN falling edge to ERRN showing valid signal during status register read−out ms 1 ms Table 22. STBN PIN PARAMETERS Symbol Parameter RPD_STBN Pull−down resistance iSTBNIL Low level input current Conditions Min Typ Max Unit 50 110 200 kW uSTBN = 0 V −1 0 1 mA Conditions Min Typ Max Unit 200 320 450 kW −1 0 1 mA Table 23. BGE PIN PARAMETERS Symbol Parameter RPD_BGE Pull−down resistance iBGEIL Low level input current uBGE = 0 V http://onsemi.com 18 NCV7381 Table 24. TxD PIN PARAMETERS Symbol Parameter Conditions Min Typ Max Unit uBDLogic_0 Low level input voltage −0.3 0.4*Vio V uBDLogic_1 High level input voltage 0.6*Vio 5.5 V 20 kW RPD_TxD Pull−down resistance C_BDTxD Input capacitance on TxD pin (Note 13) iTxDLI 5 11 10 pF uTXD = 0 V −1 0 1 mA Conditions Min Typ Max Unit 50 110 200 kW uTXEN = VIO −1 0 1 mA uTxEN = 5.25 V, VIO = 0 V −1 0 1 mA Typ Max Unit f = 5 MHz Low level input current 13. Values based on design and characterization, not tested in production Table 25. TxEN PIN PARAMETERS Symbol RPU_TxEN iTxENIH iTxENLEAK Parameter Pull−up resistance High level input current Input leakage current Digital Output Signals Table 26. DIGITAL OUTPUT SIGNALS VOLTAGE LIMITS (Pins RXD, RxEN and ERRN) Symbol Parameter Conditions Min uVDIG−OUT−LOW Low level output voltage iRxDOL = 6 mA iRxENOL = 5 mA iERRNOL = 0.7 mA (Note 14) 0 0.2*VIO V uVDIG−OUT−HIGH High level output voltage iRxDOH = −6 mA iRxENOH = −5 mA iERRNOH = −0.7 mA (Note 14) 0.8*VIO VIO V uVDIG−OUT−UV Output voltage on a digital output when VIO in undervoltage RLOAD = 100 kW to GND, Either VCC or VBAT supplied 500 mV uVDIG−OUT−OFF Output voltage on a digital output when unsupplied RLOAD = 100 kW to GND 500 mV Max Unit 6.5 ns 6.5 ns 14. uVDIG = uVIO. No undervoltage on VIO and either VCC or VBAT supplied. Table 27. RxD PIN PARAMETERS Symbol Parameter Conditions dBDRxDR15 RXD signal rise time (20%−80% VIO) dBDRxDF15 RXD signal fall time (20%−80% VIO) RxD pin loaded with 15 pF capacitor (Note 15) Min Typ dBDRxDR15 + dBDRxDF15 Sum of rise and fall time (20%−80% VIO) 13 ns |dBDRxDR15 − dBDRxDF15| Difference of rise and fall time 5 ns 8.5 ns 8.5 ns 16.5 ns 5 ns 16.5 ns 5 ns dBDRxDR25 RXD signal rise time (20%−80% VIO) dBDRxDF25 RXD signal fall time (20%−80% VIO) dBDRxDR25 + dBDRxDF25 Sum of rise and fall time (20%−80% VIO) |dBDRxDR25 − dBDRxDF25| Difference of rise and fall time dBDRxDR25_10 + dBDRxDF25_10 RXD signal sum of rise and fall time at TP4_CC (20%−80% VIO) |dBDRxDR25_10 − dBDRxDF25_10| RXD signal difference of rise and fall time at TP4_CC (20%−80% VIO) RxD pin loaded with 25 pF capacitor RxD pin loaded with 25 pF capacitor plus 10 pF at the end of a 50 W, 1 ns microstripline (Note 16) 15. Values based on design and characterization, not tested in production 16. Simulation result. Simulation performed within TJ_OP range, according to FlexRay Electrical Physical Layer Specification, Version 3.0.1 http://onsemi.com 19 NCV7381 TYPICAL CHARACTERISTICS 700 TEMP = 25°C 1200 VIO = 3.3 V TEMP = 25°C 600 VIO − uRxDOH (mV) VIO = 5 V 400 300 200 800 VIO = 5 V 600 400 200 100 0 5 10 15 20 25 0 30 0 5 10 15 20 25 iRxDOL (mA) −iRxDOH (mA) Figure 14. RxD Low Output Characteristic Figure 15. RxD High Output Characteristic 300 VBAT = 14 V TEMP = 25°C 250 VBAT − uINH (mV) uRxDOL (mV) 500 0 VIO = 3.3 V 1000 VBAT = 4.9 V 200 150 100 50 0 0 1 2 3 4 −iINH (mA) Figure 16. INH Not_Sleep Output Characteristic http://onsemi.com 20 5 30 NCV7381 5 VDC 100 nF 10 mF VIO VCC 12 VDC VBAT BP RBUS NCV7381 CBUS RxD BM 25 pF GND Figure 17. Test Setup for Dynamic Characteristics 5 VDC 3.3 VDC 22 mF 100 nF 22 mF 100 nF 100 nF VCC VIO ISO 7637−2 pulse generator 22 mF 330 pF VBAT BP RBUS 56 W NCV7381 RxD BM 15 pF 330 pF GND Figure 18. Test Setup for Measuring the Transient Immunity http://onsemi.com 21 ISO 7637−2 pulse generator NCV7381 PACKAGE DIMENSIONS SSOP 16 CASE 565AE−01 ISSUE O http://onsemi.com 22 NCV7381 ORDERING INFORMATION Part Number NCV7381DP0G NCV7381DP0R2G Description Clamp 30 FlexRay Transceiver Container† Temperature Range Package Type Quantity −40°C to +125°C SSOP 16 GREEN Tube 76 Tape & Reel 2000 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. FlexRay is a registered trademark of Daimler Chrysler AG. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 23 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCV7381/D