TI1 LMV604MAX/NOPB Lmv60x 1-mhz, low-power, general-purpose, 2.7-v operational amplifier Datasheet

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LMV601, LMV602, LMV604
SNOSC70C – APRIL 2012 – REVISED JULY 2016
LMV60x 1-MHz, Low-Power, General-Purpose, 2.7-V Operational Amplifiers
1 Features
3 Description
•
The LMV60x devices are single, dual, and quad lowvoltage, low-power operational amplifiers. They are
designed specifically for low-voltage, general-purpose
applications. Other important product characteristics
are low input bias current, rail-to-rail output, and wide
temperature range. The LMV60x have 29-nV voltage
noise at 10 KHz, 1-MHz GBW, 1-V/µs slew rate,
0.25-mV Vos. The LMV60x operates from a single
supply voltage as low as 2.7 V, while drawing 100-µA
(typical) quiescent current. In shutdown mode, the
current can be reduced to 45 pA.
1
•
•
•
•
•
•
Typical 2.7-V Supply Values; Unless Otherwise
Noted
Ensured 2.7-V and 5-V Specifications
Supply Current (Per Amplifier): 100 µA
Gain Bandwidth Product: 1 MHz
Shutdown Current (LMV601): 45 pA
Turnon Time from Shutdown (LMV601): 5 µs
Input Bias Current: 20 fA
2 Applications
•
•
•
•
•
•
•
•
•
•
The industrial-plus temperature range of −40°C to
125°C allows the LMV60x to accommodate a broad
range of extended environment applications.
Cordless and Cellular Phones
Laptops
PDAs
PCMCIA and Audio
Portable and Battery-Powered Electronic
Equipment
Supply Current Monitoring
Battery Monitoring
Buffers
Filters
Drivers
The LMV601 offers a shutdown pin that can be used
to disable the device. Once in shutdown mode, the
supply current is reduced to 45 pA (typical).
The LMV601 is offered in the tiny 6-pin SC70
package, the LMV602 in space-saving 8-pin VSSOP
and SOIC, and the LMV604 in 14-pin TSSOP and
SOIC. These small package amplifiers offer an ideal
solution for applications requiring minimum PCB
footprint. Applications with area constrained printedcircuit board requirements include portable and
battery-operated electronics.
Device Information(1)
PART NUMBER
LMV601
LMV602
LMV604
PACKAGE
BODY SIZE (NOM)
SC70 (6)
2.00 mm × 1.25 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Sample and Hold Circuit
V+
V+
-
VIN
VOUT
+
+
C = 200 pF
SAMPLE
CLOCK
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV601, LMV602, LMV604
SNOSC70C – APRIL 2012 – REVISED JULY 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5
5
5
5
6
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics – DC (2.7 V) .....................
Electrical Characteristics – AC (2.7 V)......................
Electrical Characteristics – DC (5 V) ........................
Electrical Characteristics – AC (5 V).........................
Typical Characteristics ..............................................
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 18
8.3 Dos and Don'ts........................................................ 19
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1 Layout Guideline ................................................... 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2013) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed Thermal Information table to align with JEDEC standards ..................................................................................... 5
•
Changed ON mode (LMV601) typical value for VSD in Electrical Characteristics – DC (2.7 V) from '1.7 to 2.7' to '1.7'........ 6
•
Changed ON Mode (LMV601) max value for VSD in Electrical Characteristics – DC (2.7 V) from '2.4 to 2.7' to '2.7' ........... 6
•
Changed Shutdown mode (LMV601) typical value for VSD in Electrical Characteristics – DC (2.7 V) from '0 to 1' to '0' ...... 6
•
Changed Shutdown mode (LMV601) max value for VSD in Electrical Characteristics – DC (2.7 V) from '0 to 0.8' to '0.8' ... 6
•
Deleted '–0.2 to 4.2 (Range)' from VCM in Electrical Characteristics – DC (5 V).................................................................... 7
•
Changed ON mode (LMV601) typical value for VSD in Electrical Characteristics – DC (5 V) from '3.1 to 5' to '3.1'.............. 7
•
Changed ON mode (LMV601) max value for VSD in Electrical Characteristics – DC (5 V) from '4.5 to 5' to '5' .................... 7
•
Changed Shutdown mode (LMV601) typical value for VSD in Electrical Characteristics – DC (5 V) from '0 to 1' to '1' ......... 7
•
Changed Shutdown mode (LMV601) max value for VSD in Electrical Characteristics – DC (5 V) from '0 to 0.8' to '0.8' ...... 7
Changes from Revision A (March 2012) to Revision B
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 16
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SNOSC70C – APRIL 2012 – REVISED JULY 2016
5 Pin Configuration and Functions
LMV601
DCK Package
6-Pin SC70
Top View
1
6
+IN
V
2
+
+
GND
5
SHDN
4
OUT
-
-IN
3
Pin Functions: LMV601
PIN
NAME
NO.
I/O
DESCRIPTION
GND
2
P
Supply negative input
+IN
1
I
Noninverting input
–IN
3
I
Inverting input
OUT
4
O
Output
SHDN
5
I
Active low enable input
V+
6
P
Positive supply input
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LMV602
DGK or D Packages
8-Pin VSSOP or SOIC
Top View
LMV604
PW or D Packages
14-Pin TSSOP and SOIC
Top View
Pin Functions: LMV602, LMV604
PIN
NAME
NO.
I/O
DESCRIPTION
LMV602
LMV604
+INA
3
3
I
Noninverting input, channel A
+INB
5
5
I
Noninverting input, channel B
+INC
—
10
I
Noninverting input, channel C
+IND
—
12
I
Noninverting input, channel D
–INA
2
2
I
Inverting input, channel A
–INB
6
6
I
Inverting input, channel B
–INC
—
9
I
Inverting input, channel C
–IND
—
13
I
Inverting input, channel D
OUTA
1
1
O
Output, channel A
OUTB
7
7
O
Output, channel B
OUTC
—
8
O
Output, channel C
OUTD
—
14
O
Output, channel D
V+
8
4
P
Positive (highest) power supply
V–
4
11
P
Negative (lowest) power supply
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
Differential input voltage
MAX
Supply voltage, (V+) – (V–)
Output short circuit to V+
See (3)
Output short circuit to V–
See (4)
Junction temperature, TJ
(5)
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
UNIT
±Supply Voltage
–65
6
V
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Shorting output to V+ adversely affects reliability.
Shorting output to V– adversely affects reliability.
The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM) (1) (1)
±2000
Machine model (MM) (2)
±200
UNIT
V
Human-Body Model, applicable std. MIL-STD-883, Method 3015.7.
Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22C101-C (ESD FICDM std. of JEDEC).
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Supply voltage
2.7
5.5
UNIT
V
Temperature
–40
125
°C
6.4 Thermal Information
LMV601
THERMAL METRIC
RθJA
(1)
LMV604
D
(SOIC)
DGK
(VSSOP)
D
(SOIC)
PW
(TSSOP)
6 PINS
8 PINS
8 PINS
14 PINS
14 PINS
UNIT
229.1
120.8
178.3
91.5
123.8
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
116.1
65.2
68.4
49.7
50.5
°C/W
RθJB
Junction-to-board thermal resistance
53.3
61.4
98.8
46
66.2
°C/W
ψJT
Junction-to-top characterization parameter
8.8
16.1
9.8
12.4
6.3
°C/W
ψJB
Junction-to-board characterization parameter
52.7
60.8
97.3
45.7
65.6
°C/W
(1)
Junction-to-ambient thermal resistance
LMV602
DCK
(SC70)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics – DC (2.7 V)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V, VCM = V+ / 2, VO = V+ / 2 and RL > 1 MΩ. (1)
PARAMETER
VOS
Input offset voltage
TCVOS
Input offset voltage average drift
IB
Input bias current
IOS
Input offset current
TEST CONDITIONS
MIN
TYP
MAX
LMV601
0.25
4
LMV602 and LMV604
0.55
5
1.7
µV/°C
pA
170
µA
45 pA
1
µA
Supply current
CMRR
Common-mode rejection ratio
0 V ≤ VCM ≤ 1.7 V
80
PSRR
Power supply rejection ratio
2.7 V ≤ V+ ≤ 5 V
82
VCM
Input common-mode voltage
For CMRR ≥ 50 dB
AV
Large signal voltage gain
RL = 10 kΩ to 1.35 V
VO
Output swing
IO
Output short-circuit current
ton
Turnon time from shutdown
VSD
(1)
Shutdown pin voltage range
RL = 10 kΩ to 1.35 V
fA
100
IS
Shutdown mode, VSD = 0 V (LMV601)
0
dB
dB
1.7
113
Swing high
5
Swing low
30
32
Sourcing
LMV604
24
Sinking
24
Shutdown mode (LMV601)
mV
mA
5
ON mode (LMV601)
V
dB
30
5.3
Sourcing
LMV601 and LMV602
(LMV601)
mV
0.02
6.6
Per amplifier
UNIT
µs
1.7
2.7
0
0.8
V
Values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under conditions of internal
self heating where TJ > TA.
6.6 Electrical Characteristics – AC (2.7 V)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7 V, V− = 0 V, VCM = V+ / 2, VO = V+ / 2 and RL > 1 MΩ. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SR
Slew rate
RL = 10 kΩ, (2)
1
V/µs
GBW
Gain bandwidth product
RL = 100 kΩ, CL = 200 pF
1
MHz
Φm
Phase margin
RL = 100 kΩ
72
deg
Gm
Gain margin
RL = 100 kΩ
20
dB
en
Input-referred voltage noise
f = 1 kHz
40
nV/√Hz
in
Input-referred current noise
f = 1 kHz
0.001
pA/√Hz
Total harmonic distortion
f = 1 kHz, AV = 1
RL = 600 Ω, VIN = 1 VPP
THD
(1)
(2)
6
0.017%
Values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under conditions of internal
self heating where TJ > TA.
Connected as voltage follower with 2-VPP step input. Number specified is the slower of the positive and negative slew rates.
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6.7 Electrical Characteristics – DC (5 V)
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
LMV601
VOS
Input offset voltage
TCVOS
Input offset voltage average drift
IB
Input bias current
IOS
Input offset current
LMV602 and LMV604
TYP
MAX
0.25
4
0.7
5
1.9
µV/°C
pA
6.6
Per amplifier
200
µA
0.033
1
µA
CMRR
Common-mode rejection ratio
0 V ≤ VCM ≤ 4 V
86
PSRR
Power supply rejection ratio
2.7 V ≤ V+ ≤ 5 V
82
VCM
Input common-mode voltage
For CMRR ≥ 50 dB
Shutdown mode, VSD = 0 V (LMV601)
(2)
VO
Output swing
IO
Output short-circuit current
ton
Turnon time from shutdown
VSD
(1)
(2)
Shutdown pin voltage range
0
RL = 10 kΩ to 2.5 V
RL = 10 kΩ to 2.5 V
fA
107
Supply current
Large signal voltage gain
mV
0.02
IS
AV
UNIT
dB
dB
4
V
116
Swing high
Swing low
7
30
Sourcing
dB
30
mV
7
113
Sinking
mA
75
(LMV601)
5
ON mode (LMV601)
Shutdown mode (LMV601)
µs
3.1
5
0
0.8
V
Values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under conditions of internal
self heating where TJ > TA.
RL is connected to mid-supply. The output voltage is GND + 0.2 V ≤ VO ≤ V+ − 0.2 V
6.8 Electrical Characteristics – AC (5 V)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = V+ / 2, VO = V+ / 2 and RL > 1 MΩ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SR
Slew rate
RL = 10 kΩ, (1)
GBW
Gain bandwidth product
RL = 100 kΩ, CL = 200 pF
Φm
Phase margin
RL = 100 kΩ
72
°
Gm
Gain margin
RL = 100 kΩ
20
dB
en
Input-referred voltage noise
f = 1 kHz
39
nV/√Hz
in
Input-referred current noise
f = 1 kHz
0.001
pA/√Hz
Total harmonic distortion
f = 1 kHz, AV = 1
RL = 600 Ω, VIN = 1 VPP
THD
(1)
1
V/µs
1
MHz
0.012%
Connected as voltage follower with 2-VPP step input. Number specified is the slower of the positive and negative slew rates.
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6.9 Typical Characteristics
150
1000
VS = 5 V
100
130
125°C
85°C
120
110
100
90
80
25°C
70
INPUT CURRENT (pA)
SUPPLY CURRENT (mA)
140
10
1
.1
.01
-40°C
60
.001
-40 -20
50
0 20 40 60 80 100 120 140
TEMPERATURE (C°)
Figure 2. Input Current vs Temperature
5
3.5
4.5
4
SUPPLY VOLTAGE (V)
Figure 1. Supply Current vs Supply Voltage (LMV601)
2.5
3
7.0
34
RL = 10kW
RL = 2kW
6.5
30
28
NEGATIVE SWING
26
24
POSITIVE SWING
OUTPUT VOLTAGE FROM
SUPPLY VOLTAGE (mV)
OUTPUT VOLTAGE FROM
SUPPLY VOLTAGE (mV)
32
POSITIVE SWING
5.5
5.0
4.5
NEGATIVE SWING
4.0
22
3.5
20
2.5
3.0
2.5
3
3.5
5
4
4.5
SUPPLY VOLTAGE (V)
Figure 3. Output Voltage Swing vs Supply Voltage
3.5
3
5
4.5
4
SUPPLY VOLTAGE (V)
Figure 4. Output Voltage Swing vs Supply Voltage
100
100
VS = 2.7 V
-40°C
25°C
VS = 5V
10
10
125°C
1
85°C
0.1
ISOURCE (mA)
ISOURCE (mA)
6.0
-40°C
85°C
125°C
1
25°C
0.1
0.01
0.001
0.001
0.01
1
10
0.1
OUTPUT VOLTAGE REFERENCED TO V+ (V)
Figure 5. ISOURCE vs VOUT
8
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0.01
0.001
0.01
0.1
10
1
+
OUTPUT VOLTAGE REFERENCED TO V (V)
Figure 6. ISOURCE vs VOUT
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Typical Characteristics (continued)
100
100
-40°C
VS = 2.7V
-40°C
VS = 5V
10
10
25°C
ISINK (mA)
25°C
ISINK (mA)
1
0.1
125°C
125°C
1
85°C
0.1
0.01
85°C
0.001
0.001
0.01
0.1
1
0.01
0.001
10
0.01
0.1
OUTPUT VOLTAGE REFERENCED TO V (V)
Figure 7. ISINK vs VOUT
OUTPUT VOLTAGE REFERENCED TO V (V)
Figure 8. ISINK vs VOUT
3
3
VS = 2.7V
VS = 5V
-40°C
-40°C
2.5
2.5
25°C
25°C
2
2
VOS (mV)
VOS (mV)
10
1
-
-
85°C
1.5
125°C
85°C
1.5
1
1
0.5
0.5
125°C
0
-0.2
0.3
0.8
1.3
1.8
0
-0.2
2.3
0.5
VCM (V)
Figure 9. VOS vs VCM
1
1.5
2.5
2
3
3.5 4
4.5
VCM (V)
Figure 10. VOS vs VCM
300
300
VS = ±1.35V
200
INPUT VOLTAGE (mV)
INPUT VOLTAGE (mV)
200
100
0
RL = 10 kW
-100
RL = 10 kW
100
0
RL = 2 kW
-100
-200
-200
VS = ±2.5V
RL = 2 kW
-300
-1.5
-300
-1
-0.5
0
0.5
1
1.5
-3
-2
OUTPUT VOLTAGE (V)
Figure 11. VIN vs VOUT
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-1
0
1
2
3
OUTPUT VOLTAGE (V)
Figure 12. VIN vs VOUT
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Typical Characteristics (continued)
100
80
VS = 5 V
VIN = VS/2
70
RL = 5 kW
RL = 5 kW
VS = 5 V, -PSRR
90
80
VS = 2.7 V, +PSRR
60
50
PSRR (dB)
CMRR (dB)
70
VS = 2.7 V
40
30
60
50
VS = 5 V, +PSRR
40
30
20
20
10
10
0
100
VS = 2.7 V, -PSRR
0
1k
10k
100k
100
1M
260
100k
10k
120
100
80
60
40
VS = 2.7V
RL = 10kW
VIN = 2VPP
1.2
1.1
RISING EDGE
1
0.9
FALLING EDGE
0.8
0.7
20
0
0.6
VS = 5V
0.5
2.5
10k
1k
100
FREQUENCY (Hz)
Figure 15. Input Voltage Noise vs Frequency
10
3.5
4
4.5
SUPPLY VOLTAGE (V)
Figure 16. Slew Rate vs VSUPPLY
3
RISING EDGE
RISING EDGE
1
0.8
FALLING EDGE
0.6
AV = +1
SLEW RATE (V/ms)
SLEW RATE (V/ms)
1
0.8
FALLING EDGE
0.6
0.4
AV = +1
RL = 10kW
RL = 10kW
0.2
VIN = 2VPP
VIN = 2VPP
VS = 5V
VS = 2.7V
0
0
-40 -20
0
20 40
60
80 100 120 140
TEMPERATURE (°)
Figure 17. Slew Rate vs Temperature
10
5
1.2
1.2
0.2
10M
AV = +1
1.4
1.3
180
160
140
0.4
1M
1.5
VCM = VS/2
240
220
200
SLEW RATE (V/ms)
INPUT VOLTAGE NOISE (nV/ Hz)
1k
FREQUENCY (Hz)
Figure 14. PSRR vs Frequency
FREQUENCY (Hz)
Figure 13. CMRR vs Frequency
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-40 -20
0
20 40
60
80 100 120 140
TEMPERATURE (°)
Figure 18. Slew Rate vs Temperature
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Typical Characteristics (continued)
10
10
f = 10KHz
AV = +10
VS = 2.7V, A V = +10
VS = 2.7V, VO = 1VPP
1
THD+N (%)
THD+N (%)
1
RL = 600Ω
VS = 5V, V O = 2.5VPP
0.1
AV = +1
VS = 5V, AV = +10
0.1
0.01
VS = 5V, AV = +1
VS = 2.7V, AV = +1
VS = 5V, VO = 1VPP
VS = 2.7V, VO = 1VPP
0.01
0.00
1
0.001
1
10k
100
1k
FREQUENCY (Hz)
Figure 19. THD+N vs Frequency
100k
10
PHASE
10
1
100
100
125°C
80
0.1
VO (VPP)
Figure 20. THD+N vs VOUT
100
100
0.0
1
PHASE
80
80
RL = 2kW
80
RL = 600W
RL = 100kW
20
20
-40°C
0
0
125°C
0
-20
RL = 2kW
-40
-40
-40
VS = 2.7V
-60
10k
100k
1M
FREQUENCY (Hz)
10k
1k
100
100
RL = 2kW
PHASE
CL = 0
80
PHASE
80
RL = 600W
60
60
60
20
0
0
RL = 600W
-20
GAIN (dB)
RL = 100kW
PHASE
(°)
GAIN (dB)
40
40
-40
0
CL = 1000pF
-20
-20
-40
-40
100k
1M
FREQUENCY (Hz)
-60
10M
Figure 23. Open-Loop Frequency Response
-20
CL = 500pF
VS = 5V
RL = 600W
10k
20
0
VS = 5V
-60
40
CL = 100pF
GAIN
20
RL = 2kW
1k
60
CL = 500pF
40
20
80
CL = 1000pF
RL = 100kW
GAIN
100k
1M
FREQUENCY (Hz)
Figure 22. Open-Loop Frequency Response
100
100
-60
10M
-60
-60
10M
Figure 21. Open-Loop Frequency Over Temperature
80
0
RL = 600W
-20
-20
RL = 2kW
1k
RL = 100kW 20
20
25°C
VS = 5V
-40
GAIN
PHASE
(°)
-20
40
40
PHASE
(°)
40
GAIN
GAIN (dB)
40
60
60
60
25°C
-40°C
PHASE
(°)
GAIN (dB)
60
CL = 100pF
-60
1k
10k
100k
1M
FREQUENCY (Hz)
-40
CL = 0
-60
10M
Figure 24. Gain and Phase vs CL
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Typical Characteristics (continued)
100
VS = ±2.5V
CL = 0
3.5
CL = 1000pF
60
CL = 500pF
40
CL = 100pF
GAIN
40
20
20
CL = 0
0
0
CL = 1000pF
CL = 500pF
-20
-20
CL = 100pF
VS = 5V
PHASE
(°)
GAIN (dB)
60
CAPACITIVE LOAD (nF)
80
80
-40
4
100
PHASE
-40
10k
1k
-60
10M
100k
1M
FREQUENCY (Hz)
VO = 100mVPP
2.5
2
1.5
1
0
-2.5
Figure 25. Gain and Phase vs CL
120
100
80
60
40
20
0
-2.5 -2
-1.5
-1
-0.5
0.5
0
1
1.5
0.5
1
1.5
RL = 2kW
VS = ±2.5V
RL = 2kW
VS = ±2.5V
TIME (4 ms/div)
Figure 28. Noninverting Small Signal Pulse Response
OUTPUT SIGNAL
TIME (4 ms/div)
Figure 29. Noninverting Large Signal Pulse Response
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TA = 25°C
INPUT SIGNAL
TA = 25°C
(1 V/div)
OUTPUT SIGNAL
INPUT SIGNAL
VO (V)
Figure 27. Stability vs Capacitive Load
12
-0.5 0
VO (V)
(50 mV/div)
VO = 100mVPP
-1
(50 mV/div)
RL = 1MW
140
-1.5
INPUT SIGNAL
AV = +1
OUTPUT SIGNAL
CAPACITIVE LOAD (pF)
VS = ±2.5
160
-2
Figure 26. Stability vs Capacitive Load
200
180
RL = 2kW
3
0.5
RL = 100kW
-60
AV = +1
TA = 125°C
RL = 2kW
VS = ±2.5V
TIME (4 ms/div)
Figure 30. Noninverting Small Signal Pulse Response
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RL = 2kW
VS = ±2.5V
OUTPUT SIGNAL
(50 mV/div)
INPUT SIGNAL
TA = 125°C
(1 V/div)
OUTPUT SIGNAL
INPUT SIGNAL
Typical Characteristics (continued)
TA = -40°C
RL = 2kW
VS = ±2.5V
TIME (4 ms/div)
TIME (4 ms/div)
Figure 32. Noninverting Small Signal Pulse Response
RL = 2kW
VS = ±2.5V
OUTPUT SIGNAL
TA = 25°C
RL = 2 kW
VS = ±2.5 V
(50 mV/div)
INPUT SIGNAL
TA = -40°C
(1 V/div)
OUTPUT SIGNAL
INPUT SIGNAL
Figure 31. Noninverting Large Signal Pulse Response
TIME (4 ms/div)
TIME (4 ms/div)
Figure 34. Inverting Small Signal Pulse Response
TA= 125°C
RL = 2kW
VS = ±2.5V
TIME (4 ms/div)
Figure 35. Inverting Large Signal Pulse Response
TA = 125°C
RL = 2 kW
VS = ±2.5 V
(50 mV/div)
INPUT SIGNAL
OUTPUT SIGNAL
(1 V/div)
OUTPUT SIGNAL
INPUT SIGNAL
Figure 33. Noninverting Large Signal Pulse Response
TIME (4 ms/div)
Figure 36. Inverting Small Signal Pulse Response
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TA = 125°C
RL = 2kW
VS = ±2.5V
TIME (4 ms/div)
Figure 37. Inverting Large Signal Pulse Response
RL = 2 kW
VS = ±2.5 V
TIME (4 ms/div)
Figure 38. Inverting Small Signal Pulse Response
200
INPUT SIGNAL
VS = ±2.5V
CROSSTALK REJECTION (dB)
180
(1 V/div)
OUTPUT SIGNAL
TA = -40°C
(50 mV/div)
OUTPUT SIGNAL
(1 V/div)
OUTPUT SIGNAL
INPUT SIGNAL
INPUT SIGNAL
Typical Characteristics (continued)
TA = -40°C
RL = 2kW
160
140
120
100
80
60
40
20
VS = ±2.5V
0
100
TIME (4 ms/div)
Figure 39. Inverting Large Signal Pulse Response
14
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1k
10k
100k
1M
FREQUENCY (Hz)
Figure 40. Crosstalk Rejection vs Frequency
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7 Detailed Description
7.1 Overview
The LMV60x family of amplifiers features low-voltage, low-power, and rail-to-rail output operational amplifiers
designed for low-voltage portable applications. The family is designed using all CMOS technology. This results in
an ultra-low input bias current. The LMV601 has a shutdown option, which can be used in portable devices to
increase battery life.
A simplified schematic of the LMV60x family of amplifiers is shown in Functional Block Diagram. The PMOS input
differential pair allows the input to include ground. The output of this differential pair is connected to the Class AB
turnaround stage. This Class AB turnaround has a lower quiescent current, compared to regular turnaround
stages. This results in lower offset, noise, and power dissipation, while slew rate equals that of a conventional
turnaround stage. The output of the Class AB turnaround stage provides gate voltage to the complementary
common-source transistors at the output stage. These transistors enable the device to have rail-to-rail output.
7.2 Functional Block Diagram
VDD
OUT
CLASS AB
CONTROL
InP
InM
VEE
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7.3 Feature Description
7.3.1 Class AB Turnaround Stage Amplifier
This patented folded cascode stage has a combined class AB amplifier stage, which replaces the conventional
folded cascode stage. Therefore, the class AB folded cascode stage runs at a much lower quiescent current
compared to conventional folded cascode stages. This results in significantly smaller offset and noise
contributions. The reduced offset and noise contributions in turn reduce the offset voltage level and the voltage
noise level at the input of the LMV60x. Also the lower quiescent current results in a high open-loop gain for the
amplifier. The lower quiescent current does not affect the slew rate of the amplifier nor its ability to handle the
total current swing coming from the input stage.
The input voltage noise of the device at low frequencies, below 1 kHz, is slightly higher than devices with a BJT
input stage. However, the PMOS input stage results in a much lower input bias current and the input voltage
noise drops at frequencies above 1 kHz.
7.4 Device Functional Modes
7.4.1 Low Input Bias Current
The LMV60x amplifiers have a PMOS input stage. As a result, they have a much lower input bias current than
devices with BJT input stages. This feature makes these devices ideal for sensor circuits. A typical curve of the
input bias current of the LMV601 is shown in Figure 41.
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Device Functional Modes (continued)
200
VS = 5V
TA = 25°C
INPUT BIAS (fA)
100
0
-100
-200
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
VCM (V)
Figure 41. Input Bias Current vs VCM
7.4.2 Shutdown Feature
The LMV601 is capable of being turned off to conserve power and increase battery life in portable devices. Once
in shutdown mode the supply current is drastically reduced, 1 µA maximum, and the output is tri-stated.
The device is disabled when the shutdown pin voltage is pulled low. The shutdown pin must never be left
unconnected. Leaving the pin floating results in an undefined operation mode and the device may oscillate
between shutdown and active modes.
The LMV601 typically turns on 2.8 µs after the shutdown voltage is pulled high. The device turns off in less than
400 ns after shutdown voltage is pulled low. Figure 42 and Figure 43 show the turnon and turnoff time of the
LMV601, respectively. To reduce the effect of the capacitance added to the circuit by the scope probe, in the
turnoff time circuit a resistive load of 600 Ω is added. Figure 44 and Figure 45 show the test circuits used to
obtain the two plots.
VS = 5V
VOUT
VOUT
(1 V/div)
(1 V/div)
VSHDN
VSHDN
RL = 600W
VS = 5V
TIME (1 ms/div)
TIME (400 ns/div)
Figure 42. Turnon Time
16
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Figure 43. Turnoff Time
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Device Functional Modes (continued)
V+
+
V
+
VOUT
SHDN
VIN = VS/2
+
+
-
VOUT
SHDN
VIN = VS/2
RL = 600 W
+
-
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 44. Turnon Time
Figure 45. Turnoff Time
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV60x family of amplifiers features low-voltage, low-power, and rail-to-rail output operational amplifiers
designed for low-voltage portable applications.
8.2 Typical Application
V+
V+
-
VIN
VOUT
+
+
C = 200 pF
SAMPLE
CLOCK
Copyright © 2016, Texas Instruments Incorporated
Figure 46. Sample and Hold Circuit
8.2.1 Design Requirements
The lower input bias current of the LMV601 results in a very high input impedance. The output impedance when
the device is in shutdown mode is quite high. These high impedances, and the ability of the shutdown pin to be
derived from a separate power source, make LMV601 a good choice for sample and hold circuits. The sample
clock must be connected to the shutdown pin of the amplifier to rapidly turn the device on or off.
8.2.2 Detailed Design Procedure
Figure 46 shows the schematic of a simple sample-and-hold circuit. When the sample clock is high, the first
amplifier is in normal operation mode and the second amplifier acts as a buffer. The capacitor, which appears as
a load on the first amplifier, is charging at this time. The voltage across the capacitor is that of the noninverting
input of the first amplifier because it is connected as a voltage-follower. When the sample clock is low, the first
amplifier is shut off, bringing the output impedance to a high value. The high impedance of this output, along with
the very high impedance on the input of the second amplifier, prevents the capacitor from discharging. There is
very little voltage droop while the first amplifier is in shutdown mode. The second amplifier, which is still in normal
operation mode and is connected as a voltage-follower, also provides the voltage sampled on the capacitor at its
output.
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Typical Application (continued)
Signal Amplitude
8.2.3 Application Curve
Sample (5v/div)
Vin (1v/div)
Vout (1v/div)
0
300
600
900
1200
Time (us)
1500
C002
Figure 47. Sample-and-Hold Circuit Results
8.3 Dos and Don'ts
Do properly bypass the power supplies.
Do add series resistence to the output when driving capacitive loads, particularly cables, Muxes, and ADC inputs.
Do add series current-limiting resistors and external Schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1 mA or less (1 kΩ per volt).
9 Power Supply Recommendations
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI
recommends that 10-nF capacitors be placed as close as possible to the operational amplifier power supply pins.
For a single supply, place a capacitor between V+ and V− supply leads. For dual supplies, place one capacitor
between V+ and ground, and one capacitor between V– and ground.
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10 Layout
10.1 Layout Guideline
To properly bypass the power supply, consider the placement of several components on the printed-circuit boad.
A 6.8‑µF or greater tantalum capacitor must be placed at the point where the power supply for the amplifier is
introduced onto the board. Another 0.1-µF ceramic capacitor must be placed as close as possible to the power
supply pin of the amplifier. If the amplifier is operated in a single power supply, only the V+ pin must be bypassed
with a 0.1-µF capacitor. If the amplifier is operated in a dual power supply, both V+ and V– pins must be
bypassed.
It is good practice to use a ground plane on a printed-circuit board to provide all components with a low inductive
ground connection.
TI recommends surface-mount components in 0805 size or smaller in the LMV601-N application circuits.
Designers can take advantage of the VSSOP miniature sizes to condense board layout to save space and
reduce stray capacitance.
10.2 Layout Example
Cbyp
V+
GND
INPUT
Rin
SHDN
OUTPUT
Rf
Cf
Figure 48. PCB Layout Example
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SNOSC70C – APRIL 2012 – REVISED JULY 2016
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
• LMV601 PSPICE Model (zip file)
• LMV601 PSPICE Model (zip file)
• LMV602 PSPICE Model (zip file)
• LMV604 PSPICE Model (zip file)
• TINA-TI SPICE-Based Analog Simulation Program
• DIP Adapter Evaluation Module
• TI Universal Operational Amplifier Evaluation Module
• TI Filterpro Software
11.2 Documentation Support
11.2.1 Related Documentation
For additional applications, see the following:
AN-31 Op Amp Circuit Collection (SNLA140)
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMV601
Click here
Click here
Click here
Click here
Click here
LMV602
Click here
Click here
Click here
Click here
Click here
LMV604
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMV601MG/NOPB
ACTIVE
SC70
DCK
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AUA
LMV601MGX/NOPB
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AUA
LMV602MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV60
2MA
LMV602MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV60
2MA
LMV602MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AC9A
LMV602MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AC9A
LMV604MA/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV604MA
LMV604MAX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV604MA
LMV604MT/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LMV604
MT
LMV604MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LMV604
MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2016
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LMV601MG/NOPB
SC70
DCK
6
1000
178.0
LMV601MGX/NOPB
SC70
DCK
6
3000
LMV602MAX/NOPB
SOIC
D
8
2500
LMV602MM/NOPB
VSSOP
DGK
8
LMV602MMX/NOPB
VSSOP
DGK
B0
(mm)
K0
(mm)
P1
(mm)
8.4
2.25
2.45
1.2
4.0
178.0
8.4
2.25
2.45
1.2
330.0
12.4
6.5
5.4
2.0
1000
178.0
12.4
5.3
3.4
8
3500
330.0
12.4
5.3
W
Pin1
(mm) Quadrant
8.0
Q3
4.0
8.0
Q3
8.0
12.0
Q1
1.4
8.0
12.0
Q1
3.4
1.4
8.0
12.0
Q1
LMV604MAX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LMV604MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
LMV604MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV601MG/NOPB
SC70
DCK
6
1000
210.0
185.0
35.0
LMV601MGX/NOPB
SC70
DCK
6
3000
210.0
185.0
35.0
LMV602MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMV602MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMV602MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMV604MAX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LMV604MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
LMV604MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
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