Cypress CY14E104M-ZSP25XI 4 mbit (512k x 8 / 256k x 16) nvsram with real-time-clock Datasheet

PRELIMINARY
CY14E104K/CY14E104M
4 Mbit (512K x 8 / 256K x 16) nvSRAM with
Real-Time-Clock
Features
■
15 ns, 20 ns, 25 ns, and 45 ns access times
■
Internally organized as 512K x 8 (CY14E104K) or 256K x 16
(CY14E104M)
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap® nonvolatile elements is initiated by
software, device pin, or AutoStore® on power down
■
RECALL to SRAM initiated by software or power up
■
High reliability
■
Infinite read, write, and recall cycles
■
200,000 STORE cycles to QuantumTrap
■
20 year data retention
■
Single 5V +10% operation
■
Data integrity of Cypress nvSRAM combined with full featured
Real-Time-Clock
■
Watchdog timer
■
Clock alarm with programmable interrupts
■
Capacitor or battery backup for RTC
■
Commercial and industrial temperatures
■
44/54-pin TSOP II package
■
Pb-free and RoHS compliance
Functional Description
The Cypress CY14E104K/CY14E104M combines a 4 Mbit
nonvolatile static RAM with a full featured real-time-clock in a
monolithic integrated circuit. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written an infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The real-time-clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for one time alarms or periodic
seconds, minutes, hours, or days. There is also a programmable
watchdog timer for process control.
Logic Block Diagram
VCC
VCAP VRTCcap VRTCbat
[1]
Address A0 - A18[1]
DQ0 - DQ7
CE
HSB
CY14E104K
CY14E104M
OE
INT
WE
X1
BHE
X2
BLE
VSS
Note
1. Address A0 - A18 and DQ0 - DQ7 for x8 configuration, Address A0 - A17 and Data DQ0 - DQ15 for x16 configuration.
Cypress Semiconductor Corporation
Document #: 001-09604 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 20, 2008
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CY14E104K/CY14E104M
PRELIMINARY
Pinouts
Figure 1. Pin Diagram - TSOP II
INT
[3]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
X1
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 - TSOP II
(x8)
Top View
(not to scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
HSB
NC
[2]
NC
A18
A17
A16
A15
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
30
29
28
27
26
25
24
23
VCAP
A14
A13
INT
[3]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
NC
A12
A11
A10
VRTCcap
VRTCbat
X1
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
54 - TSOP II
(x16)
Top View
(not to scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
NC [2]
A17
A16
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
NC
VRTCcap
VRTCbat
Pin Definitions
Pin Name
IO Type
A0 – A18
Input
A0 – A17
Description
Address Inputs Used to Select one of the 524, 288 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 262,144 bytes of the nvSRAM for x16 Configuration.
DQ0 – DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
operation.
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
operation.
DQ0 – DQ15
NC
No Connect No Connects. This pin is not connected to the die.
Input
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address
location latched by the falling edge of CE.
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the IO pins to tri-state.
BHE
Input
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
BLE
Input
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
X1
Output
X2
Input
WE
CE
OE
Crystal Connection. Drives crystal on start up.
Crystal Connection. For 32.768 kHz crystal.
VRTCcap
Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if VRTCbat is used.
VRTCbat
Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if VRTCcap is used.
Notes
2. Address expansion for 8 Mbit. NC pin not connected to die.
3. Address expansion for 16 Mbit. NC pin not connected to die.
Document #: 001-09604 Rev. *H
Page 2 of 28
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CY14E104K/CY14E104M
PRELIMINARY
Pin Definitions (continued)
Pin Name
IO Type
INT
Output
Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
VSS
Ground
Ground for the Device. Must be connected to ground of the system.
VCC
HSB
VCAP
Description
Power Supply Power Supply Inputs to the Device. 5.0V +10%, –10%
Input/Output Hardware Store Busy. When LOW this output indicates that a hardware store is in progress. When
pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor
keeps this pin HIGH if not connected. (connection optional)
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Device Operation
AutoStore Operation
The CY14E104K/CY14E104M nvSRAM is made up of two
functional components paired in the same physical cell. These
are a SRAM memory cell and a nonvolatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations SRAM read and write operations are inhibited. The
CY14E104K/CY14E104M supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations.
The CY14E104K/CY14E104M stores data to the nvSRAM using
one of three storage operations. These three operations are:
Hardware Store, activated by HSB; Software Store, activated by
an address sequence; AutoStore, on device power down. The
AutoStore operation is a unique feature of QuantumTrap
technology
and
is
enabled
by
default
on
the
CY14E104K/CY14E104M.
The CY14E104K/CY14E104M performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0-18 or A0-17 determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. When
the read is initiated by an address transition, the outputs are valid
after a delay of tAA (read cycle #1). If the read is initiated by CE
or OE, the outputs are valid at tACE or at tDOE, whichever is later
(read cycle #2). The data output repeatedly responds to address
changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common IO pins IO0-7 are
written into the memory if it is valid tSD before the end of a WE
controlled write or before the end of an CE controlled write. It is
recommended that OE be kept HIGH during the entire write cycle
to avoid data bus contention on common IO lines. If OE is left
LOW, internal circuitry turns off the output buffers tHZWE after WE
goes LOW.
Document #: 001-09604 Rev. *H
Figure 2. AutoStore Mode
Vcc
0.1uF
10kOhm
SRAM Read
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Vcc
WE
V CAP
V SS
V CAP
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Electrical
Characteristics on page 14 for the size of the VCAP.
To reduce unnecessary nonvolatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Page 3 of 28
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PRELIMINARY
Hardware STORE (HSB) Operation
The CY14E104K/CY14E104M provides the HSB pin to control
and acknowledge the STORE operations. The HSB pin is used
to request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14E104K/CY14E104M conditionally initiates a
STORE operation after tDELAY. An actual STORE cycle begins
only if a write to the SRAM has taken place since the last STORE
or RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition when
the STORE (initiated by any means) is in progress.
SRAM read and write operations that are in progress when HSB
is driven LOW by any means are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14E104K/CY14E104M continues SRAM operations for
tDELAY. During tDELAY, multiple SRAM read operations may take
place. If a write is in progress when HSB is pulled LOW it is
allowed a time, tDELAY, to complete. However, any SRAM write
cycles requested after HSB goes LOW is inhibited until HSB
returns HIGH.
During any STORE operation, regardless of how it is initiated,
the CY14E104K/CY14E104M continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion
of
the
STORE
operation
the
CY14E104K/CY14E104M remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Hardware RECALL (Power Up)
During power up, or after any low power condition (VCC <
VSWITCH), an internal RECALL request is latched. When VCC
again exceeds the sense voltage of VSWITCH, a RECALL cycle
is automatically initiated and takes tHRECALL to complete.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14E104K/CY14E104M
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Document #: 001-09604 Rev. *H
CY14E104K/CY14E104M
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important to use read cycles and not write cycles
in the sequence, although it is not necessary that OE be LOW
for a valid sequence. After the tSTORE cycle time is fulfilled, the
SRAM is activated again for read and write operations.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time the SRAM is again
ready for read and write operations. The RECALL operation in
no way alters the data in the nonvolatile elements.
Page 4 of 28
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CY14E104K/CY14E104M
PRELIMINARY
Table 1. Mode Selection
CE
H
WE
X
OE
X
A15 - A0
Mode
IO
Power
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[4, 5, 6]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[4, 5, 6]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[4, 5, 6]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[4,5,6]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Notes
4. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
5. While there are 19 address lines on the CY14E104K/CY14E104M, only the lower 16 lines are used to control software modes.
6. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
Document #: 001-09604 Rev. *H
Page 5 of 28
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CY14E104K/CY14E104M
PRELIMINARY
Data Protection
The CY14E104K/CY14E104M protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when VCC < VSWITCH. If the CY14E104K/ CY14E104M
is in a write mode (both CE and WE LOW) at power up, after a
RECALL, or after a STORE, the write is inhibited until a negative
transition on CE or WE is detected. This protects against
inadvertent writes during power up or brown out conditions.
Noise Considerations
Refer CY application note AN1064.
Real-Time-Clock Operation
nvTIME Operation
The CY14E104K/CY14E104M offers internal registers that
contain clock, alarm, watchdog, interrupt, and control functions.
Internal double buffering of the clock and the clock or timer
information registers prevents accessing transitional internal
clock data during a read or write operation. Double buffering also
circumvents disrupting normal timing counts or the clock
accuracy of the internal clock when accessing clock data. Clock
and alarm registers store data in BCD format.
Backup Power
The RTC in the CY14E104K/CY14E104M is intended for permanently powered operations. The VRTCcap or VRTCbat pin is
connected depending on whether a capacitor or battery is
chosen for the application. When the primary power, VCC, fails
and drops below VSWITCH, the device switches to the backup
power supply.
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of
clock operation with the primary source removed, the data stored
in nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
During backup operation, the CY14E104K/CY14E104M
consumes a maximum of 300 nanoamps at 2 volts. Capacitor or
battery values must be chosen according to the application.
Backup time values based on maximum current specifications
are shown in the following table. Nominal times are
approximately three times longer.
Table 2. RTC Backup Time
Capacitor Value
Backup Time
0.1F
72 hours
0.47F
14 days
1.0F
30 days
Clock Operations
The clock registers maintain time up to 9,999 years in one
second increments. The time can be set to any calendar time and
the clock automatically keeps track of days of the week and
month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Reading the Clock
While the double buffered RTC register structure reduces the
chance of reading incorrect data from the clock, stop internal
updates to the CY14E104K/CY14E104M clock registers before
reading clock data, to prevent reading of data in transition.
Stopping the internal register updates does not affect clock
accuracy. The updating process is stopped by writing a ‘1’ to the
read bit ‘R’ (in the flags register at 0x1FFF0), and does not restart
until a ‘0’ is written to the read bit. The RTC registers are then
read while the internal clock continues to run. Within 20 ms after
a ‘0’ is written to the read bit, all CY14E104K/CY14E104M
registers are simultaneously updated.
Setting the Clock
Setting the write bit ‘W’ (in the flags register at 0x1FFF0) to a ‘1’
stops updates to the CY14E104K/CY14E104M registers. The
correct day, date, and time is then written into the registers in 24
hour BCD format. The time written is referred to as the “Base
Time”. This value is stored in nonvolatile registers and used in
the calculation of the current time. Resetting the write bit to ‘0’
transfers those values to the actual clock counters, after which
the clock resumes normal operation.
Document #: 001-09604 Rev. *H
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, a 3V lithium is recommended and the
CY14E104K/CY14E104M sources current only from the battery
when the primary power is removed. The battery is not, however,
recharged at any time by the CY14E104K/CY14E104M. The
battery capacity must be chosen for total anticipated cumulative
down time required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x1FFF8 controls
the start and stop of the oscillator. This bit is nonvolatile and
shipped to customers in the “enabled” (set to 0) state. To
preserve the battery life when the system is in storage OSCEN
must be set to ‘1’. This turns off the oscillator circuit extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately 5 seconds (10 seconds maximum) for the
oscillator to start.
The CY14E104K/CY14E104M has the ability to detect oscillator
failure. This is recorded in the OSCF (Oscillator Failed bit) of the
flags register at the address 0x1FFF0. When the device is
powered on (VCC goes above VSWITCH) the OSCEN bit is
checked for “enabled” status. If the OSCEN bit is enabled and
the oscillator is not active, the OSCF bit is set. Check for this
condition and then write ‘0’ to clear the flag. Note that in addition
to setting the OSCF flag bit, the time registers are reset to the
“Base Time” (see Setting the Clock on page 6), which is the value
last written to the timekeeping registers. The control or
calibration registers and the OSCEN bit are not affected by the
‘oscillator failed’ condition.
Page 6 of 28
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PRELIMINARY
If the voltage on the backup supply (either VRTCcap or VRTCbat)
falls below their respective minimum level, the oscillator may fail,
leading to the oscillator failed condition which is detected when
system power is restored.
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit
which may have become set when the system was first powered
on.
Calibrating the Clock
The RTC is driven by a quartz controlled oscillator with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal, usually specified to 35 ppm limits at 25°C. This
error could equate to +1.53 minutes per month. The
CY14E104K/CY14E104M employs a calibration circuit that
improves the accuracy to +1/–2 ppm at 25°C. The calibration
circuit adds or subtracts counts from the oscillator divider circuit.
The number of times pulses are suppressed (subtracted,
negative calibration) or split (added, positive calibration)
depends on the value loaded into the five calibration bits found
in the calibration register at 0x1FFF8. Adding counts speeds the
clock up; subtracting counts slows the clock down. The
calibration bits occupy the five lower order bits in the control
register 8. These bits are set to represent any value between 0
and 31 in binary form. Bit D5 is a sign bit, where ‘1’ indicates
positive calibration and ‘0’ indicates negative calibration.
Calibration occurs within a 64 minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator cycles.
If a binary ‘1’ is loaded into the register, only the first 2 minutes
of the 64 minute cycle are modified; if a binary ‘6’ is loaded, the
first 12 are affected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles
for every 125,829,120 actual oscillator cycles. That is 4.068 or
–2.034 ppm of adjustment for every calibration step in the
calibration register.
To determine how to set the calibration, the CAL bit in the flags
register at 0x1FFF0 is set to ‘1’, which causes the INT pin to
toggle at a nominal 512 Hz. Any deviation measured from the
512 Hz indicates the degree and direction of the required
correction. For example, a reading of 512.010124 Hz indicates
a +20 ppm error, which requires the loading of a –10 (001010)
into the calibration register. Note that setting or changing the
calibration register does not affect the frequency test output
frequency.
Alarm
The alarm function compares user programmed values with the
corresponding time of day values. When a match occurs, the
alarm event occurs. The alarm drives an internal flag, AF, and
may drive the INT pin if desired.
There are four alarm match fields. They are date, hours, minutes,
and seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process.
Document #: 001-09604 Rev. *H
CY14E104K/CY14E104M
Depending on the match bits, the alarm can occur as specifically
as one particular second on one day of the month, or as
frequently as once per second continuously. The MSB of each
alarm register is a match bit. Selecting none of the match bits (all
1s) indicates that no match is required. The alarm occurs every
second. Setting the match select bit for seconds to ‘0’ causes the
logic to match the seconds alarm value to the current time of day.
Since a match occurs for only one value per minute, the alarm
occurs once per minute. Similarly, setting the seconds and
minutes match bits causes an exact match of these values. Thus,
an alarm occurs once per hour. Setting seconds, minutes, and
hours causes a match once per day. Lastly, selecting all match
values causes an exact time and date match. Selecting other bit
combinations does not produce meaningful results; however, the
alarm circuit must follow the functions described.
There are two ways to detect an alarm event: by reading the AF
flag or by monitoring the INT pin. The AF flag in the flags register
at 0x1FFF0 indicates that a date or time match has occurred.
The AF bit is set to ‘1’ when a match occurs. Reading the flags
or control register clears the alarm flag bit (and all others). A
hardware interrupt pin is used to detect an alarm event.
Watchdog Timer
The watchdog timer is a free running down counter that uses the
32 Hz clock (31.25 ms) derived from the crystal oscillator. The
oscillator must be running for the watchdog to function. It begins
counting down from the value loaded in the watchdog timer
register.
The counter consists of a loadable register and a free running
counter. On power up, the watchdog timeout value in register
0x1FFF7 is loaded into the counter load register. Counting
begins on power up and restarts from the loadable value any time
the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is
compared to the terminal value of 0. If the counter reaches this
value, it causes an internal flag and an optional interrupt output.
The timeout interrupt is prevented by setting WDS bit to ‘1’ before
the counter reaches ‘0’. This causes the counter to reload with
the watchdog timeout value and get restarted. As long as the
WDS bit is set before the counter reaches the terminal value, the
interrupt and flag never occurs.
New timeout values are written by setting the watchdog write bit
to ‘0’. When the WDW is ‘0’ (from the previous operation), new
writes to the watchdog timeout value bits D5–D0 allow the modification of timeout values. When WDW is ‘1’, then writes to bits
D5–D0 are ignored. The WDW function allows to set the WDS
bit without concern that the watchdog timer value is modified. A
logical diagram of the watchdog timer is shown in Figure 3 on
page 8. Note that setting the watchdog timeout value to ‘0’ is
otherwise meaningless and as a result, disables the watchdog
function.
The output of the watchdog timer is a flag bit WDF that is set if
the watchdog is allowed to timeout. The flag is set upon a
watchdog timeout and cleared when the flags control register is
read by the user. The user can also enable an optional interrupt
source to drive the INT pin if the watchdog timeout occurs.
Page 7 of 28
[+] Feedback
PRELIMINARY
Figure 3. Watchdog Timer Block Diagram
CY14E104K/CY14E104M
an interrupt output. Only one source is necessary to drive the pin.
The user can identify the source by reading the flags or control
register, which contains the flags associated with each source.
All flags are cleared to ‘0’ when the register is read. The cycle
must be a complete read cycle (WE HIGH); otherwise, the flags
are not cleared. The power monitor has two programmable
settings that are explained in Power Monitor on page 8.
After an interrupt source is active, the pin driver determines the
behavior of the output. It has two programmable settings. Pin
driver control bits are located in the interrupts register.
According to the programming selections, the pin is driven in the
backup mode for an alarm interrupt. In addition, the pin is an
active LOW (open drain) or an active HIGH (push pull) driver. If
programmed for operation during backup mode, it is active LOW.
Lastly, the pin provides a one shot function so that the active
condition is a pulse or a level condition. In one shot mode, the
pulse width is internally fixed at approximately 200 ms. This
mode is intended to reset a host microcontroller. In the level
mode, the pin goes to its active polarity until the flags or control
register is read by the user. This mode is used as an interrupt to
a host microcontroller. The control bits are summarized as
follows.
Power Monitor
The CY14E104K/CY14E104M provides a power management
scheme with power fail interrupt capability. It also controls the
internal switch to backup power for the clock and protects the
memory from low VCC access. The power monitor is based on
an internal band gap reference circuit that compares the VCC
voltage to various thresholds.
As described in the section AutoStore Operation on page 3,
when VSWITCH is reached as VCC decays from power loss, a data
store operation is initiated from SRAM to the nonvolatile
elements, securing the last SRAM data state. Power is also
switched from VCC to the backup supply (battery or capacitor) to
operate the RTC oscillator.
When operating from the backup source, no data is read or
written and the clock functions are not available to the user. The
clock continues to operate in the background. The updated clock
data is available to the user after tHRECALL delay (see
AutoStore/Power Up RECALL on page 16) after VCC is restored
to the device.
Interrupts
The CY14E104K/CY14E104M provides three potential interrupt
sources. They include the watchdog timer, the power monitor,
and the clock or calendar alarm. Each are individually enabled
and assigned to drive the INT pin. In addition, each has an
associated flag bit that the host processor can use to determine
the cause of the interrupt. Some of the sources have additional
control bits that determine functional behavior. In addition, the
pin driver has three bits that specify its behavior when an
interrupt occurs.
The three interrupts each have a source and an enable. Both the
source and the enable must be active (true HIGH) to generate
Document #: 001-09604 Rev. *H
Watchdog Interrupt Enable - WIE. When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog timeout occurs. When WIE is set to ‘0’, the watchdog
timer affects only the internal flag.
Alarm Interrupt Enable - AIE. When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When set to ‘0’, the alarm
match only affects the internal flag.
Power Fail Interrupt Enable - PFE. When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When set to ‘0’,
the power fail monitor affects only the internal flag.
High/Low - H/L. When set to a ‘1’, the INT pin is active HIGH
and the driver mode is push pull. The INT pin can drive HIGH
only when VCC > VSWITCH. When set to ‘0’, the INT pin is active
LOW and the drive mode is open drain. Active LOW (open drain)
is operational even in battery backup mode.
Pulse/Level - P/L. When set to ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to
‘0’, the INT pin is driven HIGH or LOW (determined by H/L) until
the flags or control register is read.
When an enabled interrupt source activates the INT pin, an
external host can read the flags or control register to determine
the cause. All flags are cleared when the register is read. If the
INT pin is programmed for level mode, then the condition clears
and the INT pin returns to its inactive state. If the pin is
programmed for pulse mode, then reading the flag also clears
the flag and the pin. The pulse does not complete its specified
duration if the flags or control register is read. If the INT pin is
used as a host reset, then the flags or control register must not
be read during a reset.
During a power on reset with no battery, the interrupt register is
automatically loaded with the value 24h. This enables the power
fail interrupt with an active LOW pulse.
Page 8 of 28
[+] Feedback
PRELIMINARY
CY14E104K/CY14E104M
Figure 4. RTC Recommended Component Configuration
Recommended Values
Y1 = 32.768KHz
RF = 10M Ohm
C1 = 0
C2 = 56 pF
.
Figure 5. Interrupt Block Diagram
Legend
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt Enable
PF - Power fail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - HIGH/LOW
Document #: 001-09604 Rev. *H
Page 9 of 28
[+] Feedback
CY14E104K/CY14E104M
PRELIMINARY
Table 3. RTC Register Map
Register
BCD Format Data
D7
0x1FFFF
0x1FFFE
D6
D5
D4
D3
D2
D1
10s Years
0
0
0x1FFFD
0
0
0x1FFFC
0
0
0x1FFFB
0
0
0x1FFFA
0
0
0
0
Years: 00–99
Months
Months: 01–12
Day Of Month
Day of Month: 01–31
0
Day of week
10s Hours
10s Minutes
0x1FFF9
10s Seconds
0x1FFF8 OSCEN
0
Day of week: 01–07
Hours
Hours: 00–23
Minutes
Minutes: 00–59
Seconds
Cal Sign
Function/Range
Years
10s
Months
10s Day of Month
D0
Seconds: 00–59
Calibration Values [7]
Calibration
Watchdog [7]
0x1FFF7
WDS
WDW
0x1FFF6
WIE
AIE
0x1FFF5
M
0
10s Alarm Date
Alarm Date
Alarm, Day of Month: 01–31
0x1FFF4
M
0
10s Alarm Hours
Alarm Hours
Alarm, Hours: 00–23
0x1FFF3
M
10 Alarm Minutes
Alarm Minutes
Alarm, Minutes: 00–59
0x1FFF2
M
10 Alarm Seconds
Alarm Seconds
Alarm, Seconds: 00–59
0x1FFF1
0x1FFF0
WDT
PFE
0
H/L
10s Centuries
WDF
AF
PF
P/L
0
0
Centuries
OSCF
0
CAL
W
Interrupts [7]
Centuries: 00–99
R
Flags[7]
Note
7. This is a binary value, not a BCD value.
Document #: 001-09604 Rev. *H
Page 10 of 28
[+] Feedback
CY14E104K/CY14E104M
PRELIMINARY
Table 4. Register Map Detail
Time Keeping - Years
D7
D6
0x1FFFF
D5
D4
D3
D2
10s Years
D1
D0
Years
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value
for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.
Time Keeping - Months
0x1FFFE
D7
D6
D5
D4
0
0
0
10s Month
D3
D2
D1
D0
Months
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one
bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12.
Time Keeping - Date
0x1FFFD
D7
D6
0
0
D5
D4
D3
10s Day of Month
D2
D1
D0
Day of Month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble contains the upper digit and operates from 0 to 3. The range for the register is 1–31. Leap years are automatically
adjusted for.
Time Keeping - Day
0x1FFFC
D7
D6
D5
D4
D3
0
0
0
0
0
D2
D1
D0
Day of Week
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1
to 7 then returns to 1. The user must assign meaning to the day value, because the day is not integrated with the date.
Time Keeping - Hours
0x1FFFB
D7
D6
12/24
0
D5
D4
D3
D2
10s Hours
D1
D0
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to 9; upper
nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0–23.
Time Keeping - Minutes
D7
0x1FFFA
D6
0
D5
D4
D3
D2
10s Minutes
D1
D0
Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains
the upper minutes digit and operates from 0 to 5. The range for the register is 0–59.
Time Keeping - Seconds
D7
0x1FFF9
D6
0
D5
D4
D3
D2
10s Seconds
D1
D0
Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains
the upper digit and operates from 0 to 5. The range for the register is 0–59.
Calibration/Control
0X1FFF8
OSCEN
D7
D6
D5
OSCEN
0
Calibration
Sign
D4
D3
D2
D1
D0
Calibration
Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator
saves battery or capacitor power during storage. On a no-battery power up, this bit is set to 0.
Calibration Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base.
Sign
Calibration These five bits control the calibration of the clock.
Document #: 001-09604 Rev. *H
Page 11 of 28
[+] Feedback
CY14E104K/CY14E104M
PRELIMINARY
Table 4. Register Map Detail (continued)
WatchDog Timer
0x1FFF7
D7
D6
WDS
WDW
D5
D4
D3
D2
D1
D0
WDT
WDS
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no effect. The bit
is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0.
WDW
Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT5–WDT0) so it cannot be written.
This allows the user to strobe the watchdog without disturbing the timeout value. Setting this bit to 0 allows bits 5–0 to
be written on the next write to the watchdog register. The new value is loaded on the next internal watchdog clock after
the write cycle is complete. This function is explained in more detail in Watchdog Timer on page 7.
WDT
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a
multiplier of the 32 Hz count (31.25 ms). The minimum range or timeout value is 31.25 ms (a setting of 1) and the
maximum timeout is 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits
are written only if the WDW bit was cleared to 0 on a previous cycle.
Interrupt Status/Control
0x1FFF6
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFIE
0
H/L
P/L
0
0
WIE
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives the INT pin and
the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag.
AIE
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When set to 0, the alarm
match only affects the AF flag.
PFIE
Power Fail Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When set to 0, the power fail
monitor affects only the PF flag.
H/L
High/Low. When set to a 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open drain, active LOW.
P/L
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately
200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until the flags or control register is read.
Alarm - Day
0x1FFF5
D7
D6
M
0
D5
D4
D3
D2
10s Alarm Date
D1
D0
Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
M
Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1 causes the match circuit
to ignore the date value.
Alarm - Hours
0x1FFF4
D7
D6
M
0
D5
D4
D3
D2
10s Alarm Hours
D1
D0
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
M
Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit
to ignore the hours value.
Alarm - Minutes
0x1FFF3
D7
D6
M
0
D5
D4
D3
10s Alarm Minutes
D2
D1
D0
Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
M
Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to 1 causes the match
circuit to ignore the minutes value.
Alarm - Seconds
0x1FFF2
D7
D6
M
0
D5
D4
10s Alarm Seconds
D3
D2
D1
D0
Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
Document #: 001-09604 Rev. *H
Page 12 of 28
[+] Feedback
CY14E104K/CY14E104M
PRELIMINARY
Table 4. Register Map Detail (continued)
M
Match. When this bit is set to 0, the seconds’ value is used in the alarm match. Setting this bit to 1 causes the match
circuit to ignore the seconds value.
Time Keeping - Centuries
0x1FFF1
D7
D6
0
0
D5
D4
D3
D2
D7
D6
D5
D4
D3
D2
D1
D0
WDF
AF
PF
OSCF
0
CAL
W
R
10s Centuries
D1
D0
Centuries
Flags
0x1FFF0
WDF
Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset
by the user. It is cleared to 0 when the Flags/Control register is read.
AF
Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the
match bits = 0. It is cleared when the Flags/Control register is read.
PF
Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold VSWITCH. It is cleared to
0 when the Flags/Control register is read.
OSCF
Oscillator Fail Flag. Set to 1 on power up only if the oscillator is not running in the first 5 ms of power on operation. This
indicates that time counts are no longer valid. The user must reset this bit to 0 to clear this condition. The chip does not
clear this flag. This bit survives power cycles.
CAL
Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin resumes
normal operation. This bit defaults to 0 (disabled) on power up.
W
Write Time. Setting the W bit to 1 freeze updates of the timekeeping registers. The user can then write them with updated
values. Setting the W bit to 0 transfers the contents of the time registers to the timekeeping counters.
R
Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places them in a holding register.
The user can then read them without concerns over changing values causing system errors. The R bit going from 0 to
1 causes the timekeeping capture, so the bit must be returned to 0 before reading again.
Document #: 001-09604 Rev. *H
Page 13 of 28
[+] Feedback
CY14E104K/CY14E104M
PRELIMINARY
Maximum Ratings
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Surface Mount Pb Soldering
Temperature (3 Seconds) .......................................... +260°C
Storage Temperature ................................. –65°C to +150°C
Output Short Circuit Current[8] ..................................... 15 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +150°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Supply Voltage on VCC Relative to GND ..........–0.5V to 7.0V
Latch Up Current ................................................... > 200 mA
Voltage Applied to Outputs
in High-Z State....................................... –0.5V to VCC + 0.5V
Operating Range
Input Voltage.............................................–0.5V to Vcc+0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V
Range
Ambient Temperature
VCC
0°C to +70°C
4.5V to 5.5V
–40°C to +85°C
4.5V to 5.5V
Commercial
Industrial
DC Electrical Characteristics
Over the Operating Range (VCC = 4.5V to 5.5V) [10]
Parameter
Description
ICC1
Average Vcc Current
ICC2
ICC3[9]
ICC4
ISB
IIX
IOZ
VIH
VIL
VOL
VOH
VCAP
Test Conditions
Min
Max
Unit
tRC = 15 ns
Commercial
tRC = 20 ns
tRC = 25 ns
tRC = 45 ns
Dependent on output loading and cycle rate.Values Industrial
obtained without output loads. IOUT = 0 mA
70
65
65
50
75
70
70
52
mA
mA
mA
All Inputs Don’t Care, VCC = Max.
Average current for duration tSTORE
Average VCC Current WE > (VCC – 0.2). All other I/P cycling.
at tRC = 200 ns, 5V,
Dependent on output loading and cycle rate. Values obtained
25°C typical
without output loads.
Average VCAP Current All Inputs Don’t Care, VCC = Max.
during AutoStore
Average current for duration tSTORE
Cycle
VCC Standby Current CE > (VCC – 0.2).All others VIN < 0.2V or >(VCC – 0.2V). Standby
current level after nonvolatile cycle is complete.
Inputs are static. f = 0MHz.
6
mA
35
mA
6
mA
3
mA
–1
+1
μA
–100
+1
μA
–1
+1
μA
Average VCC Current
during STORE
Input Leakage Current VCC = Max, VSS < VIN < VCC
(except HSB)
Input Leakage Current VCC = Max, VSS < VIN < VCC
(for HSB)
Off State Output
VCC = Max., VIN = VSS < VIN < VCC, CE or OE > VIH
Leakage Current
Input HIGH Voltage
Input LOW Voltage
Output LOW Voltage
Output HIGH Voltage
Storage Capacitor
IOUT = 4 mA
IOUT = –2 mA
Between VCAP pin and VSS, 5V Rated
2.2
VCC + 0.5
Vss – 0.5
0.8
0.4
2.4
61
82
mA
mA
mA
V
V
V
V
μF
Notes
8. Outputs shorted for no more than one second. Only one output is shorted at a time.
9. Typical conditions for the active current shown on the front page of the data sheet are average values at 25°C (room temperature), and VCC = 5V. Not 100% tested.
10. The HSB pin has IOUT=-10 uA for VOH of 2.4V.This parameter is characterized but not tested.
Document #: 001-09604 Rev. *H
Page 14 of 28
[+] Feedback
CY14E104K/CY14E104M
PRELIMINARY
Capacitance
In the following table, the capacitance parameters are listed. [11]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0V
Unit
7
pF
7
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[11]
Parameter
ΘJA
Description
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
44-TSOP II
54-TSOPII
Unit
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, in accordance with EIA/JESD51.
31.11
30.73
°C/W
5.56
6.08
°C/W
Figure 6. AC Test Loads
963Ω
5.0V
963Ω
5.0V
R1
R1
OUTPUT
OUTPUT
30 pF
R2
512Ω
R2
512Ω
5 pF
AC Test Conditions
Input Pulse Levels ................................................... 0V to 3V
Input Rise and Fall Times (10% - 90%) ....................... <5 ns
Input and Output Timing Reference Levels ....................1.5V
Table 5. RTC Characteristics
Parameters
Description
Test Conditions
Min
Max
Units
300
nA
350
nA
3.3
V
IBAK [12]
RTC Backup Current
Commercial
VRTCbat [13]
RTC Battery Pin Voltage
Commercial
1.8
Industrial
1.8
3.3
V
VRTCcap [14]
RTC Capacitor Pin Voltage
Commercial
1.5
3.6
V
Industrial
1.5
3.6
V
tOCS
RTC Oscillator Time to Start At Minimum Temperature from Power up or
Enable
Commercial
10
sec
At 25°C Temperature from Power up or Enable Commercial
5
sec
At Minimum Temperature from Power up or
Enable
Industrial
10
sec
At 25°C Temperature from Power up or Enable Industrial
5
sec
Industrial
Notes
11. These parameters are guaranteed but not tested.
12. From either VRTCcap or VRTCbat.
13. Typical = 3.0V during normal operation.
14. Typical = 2.4V during normal operation.
Document #: 001-09604 Rev. *H
Page 15 of 28
[+] Feedback
CY14E104K/CY14E104M
PRELIMINARY
AC Switching Characteristics
Parameters
15 ns
Description
Cypress
Alt
Parameters Parameters
Min
20 ns
Max
Min
25 ns
Max
Min
Max
45 ns
Min
Max
Unit
SRAM Read Cycle
tACE
tACS
Chip Enable Access Time
tRC [15]
tRC
Read Cycle Time
tAA [16]
tAA
Address Access Time
15
20
25
45
ns
tDOE
tOE
Output Enable to Data Valid
10
10
12
20
ns
tOHA
tOH
Output Hold After Address Change
3
3
3
3
ns
tLZCE [17]
tLZ
Chip Enable to Output Active
3
3
3
3
ns
[17]
tHZCE
tHZ
Chip Disable to Output Inactive
tLZOE [17]
tOLZ
Output Enable to Output Active
[17]
tHZOE
15
15
20
20
7
0
25
25
8
0
7
45
45
10
0
15
0
ns
tOHZ
Output Disable to Output Inactive
tPA
Chip Enable to Power Active
tPD [11]
tPS
Chip Disable to Power Standby
15
20
25
45
ns
tDBE
-
Byte Enable to Data Valid
10
10
12
20
ns
tLZBE
-
Byte Enable to Output Active
tHZBE
-
Byte Disable to Output Inactive
0
0
0
0
7
10
ns
tPU [11]
0
8
ns
ns
0
8
15
0
0
10
ns
ns
ns
15
ns
SRAM Write Cycle
tWC
tWC
Write Cycle Time
15
20
25
45
ns
tPWE
tWP
Write Pulse Width
10
15
20
30
ns
tSCE
tCW
Chip Enable To End of Write
15
15
20
30
ns
tSD
tDW
Data Setup to End of Write
5
8
10
15
ns
tHD
tDH
Data Hold After End of Write
0
0
0
0
ns
tAW
tAW
Address Setup to End of Write
10
15
20
30
ns
tSA
tAS
Address Setup to Start of Write
0
0
0
0
ns
tHA
tWR
Address Hold After End of Write
0
0
0
0
ns
tHZWE [17,18] tWZ
tLZWE [17]
tOW
Write Enable to Output Disable
Output Active after End of Write
3
3
3
3
ns
tBW
Byte Enable to End of Write
15
15
20
30
ns
-
7
8
10
15
ns
AutoStore/Power Up RECALL
Parameters
Description
CY14E104K/CY14E104M
Min
Max
Unit
tHRECALL [19]
Power Up RECALL Duration
20
ms
tSTORE [20]
STORE Cycle Duration
15
ms
VSWITCH
Low Voltage Trigger Level
tVCCRISE
VCC Rise Time
4.4
150
V
μs
Notes
15. WE must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE and OE both LOW.
17. Measured ±200 mV from steady state output voltage.
18. If WE is low when CE goes low, the outputs remain in the high impedance state.
19. tHRECALL starts from the time Vcc rises above VSWITCH.
20. If an SRAM write has not taken place since the last nonvolatile cycle, no STORE takes place.
Document #: 001-09604 Rev. *H
Page 16 of 28
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CY14E104K/CY14E104M
PRELIMINARY
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed.[21, 22]
Parameters
15 ns
Description
Min
15 ns
Max
Min
25 ns
Max
Min
45 ns
Max
Min
Max
Unit
tRC
STORE/RECALL Initiation Cycle Time
15
20
25
45
ns
tAS
Address Setup Time
0
0
0
0
ns
tCW
Clock Pulse Width
12
15
20
30
ns
tGHAX
Address Hold Time
1
1
1
tRECALL
RECALL Duration
200
200
200
200
μs
tSS [23,24]
Soft Sequence Processing Time
70
70
70
70
μs
ns
Hardware STORE Cycle
Parameters
CY14E104K/CY14E104M
Description
Min
Max
70
tDELAY [25]
Time Allowed to Complete SRAM Cycle
1
tHLHX
Hardware STORE Pulse Width
15
Unit
μs
ns
Switching Waveforms
Figure 7. SRAM Read Cycle #1: Address Controlled[15, 16, 26]
tRC
ADDRESS
t AA
t OHA
DQ (DATA OUT)
DATA VALID
Notes
21. The software sequence is clocked with CE controlled or OE controlled reads.
22. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles.
23. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
24. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command.
25. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read and write cycles to complete.
26. HSB must remain HIGH during read and write cycles.
Document #: 001-09604 Rev. *H
Page 17 of 28
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CY14E104K/CY14E104M
PRELIMINARY
Switching Waveforms
(continued)
Figure 8. SRAM Read Cycle #2: CE Controlled[15, 26, 28]
tRC
ADDRESS
tACE
tLZCE
CE
tPD
tHZCE
OE
tLZOE
t HZOE
tDOE
BHE , BLE
tLZBE
DQ (DATA OUT)
tHZCE
tHZBE
tDBE
DATA VALID
t PU
ACTIVE
STANDBY
ICC
Figure 9. SRAM Write Cycle #1: WE Controlled[18, 26, 27, 28]
tWC
ADDRESS
tHA
tSCE
CE
tAW
tSA
tPWE
WE
tBW
BHE , BLE
tSD
DATA VALID
DATA IN
tHZWE
DATA OUT
tHD
PREVIOUS DATA
HIGH IMPEDANCE
tLZWE
Notes
27. CE or WE must be > VIH during address transitions.
28. BHE and BLE are applicable for x16 configuration only.
Document #: 001-09604 Rev. *H
Page 18 of 28
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CY14E104K/CY14E104M
PRELIMINARY
Switching Waveforms
(continued)
Figure 10. SRAM Write Cycle #2: CE Controlled[18, 26, 27, 28]
tWC
ADDRESS
tSA
tSCE
CE
tHA
tAW
tPWE
WE
tBW
BHE , BLE
tSD
DATA IN
tHD
DATA VALID
HIGH IMPEDANCE
DATA OUT
Figure 11. AutoStore/Power Up RECALL
No STORE occurs
without atleast one
SRAM write
STORE occurs only
if a SRAM write
has happened
VCC
VSWITCH
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
tHRECALL
Read & Write Inhibited
Note
29. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
Document #: 001-09604 Rev. *H
Page 19 of 28
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CY14E104K/CY14E104M
PRELIMINARY
Switching Waveforms
(continued)
Figure 12. CE Controlled Software STORE/RECALL Cycle[22]
Figure 13. OE Controlled Software STORE/RECALL Cycle[22]
tRC
ADDRESS # 1
ADDRESS
CE
tAS
ADDRESS # 6
tCW
OE
tGHAX
Document #: 001-09604 Rev. *H
DATA VALID
a
a
DQ (DATA)
t STORE / t RECALL
DATA VALID
a
a
a
a
a
a
a
a
a
a
a a
tRC
HIGH IMPEDANCE
Page 20 of 28
[+] Feedback
PRELIMINARY
Switching Waveforms
CY14E104K/CY14E104M
(continued)
Figure 14. Hardware STORE Cycle[25]
Figure 15. Soft Sequence Processing[23, 24]
tSS
Document #: 001-09604 Rev. *H
tSS
Page 21 of 28
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PRELIMINARY
CY14E104K/CY14E104M
PART NUMBERING NOMENCLATURE
CY 14 E 104 K - ZS P 15 X C T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
P - 54 Pin
Blank - 44 Pin
Speed:
15 - 15 ns
20 - 20 ns
25 - 25 ns
45 - 45 ns
Package:
ZS - TSOP II
Data Bus:
K - x8 + RTC
M - x16 + RTC
Density:
104 - 4 Mb
Voltage:
E - 5.0V
NVSRAM
14 - AutoStore + Software Store + Hardware Store
Cypress
Document #: 001-09604 Rev. *H
Page 22 of 28
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PRELIMINARY
CY14E104K/CY14E104M
Ordering Information
Speed
(ns)
15
20
25
Ordering Code
Package
Diagram
Package Type
Operating
Range
CY14E104K-ZS15XCT
51-85087
44-pin TSOPII
Commercial
CY14E104K-ZS15XIT
51-85087
44-pin TSOPII
Industrial
CY14E104K-ZS15XI
51-85087
44-pin TSOPII
CY14E104M-ZS15XCT
51-85087
44-pin TSOPII
Commercial
Industrial
CY14E104M-ZS15XIT
51-85087
44-pin TSOPII
CY14E104M-ZS15XI
51-85087
44-pin TSOPII
CY14E104K-ZSP15XCT
51-85160
54-pin TSOPII
Commercial
CY14E104K-ZSP15XIT
51-85160
54-pin TSOPII
Industrial
CY14E104K-ZSP15XI
51-85160
54-pin TSOPII
CY14E104M-ZSP15XCT
51-85160
54-pin TSOPII
Commercial
CY14E104M-ZSP15XIT
51-85160
54-pin TSOPII
Industrial
CY14E104M-ZSP15XI
51-85160
54-pin TSOPII
CY14E104K-ZS20XCT
51-85087
44-pin TSOPII
Commercial
CY14E104K-ZS20XIT
51-85087
44-pin TSOPII
Industrial
CY14E104K-ZS20XI
51-85087
44-pin TSOPII
CY14E104M-ZS20XCT
51-85087
44-pin TSOPII
Commercial
Industrial
CY14E104M-ZS20XIT
51-85087
44-pin TSOPII
CY14E104M-ZS20XI
51-85087
44-pin TSOPII
CY14E104K-ZSP20XCT
51-85160
54-pin TSOPII
Commercial
CY14E104K-ZSP20XIT
51-85160
54-pin TSOPII
Industrial
CY14E104K-ZSP20XI
51-85160
54-pin TSOPII
CY14E104M-ZSP20XCT
51-85160
54-pin TSOPII
Commercial
CY14E104M-ZSP20XIT
51-85160
54-pin TSOPII
Industrial
CY14E104M-ZSP20XI
51-85160
54-pin TSOPII
CY14E104K-ZS25XCT
51-85087
44-pin TSOPII
Commercial
CY14E104K-ZS25XIT
51-85087
44-pin TSOPII
Industrial
CY14E104K-ZS25XI
51-85087
44-pin TSOPII
CY14E104M-ZS25XCT
51-85087
44-pin TSOPII
Commercial
Industrial
CY14E104M-ZS25XIT
51-85087
44-pin TSOPII
CY14E104M-ZS25XI
51-85087
44-pin TSOPII
CY14E104K-ZSP25XCT
51-85160
54-pin TSOPII
Commercial
CY14E104K-ZSP25XIT
51-85160
54-pin TSOPII
Industrial
CY14E104K-ZSP25XI
51-85160
54-pin TSOPII
CY14E104M-ZSP25XCT
51-85160
54-pin TSOPII
Commercial
CY14E104M-ZSP25XIT
51-85160
54-pin TSOPII
Industrial
CY14E104M-ZSP25XI
51-85160
54-pin TSOPII
Document #: 001-09604 Rev. *H
Page 23 of 28
[+] Feedback
PRELIMINARY
CY14E104K/CY14E104M
Ordering Information (continued)
Speed
(ns)
45
Ordering Code
Package
Diagram
Package Type
Operating
Range
CY14E104K-ZS45XCT
51-85087
44-pin TSOPII
Commercial
CY14E104K-ZS45XIT
51-85087
44-pin TSOPII
Industrial
CY14E104K-ZS45XI
51-85087
44-pin TSOPII
CY14E104M-ZS45XCT
51-85087
44-pin TSOPII
Commercial
Industrial
CY14E104M-ZS45XIT
51-85087
44-pin TSOPII
CY14E104M-ZS45XI
51-85087
44-pin TSOPII
CY14E104K-ZSP45XCT
51-85160
54-pin TSOPII
Commercial
CY14E104K-ZSP45XIT
51-85160
54-pin TSOPII
Industrial
CY14E104K-ZSP45XI
51-85160
54-pin TSOPII
CY14E104M-ZSP45XCT
51-85160
54-pin TSOPII
Commercial
CY14E104M-ZSP45XIT
51-85160
54-pin TSOPII
Industrial
CY14E104M-ZSP45XI
51-85160
54-pin TSOPII
All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 001-09604 Rev. *H
Page 24 of 28
[+] Feedback
CY14E104K/CY14E104M
PRELIMINARY
Package Diagrams
Figure 16. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH)
MAX
MIN.
PIN 1 I.D.
1
23
10.262 (0.404)
10.058 (0.396)
11.938 (0.470)
11.735 (0.462)
22
EJECTOR PIN
44
TOP VIEW
0.800 BSC
(0.0315)
OR E
K X A
SG
BOTTOM VIEW
0.400(0.016)
0.300 (0.012)
10.262 (0.404)
10.058 (0.396)
BASE PLANE
0.210 (0.0083)
0.120 (0.0047)
0°-5°
0.10 (.004)
0.150 (0.0059)
0.050 (0.0020)
1.194 (0.047)
0.991 (0.039)
18.517 (0.729)
18.313 (0.721)
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
51-85087-*A
Document #: 001-09604 Rev. *H
Page 25 of 28
[+] Feedback
PRELIMINARY
Package Diagrams
CY14E104K/CY14E104M
(continued)
Figure 17. 54-Pin TSOP II (51-85160)
51-85160-**
Document #: 001-09604 Rev. *H
Page 26 of 28
[+] Feedback
PRELIMINARY
CY14E104K/CY14E104M
Document History Page
Document Title: CY14E104K/CY14E104M 4 Mbit (512K x 8 / 256K x 16) nvSRAM with Real-Time-Clock
Document Number: 001-09604
Orig. of
Rev. ECN No. Submission
Description of Change
Date
Change
**
493192
See ECN
TUP
New Data Sheet
*A
499597
See ECN
PCI
Removed 35 ns speed bin.
Added 55 ns speed bin. Updated AC table for the same.
Changed “Unlimited” read/write to “infinite” read/write
Features section: Changed typical ICC at 200-ns cycle time to 8 mA
Changed STORE cycles from 500K to 200K cycles.
Shaded Commercial grade in operating range table.
Modified Icc/Isb specs.
Changed VCAP value in DC table
Modified part nomenclature table. Changes reflected in the ordering information table.
*B
517928
See ECN
TUP
Removed 55ns speed bin
Changed the pinout for 44TSOPII and 54TSOPII packages
Changed ISB to 1mA. Changed ICC4 to 3mA
Changed tSTORE to 15ns. Changed tPWE to 10ns
Changed tSCE to 15ns. Changed tSD to 5ns
Changed tAW to 10ns. Removed tHLBL
Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW
Removed min. specification for Vswitch
Changed tGLAX to 1ns. Added tDELAY max. of 70us
Changed tSS specification from 70us min. to 70us max.
*C
774157
See ECN
UHA
Changed the data sheet from Advance information to Preliminary
Changed tDBE to 10ns in 15ns part
Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns
Changed tBW in 15ns part to 15ns and in 25ns part to 20ns
Changed tGLAX to tGHAX
Changed the value of ICC3 to 25mA
Changed the value of tAW to15ns in 15ns part
Changed Note 1 to include 16Mbit
In AC test loads changed the value of R1 to 963Ω and R2 to 512Ω
*D
914280
See ECN
UHA
Changed the figure-14 title from 54-Pb to 54 Pin
Included all the information for 45ns part in this data sheet
*E
1890926
See ECN
vsutmp8 Updated logic block diagram
/AESA Added Footnote 1, 2 and 3.
Updated Pin definition table
Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8).
Corrected typo in VIL min spec
Changed Vswitch value from 2.65V to 4.4V
Changed the value of ICC3 from 25mA to 13mA
Changed ISB value from 1mA to 2mA
updated ordering information table
Changed package diagrams title
The pins X1 and X2 interchanged in 44TSOP II(x8) and 54TSOP II(x16) pinout.
*F
2267286
See ECN
GVCH/ Rearranging of “Features”. Updated Figure 2 (Autostore mode)
PYRS RTC Register Map:Register 0x1FFF6:Changed D4 from ABE to 0
Register Map Detail:0x1FFF6:Changed D4 from ABE to 0 and removed ABE Info
Changed ICC2 & ICC4 from 3mA to 6mA. Changed ICC3 from 13mA to 15mA
Changed ISB from 2mA to 3mA
Added input leakage current (IIX) for HSB in DC Electrical Characteristics table
Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max value
Changed Vrtccap max from 2.7V to 3.6V. Changed tRECALL from 100 to 200us
45ns speed information is added in Software Controlled Store/Recall Cycle Table
Corrected typo in tAW value from 15ns to 10ns for 15ns part
Reframed footnote 6, 18 and 25. Added footnote 29
Added footnote 18 to figure 8 and footnote 18, 26 and 27 to figure 9.
Document #: 001-09604 Rev. *H
Page 27 of 28
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PRELIMINARY
CY14E104K/CY14E104M
Document Title: CY14E104K/CY14E104M 4 Mbit (512K x 8 / 256K x 16) nvSRAM with Real-Time-Clock
Document Number: 001-09604
Orig. of
Rev. ECN No. Submission
Description of Change
Date
Change
*G
2483627
See ECN
GVCH/ Removed 8 mA typical ICC at 200 ns cycle time in Feature section
PYRS Referenced footnote 9 to ICC3 in DC Characteristics table
Changed ICC3 from 15 mA to 35 mA
Changed Vcap minimum value from 54 uF to 61 uF
Changed tAVAV to tRC. Changed VRTCcap minimum value from 1.2V to 1.5V
Figure 12:Changed tSA to tAS and tSCE to tCW
*H
2519319
06/20/08
GVCH/ Added 20 ns access speed in “Features”
PYRS Added ICC1 for tRC=20 ns for both industrial and Commecial temperature Grade
Updated thermal resistance values for 44-TSOP II and 54-TSOP II packages
Added AC Switching Characteristics specs for 20 ns access speed
Added Software controlled STORE/RECALL cycle specs for 20 ns access speed
Updated ordering information and Part numbering nomenclature
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-09604 Rev. *H
Revised June 20, 2008
Page 28 of 28
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. All products
and company names mentioned in this document may be the trademarks of their respective holders.
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