SLAS396A − JULY 2003 − REVISED APRIL 2004
Low Supply-Voltage Range, 2.7 V . . . 3.6 V
Ultralow-Power Consumption:
Brownout Detector
Supply Voltage Supervisor/Monitor With
− Active Mode: 400 µA at 1 MHz, 3.0 V
− Standby Mode: 1.6 µA
− Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Wake-Up From Standby Mode in less
than 6 µs
Frequency-Locked Loop, FLL+
16-Bit RISC Architecture, 125-ns
Instruction Cycle Time
Embedded Signal Processing for
Single-Phase Energy Metering with
Integrated Analog Front-End and
Temperature Sensor (ESP430CE1)
16-Bit Timer_A With Three
Capture/Compare Registers
Integrated LCD Driver for 128 Segments
Serial Communication Interface (USART),
Asynchronous UART or Synchronous SPI
selectable by software
Programmable Level Detection
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Bootstrap Loader in Flash Devices
Family Members Include:
− MSP430FE423:
8KB + 256B Flash Memory,
256B RAM
− MSP430FE425:
16KB + 256B Flash Memory,
512B RAM
− MSP430FE427:
32KB + 256B Flash Memory,
1KB RAM
Available in 64-Pin Quad Flat Pack (QFP)
For Complete Module Descriptions, Refer
to the MSP430x4xx Family User’s Guide,
Literature Number SLAU056
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.
The MSP430FE42x series are microcontroller configurations with three independent 16-bit sigma-delta A/D
converters and embedded signal processor core used to measure and calculate single-phase energy in both
2 and 3 wire configurations. Also included is a built-in 16-bit timer, 128 LCD segment drive capability, and 14
I/O pins.
Typical applications include 2-wire and 3-wire single-phase metering including tamper-resistant meter
implementations.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
−40°C to 85°C
PLASTIC 64-PIN QFP
(PM)
MSP430FE423IPM
MSP430FE425IPM
MSP430FE427IPM
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003 − 2004 Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # # "#
'' *+( '"! $!#, '# #!#&+ !&"'#
#, && $##(
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SLAS396A − JULY 2003 − REVISED APRIL 2004
AVCC
DVSS
AVSS
P2.3/SVSIN
P2.4/UTXD0
P2.5/URXD0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1/S31
P1.3/SVSOUT/S30
P1.4/S29
pin designation
DVCC
I1+
I1−
I2+
I2−
V1+
V1−
XIN
XOUT
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
42
9
40
VREF
10
39
P2.2/STE0
S0
S1
S2
S3
S4
11
38
12
37
13
36
14
35
15
34
8
MSP430FE42x
41
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
† Open connection recommended for all unused analog inputs.
2
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P1.5/TACLK/ACLK/S28
P1.6/SIMO0/S27
P1.7/SOMI0/S26
P2.0/TA2/S25
P2.1/UCLK0/S24
R33
R23
R13
R03
COM3
COM2
COM1
COM0
S23
S22
S21
SLAS396A − JULY 2003 − REVISED APRIL 2004
functional block diagram
XIN
XOUT
DVCC
DVSS
AVCC
P1
AVSS RST/NMI
P2
8
Oscillator
FLL+
ACLK
32KB Flash
1KB RAM
SMCLK 16KB Flash
512B RAM
8KB Flash
256B RAM
6
USART0
I/O Port 1/2
14 I/Os,
with
Interrupt
Capability
UART or
SPI
Function
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
4
TMS
TCK
TDI/TCLK
TDO/TDI
Watchdog
Timer
Timer_A3
3 CC Reg
15/16-Bit
ESP430CE1
Embedded
Signal
Processing,
Analog
Front-End
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
128
Segments
1,2,3,4 MUX
fLCD
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MSP430FE42x Terminal Functions
TERMINAL
PN
NAME
I/O
DESCRIPTION
NO.
DVCC
1
I1+
I1−
2
I
Digital supply voltage, positive terminal. Supplies all digital parts.
Current 1 positive analog input. − Internal connection to SD16 Channel 0 A0+. (see Note 1)
3
I
Current 1 negative analog input. − Internal connection to SD16 Channel 0 A0−. (see Note 1)
I2+
I2−
4
I
Current 2 positive analog input. − Internal connection to SD16 Channel 1 A0+. (see Note 1)
5
I
Current 2 negative analog input. − Internal connection to SD16 Channel 1 A0−. (see Note 1)
V1+
V1−
6
I
Voltage 1 positive analog input. − Internal connection to SD16 Channel 2 A0+. (see Note 1)
7
I
Voltage 1 negative analog input. − Internal connection to SD16 Channel 2 A0−. (see Note 1)
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
9
O
Output terminal of crystal oscillator XT1
VREF
P2.2/STE0
10
I/O
Input for an external reference voltage / internal reference voltage output (can be used as mid-voltage)
11
I/O
General-purpose digital I/O / slave transmit enable—USART0/SPI mode
S0
12
O
LCD segment output 0
S1
13
O
LCD segment output 1
S2
14
O
LCD segment output 2
S3
15
O
LCD segment output 3
S4
16
O
LCD segment output 4
S5
17
O
LCD segment output 5
S6
18
O
LCD segment output 6
S7
19
O
LCD segment output 7
S8
20
O
LCD segment output 8
S9
21
O
LCD segment output 9
S10
22
O
LCD segment output 10
S11
23
O
LCD segment output 11
S12
24
O
LCD segment output 12
S13
25
O
LCD segment output 13
S14
26
O
LCD segment output 14
S15
27
O
LCD segment output 15
S16
28
O
LCD segment output 16
S17
29
O
LCD segment output 17
S18
30
O
LCD segment output 18
S19
31
O
LCD segment output 19
S20
32
O
LCD segment output 20
S21
33
O
LCD segment output 21
S22
34
O
LCD segment output 22
S23
35
O
LCD segment output 23
COM0
36
O
Common output, COM0−3 are used for LCD backplanes.
COM1
37
O
Common output, COM0−3 are used for LCD backplanes.
COM2
38
O
Common output, COM0−3 are used for LCD backplanes.
COM3
39
O
Common output, COM0−3 are used for LCD backplanes.
R03
40
I
Input port of fourth positive (lowest) analog LCD level (V5)
NOTE 1: Open connection recommended for all unused analog inputs.
4
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MSP430FE42x Terminal Functions (Continued)
TERMINAL
PN
NAME
I/O
DESCRIPTION
NO.
R13
41
I
Input port of third most positive analog LCD level (V4 or V3)
R23
42
I
Input port of second most positive analog LCD level (V2)
R33
43
O
Output port of most positive analog LCD level (V1)
P2.1/UCLK0/S24
44
I/O
General-purpose digital I/O / external clock input-USART0/UART or SPI mode, clock output—USART0/SPI
mode / LCD segment output 24 (See Note 1)
P2.0/TA2/S25
45
I/O
General-purpose digital I/O / Timer_A Capture: CCI2A input, Compare: Out2 output / LCD segment output
25 (See Note 1)
P1.7/SOMI0/S26
46
I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 26
(See Note 1)
P1.6/SIMO0/S27
47
I/O
General-purpose digital I/O / slave in/master out of USART0/SPI mode / LCD segment output 27
(See Note 1)
P1.5/TACLK/
ACLK/S28
48
I/O
General-purpose digital I/O / Timer_A and SD16 clock signal TACLK input / ACLK output (divided by 1,
2, 4, or 8) / LCD segment output 28 (See Note 1)
P1.4/S29
49
I/O
General-purpose digital I/O / LCD segment output 29 (See Note 1)
P1.3/SVSOUT/
S30
50
I/O
General-purpose digital I/O / SVS: output of SVS comparator / LCD segment output 30 (See Note 1)
P1.2/TA1/S31
51
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A, CCI1B input, Compare: Out1 output / LCD segment
output 31 (See Note 1)
P1.1/TA0/MCLK
52
I/O
General-purpose digital I/O / Timer_A, Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0
53
I/O
General-purpose digital I/O / Timer_A, Capture: CCI0A input, Compare: Out0 output / BSL transmit
TDO/TDI
54
I/O
Test data output port. TDO/TDI data output or programming data input terminal.
TDI/TCLK
55
I
Test data input or test clock input. The device protection fuse is connected to TDI.
TMS
56
I
Test mode select. TMS is used as an input port for device programming and test.
TCK
57
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
58
I
Reset input or nonmaskable interrupt input port
P2.5/URXD0
59
I/O
General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0
60
I/O
General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/SVSIN
61
I/O
General-purpose digital I/O / Analog input to brownout, supply voltage supervisor
AVSS
62
Analog supply voltage, negative terminal. Supplies SD16, SVS, brownout, oscillator, FLL+, and LCD
resistive divider circuitry.
DVSS
63
Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via
AVCC/AVSS.
AVCC
64
Analog supply voltage, positive terminal. Supplies SD16, SVS, brownout, oscillator, FLL+, and LCD
resistive divider circuitry; must not power up prior to DVCC.
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g. CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Indirect
Indirect
autoincrement
Register
Indexed
Symbolic (PC relative)
Absolute
Immediate
NOTE: S = source
6
S D
SYNTAX
EXAMPLE
MOV Rs,Rd
MOV R10,R11
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
OPERATION
R10
−−> R11
M(2+R5)−−> M(6+R6)
MOV EDE,TONI
M(EDE) −−> M(TONI)
MOV &MEM,&TCDAT
M(MEM) −−> M(TCDAT)
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) −−> M(Tab+R6)
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) −−> R11
R10 + 2−−> R10
MOV #X,TONI
MOV #45,TONI
D = destination
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#45
−−> M(TONI)
SLAS396A − JULY 2003 − REVISED APRIL 2004
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
Active mode AM;
−
All clocks are active
Low-power mode 0 (LPM0);
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ Loop control remains active
Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ Loop control is disabled
Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and FLL+ loop control and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the ROM with an address range
0FFFFh − 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External Reset
Watchdog
Flash memory
PC Out-of-Range (see Note 4)
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
ESP430
MBCTL_OUTxIFG,
MBCTL_INxIFG
(see Notes 1 and 2)
Maskable
0FFFAh
13
SD16
SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable
0FFF8h
12
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USART0 Receive
URXIFG0
Maskable
0FFF2h
9
USART0 Transmit
UTXIFG0
Maskable
8
7
Timer_A3
TACCR0 CCIFG (see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 and TACCR2
CCIFGs, and TACTL TAIFG
(see Notes 1 and 2)
Maskable
0FFEAh
5
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
Maskable
0FFE8h
4
0FFE6h
3
0FFE4h
2
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h
0, lowest
NOTES: 1.
2.
3.
4.
8
0FFF0h
0FFEEh
Multiple source flags
Interrupt flags are located in the module.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h-01FFh).
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special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7
Address
0h
6
UTXIE0
rw–0
URXIE0
rw–0
5
4
ACCVIE
NMIIE
rw–0
3
2
1
OFIE
rw–0
rw–0
0
WDTIE
rw–0
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
Flash access violation interrupt enable
URXIE0:
USART0: UART and SPI receive-interrupt enable
UTXIE0:
USART0: UART and SPI transmit-interrupt enable
7
Address
1h
6
5
4
3
2
1
4
3
2
1
0
BTIE
rw-0
BTIE:
Basic Timer1 interrupt enable
interrupt flag register 1 and 2
7
Address
02h
6
UTXIFG0
rw–1
5
URXIFG0
NMIIFG
rw–0
OFIFG
rw–0
rw–1
0
WDTIFG
rw–0
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC
power up or a reset condition at the RST/NMI pin in reset mode.
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
URXIFG0:
USART0: UART and SPI receive flag
UTXIFG0:
USART0: UART and SPI transmit flag
7
Address
3h
6
5
4
3
2
1
0
BTIFG
rw-0
BTIFG:
Basic Timer1 interrupt flag
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module enable registers 1 and 2
7
UTXE0
Address
04h
rw–0
6
URXE0
USPIE0
5
4
3
1
2
1
0
rw–0
URXE0:
USART0: UART mode receive enable
UTXE0:
USART0: UART mode transmit enable
USPIE0:
USART0: SPI mode transmit and receive enable
Address
2
7
6
5
4
3
0
05h
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset by PUC.
SFR Bit Not Present in Device
Legend: rw:
rw-0:
memory organization
MSP430FE423
MSP430FE425
MSP430FE427
Size
Flash
Flash
8KB
0FFFFh − 0FFE0h
0FFFFh − 0E000h
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
Information memory
Size
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory
Size
1kB
0FFFh − 0C00h
1kB
0FFFh − 0C00h
1kB
0FFFh − 0C00h
Size
256 Byte
02FFh − 0200h
512 Byte
03FFh − 0200h
1KB
05FFh − 0200h
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
Memory
Interrupt vector
Code memory
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
10
BSL Function
PM Package Pins
Data Transmit
53 - P1.0
Data Receive
52 - P1.1
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flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
8KB
16KB
0FFFFh 0FFFFh
32KB
0FFFFh
0FE00h 0FE00h 0FE00h
0FDFFh 0FDFFh 0FDFFh
Segment 0
With Interrupt Vectors
Segment 1
0FC00h 0FC00h 0FC00h
0FBFFh 0FBFFh 0FBFFh
Segment 2
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
Main Memory
0E400h 0C400h
0E3FFh 0C3FFh
083FFh
0E200h 0C200h
0E1FFh 0C1FFh
08200h
081FFh
0E000h
010FFh
0C000h
010FFh
08000h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
08400h
Segment n−1
Segment n
Segment A
Information Memory
Segment B
01000h
01000h
01000h
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, literature
number SLAU056.
oscillator and system clock
The clock system in the MSP430FE42x family of devices is supported by the FLL+ module that includes support
for a 32768 Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and
low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The FLL+ module
provides the following clock signals:
Auxiliary clock (ACLK), sourced from a 32768 Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external
pins):
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of P2.
Read/write access to port-control registers is supported by all instructions.
NOTE:
Six bits of port P2, P2.0 to P2.5, are available on external pins - but all control and data bits for port
P2 are implemented.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
12
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WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
Device Input Signal
Module Input Name
48 - P1.5
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
48 - P1.5
TACLK
INCLK
53 - P1.0
TA0
CCI0A
52 - P1.1
TA0
CCI0B
DVSS
DVCC
GND
51 - P1.2
51 - P1.2
45 - P2.0
TA1
VCC
CCI1A
TA1
CCI1B
DVSS
DVCC
GND
TA2
VCC
CCI2A
ACLK (internal)
CCI2B
DVSS
DVCC
GND
Module Block
Module Output Signal
Timer
NA
Output Pin Number
53 - P1.0
CCR0
TA0
51 - P1.2
CCR1
TA1
45 - P2.0
CCR2
TA2
VCC
USART0
The MSP430FE42x devices have one hardware universal synchronous/asynchronous receive transmit
(USART0) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels.
ESP430CE1
The ESP430CE1 module integrates a hardware multiplier, three independent 16-bit Sigma-Delta A/D
converters (SD16) and an embedded signal processor (ESP430). The ESP430CE1 module measures 2 or
3-wire, single-phase energy and automatically calculates parameters which are made available to the MSP430
CPU. The module can be calibrated and initialized to accurately calculate energy, power factor, etc for a wide
range of metering sensor configurations.
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13
SLAS396A − JULY 2003 − REVISED APRIL 2004
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog Timer control
WDTCTL
0120h
Timer_A3
Timer_A interrupt vector
TAIV
012Eh
Timer_A control
TACTL
0160h
Capture/compare control 0
TACCTL0
0162h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 2
TACCTL2
0166h
Reserved
0168h
Reserved
016Ah
Reserved
016Ch
Reserved
016Eh
Timer_A register
TAR
0170h
Capture/compare register 0
TACCR0
0172h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 2
TACCR2
0176h
Reserved
0178h
Reserved
017Ah
Reserved
017Ch
Reserved
Hardware Multiplier
(see Note 1)
Flash
SD16 (see Note 1)
(see also: Peripherals
with Byte Access)
017Eh
Sum extend
SUMEXT
013Eh
Result high word
RESHI
013Ch
Result low word
RESLO
013Ah
Second operand
OP2
0138h
Multiply signed + accumulate/operand1
MACS
0136h
Multiply + accumulate/operand1
MAC
0134h
Multiply signed/operand1
MPYS
0132h
Multiply unsigned/operand1
MPY
0130h
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
General Control
SD16CTL
0100h
Channel 0 Control
SD16CCTL0
0102h
Channel 1 Control
SD16CCTL1
0104h
Channel 2 Control
SD16CCTL2
0106h
Reserved
0108h
Reserved
010Ah
Reserved
010Ch
Reserved
010Eh
Interrupt vector word register
SD16IV
0110h
Channel 0 conversion memory
SD16MEM0
0112h
NOTE 1: Module is contained within ESP430CE1. Registers not accessible when ESP430 is active. ESP430 must be disabled or suspended
to allow CPU access to these modules.
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PERIPHERALS WITH WORD ACCESS
SD16
(continued, see Note 1)
Channel 1 conversion memory
SD16MEM1
0114h
Channel 2 conversion memory
SD16MEM2
0116h
Reserved
0118h
Reserved
011Ah
Reserved
011Ch
Reserved
ESP430 (ESP430CE1)
011Eh
ESP430 Control
ESPCTL
0150h
Mailbox Control
MBCTL
0152h
Mailbox In 0
MBIN0
0154h
Mailbox In 1
MBIN1
0156h
Mailbox Out 0
MBOUT0
0158h
Mailbox Out 1
MBOUT1
015Ah
ESP430 Return Value 0
RET0
01C0h
:
:
:
ESP430 Return Value 31
RET31
01FEh
Channel 0 Input Control
SD16INCTL0
0B0h
Channel 1 Input Control
SD16INCTL1
0B1h
Channel 2 Input Control
SD16INCTL2
0B2h
PERIPHERALS WITH BYTE ACCESS
SD16 (see Note 1)
(see also: Peripherals
with Word Access)
Reserved
0B3h
Reserved
0B4h
Reserved
0B5h
Reserved
0B6h
Reserved
0B7h
Channel 0 preload
SD16PRE0
0B8h
Channel 1 preload
SD16PRE1
0B9h
Channel 2 preload
SD16PRE2
0BAh
Reserved
0BBh
Reserved
0BCh
Reserved
0BDh
Reserved
0BEh
Reserved
LCD
0BFh
LCD memory 20
LCDM20
0A4h
:
:
:
LCD memory 16
LCDM16
0A0h
LCD memory 15
LCDM15
09Fh
:
:
:
LCD memory 1
LCDM1
091h
LCD control and mode
LCDCTL
090h
NOTE 1: Module is contained within ESP430CE1. Registers not accessible when ESP430 is active. ESP430 must be disabled or suspended
to allow CPU access to these modules.
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15
SLAS396A − JULY 2003 − REVISED APRIL 2004
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
USART0
Transmit buffer
U0TXBUF
077h
Receive buffer
U0RXBUF
076h
Baud rate
U0BR1
075h
Baud rate
U0BR0
074h
Modulation control
U0MCTL
073h
Receive control
U0RCTL
072h
Transmit control
U0TCTL
071h
USART control
U0CTL
070h
Brownout, SVS
SVS control register
SVSCTL
056h
FLL+ Clock
FLL+ Control1
FLL_CTL1
054h
FLL+ Control0
FLL_CTL0
053h
System clock frequency control
SCFQCTL
052h
System clock frequency integrator
SCFI1
051h
System clock frequency integrator
SCFI0
050h
BT counter2
BTCNT2
047h
BT counter1
BTCNT1
046h
BT control
BTCTL
040h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable 2
ME2
005h
SFR module enable 1
ME1
004h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable2
IE2
001h
SFR interrupt enable1
IE1
000h
Basic Timer1
Port P2
Port P1
Special Functions
16
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absolute maximum ratings†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 4.1 V
Voltage applied to any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNITS
Supply voltage during program execution; SVS, ESP430 and SD16
disabled. VCC (AVCC = DVCC = VCC)
MSP430FE42x
1.8
3.6
V
Supply voltage during program execution; SVS enabled, ESP430 and
SD16 disabled. VCC (AVCC = DVCC = VCC) (see Note 1)
MSP430FE42x
2.2
3.6
V
Supply voltage during program execution; ESP430 or SD16 enabled or
during programming of flash memory. VCC (AVCC = DVCC = VCC)
MSP430FE42x
2.7
3.6
V
0
0
V
MSP430FE42x
−40
85
°C
450
8000
kHz
1000
8000
kHz
DC
8.4
DC
8.4
Supply voltage, VSS (AVSS = DVSS = VSS)
Operating free-air temperature range, TA
LFXT1 crystal frequency, f(LFXT1)
(see Note 2)
LF selected, XTS_FLL=0
Watch crystal
XT1 selected, XTS_FLL=1
Ceramic resonator
XT1 selected, XTS_FLL=1
Crystal
Processor frequency (signal MCLK), f(System) (see Note 3)
VCC = 2.7 V
VCC = 3.6 V
32768
Hz
MHz
NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.
POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry.
2. The LFXT1 oscillator in LF-mode requires a watch crystal.
3. For frequencies above 8 MHz, MCLK is sourced by the built-in oscillator (DCO and FLL+).
POST OFFICE BOX 655303
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SLAS396A − JULY 2003 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current, (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
I(AM)
Active mode,
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
(program executes in flash)
TA = −40°C to 85°C
VCC = 3 V
400
500
µA
I(LPM0)
Low-power mode, (LPM0/LPM1)
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
FN_8=FN_4=FN_3=FN_2=0
TA = −40°C to 85°C
VCC = 3 V
130
150
µA
I(LPM2)
Low-power mode, (LPM2)
TA = −40°C to 85°C
TA = −40°C
VCC = 3 V
10
22
µA
1.5
2.0
1.6
2.1
1.7
2.2
TA = 85°C
TA = −40°C
2.0
2.6
0.1
0.5
TA = 25°C
TA = 85°C
0.1
0.5
0.8
2.5
I(LPM3)
I(LPM4)
TA = 25°C
TA = 60°C
Low-power mode, (LPM3)
Low-power mode, (LPM4)
VCC = 3 V
VCC = 3 V
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
The current consumption in LPM2, LPM3, and LPM4 are measured with active Basic Timer1 and LCD (ACLK selected).
The current consumption of the ESP430CE1 and the SVS module are specified in their respective sections.
LPMx currents measured with WDT disabled.
The currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal.
current consumption of active mode versus system frequency, F version
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
current consumption of active mode versus supply voltage, F version
fSystem − Maximum Processor Frequency − MHz
I(AM) = I(AM) [3 V] + 170 µA/V × (VCC – 3 V)
f (MHz)
Supply Voltage Range with
ESP430 or SD16 Enabled and During
Programming of the Flash Memory
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
8.4 MHz
Supply Voltage Range
During Program
Execution
6 MHz
4.15 MHz
1.8 V
2.7 V
3V
3.6 V
VCC − Supply Voltage − V
Figure 1. Frequency vs Supply Voltage
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
µA
A
µA
SLAS396A − JULY 2003 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − Ports P1 and P2; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIT+
VIT−
Positive-going input threshold voltage
VCC = 3 V
VCC = 3 V
1.5
1.98
V
Negative-going input threshold voltage
0.9
1.3
V
Vhys
Input voltage hysteresis (VIT+ − VIT−)
VCC = 3 V
0.45
1
V
inputs Px.x, TAx
PARAMETER
TEST CONDITIONS
VCC
3V
MIN
TYP
MAX
UNIT
1.5
cycle
3V
50
ns
50
ns
t(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, External trigger signal
for the interrupt flag, (see Note 1)
t(cap)
Timer_A, capture timing
TAx
3V
f(TAext)
Timer_A clock frequency
externally applied to pin
TACLK, INCLK t(H) = t(L)
3V
10
MHz
f(TAint) Timer_A clock frequency
SMCLK or ACLK signal selected
3V
10
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
leakage current (see Note 1)
PARAMETER
Ilkg(P1.x)
Ilkg(P2.x)
Leakage
current
TEST CONDITIONS
Port P1
Port 1: V(P1.x) (see Note 2)
Port P2
Port 2: V(P2.x) (see Note 2)
MIN
NOM
MAX
±50
VCC = 3 V
±50
UNIT
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as an input.
outputs − Ports P1 and P2
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH(max) = −1.5 mA,
IOH(max) = −6 mA,
VOL
Low-level output voltage
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
MIN
VCC = 3 V,
VCC = 3 V,
See Note 1
VCC = 3 V,
VCC = 3 V,
See Note 1
See Note 2
MAX
UNIT
VCC−0.25
VCC−0.6
VCC
VCC
V
VSS
VSS
VSS+0.25
VSS+0.6
V
See Note 2
TYP
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the
maximum specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the
maximum specified voltage drop.
output frequency
PARAMETER
TEST CONDITIONS
MIN
VCC = 3 V
DC
fPx.y
(1 ≤ x ≤ 2, 0 ≤ y ≤ 7)
CL = 20 pF,
IL = ± 1.5mA
fACLK,
fMCLK,
fSMCLK
P1.1/TA0/MCLK
P1.5/TACLK/ACLK/S28
CL = 20 pF
VCC = 3 V
P1.5/TACLK/ACLK/
S28, CL = 20 pF
VCC = 3 V
fACLK = fLFXT1 = fXT1
fACLK = fLFXT1 = fLF
tXdc
Duty cycle of output frequency
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 3 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
12
MHz
12
MHz
40%
60%
30%
70%
fACLK = fLFXT1
fMCLK = fDCOCLK
TYP
50%
50%−
15 ns
50%
50%+
15 ns
19
SLAS396A − JULY 2003 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1 and P2 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
30
I OL − Typical Low-level Output Current − mA
I OL − Typical Low-level Output Current − mA
50
VCC = 2.2 V
P2.1
TA = 25°C
25
TA = 85°C
20
15
10
5
0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P2.1
40
TA = 85°C
30
20
10
0
0.0
2.5
TA = 25°C
0.5
VOL − Low-Level Output Voltage − V
1.0
Figure 2
I OL − Typical High-level Output Current − mA
I OL − Typical High-level Output Current − mA
−5
−10
−15
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
−10
−20
−30
TA = 85°C
−40
TA = 25°C
−50
0.0
0.5
1.0
1.5
Figure 5
One output loaded at a time
POST OFFICE BOX 655303
2.0
2.5
3.0
VOH − High-Level Output Voltage − V
Figure 4
20
3.5
VCC = 3 V
P2.1
VOH − High-Level Output Voltage − V
NOTE:
3.0
0
VCC = 2.2 V
P2.1
−30
0.0
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
−25
2.0
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−20
1.5
VOL − Low-Level Output Voltage − V
• DALLAS, TEXAS 75265
3.5
SLAS396A − JULY 2003 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
f = 1 MHz
td(LPM3)
f = 2 MHz
Delay time
UNIT
6
6
VCC = 3 V
f = 3 MHz
µs
6
RAM (see Note 1)
PARAMETER
TEST CONDITIONS
VRAMh
MIN
CPU halted (see Note 1)
TYP
MAX
1.6
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program
execution should take place during this supply voltage condition.
LCD
PARAMETER
V(33)
V(23)
TEST CONDITIONS
MIN
Voltage at R33
V(13)
V(33) − V(03)
VCC = 3 V
Voltage at R13
Voltage at R33/R03
I(R03)
2.5
R03 = VSS
I(R13)
Input leakage
V(Sxx1)
V(Sxx2)
Segment line
voltage
A,
I(Sxx) = −3 µA,
VCC = 3 V
V(Sxx3)
UNIT
V
VCC +0.2
±20
No load at all
segment and
common lines,
VCC = 3 V
R13 = VCC/3
R23 = 2 × VCC/3
I(R23)
V(Sxx0)
MAX
VCC +0.2
(V33−V03) × 2/3 + V03
(V(33)−V(03)) × 1/3 + V(03)
Voltage at R23
Analog voltage
TYP
2.5
±20
nA
±20
V(03)
V(13)
V(03) − 0.1
V(13) − 0.1
V(23)
V(33)
V(23) − 0.1
V(33) + 0.1
V
USART0 (see Note 1)
PARAMETER
t(τ)
TEST CONDITIONS
USART0: deglitch time
MIN
VCC = 3 V
NOM
MAX
280
500
150
UNIT
ns
NOTE 1: The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t(τ) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD0 line.
POR brownout, reset (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
td(BOR)
VCC(start)
dVCC/dt ≤ 3 V/s (see Figure 6)
V(B_IT−)
Vhys(B_IT−)
dVCC/dt ≤ 3 V/s (see Figure 6, Figure 7, Figure 8)
dVCC/dt ≤ 3 V/s (see Figure 6)
t(reset)
Brownout
MIN
TYP
MAX
UNIT
2000
µs
0.7 × V(B_IT−)
Pulse length needed at RST/NMI pin to accepted reset internally,
VCC = 3 V
70
2
130
V
1.71
V
180
mV
µs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−)
+ Vhys(B_IT−) is ≤ 1.8 V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−).
The default FLL+ settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.
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electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
td(BOR)
Figure 6. POR/Brownout Reset (BOR) vs Supply Voltage
VCC
2
VCC (min) − V
tpw
3V
V cc = 3 V
Typical Conditions
1.5
1
VCC(min)
0.5
0
0.001
1
1000
1 ns
tpw − Pulse Width − µs
1 ns
tpw − Pulse Width − µs
Figure 7. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
VCC (min) − V
2
1.5
tpw
3V
V cc = 3 V
Typical Conditions
1
VCC(min)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw − Pulse Width − µs
tpw − Pulse Width − µs
Figure 8. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
22
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electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SVS (supply voltage supervisor/monitor) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
t(SVSR)4
dVCC/dt > 30 V/ms (see Figure 9)
dVCC/dt ≤ 30 V/ms
5
td(SVSon)
tsettle
SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V
VLD ≠ 0‡
20
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 9)
NOM
MAX
150
2000
1.55
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 9)
VLD = 2 .. 14
Vhys(SVS_IT−)
VCC/dt ≤ 3 V/s (see Figure 9), external voltage applied
on P2.3
VCC/dt ≤ 3 V/s (see Figure 9)
V(SVS_IT−)
VCC/dt ≤ 3 V/s (see Figure 9), external voltage applied
on P2.3
VLD = 15
70
120
V(SVS_IT−)
x 0.004
UNIT
µs
150
µs
12
µs
1.7
V
155
mV
V(SVS_IT−)
x 0.008
4.4
10.4
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.25
VLD = 3
2.05
2.2
2.37
VLD = 4
2.14
2.3
2.48
VLD = 5
2.24
2.4
2.6
VLD = 6
2.33
2.5
2.71
VLD = 7
2.46
2.65
2.86
VLD = 8
2.58
2.8
3
VLD = 9
2.69
2.9
3.13
VLD = 10
2.83
3.05
3.29
VLD = 11
2.94
3.2
VLD = 12
3.11
3.35
VLD = 13
3.24
VLD = 14
3.43
3.5
3.7†
3.42
3.61†
3.76†
VLD = 15
1.1
1.2
mV
V
3.99†
1.3
ICC(SVS)
VLD ≠ 0, VCC = 2.2 V/3 V
10
15
µA
(see Note 1)
† The recommended operating voltage range is limited to 3.6 V.
‡ tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data.
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electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
VCC
V
(SVS_IT−)
V(SVSstart)
Software Sets VLD>0:
SVS is Active
Vhys(SVS_IT−)
Vhys(B_IT−)
V(B_IT−)
VCC(start)
Brownout
Brownout
Region
Brownout
Region
1
0
td(BOR)
SVS out
td(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT−)
1
0
td(SVSon)
Set POR
1
td(SVSR)
Undefined
0
Figure 9. SVS Reset (SVSR) vs Supply Voltage
VCC
3V
tpw
2
Rectangular Drop
VCC(min) − V
1.5
VCC(min)
Triangular Drop
1
1 ns
0.5
1 ns
VCC
3V
tpw
0
1
10
100
1000
tpw − Pulse Width − µs
VCC(min)
tf = tr
tf
tr
t − Pulse Width − µs
Figure 10. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
24
POST OFFICE BOX 655303
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SLAS396A − JULY 2003 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
f(DCOCLK)
f(DCO2)
N(DCO)=01E0h, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0
3V
FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1
3V
0.3
0.7
1.3
MHz
f(DCO27)
f(DCO2)
FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1, (see Note 1)
3V
2.7
6.1
11.3
MHz
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
3V
0.8
1.5
2.5
MHz
f(DCO27)
f(DCO2)
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1, (see Note 1)
3V
6.5
12.1
20
MHz
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
3V
1.3
2.2
3.5
MHz
f(DCO27)
f(DCO2)
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1, (see Note 1)
3V
10.3
17.9
28.5
MHz
FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1
3V
2.1
3.4
5.2
MHz
f(DCO27)
f(DCO2)
FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1, (see Note 1)
3V
16
26.6
41
MHz
FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1
3V
4.2
6.3
9.2
MHz
f(DCO27)
FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1, (see Note 1)
46
70
MHz
Sn
Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n), (see Figure 12 for taps 21 to 27)
Dt
Temperature drift, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0, (see Note 2)
DV
Drift with VCC variation, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0 (see Note 2)
1
UNIT
MHz
3V
30
1 < TAP ≤ 20
1.06
1.11
TAP = 27
1.07
1.17
3V
–0.2
–0.3
–0.4
%/C
0
5
15
%/V
NOTES: 1. Do not exceed the maximum system frequency.
2. This parameter is not production tested.
f
f
f
(DCO)
f
(DCO3V)
(DCO)
(DCO205C)
1.0
1.0
0
1.8
2.4
3.0
3.6
VCC − V
−40
−20
0
20
40
60
85
TA − °C
Figure 11. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
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SLAS396A − JULY 2003 − REVISED APRIL 2004
Sn - Stepsize Ratio between DCO Taps
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 12. DCO Tap Step Size
f(DCO)
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
29 to 25 in SCFI1 {N{DCO}}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 13. Five Overlapping DCO Ranges Controlled by FN_x Bits
26
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SLAS396A − JULY 2003 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
CXIN
CXOUT
VIL
VIH
Integrated input capacitance
(see Note 4)
Integrated output capacitance
(see Note 4)
Input levels at XIN
TEST CONDITIONS
OSCCAPx = 0h
VCC
3V
OSCCAPx = 1h
3V
10
OSCCAPx = 2h
3V
14
OSCCAPx = 3h
3V
18
OSCCAPx = 0h
3V
0
OSCCAPx = 1h
3V
10
OSCCAPx = 2h
3V
14
OSCCAPx = 3h
3V
see Note 3
2.2 V/3 V
MIN
TYP
MAX
UNIT
0
pF
pF
18
VSS
0.8×VCC
0.2×VCC
VCC
V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2pF. The effective load capacitor for the crystal is
(CXIN x CXOUT) / (CXIN + CXOUT). It is independent of XTS_FLL .
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines must be
observed:
• Keep as short a trace as possible between the ’FE42x and the crystal.
• Design a good ground plane around oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to XIN an XOUT pins.
• Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
• Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation.
This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
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27
SLAS396A − JULY 2003 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ESP430CE1, SD16 and ESP430 power supply and recommended operating conditions
PARAMETER
Analog supply
voltage
AVCC
IESP430CE1
ISD16
Total Digital &
Analog supply
current when
ESP430 and SD16
active
(IAVCC + IDVCC)
Analog supply
current: 1 active
SD16 channel
including internal
reference
(ESP430 disabled)
fMAINS
Mains frequency
range
fSD16
Analog front-end
input clock
frequency
TEST CONDITIONS
VCC
AVCC = DVCC
AVSS = DVSS = 0V
SD16LP = 0,
fMCLK = 4MHz,
fSD16 = fMCLK/4,
SD16REFON = 1,
SD16VMIDON = 0
SD16LP = 1,
fMCLK = 2MHz,
fSD16 = fMCLK/4,
SD16REFON = 1,
SD16VMIDON = 0
MIN
TYP
2.7
MAX
3.6
GAIN(V): 1, GAIN(I1): 1, I2: off
3V
2.0
2.6
GAIN(V): 1, GAIN(I1): 32, I2: off
3V
2.4
3.3
GAIN(V): 1, GAIN(I1): 1, GAIN(I2): 1
3V
2.7
3.6
GAIN(V): 1, GAIN(I1): 32, GAIN(I2): 32
3V
3.4
4.9
GAIN(V): 1, GAIN(I1): 1, I2: off
3V
1.5
2.1
GAIN(V): 1, GAIN(I1): 32, I2: off
3V
1.6
2.1
GAIN(V): 1, GAIN(I1): 1, GAIN(I2): 1
3V
2.1
2.8
GAIN(V): 1, GAIN(I1): 32, GAIN(I2): 32
3V
2.2
3.0
SD16LP = 0,
fSD16 = 1 MHz,
SD16OSR = 256
GAIN: 1, 2
3V
650
950
GAIN: 4, 8, 16
3V
730
1100
GAIN: 32
3V
1050
1550
GAIN: 1
3V
620
930
GAIN: 32
3V
700
1060
SD16LP = 1,
fSD16 = 0.5 MHz,
SD16OSR = 256
33
80
SD16LP = 0 (Low power mode disabled)
3V
1
SD16LP = 1 (Low power mode enabled)
3V
0.5
UNIT
V
mA
µA
Hz
MHz
ESP430CE1, SD16 input range (see Note 1)
PARAMETER
VID
Differential input
voltage range for
specified
performance
(see Note 2)
TEST CONDITIONS
VCC
MIN
TYP
SD16GAINx = 1, SD16REFON = 1
±500
SD16GAINx = 2, SD16REFON = 1
±250
SD16GAINx = 4, SD16REFON = 1
±125
SD16GAINx = 8, SD16REFON = 1
±62
SD16GAINx = 16, SD16REFON = 1
±31
SD16GAINx = 32, SD16REFON = 1
±15
MAX
UNIT
mV
Input impedance
(one input pin
to AVSS)
fSD16 = 1MHz, SD16GAINx = 1
3V
200
ZI
fSD16 = 1MHz, SD16GAINx = 32
3V
75
Differential
Input impedance
(IN+ to IN−)
fSD16 = 1MHz, SD16GAINx = 1
3V
300
400
ZID
fSD16 = 1MHz, SD16GAINx = 32
3V
100
150
VI
Absolute input
voltage range
AVSS1.0V
AVCC
V
VIC
Common-mode
input voltage range
AVSS1.0V
AVCC
V
kΩ
kΩ
NOTES: 1. All parameters pertain to each SD16 channel.
2. The analog input range depends on the reference voltage applied to VREF. If VREF is sourced externally, the full-scale range
is defined by VFSR+ = +(VREF/2)/GAIN and VFSR− = −(VREF/2)/GAIN. The analog input range should not exceed 80% of
VFSR+ or VFSR−.
28
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SLAS396A − JULY 2003 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ESP430CE1, SD16 performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1)
PARAMETER
SINAD
G
Signal-to-Noise +
Distortion Ratio
Nominal Gain
EOS
Offset Error
dEOS/dT
Offset Error Temperature Coefficient
CMRR
Common-Mode
Rejection Ratio
PSRR
Power Supply
Rejection Ratio
XT
Crosstalk
TEST CONDITIONS
SD16GAINx = 1,Signal Amplitude = 500mV
VCC
3V
83.5
85
SD16GAINx = 2,Signal Amplitude = 250mV
3V
81.5
84
3V
76
79.5
3V
73
76.5
SD16GAINx = 16,Signal Amplitude = 31mV
3V
69
73
SD16GAINx = 32,Signal Amplitude = 15mV
3V
62
69
SD16GAINx = 1
3V
0.97
1.00
1.02
SD16GAINx = 2
3V
1.90
1.96
2.02
SD16GAINx = 4
3V
3.76
3.86
3.96
SD16GAINx = 8
3V
7.36
7.62
7.84
SD16GAINx = 16
3V
14.56
15.04
15.52
SD16GAINx = 32
3V
27.20
28.35
29.76
SD16GAINx = 1
3V
±0.2
SD16GAINx = 32
3V
±1.5
%FSR
SD16GAINx = 1
3V
±4
±20
SD16GAINx = 32
3V
±20
±100
ppm
FSR/C
SD16GAINx = 1, Common-mode input signal:
VID = 500 mV, fIN = 50 Hz, 100 Hz
3V
>90
SD16GAINx = 32, Common-mode input signal:
VID = 16 mV, fIN = 50 Hz, 100 Hz
3V
>75
SD16GAINx = 1
3V
>80
dB
3V
<−100
dB
SD16GAINx = 4,Signal Amplitude = 125mV
SD16GAINx = 8,Signal Amplitude = 62mV
fIN = 50Hz,
100Hz
MIN
TYP
MAX
UNIT
dB
dB
ESP430CE1, SD16 temperature sensor
PARAMETER
TCSensor
Sensor temperature
coefficient
Sensor offset
VOffset,sensor
voltage
VSensor
Sensor output
voltage
(see Note 3)
TEST CONDITIONS
VCC
MIN
See Note 1
1.18
See Note 1
−100
TYP
1.32
MAX
UNIT
1.46
mV/K
100
mV
Temperature sensor voltage at TA = 85°C
3V
435
475
515
Temperature sensor voltage at TA = 25°C
3V
355
395
435
Temperature sensor voltage at TA = 0°C (see Note 1)
3V
320
360
400
mV
NOTES: 1. Not production tested, limits characterized.
2. The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV]
3. Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
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29
SLAS396A − JULY 2003 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ESP430CE1, SD16 built-in voltage reference
PARAMETER
TEST CONDITIONS
VCC
VREF
Internal reference
voltage
SD16REFON = 1, SD16VMIDON = 0
3V
IREF
Reference supply
current
SD16REFON = 1, SD16VMIDON = 0
TC
Temperature
coefficient
SD16REFON = 1, SD16VMIDON = 0
CREF
VREF load
capacitance
SD16REFON = 1, SD16VMIDON = 0 (see Note 1)
ILOAD
VREF(I) maximum
load current
SD16REFON = 0
MIN
1.14
TYP
MAX
UNIT
1.20
1.26
V
3V
175
260
µA
3V
20
50
ppm/K
100
nF
±200
3V
nA
NOTES: 1. There is no capacitance required on VREF. However, a capacitance of at least 100nF is recommended to reduce any reference
voltage noise.
ESP430CE1, SD16 reference output buffer
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VREF,BUF
Reference buffer
output voltage
SD16REFON = 1, SD16VMIDON = 1
3V
1.2
IREF,BUF
Reference Supply +
Reference output
buffer quiescent
current
SD16REFON = 1, SD16VMIDON = 1
3V
385
CREF(O)
ILOAD,Max
Required load
capacitance on
VREF
Maximum load
current on VREF
Maximum voltage
variation vs. load
current
SD16REFON = 1, SD16VMIDON = 1
MAX
V
600
470
SD16REFON = 1, SD16VMIDON = 1
3V
|ILOAD| = 0 to 1mA
3V
UNIT
µA
nF
−15
±1
mA
+15
mV
ESP430CE1, SD16 external reference input
PARAMETER
VREF(I)
IREF(I)
30
Input voltage range
SD16REFON = 0
TEST CONDITIONS
VCC
3V
Input current
SD16REFON = 0
3V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
1.0
TYP
1.25
MAX
UNIT
1.5
V
50
nA
SLAS396A − JULY 2003 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ESP430CE1, active energy measurement test conditions and accuracy, TA = 25°C (See Note 1)
fACLK = 32,768 Hz (watch crystal)
fMCLK = 4.194MHz (FLL+)
fSD16 = fMCLK/4 = 1.049MHz
Single point calibration at I = 10 A, PF = 0.5 lagging
Measurements according to IEC1036
Input conditions (unless otherwise noted):
IB = 6 A, IMAX = n * IB = 60 A, n = 10, VN = 230 V, fMAINS = 50 Hz
PARAMETER
TEST CONDITIONS
VCC
3V
I = 0.05*IB, V = VN, PF = 1.0
I = 0.1*IB to IMAX, V = VN, PF = 1.0
I = 0.1*IB, V = VN, PF = 0.5 lagging
Maximum error
V1 SD16GAINx = 1
I1 SD16GAINx = 1
I = 0.2*IB to IMAX, V = VN, PF = 0.5 lagging
I = 0.1*IB, V = VN, PF = 0.8 leading
I = 0.2*IB to IMAX, V = VN, PF = 0.8 leading
See Figure 14:
R1 = 0Ω, RB = 12.4Ω
I = 0.2*IB to IMAX, V = VN, PF = 0.25 lagging
MIN
TYP
MAX
UNIT
±0.17
3V
±0.18
3V
±0.19
3V
±0.27
3V
±0.15
3V
±0.24
3V
±0.38
%
Input conditions (unless otherwise noted):
IB = 10 A, IMAX = n * IB = 60 A, n = 6, VN = 230 V, fMAINS = 50 Hz
PARAMETER
TEST CONDITIONS
VCC
3V
I = 0.05*IB, V = VN, PF = 1.0
I = 0.1*IB to IMAX, V = VN, PF = 1.0
I = 0.1*IB, V = VN, PF = 0.5 lagging
Maximum error
V1 SD16GAINx = 1
I1 SD16GAINx = 32
I = 0.2*IB to IMAX, V = VN, PF = 0.5 lagging
I = 0.1*IB, V = VN, PF = 0.8 leading
I = 0.2*IB to IMAX, V = VN, PF = 0.8 leading
See Figure 15:
Rshunt = 0.2mΩ
I = 0.2*IB to IMAX, V = VN, PF = 0.25 lagging
MIN
TYP
MAX
UNIT
±0.11
3V
±0.18
3V
±0.45
3V
±0.33
3V
±0.10
3V
±0.18
3V
±0.51
%
NOTES: 1. Measurements performed using complete hardware solution. Error shown contain temperature dependencies of all components
including the MSP430FE42x, crystal, and discrete components.
2. I1 SD16GAIN x = 1,4: CT part number = T60404−E4624−X101 ( Vacuumschmelze)
I1 SD16GAINx = 8: shunt part number = A−H2−R005−F1−K2−0.1 (Isabellenhütte Heusler GmbH KG)
I1 SD16GAINx = 32: shunt part number = BVO−M−R0002−5.0 (Isabellenhütte Heusler GmbH KG)
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SLAS396A − JULY 2003 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
I
1uH
CT
R1
1uH
1k
990k
I1+
33nF
RB
1k
1.5k
I1−
33nF
1uH
1k
V1+
33nF
1k
V1−
33nF
Figure 14. Energy measurement test circuitry (SD16GAINx = 1, 4)
I
1uH
1uH
1k
I1+
Rshunt
990k
33nF
1k
V1+
1k
I1−
33nF
1.5k
1uH
33nF
1k
V1−
33nF
Figure 15. Energy measurement test circuitry (SD16GAINx = 8, 32)
32
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ESP430CE1, I1 SD16GAINx = 1 typical characteristics (see Note 1)
MEASUREMENT ERROR AS % OF READING
(TA = 25°C)
1.00
fMAINS = 50 Hz
VLINE = 230 V
0.75
0.50
Error − %
PF = 0.5 lag
PF = 0
0.25
0.00
−0.25
PF = 0.8 lead
−0.50
−0.75
−1.00
0.01
0.10
1.00
10.00
100.00
Line Current − A
Figure 16
MEASUREMENT ERROR AS % OF READING
(TA = −40°C)
1.00
0.75
0.50
MEASUREMENT ERROR AS % OF READING
(TA = 85°C)
1.00
fMAINS = 50 Hz
VLINE = 230 V
PF = 0.5 lag
0.75
PF = 0
fMAINS = 50 Hz
VLINE = 230 V
0.50
PF = 0
PF = 0.8 lead
0.25
Error − %
Error − %
0.25
PF = 0.8 lead
0.00
0.00
−0.25
−0.25
−0.50
−0.50
−0.75
−0.75
PF = 0.5 lag
−1.00
0.01
0.10
1.00
10.00
100.00
−1.00
0.01
0.10
1.00
Line Current − A
Line Current − A
Figure 17
Figure 18
10.00
100.00
NOTES: 1. Results corrected for typical phase error of CT used. (−40°C to 25°C: −0.7°; 25°C to 85°C: +0.5°)
See Figure 14 for test circuitry: CT part number = T60404−E4624−X101 ( Vacuumschmelze), R1 = 0Ω, RB = 12.4Ω
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ESP430CE1, I1 SD16GAINx = 4 typical characteristics (see Note 1)
MEASUREMENT ERROR AS % OF READING
(TA = 25°C)
1.00
0.75
fMAINS = 50 Hz
VLINE = 230 V
0.50
PF = 0
Error − %
0.25
0.00
PF = 0.5 lag
−0.25
PF = 0.8 lead
−0.50
−0.75
−1.00
0.01
0.10
1.00
10.00
100.00
Line Current − A
Figure 19
MEASUREMENT ERROR AS % OF READING
(TA = −40°C)
1.00
0.75
MEASUREMENT ERROR AS % OF READING
(TA = 85°C)
1.00
fMAINS = 50 Hz
VLINE = 230 V
0.75
fMAINS = 50 Hz
VLINE = 230 V
PF = 0.8 lead
0.50
0.50
PF = 0
PF = 0.8 lead
0.25
Error − %
Error − %
0.25
0.00
−0.25
PF = 0.5 lag
0.00
−0.25
−0.50
−0.50
−0.75
−0.75
−1.00
0.01
0.10
PF = 0
1.00
10.00
100.00
−1.00
0.01
PF = 0.5 lag
0.10
1.00
Line Current − A
Line Current − A
Figure 20
Figure 21
10.00
NOTES: 1. Results corrected for typical phase error of CT used. (−40°C to 25°C: −0.7°; 25°C to 85°C: +0.5°)
See Figure 14 for test circuitry: CT part number = T60404−E4624−X101 ( Vacuumschmelze), R1 = 9.36Ω, RB = 3.16Ω
34
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ESP430CE1, I1 SD16GAINx = 8 typical characteristics (see Note 1)
MEASUREMENT ERROR AS % OF READING
(TA = 25°C)
1.00
0.75
fMAINS = 50 Hz
VLINE = 230 V
PF = 0.5 lag
0.50
Error − %
0.25
0.00
PF = 0
−0.25
PF = 0.8 lead
−0.50
−0.75
−1.00
0.01
0.10
1.00
10.00
100.00
Line Current − A
Figure 22
MEASUREMENT ERROR AS % OF READING
(TA = −40°C)
1.00
MEASUREMENT ERROR AS % OF READING
(TA = 85°C)
1.00
fMAINS = 50 Hz
VLINE = 230 V
0.75
0.75
fMAINS = 50 Hz
VLINE = 230 V
PF = 0.5 lag
PF = 0.5 lag
0.50
0.50
0.25
Error − %
Error − %
0.25
0.00
PF = 0
−0.25
PF = 0.8 lead
0.00
−0.25
PF = 0
PF = 0.8 lead
−0.50
−0.50
−0.75
−0.75
−1.00
0.01
0.10
1.00
10.00
100.00
−1.00
0.01
Line Current − A
0.10
1.00
10.00
100.00
Line Current − A
Figure 23
Figure 24
NOTES: 1. See Figure 15 for test circuitry: shunt part number = A−H2−R005−F1−K2−0.1 (Isabellenhütte Heusler GmbH KG)
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ESP430CE1, I1 SD16GAINx = 32 typical characteristics (see Note 1)
MEASUREMENT ERROR AS % OF READING
(TA = 25°C)
1.00
0.75
fMAINS = 50 Hz
VLINE = 230 V
PF = 0.5 lag
0.50
Error − %
0.25
0.00
PF = 0
−0.25
PF = 0.8 lead
−0.50
−0.75
−1.00
0.01
0.10
1.00
10.00
100.00
Line Current − A
Figure 25
MEASUREMENT ERROR AS % OF READING
(TA = −40°C)
1.00
0.75
MEASUREMENT ERROR AS % OF READING
(TA = 85°C)
1.00
fMAINS = 50 Hz
VLINE = 230 V
0.75
0.50
fMAINS = 50 Hz
VLINE = 230 V
0.50
PF = 0.5 lag
PF = 0.5 lag
0.25
Error − %
Error − %
0.25
0.00
−0.25
PF = 0
0.00
PF = 0.8 lead
PF = 0
−0.25
PF = 0.8 lead
−0.50
−0.50
−0.75
−0.75
−1.00
0.01
0.10
1.00
10.00
100.00
−1.00
0.01
Line Current − A
0.10
1.00
10.00
Line Current − A
Figure 26
Figure 27
NOTES: 1. See Figure 15 for test circuitry: shunt part number = BVO−M−R0002−5.0 (Isabellenhütte Heusler GmbH KG)
36
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electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Flash Memory
TEST
CONDITIONS
PARAMETER
VCC(PGM/
ERASE)
VCC
MIN
NOM
MAX
UNIT
Program and Erase supply voltage
2.7
3.6
V
fFTG
IPGM
Flash Timing Generator frequency
257
476
kHz
Supply current from DVCC during program
2.7 V/ 3.6 V
3
5
mA
IERASE
tCPT
Supply current from DVCC during erase
2.7 V/ 3.6 V
3
7
mA
Cumulative program time
see Note 1
2.7 V/ 3.6 V
4
ms
tCMErase
Cumulative mass erase time
see Note 2
2.7 V/ 3.6 V
Program/Erase endurance
TJ = 25°C
200
104
ms
105
tRetention
Data retention duration
tWord
tBlock, 0
Word or byte program time
Block program time for 1st byte or word
tBlock, 1-63
tBlock, End
Block program time for each additional byte or word
tMass Erase
tSeg Erase
Mass erase time
5297
Segment erase time
4819
Block program end-sequence wait time
cycles
100
years
35
30
21
see Note 3
tFTG
6
NOTES: 1. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if the block write
feature is used.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG Interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
RInternal
Internal pull-up resistance on TMS, TCK, TDI/TCLK
see Note 2
VCC
MIN
2.2 V
0
NOM
MAX
UNIT
5
MHz
3V
0
10
MHz
2.2 V/ 3 V
25
60
90
kΩ
MIN
NOM
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VCC(FB)
VFB
Supply voltage during fuse-blow condition
IFB
tFB
Supply current into TDI/TCLK during fuse blow
TA = 25°C
Voltage level on TDI/TCLK for fuse-blow
VCC
2.5
6
Time to blow fuse
UNIT
V
7
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
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APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.1, input/output with Schmitt-trigger
Pad Logic
CAPD.x
P1SEL.x
0: Input
1: Output
0
P1DIR.x
Direction Control
From Module
P1OUT.x
1
0
1
Module X OUT
Bus
keeper
P1.0/TA0
P1.1/TA0/MCLK
P1IN.x
EN
D
Module X IN
P1IE.x
P1IRQ.x
P1IFG.x
Q
EN
Set
Interrupt
Edge
Select
P1IES.x
P1SEL.x
NOTE: 0 ≤ x ≤ 1.
Port Function is Active if CAPD.x = 0
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
CAPD.x
P1SEL.0
P1DIR.0
P1DIR.0
P1OUT.0
Out0 Sig.†
P1IN.0
CCI0A†
P1IE.0
P1IFG.0
P1IES.0
DVSS
P1SEL.1
P1DIR.1
P1DIR.1
P1OUT.1
MCLK
P1IN.1
CCI0B†
P1IE.1
P1IFG.1
P1IES.1
DVSS
† Timer_A3
38
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APPLICATION INFORMATION
input/output schematic (continued)
Port P1, P1.2 to P1.7, input/output with Schmitt-trigger
Pad Logic
Port/LCD
Segment xx
DVSS
P1SEL.x
0: Input
1: Output
0
P1DIR.x
Direction Control
From Module
P1OUT.x
1
0
1
Module X OUT
Bus
keeper
P1.2/TA1/S31
P1.3/SVSOUT/S30
P1.4/S29
P1.5/TACLK/ACLK/S28
P1.6/SIMO0/S27
P1.7/SOMI0/S26
P1IN.x
EN
D
Module X IN
P1IE.x
P1IRQ.x
P1IFG.x
Q
EN
Interrupt
Edge
Select
Set
P1IES.x
P1SEL.x
NOTE: 2 ≤ x ≤ 7.
Port Function is Active if Port/LCD = 0
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P1SEL.2
P1DIR.2
P1DIR.2
P1OUT.2
Out1 Sig.†
P1IN.2
CCI1A†
P1IE.2
P1IFG.2
P1IES.2
P1SEL.3
P1DIR.3
P1DIR.3
P1OUT.3
SVSOUT
P1IN.3
unused
P1IE.3
P1IFG.3
P1IES.3
P1SEL.4
P1DIR.4
P1DIR.4
P1OUT.4
DVSS
P1IN.4
unused
P1IE.4
P1IFG.4
P1IES.4
P1SEL.5
P1DIR.5
P1DIR.5
P1OUT.5
ACLK
P1IN.5
TACLK†
P1IE.5
P1IFG.5
P1IES.5
P1SEL.6
P1DIR.6
DCM_SIMO
P1OUT.6
SIMO0(o)‡
P1IN.6
SIMO0(i)‡
P1IE.6
P1IFG.6
P1IES.6
P1SEL.7
P1DIR.7
DCM_SOMI
P1OUT.7
SOMI0(o)‡
P1IN.7
SOMI0(i)‡
P1IE.7
P1IFG.7
P1IES.7
Port/LCD
Segment
S31
0: LCDM
< 0E0h
1: LCDM
≥ 0E0h
S30
S29
S28
0: LCDM
< 0C0h
1: LCDM
≥ 0C0h
S27
S26
† Timer_A3
‡ USART0
Direction Control for SIMO0
SYNC
MM
DCM_SIMO
Direction Control for SOMI0
SYNC
MM
STC
STC
STE
STE
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DCM_SOMI
39
SLAS396A − JULY 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.0 to P2.1, input/output with Schmitt-trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD
Segment xx
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
P2OUT.x
1
Module X OUT
Bus
Keeper
P2.0/TA2/S25
P2.1/UCLK0/S24
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
P2IFG.x
EN
Interrupt
Edge
Select
Q
Set
P2IES.x
NOTE: 0 ≤ x ≤ 1.
Port Function is Active if Port/LCD = 0
P2SEL.x
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
Port/LCD
Segment
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
Out2sig.†
P2IN.0
CCI2A †
P2IE.0
P2IFG.0
P2IES.0
S25
P2Sel.1
P2DIR.1
P2OUT.1
UCLK0(o)‡
P2IN.1
UCLK0(i)‡
P2IE.1
P2IFG.1
P2IES.1
0: LCDM
< 0E0h
1: LCDM
≥ 0E0h
DCM_UCLK
† Timer_A3
‡ USART0
Direction Control for UCLK0
SYNC
MM
DCM_UCLK
STC
STE
40
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S24
SLAS396A − JULY 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.2 to P2.5, input/output with Schmitt-trigger
To BrownOut/SVS for P2.3/SVSIN
Pad Logic
DVSS
DVSS
CAPD.x
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
P2OUT.x
1
0
1
Module X OUT
Bus
keeper
P2.2/STE0
P2.3/SVSIN
P2.4/UTXD0
P2.5/URXD0
P2IN.x
EN
D
Module X IN
P2IE.x
P2IRQ.x
P2IFG.x
Q
EN
Set
Interrupt
Edge
Select
P2IES.x
P2SEL.x
NOTE: 2 ≤ x ≤ 5
Port function is active if CAPD.x = 0
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
CAPD.x
P2SEL.2
P2DIR.2
DVSS
P2OUT.2
DVSS
P2IN.2
STE0†
P2IE.2
P2IFG.2
P2IES.2
DVSS
P2SEL.3
P2DIR.3
P2DIR.3
P2OUT.3
DVSS
P2IN.3
unused
P2IE.3
P2IFG.3
P2IES.3
SVSCTL VLD
= 1111b
P2SEL.4
P2DIR.4
DVCC
P2OUT.4
UTXD0†
P2IN.4
unused
P2IE.4
P2IFG.4
P2IES.4
DVSS
P2SEL.5
P2DIR.5
DVSS
P2OUT.5
DVSS
P2IN.5
URXD0†
P2IE.5
P2IFG.5
P2IES.5
DVSS
† USART0
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SLAS396A − JULY 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, unbonded GPIOs P2.6 and P2.7
P2SEL.x
0: Input
1: Output
0
P2DIR.x
1
Direction Control
From Module
0
P2OUT.x
1
Module X OUT
P2IN.x
Node Is Reset With PUC
EN
Bus Keeper
Module X IN
P2IRQ.x
D
P2IE.x
P2IFG.x
PUC
Interrupt
Edge
Select
EN
Q
Set
Interrupt
Flag
P2IES.x
P2SEL.x
NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins
P2Sel.x
P2DIR.x
DIRECTION
CONTROL
FROM MODULE
P2OUT.x
MODULE X OUT
P2IN.x
MODULE X IN
P2IE.x
P2IFG.x
P2IES.x
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
DVSS
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
DVSS
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
NOTE: Unbonded GPIOs 6 and 7 of port P2 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software
interrupts.
42
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APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DVCC
TDI
Burn and Test
Fuse
TDI/TLCK
Test
and
Emulation
DVCC
TMS
Module
TMS
DVCC
TCK
TCK
RST/NMI
Tau ~ 50 ns
Brownout
TCK
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
G
D
U
S
G
D
U
S
43
SLAS396A − JULY 2003 − REVISED APRIL 2004
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1.8 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 28). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
The JTAG pins are terminated internally, and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
ITDI/TCLK
ITF
Figure 28. Fuse Check Mode Current, MSP430FE42x
44
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MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
POST OFFICE BOX 655303
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1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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