Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CC2541-Q1 SWRS128 – JUNE 2014 CC2541-Q1 SimpleLink™ Bluetooth® Low Energy Wireless MCU for Automotive 1 Device Overview 1.1 Features 1 • RF – 2.4-GHz Bluetooth Low Energy Compliant and Proprietary RF Wireless MCU – Supports Data Rates of 250 kbps, 500 kbps, 1 Mbps, and 2 Mbps – Excellent Link Budget, Enabling Long-Range Applications Without External Front End – Programmable Output Power up to 0 dBm – Excellent Receiver Sensitivity (–94 dBm at 1 Mbps), Selectivity, and Blocking Performance – Suitable for Systems Targeting Compliance With Worldwide Radio Frequency Regulations: ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan) • Layout – Few External Components – 6 mm × 6 mm QFN-40 Package • Low Power – Active-Mode RX Down to: 18.3 mA – Active-Mode TX (0 dBm): 18.6 mA – Power Mode 1 (4-µs Wake-Up): 270 µA – Power Mode 2 (Sleep Timer On): 1 µA – Power Mode 3 (External Interrupts): 0.5 µA – Wide Supply-Voltage Range (2 V to 3.6 V) • Microcontroller – High-Performance and Low-Power 8051 Microcontroller Core With Code Prefetch – 256KB In-System Programmable Flash – 8KB of RAM With Retention in All Power Modes – Hardware Debug Support – Extensive Baseband Automation, Including Auto-Acknowledgment and Address Decoding – Retention of All Relevant Registers in All Power Modes • Peripherals – Powerful Five-Channel DMA – IR Generation Circuitry – General-Purpose Timers (One 16-Bit, Two 8-Bit) – 32-kHz Sleep Timer With Capture – Accurate Digital RSSI Support – Battery Monitor and Temperature Sensor – 12-Bit ADC With Eight Channels and Configurable Resolution – AES Security Coprocessor – Two Powerful USARTs With Support for Several Serial Protocols – 23 General-Purpose I/O Pins (21 × 4 mA, 2 × 20 mA) – I2C interface – 2 I/O Pins Have LED Driving Capabilities – Watchdog Timer – Integrated High-Performance Comparator • Development Tools – CC2541 Evaluation Module – SmartRF™ Software – IAR Embedded Workbench™ Available • Bluetooth v4.0 Compliant Protocol Stack for Single-Mode BLE Solution – Complete Power-Optimized Stack, Including Controller and Host • GAP – Central, Peripheral, Observer, or Broadcaster (Including Combination Roles) • ATT / GATT – Client and Server • SMP – AES-128 Encryption and Decryption • L2CAP – Sample Applications and Profiles • Generic Applications for GAP Central and Peripheral Roles • Proximity, Accelerometer, Simple Keys, and Battery GATT Services • More Applications Supported in BLE Software Stack – Multiple Configuration Options • Single-Chip Configuration, Allowing Applications to Run on CC2541-Q1 • Network Processor Interface for Applications Running on an External Microcontroller – BTool–Windows PC Application for Evaluation, Development, and Test – Over the Air Update Capable 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CC2541-Q1 SWRS128 – JUNE 2014 1.2 • • • • • • www.ti.com Applications 2.4-GHz Bluetooth Low-Energy Systems Proprietary 2.4-GHz Systems Keyless Entry (Passive and Remote) Tire Pressure Monitoring Proximity Sensing Interface and Control 1.3 • • • • • • Diagnostics and Maintenance Cable Replacement Sensor Nodes Infotainment and Media Smart Phone Connectivity Beacons Description The CC2541-Q1 is a power-optimized true Wireless MCU solution for both Bluetooth low energy and proprietary 2.4-GHz applications. This device enables the building of robust nework nodes with low total bill-of-material costs. The CC2541-Q1 combines the excellent performance of a leading RF transceiver with an industry-standard enhanced 8051 MCU, in-system programmable flash memory, 8KB of RAM, and many other powerful supporting features and peripherals. The CC2541-Q1 is highly suited for systems in which ultralow power consumption is required, which is specified by various operating modes. Short transition times between operating modes further enable low power consumption. The CC2541-Q1 comes in a 6 mm x 6 mm QFN40 package. Device Information (1) PACKAGE BODY SIZE CC2541F256TRHARQ1 PART NUMBER RHA (40) 6.00 mm × 6.00 mm CC2541F256TRHATQ1 RHA (40) 6.00 mm × 6.00 mm (1) 2 For more information, see Section 8, Mechanical Packaging and Orderable Information. Device Overview Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com 1.4 SWRS128 – JUNE 2014 Functional Block Diagram Figure 1-1 shows the CC2541-Q1 block diagram. XOSC_Q2 32-MHz CRYSTAL OSC XOSC_Q1 P2_4 32.768-kHz CRYSTAL OSC P2_3 P2_2 HIGHSPEED RC-OSC DEBUG INTERFACE P2_1 DCOUPL POWER-ON RESET BROWN OUT CLOCK MUX and CALIBRATION SFR Bus RESET VDD (2 V–3.6 V) ON-CHIP VOLTAGE REGULATOR WATCHDOG TIMER RESET_N 32-kHz RC-OSC SLEEP TIMER POWER MANAGEMENT CONTROLLER P2_0 PDATA P1_7 P1_6 SRAM FLASH FLASH XRAM 8051 CPU CORE P1_5 RAM IRAM P1_4 SFR MEMORY ARBITRATOR P1_3 P1_2 DMA P1_1 UNIFIED P1_0 IRQ CTRL FLASH CTRL P0_7 P0_6 ANALOG COMPARATOR P0_5 Radio Arbiter P0_3 P0_2 AES ENCRYPTION AND DECRYPTION Link Layer Engine DEMODULATOR SCL MODULATOR 2 I C USART 0 RECEIVE USART 1 FREQUENCY SYNTHESIZER SDA SYNTH DS ADC AUDIO/DC RADIO REGISTERS SFR Bus I/O CONTROLLER P0_1 P0_0 1 KB SRAM FIFOCTRL P0_4 TRANSMIT TIMER 1 (16-Bit) TIMER 2 (BLE LL TIMER) RF_P TIMER 3 (8-Bit) TIMER 4 (8-Bit) RF_N DIGITAL ANALOG MIXED B0301-13 Figure 1-1. Block Diagram Device Overview Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 3 CC2541-Q1 SWRS128 – JUNE 2014 www.ti.com Table of Contents 1 2 3 Device Overview ......................................... 1 4.15 Analog Temperature Sensor ........................ 13 1.1 Features .............................................. 1 4.16 Comparator Characteristics ......................... 13 1.2 Applications ........................................... 2 4.17 ADC Characteristics................................. 14 1.3 Description ............................................ 2 4.18 DC Characteristics .................................. 15 1.4 Functional Block Diagram ............................ 3 4.19 Control Input AC Characteristics .................... 15 Revision History ......................................... 5 Terminal Configuration and Functions .............. 6 4.20 SPI AC Characteristics .............................. 16 4.21 Debug Interface AC Characteristics .......................................... 6 3.2 Pin Descriptions ...................................... 7 Specifications ............................................ 8 4.1 Absolute Maximum Ratings .......................... 8 4.2 Handling Ratings ..................................... 8 4.3 Recommended Operating Conditions ................ 8 4.4 Thermal Characteristics for RHA Package ........... 8 4.5 Electrical Characteristics ............................. 9 4.6 General Characteristics .............................. 9 4.7 RF Receive Section ................................. 10 4.8 RF Transmit Section ................................ 11 4.9 32-MHz Crystal Oscillator ........................... 11 4.10 32.768-kHz Crystal Oscillator ....................... 12 4.11 32-kHz RC Oscillator ................................ 12 4.12 16-MHz RC Oscillator ............................... 12 4.13 RSSI Characteristics ................................ 13 4.14 Frequency Synthesizer Characteristics ............. 13 4.22 Timer Inputs AC Characteristics .................... 18 4.23 Typical Characteristics .............................. 19 3.1 4 4 Pin Diagram 5 6 7 8 ................ 17 Detailed Description ................................... 21 5.1 Functional Block Diagram ........................... 21 5.2 Block Descriptions................................... 21 Application Information ............................... 24 6.1 Input/Output Matching............................... 24 6.2 Crystal ............................................... 25 6.3 On-Chip 1.8-V Voltage Regulator Decoupling ...... 25 6.4 Power-Supply Decoupling and Filtering............. 25 Device and Documentation Support ............... 26 7.1 Documentation Support ............................. 26 7.2 Trademarks.......................................... 27 7.3 Electrostatic Discharge Caution ..................... 27 7.4 Glossary ............................................. 27 Mechanical, Packaging, and Orderable Information .............................................. 27 Table of Contents Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com SWRS128 – JUNE 2014 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2014 * Initial release. Revision History Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 5 CC2541-Q1 SWRS128 – JUNE 2014 www.ti.com 3 Terminal Configuration and Functions The CC2541-Q1 pinout is shown in Figure 3-1 and a short description of the pins follows. DVDD1 P1_6 P1_7 P2_0 P2_1 P2_2 P2_3 / OSC32K_Q2 P2_4 / OSC32K_Q1 40 39 38 37 36 35 34 33 32 AVDD6 DCOUPL Pin Diagram 31 30 R_BIAS 2 29 AVDD4 SDA 3 28 AVDD1 GND 4 27 AVDD2 26 RF_N 25 RF_P GND 1 SCL P1_5 5 P1_4 6 P1_3 7 24 AVDD3 P1_2 8 23 XOSC_Q2 P1_1 9 22 XOSC_Q1 12 13 14 15 16 17 18 19 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 21 20 AVDD5 RESET_N 10 11 P1_0 DVDD2 AGND Exposed Die Attached Pad P0_7 3.1 P0076-14 NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip. Figure 3-1. RHA PACKAGE (TOP VIEW) 6 Terminal Configuration and Functions Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com 3.2 SWRS128 – JUNE 2014 Pin Descriptions Table 3-1. Pin Descriptions PINS TYPE DESCRIPTION NAME NO. AVDD1 28 Power (analog) 2-V–3.6-V analog power-supply connection AVDD2 27 Power (analog) 2-V–3.6-V analog power-supply connection AVDD3 24 Power (analog) 2-V–3.6-V analog power-supply connection AVDD4 29 Power (analog) 2-V–3.6-V analog power-supply connection AVDD5 21 Power (analog) 2-V–3.6-V analog power-supply connection AVDD6 31 Power (analog) 2-V–3.6-V analog power-supply connection DCOUPL 40 Power (digital) 1.8-V digital power-supply decoupling. Do not use for supplying external circuits. DVDD1 39 Power (digital) 2-V–3.6-V digital power-supply connection DVDD2 10 Power (digital) 2-V–3.6-V digital power-supply connection GND 1 Ground pin GND — Ground GND 4 Ground pin Connect to GND P0_0 19 Digital I/O Port 0.0 P0_1 18 Digital I/O Port 0.1 P0_2 17 Digital I/O Port 0.2 P0_3 16 Digital I/O Port 0.3 P0_4 15 Digital I/O Port 0.4 P0_5 14 Digital I/O Port 0.5 P0_6 13 Digital I/O Port 0.6 P0_7 12 Digital I/O Port 0.7 P1_0 11 Digital I/O Port 1.0 – 20-mA drive capability P1_1 9 Digital I/O Port 1.1 – 20-mA drive capability P1_2 8 Digital I/O Port 1.2 P1_3 7 Digital I/O Port 1.3 P1_4 6 Digital I/O Port 1.4 P1_5 5 Digital I/O Port 1.5 P1_6 38 Digital I/O Port 1.6 P1_7 37 Digital I/O Port 1.7 P2_0 36 Digital I/O Port 2.0 P2_1/DD 35 Digital I/O Port 2.1 / debug data P2_2/DC 34 Digital I/O Port 2.2 / debug clock P2_3/ OSC32K_Q2 33 Digital I/O, Analog I/O Port 2.3/32.768 kHz XOSC P2_4/ OSC32K_Q1 32 Digital I/O, Analog I/O Port 2.4/32.768 kHz XOSC RBIAS 30 Analog I/O External precision bias resistor for reference current RESET_N 20 Digital input Reset, active-low RF_N 26 RF I/O Negative RF input signal to LNA during RX Negative RF output signal from PA during TX RF_P 25 RF I/O Positive RF input signal to LNA during RX Positive RF output signal from PA during TX SCL 2 I2C clock or digital I/O Can be used as I2C clock pin or digital I/O. Leave floating if not used. If grounded disable pull up SDA 3 I2C clock or digital I/O Can be used as I2C data pin or digital I/O. Leave floating if not used. If grounded disable pull up XOSC_Q1 22 Analog I/O 32-MHz crystal oscillator pin 1 or external clock input XOSC_Q2 23 Analog I/O 32-MHz crystal oscillator pin 2 Connect to GND The ground pad must be connected to a solid ground plane. Terminal Configuration and Functions Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 7 CC2541-Q1 SWRS128 – JUNE 2014 www.ti.com 4 Specifications Absolute Maximum Ratings (1) 4.1 over operating free-air temperature range (unless otherwise noted) Supply voltage All supply pins must have the same voltage Voltage on any digital pin MIN MAX UNIT –0.3 3.9 V –0.3 VDD + 0.3 ≤ 3.9 V 10 dBm Input RF level (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4.2 Handling Ratings Tstg Storage temperature range MIN MAX UNIT –40 125 °C –1 1 –2 2 –500 500 All pins VESD Electrostatic discharge (ESD) performance: Human Body Model (HBM), per AEC All pins Q100-002 (1) (Excluding pins 25 and 26) Charged Device Model (CDM), per AEC Q100-011 (1) kV V AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 4.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Operating ambient temperature range, TA Operating supply voltage 4.4 NOM MAX UNIT –40 105 °C 2 3.6 V Thermal Characteristics for RHA Package NAME DESCRIPTION °C/W AIR FLOW (m/s) (1) RΘJC Junction-to-case (top) 16.1 0.00 RΘJB Junction-to-board 5.5 0.00 RΘJA Junction-to-free air 30.6 0.00 PsiJT Junction-to-package top 0.2 0.00 PsiJB Junction-to-board 5.4 0.00 RθJC Junction-to-case (bottom) 1.0 0.00 (1) 8 m/s = meters per second Specifications Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com 4.5 SWRS128 – JUNE 2014 Electrical Characteristics Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V, 1 Mbps, GFSK, 250-kHz deviation, Bluetooth low energy mode, and 0.1% BER PARAMETER Icore Iperi 4.6 TEST CONDITIONS Core current consumption Peripheral current consumption (Adds to core current Icore for each peripheral unit activated) MIN TYP MAX UNIT RX mode, standard mode, no peripherals active, low MCU activity 18.3 RX mode, high-gain mode, no peripherals active, low MCU activity 20.8 TX mode, –20 dBm output power, no peripherals active, low MCU activity 17.2 TX mode, 0 dBm output power, no peripherals active, low MCU activity 18.6 Power mode 1. Digital regulator on; 16-MHz RCOSC and 32MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD and sleep timer active; RAM and register retention 270 Power mode 2. Digital regulator off; 16-MHz RCOSC and 32MHz crystal oscillator off; 32.768-kHz XOSC, POR, and sleep timer active; RAM and register retention 1 mA Power mode 3. Digital regulator off; no clocks; POR active; RAM and register retention 0.5 Low MCU activity: 32-MHz XOSC running. No radio or peripherals. Limited flash access, no RAM access. 6.7 Timer 1. Timer running, 32-MHz XOSC used 90 Timer 2. Timer running, 32-MHz XOSC used 90 Timer 3. Timer running, 32-MHz XOSC used 60 Timer 4. Timer running, 32-MHz XOSC used 70 Sleep timer, including 32.753-kHz RCOSC 0.6 ADC, when converting 1.2 µA mA μA mA General Characteristics Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT WAKE-UP AND TIMING Power mode 1 → Active Digital regulator on, 16-MHz RCOSC and 32-MHz crystal oscillator off. Start-up of 16-MHz RCOSC 4 μs Power mode 2 or 3 → Active Digital regulator off, 16-MHz RCOSC and 32-MHz crystal oscillator off. Start-up of regulator and 16-MHz RCOSC 120 μs Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC, with 32-MHz XOSC OFF 500 μs With 32-MHz XOSC initially on 180 μs Proprietary auto mode 130 BLE mode 150 Active → TX or RX RX/TX turnaround μs RADIO PART RF frequency range Programmable in 1-MHz steps Data rate and modulation format 2 Mbps, GFSK, 500-kHz deviation 2 Mbps, GFSK, 320-kHz deviation 1 Mbps, GFSK, 250-kHz deviation 1 Mbps, GFSK, 160-kHz deviation 500 kbps, MSK 250 kbps, GFSK, 160-kHz deviation 250 kbps, MSK 2379 2496 Specifications Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 MHz 9 CC2541-Q1 SWRS128 – JUNE 2014 4.7 www.ti.com RF Receive Section Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C, VDD = 3 V, fc = 2440 MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1 Mbps, GFSK, 250-kHz Deviation, Bluetooth low energy Mode, 0.1% BER Receiver sensitivity (1) (2) Saturation (2) Co-channel rejection High-gain mode –94 Standard mode –88 BER < 0.1% (2) In-band blocking rejection (2) 5 dBm Wanted signal –67 dBm –6 dB ±1 MHz offset, 0.1% BER, wanted signal –67 dBm –2 ±2 MHz offset, 0.1% BER, wanted signal –67 dBm 26 ±3 MHz offset, 0.1% BER, wanted signal –67 dBm 34 >6 MHz offset, 0.1% BER, wanted signal –67 dBm Out-of-band blocking rejection (2) dBm dB 33 Minimum interferer level < 2 GHz (Wanted signal –67 dBm) –21 Minimum interferer level [2 GHz, 3 GHz] (Wanted signal –67 dBm) –27 Minimum interferer level > 3 GHz (Wanted signal –67 dBm) dBm –8 Intermodulation (2) Minimum interferer level Frequency error tolerance (3) Including both initial tolerance and drift. Sensitivity better than -67dBm, 250 byte payload. BER 0.1% Symbol rate error tolerance (4) Maximum packet length. Sensitivity better than –67 dBm, 250 byte payload. BER 0.1% –36 dBm –250 250 kHz –80 80 ppm ALL RATES/FORMATS Spurious emission in RX. Conducted measurement f < 1 GHz –67 dBm Spurious emission in RX. Conducted measurement f > 1 GHz –57 dBm (1) (2) (3) (4) 10 The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command. The default value is standard mode. Results based on standard-gain mode. Difference between center frequency of the received RF signal and local oscillator frequency Difference between incoming symbol rate and the internally generated symbol rate Specifications Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com 4.8 SWRS128 – JUNE 2014 RF Transmit Section Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz PARAMETER Output power Programmable output power range TEST CONDITIONS MIN TYP Delivered to a single-ended 50-Ω load through a balun using maximum recommended output power setting 0 Delivered to a single-ended 50-Ω load through a balun using minimum recommended output power setting –20 MAX UNIT dBm Delivered to a single-ended 50-Ω load through a balun using minimum recommended output power setting f < 1 GHz 20 dB –52 dBm Spurious emission conducted f > 1 GHz –48 dBm measurement Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan) Optimum load impedance Differential impedance as seen from the RF port (RF_P and RF_N) toward the antenna Ω 70 +j30 Designs with antenna connectors that require conducted ETSI compliance at 64 MHz should insert an LC resonator in front of the antenna connector. Use a 1.6-nH inductor in parallel with a 1.8-pF capacitor. Connect both from the signal trace to a good RF ground. 4.9 32-MHz Crystal Oscillator Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V PARAMETER TEST CONDITIONS MIN Crystal frequency TYP MAX 32 Crystal frequency accuracy requirement (1) UNIT MHz –40 40 ppm ESR Equivalent series resistance 6 60 Ω C0 Crystal shunt capacitance 1 7 pF CL Crystal load capacitance 10 16 pF Start-up time Power-down guard time (1) 0.25 The crystal oscillator must be in power down for a guard time before it is used again. This requirement is valid for all modes of operation. The need for power-down guard time can vary with crystal type and load. 3 ms ms Including aging and temperature dependency, as specified by [1] Specifications Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 11 CC2541-Q1 SWRS128 – JUNE 2014 4.10 www.ti.com 32.768-kHz Crystal Oscillator Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V PARAMETER TEST CONDITIONS MIN Crystal frequency TYP MAX UNIT 40 ppm 32.768 Crystal frequency accuracy requirement (1) –40 kHz ESR Equivalent series resistance 40 130 kΩ C0 Crystal shunt capacitance 0.9 2 pF CL Crystal load capacitance 12 16 pF Start-up time 0.4 (1) s Including aging and temperature dependency, as specified by [1] 4.11 32-kHz RC Oscillator Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V. PARAMETER Calibrated frequency TEST CONDITIONS MIN (1) UNIT kHz ±0.2% Temperature coefficient (2) 0.4 %/°C 3 %/V 2 ms (3) Calibration time (4) (1) (2) (3) (4) MAX 32.753 Frequency accuracy after calibration Supply-voltage coefficient TYP The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977. Frequency drift when temperature changes after calibration Frequency drift when supply voltage changes after calibration When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator is performed while SLEEPCMD.OSC32K_CALDIS is set to 0. 4.12 16-MHz RC Oscillator Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V PARAMETER Frequency TEST CONDITIONS (1) MIN TYP 16 Uncalibrated frequency accuracy ±18% Calibrated frequency accuracy ±0.6% Start-up time Initial calibration time (1) (2) 12 (2) MAX UNIT MHz 10 μs 50 μs The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2. When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator is performed while SLEEPCMD.OSC_PD is set to 0. Specifications Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com 4.13 SWRS128 – JUNE 2014 RSSI Characteristics Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER Useful RSSI range (1) RSSI offset (1) Reduced gain by AGC algorithm 64 High gain by AGC algorithm 64 Reduced gain by AGC algorithm 79 High gain by AGC algorithm 99 Absolute uncalibrated accuracy (1) dB dBm ±6 dB 1 dB Step size (LSB value) All Other Rates/Formats Useful RSSI range (1) RSSI offset (1) Standard mode 64 High-gain mode 64 Standard mode 98 High-gain mode 107 Absolute uncalibrated accuracy (1) dBm ±3 dB 1 dB Step size (LSB value) (1) dB Assuming CC2541-Q1 EM reference design. Other RF designs give an offset from the reported value. 4.14 Frequency Synthesizer Characteristics Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz PARAMETER TEST CONDITIONS Phase noise, unmodulated carrier 4.15 MIN TYP At ±1-MHz offset from carrier –109 At ±3-MHz offset from carrier –112 At ±5-MHz offset from carrier –119 MAX UNIT dBc/Hz Analog Temperature Sensor Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V PARAMETER TEST CONDITIONS Output MIN TYP MAX 1480 Temperature coefficient Voltage coefficient Initial accuracy without calibration Measured using integrated ADC, internal band-gap voltage reference, and maximum resolution UNIT 12-bit 4.5 / 1°C 1 0.1 V ±10 °C Accuracy using 1-point calibration ±5 °C Current consumption when enabled 0.5 mA 4.16 Comparator Characteristics TA = 25°C, VDD = 3 V. All measurement results are obtained using the CC2541-Q1 reference designs, post-calibration. PARAMETER TEST CONDITIONS MIN TYP MAX Common-mode maximum voltage VDD Common-mode minimum voltage –0.3 Input offset voltage Offset vs temperature Offset vs operating voltage UNIT V 1 mV 16 µV/°C 4 mV/V Supply current 230 nA Hysteresis 0.15 mV Specifications Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 13 CC2541-Q1 SWRS128 – JUNE 2014 4.17 www.ti.com ADC Characteristics TA = 25°C and VDD = 3 V PARAMETER ENOB (1) TEST CONDITIONS MIN VDD is voltage on AVDD5 pin 0 VDD V VDD is voltage on AVDD5 pin 0 VDD V External reference voltage differential VDD is voltage on AVDD5 pin 0 VDD Simulated using 4-MHz clock speed 197 kΩ Full-scale signal (1) Peak-to-peak, defines 0 dBFS 2.97 V Effective number of bits Single-ended input, 7-bit setting 5.7 Single-ended input, 9-bit setting 7.5 Single-ended input, 10-bit setting 9.3 Single-ended input, 12-bit setting 10.3 Differential input, 7-bit setting 6.5 Differential input, 9-bit setting 8.3 Differential input, 10-bit setting 10 Differential input, 12-bit setting 11.5 Signal to nonharmonic ratio 12-bit setting, clocked by RCOSC 10.9 7-bit setting, both single and differential 0–20 Single ended input, 12-bit setting, –6 dBFS (1) –75.2 Differential input, 12-bit setting, –6 dBFS (1) –86.6 79.3 78.8 dB 88.9 Common-mode rejection ratio >84 dB Crosstalk Single ended input, 12-bit setting, 1-kHz sine (0 dBFS), limited by ADC resolution >84 dB Offset Midscale –3 mV Differential nonlinearity Integral nonlinearity 0.68% 12-bit setting, mean (1) 0.05 12-bit setting, maximum (1) 0.9 12-bit setting, mean (1) 4.6 12-bit setting, maximum (1) 13.3 12-bit setting, mean, clocked by RCOSC 10 12-bit setting, max, clocked by RCOSC 29 (1) 35.4 Single ended input, 9-bit setting (1) 46.8 Single ended input, 10-bit setting (1) 57.5 (1) Signal-to-noise-and-distortion 66.6 Single ended input, 12-bit setting Differential input, 7-bit setting (1) 40.7 Differential input, 9-bit setting (1) 51.6 Differential input, 10-bit setting (1) 61.8 (1) 70.8 Differential input, 12-bit setting Conversion time 14 (1) Differential input, 12-bit setting, 1-kHz sine (0 dBFS), limited by ADC resolution Single ended input, 7-bit setting (1) dB Differential input, 12-bit setting, –6 dBFS (1) Gain error SINAD (–THD+N) kHz 70.2 Differential input, 12-bit setting (1) Single-ended input, 12-bit setting, –6 dBFS bits 9.7 Single-ended input, 12-bit setting (1) INL V Input resistance, signal Total harmonic distortion DNL UNIT External reference voltage Useful power bandwidth CMRR MAX Input voltage 10-bit setting, clocked by RCOSC THD TYP 7-bit setting 20 9-bit setting 36 10-bit setting 68 12-bit setting 132 LSB LSB dB μs Measured with 300-Hz sine-wave input and VDD as reference. Specifications Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com SWRS128 – JUNE 2014 ADC Characteristics (continued) TA = 25°C and VDD = 3 V PARAMETER TEST CONDITIONS MIN TYP Power consumption Internal reference VDD coefficient UNIT mA 4 Internal reference temperature coefficient Internal reference voltage 4.18 MAX 1.2 mV/V 0.4 mV/10°C 1.24 V DC Characteristics TA = 25°C, VDD = 3 V PARAMETER TEST CONDITIONS MIN TYP Logic-0 input voltage MAX 0.5 Logic-1 input voltage 2.4 Input equals 0 V –50 50 Logic-1 input current Input equals VDD –50 50 20 Logic-0 output voltage, 4- mA pins Output load 4 mA Logic-1 output voltage, 4-mA pins Output load 4 mA Logic-0 output voltage, 20- mA pins Output load 20 mA Logic-1 output voltage, 20-mA pins Output load 20 mA 4.19 V V Logic-0 input current I/O-pin pullup and pulldown resistors UNIT nA nA kΩ 0.5 2.5 V V 0.5 2.5 V V Control Input AC Characteristics TA = –40°C to 105°C, VDD = 2 V to 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 32 MHz System clock, fSYSCLK tSYSCLK = 1/ fSYSCLK The undivided system clock is 32 MHz when crystal oscillator is used. The undivided system clock is 16 MHz when calibrated 16-MHz RC oscillator is used. 16 RESET_N low duration See item 1, Figure 4-1. This is the shortest pulse that is recognized as a complete reset pin request. Note that shorter pulses may be recognized but do not lead to complete reset of all modules within the chip. 1 µs Interrupt pulse duration See item 2, Figure 4-1.This is the shortest pulse that is recognized as an interrupt request. 20 ns RESET_N 1 2 Px.n T0299-01 Figure 4-1. Control Input AC Characteristics Specifications Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 15 CC2541-Q1 SWRS128 – JUNE 2014 4.20 www.ti.com SPI AC Characteristics TA = –40°C to 105°C, VDD = 2 V to 3.6 V PARAMETER t1 TEST CONDITIONS SCK period SCK duty cycle MIN Master, RX and TX 250 Slave, RX and TX 250 Master TYP MAX UNIT ns 50% Master 63 Slave 63 Master 63 Slave 63 t2 SSN low to SCK t3 SCK to SSN high t4 MOSI early out Master, load = 10 pF 7 ns t5 MOSI late out Master, load = 10 pF 10 ns t6 MISO setup Master 90 t7 MISO hold Master 10 SCK duty cycle Slave t10 MOSI setup Slave 35 ns t11 MOSI hold Slave 10 ns t9 MISO late out Slave, load = 10 pF Operating frequency ns ns ns ns 50% ns 95 Master, TX only 8 Master, RX and TX 4 Slave, RX only 8 Slave, RX and TX 4 ns MHz SCK t2 t3 SSN t4 D0 MOSI t6 MISO X t5 X D1 t7 D0 X T0478-01 Figure 4-2. SPI Master AC Characteristics 16 Specifications Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com SWRS128 – JUNE 2014 SCK t2 t3 SSN t8 D0 MISO X t10 MOSI X t9 D1 t11 D0 X T0479-01 Figure 4-3. SPI Slave AC Characteristics 4.21 Debug Interface AC Characteristics TA = –40°C to 105°C, VDD = 2 V to 3.6 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 12 MHz fclk_dbg Debug clock frequency (see Figure 4-4) t1 Allowed high pulse on clock (see Figure 4-4) 35 ns t2 Allowed low pulse on clock (see Figure 4-4) 35 ns t3 EXT_RESET_N low to first falling edge on debug clock (see Figure 4-6) 167 ns t4 Falling edge on clock to EXT_RESET_N high (see Figure 46) 83 ns t5 EXT_RESET_N high to first debug command (see Figure 46) 83 ns t6 Debug data setup (see Figure 4-5) 2 ns t7 Debug data hold (see Figure 4-5) 4 ns t8 Clock-to-data delay (see Figure 4-5) Load = 10 pF 30 ns Time DEBUG_ CLK P2_2 t1 t2 1/fclk_dbg T0436-01 Figure 4-4. Debug Clock – Basic Timing Specifications Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 17 CC2541-Q1 SWRS128 – JUNE 2014 www.ti.com Time DEBUG_ CLK P2_2 RESET_N t3 t4 t5 T0437-01 Figure 4-5. Debug Enable Timing Time DEBUG_ CLK P2_2 DEBUG_DATA (to CC2541) P2_1 DEBUG_DATA (from CC2541) P2_1 t6 t8 t7 Figure 4-6. Data Setup and Hold Timing 4.22 Timer Inputs AC Characteristics TA = –40°C to 105°C, VDD = 2 V to 3.6 V PARAMETER Input capture pulse duration 18 TEST CONDITIONS Synchronizers determine the shortest input pulse that can be recognized. The synchronizers operate at the current system clock rate (16 MHz or 32 MHz). Specifications MIN 1.5 TYP MAX UNIT tSYSCLK Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com SWRS128 – JUNE 2014 4.23 Typical Characteristics 22 20.5 21.5 20 Current (mA) Current (mA) 21 20.5 20 19.5 19.5 19 19 18.5 18.5 18 -40 -20 0 20 40 60 Temperature (qC) 80 18 -40 100 0 20 40 60 Temperature (qC) 80 100 Figure 4-8. TX Current vs Temperature -80 2.5 -82 2 1.5 -84 Level (dBm) Level (dBm) Figure 4-7. RX Current vs Temperature -20 -86 -88 1 0.5 0 -90 -0.5 -92 -40 -20 0 20 40 60 Temperature (qC) 80 -1 -40 100 Figure 4-9. RX Sensitivity vs Temperature -20 0 20 40 60 Temperature (qC) 80 100 Figure 4-10. TX Power vs Temperature 19.2 20 19.1 Current (mA) Current (mA) 19.5 19 19 18.9 18.8 18.5 18.7 18 18.6 2 2.2 2.4 2.6 2.8 3 Voltage (V) 3.2 3.4 Figure 4-11. RX Current vs Supply Voltage 3.6 2 2.2 2.4 2.6 2.8 3 Voltage (V) 3.2 3.4 3.6 Figure 4-12. TX Current vs Supply Voltage Specifications Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 19 CC2541-Q1 SWRS128 – JUNE 2014 www.ti.com −84 4 −86 2 Level (dBm) Level (dBm) Typical Characteristics (continued) −88 −90 −92 0 −2 2 2.2 2.4 2.6 2.8 3 Frequency (MHz) 3.2 3.4 −4 3.6 2 2.2 1-Mbps GFSK 250-kHz Standard Gain Setting TA = 25°C 2.8 3 Voltage (V) 3.2 3.4 3.6 G008 Figure 4-14. TX Power vs Supply Voltage 4 −86 2 Level (dBm) −84 −88 2.6 TX Power Setting = 0 dBm TA = 25°C Figure 4-13. RX Sensitivity vs Supply Voltage Level (dBm) 2.4 G007 0 −90 −2 −92 2400 2410 2420 2430 2440 2450 2460 2470 2480 Frequency (MHz) G009 −4 2400 2410 2420 2430 2440 2450 2460 2470 2480 Frequency (MHz) G010 1-Mbps GFSK 250-kHz Standard Gain Setting TA = 25°C Vcc = 3 V Figure 4-15. RX Sensitivity vs Frequency TX Power Setting = 0 dBm TA = 25°C Vcc = 3 V Figure 4-16. TX Power vs Frequency Table 4-1. Output Power (1) (2) (1) (2) 20 TX POWER Setting Typical Output Power (dBm) 0xE1 0 0xD1 –2 0xC1 –4 0xB1 –6 0xA1 –8 0x91 –10 0x81 –12 0x71 –14 0x61 –16 0x51 –18 0x41 –20 Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz. See SWRU191 for recommended register settings. 1 Mbsp, GFSK, 250-kHz deviation, Bluetooth low energy mode, 1% BER Specifications Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com SWRS128 – JUNE 2014 5 Detailed Description 5.1 Functional Block Diagram A block diagram of the CC2541-Q1 is shown in Figure 5-1. The modules can be roughly divided into one of three categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related modules. In the following subsections, a short description of each module is given. XOSC_Q2 32-MHz CRYSTAL OSC XOSC_Q1 P2_4 32.768-kHz CRYSTAL OSC P2_3 P2_2 HIGHSPEED RC-OSC DEBUG INTERFACE P2_1 DCOUPL POWER-ON RESET BROWN OUT CLOCK MUX and CALIBRATION SFR Bus RESET VDD (2 V–3.6 V) ON-CHIP VOLTAGE REGULATOR WATCHDOG TIMER RESET_N 32-kHz RC-OSC SLEEP TIMER POWER MANAGEMENT CONTROLLER P2_0 PDATA P1_7 P1_6 8051 CPU CORE P1_5 RAM SRAM FLASH FLASH XRAM IRAM P1_4 SFR MEMORY ARBITRATOR P1_3 P1_2 DMA P1_1 UNIFIED P1_0 IRQ CTRL FLASH CTRL P0_7 P0_6 ANALOG COMPARATOR P0_5 Radio Arbiter P0_3 P0_2 AES ENCRYPTION AND DECRYPTION Link Layer Engine DEMODULATOR SCL MODULATOR 2 I C USART 0 RECEIVE USART 1 FREQUENCY SYNTHESIZER SDA SYNTH DS ADC AUDIO/DC RADIO REGISTERS SFR Bus I/O CONTROLLER P0_1 P0_0 1 KB SRAM FIFOCTRL P0_4 TRANSMIT TIMER 1 (16-Bit) TIMER 2 (BLE LL TIMER) RF_P TIMER 3 (8-Bit) TIMER 4 (8-Bit) RF_N DIGITAL ANALOG MIXED B0301-13 Figure 5-1. CC2541-Q1 Block Diagram 5.2 Block Descriptions A block diagram of the CC2541-Q1 is shown in Figure 5-1. The modules can be roughly divided into one of three categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related modules. In the following subsections, a short description of each module is given. Detailed Description Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 21 CC2541-Q1 SWRS128 – JUNE 2014 5.2.1 www.ti.com CPU and Memory The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR, DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit. The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same physical memory. The SFR bus is drawn conceptually in Figure 5-1 as a common bus that connects all hardware peripherals to the memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio register bank, even though these are indeed mapped into XDATA memory space. The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The SRAM is an ultralow-power SRAM that retains its contents even when the digital part is powered off (power mode 2 and mode 3). The 256 KB flash block provides in-circuit programmable non-volatile program memory for the device, and maps into the CODE and XDATA memory spaces. 5.2.2 Peripherals Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4bytewise programming. See User Guide for details on the flash controller. A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memory space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers, ADC interface, etc.) can be used with the DMA controller for efficient operation by performing data transfers between a single SFR or XREG address and flash/SRAM. Each CC2541-Q1 contains a unique 48-bit IEEE address that can be used as the public device address for a Bluetooth device. Designers are free to use this address, or provide their own, as described in the Bluetooth specfication. The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which is associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced even if the device is in a sleep mode (power modes 1 and 2) by bringing the CC2541-Q1 back to the active mode. The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging. Through this debug interface, it is possible to erase or program the entire flash memory, control which oscillators are enabled, stop and start execution of the user program, execute instructions on the 8051 core, set code breakpoints, and single-step through instructions in the code. Using these techniques, it is possible to perform in-circuit debugging and external flash programming elegantly. The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral modules control certain pins or whether they are under software control, and if so, whether each pin is configured as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects to the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications. The sleep timer is an ultralow-power timer that can either use an external 32.768-kHz crystal oscillator or an internal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes except power mode 3. Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power mode 1 or mode 2. 22 Detailed Description Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com SWRS128 – JUNE 2014 A built-in watchdog timer allows the CC2541-Q1 to reset itself if the firmware hangs. When enabled by software, the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out. Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction. Timer 2 is a 40-bit timer. It has a 16-bit counter with a configurable timer period and a 24-bit overflow counter that can be used to keep track of the number of periods that have transpired. A 40-bit capture register is also used to record the exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which transmission ends. There are two 16-bit output compare registers and two 24-bit overflow compare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts. Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter channels can be used as PWM output. USART 0 and USART 1 are each configurable as either an SPI master/slave or a UART. They provide double buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex applications. Each USART has its own high-precision baud-rate generator, thus leaving the ordinary timers free for other uses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly instead of using some oversampling scheme, and are thus well-suited for high data rates. The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with 128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware support for CCM. The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4kHz, respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are possible. The inputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a single-ended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC can automate the process of periodic sampling or conversion over a sequence of channels. The I2C module provides a digital peripheral connection with two pins and supports both master and slave operation. I2C support is compliant with the NXP I2C specification version 2.1 and supports standard mode (up to 100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit device addressing modes are supported, as well as master and slave modes. The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin interrupt. Detailed Description Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 23 CC2541-Q1 SWRS128 – JUNE 2014 www.ti.com 6 Application Information Few external components are required for the operation of the CC2541-Q1. A typical application circuit is shown in Figure 6-1. 2 V±3.6 V Power Supply Optional 32-kHz Crystal(1) C331 XTAL2 C401 3 SDA AVDD6 31 P2_4/XOSC32K_Q1 32 P2_2 34 P2_1 35 P2_0 36 P1_7 37 P1_6 38 2 SCL P2_3/XOSC32K_Q2 33 1 GND DVDD1 39 DCOUPL 40 C321 R301 RBIAS 30 AVDD4 29 C251 AVDD1 28 4 GND Antenna (50 ) L251 C252 AVDD2 27 5 P1_5 6 P1_4 L252 RF_N 26 CC2541Q1 L253 C261 RF_P 25 L261 DIE ATTACH PAD: AVDD3 24 19 P0_0 18 P0_1 17 P0_2 16 P0_3 15 P0_4 14 P0_5 10 DVDD2 13 P0_6 XOSC_Q1 22 12 P0_7 XOSC_Q2 23 9 P1_1 11 P1_0 8 P1_2 20 RESET_N 7 P1_3 C262 C253 AVDD5 21 XTAL1 C221 C231 (1) 32-kHz crystal is mandatory when running the BLE protocol stack in low-power modes, except if the link layer is in the standby state (Vol. 6 Part B Section 1.1 in [1]). NOTE: Different antenna alternatives will be provided as reference designs. Power supply decoupling capacitors are not shown. Digital I/O not connected Figure 6-1. CC2541-Q1 Application Circuit Table 6-1. Overview of External Components (Excluding Supply Decoupling Capacitors) Component 6.1 Description C401 Decoupling capacitor for the internal 1.8-V digital voltage regulator R301 Precision resistor ±1%, used for internal biasing Value 1 µF 56 kΩ Input/Output Matching When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The balun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2541-Q1EM, for recommended balun. 6.2 Crystal 24 Application Information Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com SWRS128 – JUNE 2014 An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz crystal oscillator. See Section 4.9 for details. The load capacitance seen by the 32-MHz crystal is given by: 1 CL = + Cparasitic 1 1 + C221 C231 (1) XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for 32.768-kHz crystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very sleep-current consumption and accurate wake-up times are needed. The load capacitance seen by 32.768-kHz crystal is given by: 1 CL = + Cparasitic 1 1 + C321 C331 the low the (2) A series resistor may be used to comply with the ESR requirement. 6.3 On-Chip 1.8-V Voltage Regulator Decoupling The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor (C471) for stable operation. 6.4 Power-Supply Decoupling and Filtering Proper power-supply decoupling must be used for optimum performance. The placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the best performance in an application. TI provides a compact reference design that should be followed very closely. Application Information Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 25 CC2541-Q1 SWRS128 – JUNE 2014 www.ti.com 7 Device and Documentation Support 7.1 Documentation Support 7.1.1 Related Documentation 1. Bluetooth® Core Technical Specification document, version 4.0 http://www.bluetooth.com/SiteCollectionDocuments/Core_V40.zip 2. CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee® Applications/CC2541-Q1 System-on-Chip Solution for 2.4-GHz Bluetooth low energy Applications (SWRU191) 3. Current Savings in CC254x Using the TPS62730 (SWRA365). 7.1.1.1 Additional Information Texas Instruments offers a wide selection of cost-effective, low-power RF solutions for proprietary and standard-based wireless applications for use in industrial and consumer applications. Our selection includes RF transceivers, RF transmitters, RF front ends, and System-on-Chips as well as various software solutions for the sub-1- and 2.4-GHz frequency bands. In addition, Texas Instruments provides a large selection of support collateral such as development tools, technical documentation, reference designs, application expertise, customer support, third-party and university programs. The Low-Power RF E2E Online Community provides technical support forums, videos and blogs, and the chance to interact with fellow engineers from all over the world. With a broad selection of product solutions, end application possibilities, and a range of technical support, Texas Instruments offers the broadest low-power RF portfolio. We make RF easy! For more information on low-power RF, see Section 7.1.1.2, Section 7.1.1.3, and Section 7.1.1.4. 7.1.1.2 • • • Texas Instruments Low-Power RF Website Forums, videos, and blogs RF design help E2E interaction Join us today at www.ti.com/lprf-forum. 7.1.1.3 Texas Instruments Low-Power RF Developer Network Texas Instruments has launched an extensive network of low-power RF development partners to help customers speed up their application development. The network consists of recommended companies, RF consultants, and independent design houses that provide a series of hardware module products and design services, including: • RF circuit, low-power RF, and ZigBee® design services • Low-power RF and ZigBee module solutions and development tools • RF certification services and RF circuit manufacturing Need help with modules, engineering services or development tools? Search the Low-Power RF Developer Network tool to find a suitable partner. www.ti.com/lprfnetwork 26 Device and Documentation Support Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2541-Q1 CC2541-Q1 www.ti.com 7.1.1.4 SWRS128 – JUNE 2014 Low-Power RF eNewsletter The Low-Power RF eNewsletter keeps you up-to-date on new products, news releases, developers’ news, and other news and events associated with low-power RF products from TI. The Low-Power RF eNewsletter articles include links to get more online information. Sign up today on www.ti.com/lprfnewsletter 7.2 Trademarks SimpleLink is a trademark of Texas Instruments. Bluetooth is a registered trademark of Bluetooth SIG, Inc.. ZigBee is a registered trademark of ZigBee Alliance. All other trademarks are the property of their respective owners. 7.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 7.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 8 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2014, Texas Instruments Incorporated Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: CC2541-Q1 27 PACKAGE OPTION ADDENDUM www.ti.com 15-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CC2541F256TRHARQ1 ACTIVE VQFN RHA 40 1 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 CC2541Q1 F256 CC2541F256TRHATQ1 ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 CC2541Q1 F256 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Jul-2016 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CC2541-Q1 : • Catalog: CC2541 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CC2541F256TRHARQ1 VQFN RHA 40 1 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 CC2541F256TRHATQ1 VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CC2541F256TRHARQ1 VQFN RHA CC2541F256TRHATQ1 VQFN RHA 40 1 336.6 336.6 28.6 40 250 213.0 191.0 55.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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