High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux (4-Bit, 1 of 2) Bus Switch ADG3257 FUNCTIONAL BLOCK DIAGRAM FEATURES 1B1 1A 100 ps propagation delay through the switch 2 Ω switches connect inputs to outputs Data rates up to 933 Mbps Single 3.3 V/5 V supply operation Level translation operation Ultralow quiescent supply current (1 nA typical) 3.5 ns switching Switches remain in the off state when power is off Standard 3257 type pinout 1B2 2B1 2A 2B2 3B1 3A 3B2 4B1 4A 4B2 APPLICATIONS S BE 02914-001 LOGIC Bus switching Bus isolation Level translation Memory switching/interleaving Figure 1. GENERAL DESCRIPTION The ADG3257 is a CMOS bus switch comprised of four 2:1 multiplexers/demultiplexers with high impedance outputs. The device is manufactured on a CMOS process. This provides low power dissipation yet high switching speed and very low on resistance, allowing the inputs to be connected to the outputs without adding propagation delay or generating additional ground bounce noise. The ADG3257 operates from a single 3.3 V/5 V supply. The control logic for each switch is shown in Table 1. These switches are bidirectional when on. In the off state, signal levels are blocked up to the supplies. When the power supply is off, the switches remain in the off state, isolating Port A and Port B. PRODUCT HIGHLIGHTS 1. 0.1 ns propagation delay through switch. 2. 2 Ω switches connect inputs to outputs. 3. Bidirectional operation. 4. Ultralow power dissipation. 5. 16-lead QSOP package. This bus switch is suited to both switching and level translation applications. It can be used in applications requiring level translation from 3.3 V to 2.5 V when powered from 3.3 V. Additionally, with a diode connected in series with 5 V VDD, the ADG3257 may also be used in applications requiring 5 V to 3.3 V level translation. Table 1. Truth Table BE S Function H L L X L H Disable A = B1 A = B2 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved. ADG3257 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Test Circuits ........................................................................................9 General Description ......................................................................... 1 Applications Information .............................................................. 10 Product Highlights ........................................................................... 1 Mixed Voltage Operation, Level Translation .......................... 10 Revision History ............................................................................... 2 Memory Switching ..................................................................... 10 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 11 Absolute Maximum Ratings............................................................ 5 Ordering Guide .......................................................................... 11 ESD Caution .................................................................................. 5 REVISION HISTORY 03/08—Rev. D to Rev. E Updated Format .................................................................... Universal Changes to Features.............................................................................1 Changes to General Description .......................................................1 Changes to Absolute Maximum Ratings ..........................................5 Changes to Pin Configuration and Function Descriptions ...........6 Changes to Test Circuits .....................................................................9 Changes to Ordering Guide ...............................................................11 11/04—Rev. C to Rev. D Changes to Specifications ...................................................................2 Changes to Ordering Guide ...............................................................4 04/03—Rev. A to Rev. B Updated Outline Dimensions ............................................................8 06/02—Rev. 0 to Rev. A Edits to Features ...................................................................................1 Rev. E | Page 2 of 12 ADG3257 SPECIFICATIONS VCC = 5.0 V ± 10%, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 DC ELECTRICAL CHARACTERISTICS Input High Voltage Input Low Voltage Input Leakage Current Off State Leakage Current On State Leakage Current Maximum Pass Voltage 4 CAPACITANCE4 A Port Off Capacitance B Port Off Capacitance A, B Port On Capacitance Control Input Capacitance SWITCHING CHARACTERISTICS4 Propagation Delay A to B or B to A, tPD Propagation Delay Matching 6 Bus Enable Time BE to A or B Bus Disable Time BE to A or B Bus Select Time S to A or B Enable Disable Maximum Data Rate DIGITAL SWITCH On Resistance On-Resistance Matching POWER REQUIREMENTS VCC Quiescent Power Supply Current Increase in ICC per Input4, 7 Symbol Conditions 2 Min B Version Typ 3 Max VINH VINL II IOZ IOZ VP 0 ≤ VIN ≤ 5.5 V 0 ≤ A, B ≤ VCC 0 ≤ A, B ≤ VCC VIN = VCC = 5 V, IO = −5 μA CA OFF CB OFF CA, CB ON CIN f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz 7 5 11 4 tPHL, tPLH 5 VA = 0 V, CL = 50 pF VA = 0 V, CL = 50 pF CL = 50 pF, RL = 500 Ω CL = 50 pF, RL = 500 Ω 0.0075 5 3.5 tPZH, tPZL tPHZ, tPLZ 2.4 −0.3 tSEL_EN tSEL_DIS CL = 50 pF, RL = 500 Ω CL = 50 pF, RL = 500 Ω VA = 2 V p-p RON VA = 0 V IO = 48 mA, 15 mA, 8 mA, TA = 25°C IO = 48 mA, 15 mA, 8 mA VA = 2.4 V IO = 48 mA, 15 mA, 8 mA, TA = 25°C IO = 48 mA, 15 mA, 8 mA VA = 0 V, IO = 48 mA, 15 mA, 8 mA ΔRON 3.9 1 1 ±0.01 ±0.01 ±0.01 4.2 Digital inputs = 0 V or VCC VCC = 5.5 V, one input at 3.0 V; others at VCC or GND 1 V V μA μA μA V pF pF pF pF 0.10 0.035 7.5 7 ns ns ns ns 8 5 933 12 8 ns ns Mbps 2 4 5 Ω Ω 3 6 7 Ω Ω Ω 5.5 1 200 V μA μA 0.15 3.0 ICC ΔICC +0.8 ±1 ±1 ±1 4.4 Unit 0.001 Temperature range is: Version B: –40°C to +85°C. See Test Circuits section. 3 All typical values are at TA = 25°C, unless otherwise noted. 4 Guaranteed by design, not subject to production test. 5 The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 6 Propagation delay matching between channels is calculated from on-resistance matching of worst-case channel combinations and load capacitance. 7 This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute no significant ac or dc currents as they transition. 2 Rev. E | Page 3 of 12 ADG3257 VCC = 3.3 V ± 10%, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 3. 1 Parameter DC ELECTRICAL CHARACTERISTICS Input High Voltage Input Low Voltage Input Leakage Current Off State Leakage Current On State Leakage Current Maximum Pass Voltage 4 CAPACITANCE4 A Port Off Capacitance B Port Off Capacitance A, B Port On Capacitance Control Input Capacitance SWITCHING CHARACTERISTICS4 Propagation Delay A to B or B to A, tPD Propagation Delay Matching 6 Bus Enable Time BE to A or B Bus Disable Time BE to A or B Bus Select Time S to A or B Enable Disable Maximum Data Rate DIGITAL SWITCH On Resistance On-Resistance Matching POWER REQUIREMENTS VCC Quiescent Power Supply Current Increase in ICC per Input4, 7 Symbol Conditions 2 B Version Min Typ 3 Max VINH VINL II IOZ IOZ VP 0 ≤ VIN ≤ 3.6 V 0 ≤ A, B ≤ VCC 0 ≤ A, B ≤ VCC VIN = VCC = 3.3 V, IO = −5 μA CA OFF CB OFF CA, CB ON CIN f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz 7 5 11 4 tPHL, tPLH 5 VA = 0 V, CL = 50 pF VA = 0 V, CL = 50 pF CL = 50 pF, RL = 500 Ω CL = 50 pF, RL = 500 Ω 0.01 5.5 4.5 tPZH, tPZL tPHZ, tPLZ 2.0 −0.3 2.3 1 1 ±0.01 ±0.01 ±0.01 2.6 +0.8 ±1 ±1 ±1 2.8 Unit V V μA μA μA V pF pF pF pF 0.10 0.04 9 8.5 ns ns ns ns tSEL_EN tSEL_DIS CL = 50 pF, RL = 500 Ω CL = 50 pF, RL = 500 Ω VA = 2 V p-p 8 6 933 12 9 ns ns Mbps RON 2 4 5 7 8 ΔRON VA = 0 V, IO = 15 mA, 8 mA, TA = 25°C VA= 0 V, Io = 15 mA, 8 mA VA = 1 V, IO = 15 mA, 8 mA, TA = 25°C VA= 1 V, Io = 15 mA, 8 mA VA = 0 V, IO = 15 mA, 8 mA Ω Ω Ω Ω Ω ICC ΔICC Digital inputs = 0 V or VCC VCC = 3.3 V, one input at 3.0 V; others at VCC or GND 5.5 1 200 V μA μA 4 0.2 3.0 1 0.001 Temperature range is: Version B: −40°C to +85°C. See Test Circuits section. All typical values are at TA = 25°C, unless otherwise noted. 4 Guaranteed by design, not subject to production test. 5 The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 6 Propagation delay matching between channels is calculated from on-resistance matching of worst-case channel combinations and load capacitance. 7 This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute no significant ac or dc currents as they transition. 2 3 Rev. E | Page 4 of 12 ADG3257 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Parameter VCC to GND Digital Inputs to GND DC Input Voltage DC Output Current Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature QSOP Package θJA Thermal Impedance Lead Soldering Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) Soldering (Pb-Free) Reflow, Peak Temperature Time at Peak Temperature Rating −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +6 V 100 mA −40°C to +85°C −65°C to +150°C 150°C ESD CAUTION 149.97°C/W 300°C 220°C 260(+0/−5)°C 20 sec to 40 sec Rev. E | Page 5 of 12 ADG3257 S 1 16 VCC 1B1 2 15 BE 1B2 3 1A 4 ADG3257 14 TOP VIEW (Not to Scale) 4B1 13 4B2 2B1 5 12 4A 2B2 6 11 3B1 7 10 3B2 GND 8 2A 9 3A 02914-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2, 3, 5, 6, 10, 11, 13, 14 4, 7, 9, 12 8 15 16 Mnemonic S 1B1, 1B2, 2B1, 2B2, 3B2, 3B1, 4B2, 4B1 1A, 2A, 3A, 4A GND BE VCC Rev. E | Page 6 of 12 Description Port Select. Port B, Inputs or Outputs. Port A, Inputs or Outputs. Negative Power Supply. Output Enable (Active Low). Positive Power Supply. ADG3257 TYPICAL PERFORMANCE CHARACTERISTICS 20 20 VCC = 3V TA = 25°C 15 12 RON (Ω) RON (Ω) 16 VCC = 5.0V 10 +85°C 8 VCC = 4.5V 5 +25°C 4 0 1 2 3 4 0 5 0 0.5 1.0 1.5 2.0 2.5 3.0 VA/VB (V) VA/VB (V) Figure 6. On Resistance vs. Input Voltage for Different Temperatures Figure 3. On Resistance vs. Input Voltage 20 02914-006 0 –40°C 02914-003 VCC = 5.5V 10m TA = 25°C TA = 25°C 1m 16 100µ 12 CURRENT (A) RON (Ω) VCC = 3.0V 8 VCC = 2.7V VCC = 5V 10µ VCC = 3V 1µ 4 0 0.5 1.0 1.5 2.0 2.5 10n 0.1 3.0 VA/VB (V) 10 100 1k 10k Figure 7. ICC vs. Enable Frequency 20 5 VCC = 5V TA = 25°C VCC = 5.5V 4 OUTPUT VOLTAGE (V) 15 10 +85°C 5 +25°C 1 3 2 02914-005 1 –40°C 0 VCC = 5.0V VCC = 4.5V 2 3 4 0 5 VA/VB (V) 02914-008 RON (Ω) 1 FREQUENCY (kHz) Figure 4. On Resistance vs. Input Voltage 0 02914-007 0 100n 02914-004 VCC = 3.3V 0 1 2 3 4 INPUT VOLTAGE (V) Figure 8. Maximum Pass Voltage Figure 5. On Resistance vs. Input Voltage for Different Temperatures Rev. E | Page 7 of 12 5 ADG3257 3.6 TA = 25°C VCC = 3.6V VCC = 3.3V 2.0 VCC = 3.0V 02914-009 0 40mV/DIV 180ps/DIV 0 0.5 1.0 1.5 2.0 2.5 3.0 VCC = 5V VIN = 2V p-p 933MBPS 20dB ATTENUATION TA = 25°C 3.5 INPUT VOLTAGE (V) Figure 9. Maximum Pass Voltage 40mV/DIV 267ps/DIV VCC = 5V VIN = 2V p-p 622MBPS 20dB ATTENUATION TA = 25°C Figure 11. 933 Mbps Eye Diagram Figure 10. 622 Mbps Eye Diagram Rev. E | Page 8 of 12 02914-011 1.0 02914-010 OUTPUT VOLTAGE (V) 3.0 ADG3257 TEST CIRCUITS VCC 2 × VCC S1 Test tPLH, tPHL tPLZ, tPZL tPHZ, tPZH tSEL OPEN VIN PULSE GENERATOR1 RL VOUT GND DUT RL 1PULSE GENERATOR FOR ALL PULSES: t < 2.5ns, t < 2.5ns. F R 2C = INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES. L 3R IS THE TERMINATION RESISTOR; SHOULD BE EQUAL TO Z T OUT OF THE PULSE GENERATOR. Figure 12. Load Circuit Symbol RL ΔV CL VIH VT SWITCH INPUT 0V tPHL VOH OUTPUT VT VOL 02914-013 tPLH Figure 13. Propagation Delay DISABLE ENABLE CONTROL INPUTS VIH VT 0V tPZL tPLZ VCC VCC VT VOL + ΔV tPHZ tPZH VOH OUTPUT S1 @ 2VCC VOL VT 0V VOH – ΔV 0V 02914-014 OUTPUT S1 @ 2VCC LOW S1 Open 2 × VCC GND Open Table 7. Test Conditions 02914-012 CL2 RT3 Table 6. Switch S1 Condition Figure 14. Select, Enable, and Disable Times Rev. E | Page 9 of 12 VCC = 5 V ± 10% 500 300 50 VCC = 3.3 V ± 10% 500 300 50 Unit Ω mV pF ADG3257 APPLICATIONS INFORMATION MIXED VOLTAGE OPERATION, LEVEL TRANSLATION Bus switches can be used to provide a solution for mixed voltage systems where interfacing bidirectionally between 5 V and 3.3 V devices is required. To interface between 5 V and 3.3 V buses, an external diode is placed in series with the 5 V power supply as shown in Figure 15. Similarly, the device could be used to translate bidirectionally between 3.3 V to 2.5 V systems. In this case, there is no need for an external diode. The internal VTH drop is 1 V, so with a VCC = 3.3 V the bus switch limits the output voltage to VCC − 1 V = 2.3 V VCC = 5V VOUT 3.3V 3.3V SUPPLY 3.3V ADG3257 2.5V 2.5V 3.3V CPU/DSP/ MICROPROCESSOR/ MEMORY 5V MEMORY 5V I/O SWITCH INPUT 0V 3.3V VIN Figure 17. 3.3 V to 2.5 V Level Translation Using the ADG3257 Bus Switch 5V 3.3V 02914-015 3.3V 2.5V 02914-017 BE SWITCH OUTPUT 2.5V 3.3V MEMORY SWITCHING Figure 15. Level Translation Between 5 V and 3.3 V Devices The diode drops the internal gate voltage down to 4.3 V. The bus switch limits the voltage present on the output to VCC − External Diode Drop = VTH This quad bus switch may be used to allow switching between different memory banks, thus allowing additional memory and decreasing capacitive loading. Figure 18 illustrates the ADG3257 in such an application. Therefore, assuming a diode drop of 0.7 V and a VTH of 1 V, the output voltage is limited to 3.3 V with a logic high. SDRAM NO. 1 SDRAM NO. 2 VOUT 5V SUPPLY 3.3V SWITCH OUTPUT SDRAM NO. 7 5V VIN LOGIC Figure 16. Input Voltage to Output Voltage BE 02914-018 SWITCH INPUT 02914-016 0V SDRAM NO. 8 S Figure 18. Allows Additional Memory Modules Without Added Drive or Delay Rev. E | Page 10 of 12 ADG3257 OUTLINE DIMENSIONS 0.197 0.193 0.189 9 16 0.158 0.154 0.150 1 8 0.244 0.236 0.228 PIN 1 0.069 0.053 0.065 0.049 0.010 0.025 0.004 BSC COPLANARITY 0.004 0.012 0.008 SEATING PLANE 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137-AB Figure 19. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches ORDERING GUIDE Model ADG3257BRQ ADG3257BRQ-REEL ADG3257BRQ-REEL7 ADG3257BRQZ 1 ADG3257BRQZ-REEL1 ADG3257BRQZ-REEL71 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] 16-Lead Shrink Small Outline Package [QSOP] Z = RoHS Compliant Part. Rev. E | Page 11 of 12 Package Option RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 ADG3257 NOTES ©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02914-0-3/08(E) Rev. E | Page 12 of 12