ISSI IS62WV2568BLL-70H 256k x 8 low voltage, ultra low power cmos static ram Datasheet

IS62WV2568ALL
IS62WV2568BLL
ISSI
256K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
®
JUNE 2005
FEATURES
DESCRIPTION
• High-speed access time: 55ns, 70ns
The ISSI IS62WV2568ALL / IS62WV2568BLL are highspeed, 2M bit static RAMs organized as 256K words by 8
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields highperformance and low power consumption devices.
• CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
• TTL compatible interface levels
• Single power supply
– 1.65V--2.2V VCC (62WV2568ALL)
– 2.5V--3.6V VCC (62WV2568BLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial temperature available
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62WV2568ALL and IS62WV2568BLL are packaged
in the JEDEC standard 32-pin TSOP (TYPE I), sTSOP
(TYPE I), and 36-pin mini BGA.
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CS2
CS1
OE
CONTROL
CIRCUIT
WE
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
1
IS62WV2568ALL,
ISSI
IS62WV2568BLL
®
PIN DESCRIPTIONS
A0-A17
Address Inputs
CS1
Chip Enable 1 Input
CS2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
NC
No Connection
Vcc
Power
GND
Ground
PIN CONFIGURATION
36-pin mini BGA (B) (6mm x 8mm)
1
2
2
3
4
5
32-pin TSOP (TYPE I), sTSOP (TYPE I)
6
A
A0
A1
CS2
A3
A6
A8
B
I/O4
A2
WE
A4
A7
I/O0
C
I/O5
NC
A5
D
GND
Vcc
E
Vcc
GND
F
I/O6
G
I/O7
H
A9
I/O1
NC
A17
OE
CS1
A16
A15
I/O3
A10
A11
A12
A13
A14
I/O2
A11
A9
A8
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
IS62WV2568ALL,
ISSI
IS62WV2568BLL
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TSTG
PT
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
Value
–0.2 to Vcc+0.3
–65 to +150
1.0
Unit
V
°C
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
OPERATING RANGE (Vcc)
Range
Ambient Temperature
IS62WV2568ALL
0°C to +70°C
–40°C to +85°C
1.65V - 2.2V
1.65V - 2.2V
Commercial
Industrial
IS62WV2568BLL
2.5V - 3.6V
2.5V - 3.6V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Vcc
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = -0.1 mA
IOH = -1 mA
1.65-2.2V
2.5-3.6V
1.4
2.2
—
—
V
V
VOL
Output LOW Voltage
IOL = 0.1 mA
IOL = 2.1 mA
1.65-2.2V
2.5-3.6V
—
—
0.2
0.4
V
V
VIH
Input HIGH Voltage
1.65-2.2V
2.5-3.6V
1.4
2.2
VCC + 0.2
VCC + 0.3
V
V
VIL(1)
Input LOW Voltage
1.65-2.2V
2.5-3.6V
–0.2
–0.2
0.4
0.6
V
V
ILI
Input Leakage
GND ≤ VIN ≤ VCC
–1
1
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
–1
1
µA
Notes:
1. VIL (min.) = –1.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
3
IS62WV2568ALL,
ISSI
IS62WV2568BLL
®
CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
8
pF
VOUT = 0V
10
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
62WV2568ALL
(Unit)
62WV2568BLL
(Unit)
0.4V to Vcc-0.2V
5 ns
VREF
0.4V to Vcc-0.3V
5ns
VREF
See Figures 1 and 2
See Figures 1 and 2
1.65-2.2V
2.5V - 3.6V
R1(Ω)
3070
3070
R2(Ω)
3150
3150
VREF
0.9V
1.5V
VTM
1.8V
2.8V
AC TEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1
4
5 pF
Including
jig and
scope
R2
R2
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
IS62WV2568ALL,
ISSI
IS62WV2568BLL
®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
62WV2568ALL (1.65V - 2.2V)
Symbol Parameter
Test Conditions
ICC
Vcc Dynamic Operating
Supply Current
Operating Supply
Current
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
IOUT = 0 mA, f = fMAX
Ind.
VCC = Max.,
Com.
IOUT = 0 mA, f = 0
Ind.
VCC = Max.,
Com.
VIN = VIH or VIL
Ind.
CS1 = VIH , CS2 = VIL,
f = 1 MHZ
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
CS1 ≥ VCC – 0.2V,
CS2 ≤ 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
ICC1
ISB1
ISB2
Max.
70 ns
15
15
3
3
0.3
0.3
Unit
5
10
µA
Max.
55 ns
30
35
3
3
0.3
0.3
Max.
70 ns
25
30
3
3
0.3
0.3
Unit
10
10
10
10
µA
Com.
Ind.
mA
mA
mA
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
62WV2568BLL (2.5V - 3.6V)
Symbol Parameter
Test Conditions
ICC
Vcc Dynamic Operating
Supply Current
Operating Supply
Current
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
IOUT = 0 mA, f = fMAX
Ind.
VCC = Max.,
Com.
IOUT = 0 mA, f = 0
Ind.
VCC = Max.,
Com.
VIN = VIH or VIL
Ind.
CS1 = VIH , CS2 = VIL,
f = 1 MHZ
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
CS1 ≥ VCC – 0.2V,
CS2 ≤ 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
ICC1
ISB1
ISB2
Com.
Ind.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
mA
mA
mA
5
IS62WV2568ALL,
ISSI
IS62WV2568BLL
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
55 ns
Min.
Max.
70 ns
Min.
Max.
Unit
tRC
Read Cycle Time
55
—
70
—
ns
tAA
Address Access Time
—
55
—
70
ns
tOHA
Output Hold Time
10
—
10
—
ns
tACS1/tACS2
CS1/CS2 Access Time
—
55
—
70
ns
tDOE
OE Access Time
—
25
—
35
ns
tHZOE(2)
OE to High-Z Output
—
20
—
25
ns
OE to Low-Z Output
5
—
5
—
ns
(2)
tHZCS1/tHZCS2
CS1/CS2 to High-Z Output
0
20
0
25
ns
(2)
tLZCS1/tLZCS2
CS1/CS2 to Low-Z Output
10
—
10
—
ns
tLZOE(2)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH)
tRC
ADDRESS
tAA
tOHA
DOUT
6
PREVIOUS DATA VALID
tOHA
DATA VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
IS62WV2568ALL,
ISSI
IS62WV2568BLL
®
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
CS1
tHZOE
tLZOE
tACS1/tACS2
CS2
DOUT
tLZCS1/
tLZCS2
HIGH-Z
tHZCS
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1= VIL. CS2=WE=VIH.
3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
7
IS62WV2568ALL,
ISSI
IS62WV2568BLL
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
tWC
55 ns
Min.
Max.
Parameter
Write Cycle Time
tSCS1/tSCS2 CS1/CS2 to Write End
tAW
Address Setup Time to Write End
70 ns
Min. Max.
Unit
55
—
70
—
ns
45
—
60
—
ns
45
—
60
—
ns
tHA
tSA
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
tPWE
tSD
WE Pulse Width
40
—
50
—
ns
Data Setup to Write End
25
—
30
—
ns
tHD
tHZWE(3)
Data Hold from Write End
0
—
0
—
ns
WE LOW to High-Z Output
—
20
—
20
ns
tLZWE(3)
WE HIGH to Low-Z Output
5
—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go
inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
8
tHD
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
IS62WV2568ALL,
ISSI
IS62WV2568BLL
®
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
tHD
DATA-IN VALID
9
IS62WV2568ALL,
ISSI
IS62WV2568BLL
®
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Max.
Unit
VDR
Vcc for Data Retention
See Data Retention Waveform
1.0
3.6
V
IDR
Data Retention Current
Vcc = 1.0V, CS1/CS2 ≥ Vcc – 0.2V
—
10
µA
tSDR
Data Retention Setup Time
See Data Retention Waveform
0
—
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
—
ns
DATA RETENTION WAVEFORM (CS1
CS1 Controlled)
Data Retention Mode
tSDR
3.0V
2.2V
tRDR
VCC
VDR
CS1 ³ VCC
CS1
GND
- 0.2V
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
3.0
VCC
CS2
2.2V
tSDR
tRDR
VDR
0.4V
CS2 ≤ 0.2V
GND
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
IS62WV2568ALL,
ISSI
IS62WV2568BLL
®
PLASTIC sTSOP - 32 PINS
Package Code: H (Type 1)
A2
A
A1
1
N
E
b
e
D1
S
SEATING PLANE
D
L
α
C
PLASTIC sTSOP (H-TYPE 1)
MILLIMETERS
Symbol
Min.
INCHES
Max.
Min.
Max.
REF. STD
N0. Leads
32
A
—
1.25
—
0.049
A1
0.05
—
0.002
—
A2
0.95
1.05
0.037
0.041
b
0.17
0.23
0.007
0.009
C
0.142
0.158
0.0056
0.0082
D
13.2
13.6
0.520
0.535
D1
11.7
11.9
0.461
0.469
E
7.9
8.1
0.311
0.319
e
0.50
BSC
0.020
BSC
L
0.30
0.70
0.012
0.028
S
0.278
TYP.
0.0109
TYP.
α
0
0
0
5
0
0
1. Controlling dimension: millimeters, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include
mold flash protrusion and should be
measured from the bottom of the package.
4. Formed leads shall be planar with respect
to one another within 0.004 inches at the
seating plane.
50
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
Notes:
11
IS62WV2568ALL,
ISSI
IS62WV2568BLL
®
PLASTIC TSOP - 32 PINS
Package Code: T (Type 1)
1
E
H
N
D
SEATING PLANE
A
S
B
e
L
A1
α
C
PLASTIC TSOP (T-TYPE 1)
Notes:
MILLIMETERS
Symbol
Min.
INCHES
Max.
Min.
Max.
REF. STD
N0. Leads
32
A
—
1.20
—
0.047
A1
0.05
0.25
0.002
0.010
B
0.17
0.23
0.007
0.009
C
0.12
0.17
0.006
0.014
D
7.90
8.10
0.308
0.316
E
18.30
18.50
0.714
0.722
H
19.80
20.20
0.722
0.788
e
0.50
BSC
0.020
BSC
L
0.40
0.60
0.016
0.024
α
12
0
0
0
8
0
0
1. Controlling dimension: millimeters, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold
flash protrusion and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect
to one another within 0.004 inches at the
seating plane.
80
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
IS62WV2568ALL,
ISSI
IS62WV2568BLL
®
Mini Ball Grid Array
Package Code: B (36-pin) (6mm x 8mm, 8mm x 10 mm)
6
5
4
3
2
1
A
e
B
C
D
D
D1
E
F
G
H
e
E
E1
A2
A
A1
SEATING PLANE
Notes:
1.
2.
3.
4.
Controlling dimension: millimeters, unless otherwise specified.
BSC = Basic lead spacing between centers.
Dimensions D1 and E do not include mold flash protrusion and should be measured from the bottom of the package.
Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
Mini Ball Grid Array - 8mm x 10mm
Mini Ball Grid Array - 6mm x 8mm
Sym.
MILLIMETER
MILLIMETERS
INCHES
Min. Typ. Max.
Min. Typ Max.
Min. Typ. Max.
N0.
Leads
N0.
Leads
36
1.00
—
1.35
.039
—
36
.053
A
1.00
—
1.35
.039
—
.053
0.24
—
0.030
.009
—
.011
—
—
.023
—
—
.393
.397
A1
0.24
—
.030
.009
—
.011
A1
A2
.600
—
—
.023
—
—
A2
.600
D
7.90 8.00
8.10
.311
.314
.318
D
9.90 10.00 10.10
D1
E
Min. Typ Max.
REF.
STD
REF.
STD
A
Sym.
INCHES
5.25BSC
5.90 6.00
D1
.206BSC
6.10
.232
.236
.240
E
.389
5.25BSC
7.90
8.00
.206BSC
8.10
.311
.314
E1
3.75BSC
.147BSC
E1
3.75BSC
.147BSC
e
0.75BSC
.029BSC
e
0.75BSC
.029BSC
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
.318
13
IS62WV2568ALL,
IS62WV2568BLL
ISSI
®
ORDERING INFORMATION
IS62WV2568ALL (1.65V - 2.2V)
Commercial Range: 0°C to +70°C
Speed (ns)
70
Order Part No.
Package
IS62WV2568ALL-70T
TSOP, TYPE I,
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
70
IS62WV2568ALL-70TI
TSOP, TYPE I
70
IS62WV2568ALL-70BI
mini BGA (6mm x 8mm)
70
IS62WV2568ALL-70HI
sTSOP, TYPE I
IS62WV2568BLL (2.5V - 3.6V)
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part No.
Package
70
IS62WV2568BLL-70T
TSOP, TYPE I
70
IS62WV2568BLL-70B
mini BGA (6mm x 8mm)
70
IS62WV2568BLL-70H
sTSOP, TYPE I
Industrial Range: –40°C to +85°C
Speed (ns)
14
Order Part No.
Package
55
IS62WV2568BLL-55TI
TSOP, TYPE I
55
IS62WV2568BLL-55TLI
TSOP, TYPE I, Lead-free
55
IS62WV2568BLL-55BI
mini BGA (6mm x 8mm)
55
IS62WV2568BLL-55BLI
mini BGA (6mm x 8mm), Lead-free
55
IS62WV2568BLL-55HI
sTSOP, TYPE I
55
IS62WV2568BLL-55HLI
sTSOP, TYPE I, Lead-free
70
IS62WV2568BLL-70TI
TSOP, TYPE I
70
IS62WV2568BLL-70BI
mini BGA (6mm x 8mm)
70
IS62WV2568BLL-70HI
sTSOP, TYPE I
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/20/05
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