Freescale MCIMX356AVM5B Multimedia applications processor for automotive product Datasheet

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MCIMX35SR2AEC
Rev. 1, 12/2008
MCIMX35
MCIMX35 (i.MX35)
Multimedia
Applications
Processor for
Automotive Products
Package Information
Plastic package
Case 5284 17 x 17 mm, 0.8 mm Pitch
Ordering Information
See Table 1 on page 3 for ordering information.
1
1
Introduction
The i.MX35 Auto Application Processor family is
designed for automotive infotainment and
navigation applications. They are AECQ100
Grade 3 qualified and rated for ambient operating
temperatures up to 85°C.
2
3
4
The i.MX35 multimedia applications processor
represents the next step in low-power,
high-performance application processors.
Based on an ARM11 microprocessor core running
at up to 532 Mhz, the device offers specific features
and optimized system cost for the target
applications.
• Audio connectivity and telematics
— Compressed Audio playback from
storage devices (CD, USB, HDD or SD
card)
— PlayFromDevice (1-wire and 2-wire
support) for portable media players
— iPod/iPhone control and playback
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional Description and Application Information . . . . . 5
2.1 Application Processor Domain Overview. . . . . . . . . 5
2.2 Shared Domain Overview . . . . . . . . . . . . . . . . . . . . 6
2.3 Advanced Power Management Overview . . . . . . . . 6
2.4 ARM11 Microprocessor Core . . . . . . . . . . . . . . . . . 6
2.5 Module Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Descriptions: Special Function Related Pins . . . . 12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 i.MX35 Chip-Level Conditions . . . . . . . . . . . . . . . . 12
4.2 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . 17
4.5 I/O Pad DC Electrical Characteristics . . . . . . . . . . 17
4.6 I/O Pad AC Electrical Characteristics . . . . . . . . . . 22
4.7 Module-Level AC Electrical Specifications. . . . . . . 28
Package Information and Pinout . . . . . . . . . . . . . . . . . . 128
5.1 MAPBGA Production Package 1568-01, 17 x 17 mm,
0.8 Pitch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.2 Production Package Outline Drawing . . . . . . . . . 129
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . 136
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Preliminary—Subject to Change Without Notice
•
— High-speed CD ripping to USB, SD/MMC or HDD for virtual CD changer
— Audio processing for hands-free telephony: Bluetooth, AEC/NS, Microphone beam forming,
and so on.
— Speech recognition
A/V Connectivity and Navigation
— Includes audio connectivity and telematics features
— Map display & route calculation
— QVGA video decode, WVGA video display
— Sophisticated graphical user interface
The i.MX35 processor takes advantage of the ARM1136JF-S™ core running at 532 MHz that is boosted
by a multi-level cache system, and features peripheral devices such as an autonomous image processing
unit, a vector floating point (VFP11) co-processor, and a RISC-based DMA controller.
The i.MX35 supports connections to various types of external memories, such as SDRAM, Mobile DDR
and DDR2, SLC and MLC NAND Flash, NOR Flash and SRAM. The device can be connected to a variety
of external devices such as high-speed USB2.0 OTG, ATA, MMC/SDIO, and Compact Flash.
1.1
Features
The i.MX35 is designed for automotive infotainment video-enabled applications. The i.MX35 provides
low-power solutions for high-performance demanding multimedia and graphics applications.
The MCIMX35 is based on the ARM1136 Platform, which has the following features:
• ARM1136JF-S processor
• 16-Kbyte L1 instruction cache
• 16-Kbyte L1 data cache
• 128-Kbyte L2 cache
• 128 Kbytes of internal SRAM
• Vector floating point unit (VFP11)
To boost multimedia performance, the following hardware accelerators are integrated:
• Image processing unit (IPU)
• OpenVG 1.1 Graphics Processing Unit (GPU) (not available for the MCIMX351)
The MCIMX35 provides the following interfaces to external devices (some of them are muxed and not
available simultaneously):
• 2 controller area network (CAN) interfaces
• 2 SDIO/MMC interfaces, 1 SDIO/CE-ATA interface (CE-ATA is not available for the
MCIMX351)
• 32-bit mobile DDR, DDR2 (4-bank architecture), and SDRAM (up to 133 MHz)
• 2 configurable serial peripheral interfaces (CSPI) (up to 52 Mbps each)
• Enhanced serial audio interface (ESAI)
• 2 synchronous serial interfaces (SSI)
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Ethernet MAC 10/100 Mbps
1 USB 2.0 Host with ULPI interface or internal full-speed PHY. Up to 480Mbps if external HS
PHY is used.
1 USB 2.0 OTG (up to 480 Mbps) controller with internal high-speed OTG PHY
Flash Controller—MLC/SLC NAND and NOR
GPIO with interrupt capabilities
3 I2C modules (up to 400 Kbytes each)
JTAG
Key pad port
Media local bus (MLB) interface
Asynchronous sample rate converter (ASRC)
1-Wire
Parallel camera sensor (4/8/10/16-bit data port for video color models: YCC, YUV, 30 MPixels/s)
Parallel display (primary up to 24-bit, 1024 x 1024)
Parallel ATA (up to 66 Mbytes)
PWM
SPDIF transceiver
3 UART (up to 4.0 Mbps each)
1.2
Ordering Information
Table 1 provides the ordering information for the i.MX35 processor.
Table 1. Ordering Information
Description
Part Number
Silicon
Revision
Type
Package1
Speed
Operating
Temperature
Range (°C)
i.MX351
MCIMX351AVM4B
2.0
Automotive
5284
400 MHz
-40 to 85
i.MX351
MCIMX351AVM5B
2.0
Automotive
5284
532 MHz
-40 to 85
i.MX355
MCIMX355AVM4B
2.0
Automotive
5284
400 MHz
-40 to 85
i.MX355
MCIMX355AVM5B
2.0
Automotive
5284
532 MHz
-40 to 85
i.MX356
MCIMX356AVM4B
2.0
Automotive
5284
400 MHz
-40 to 85
i.MX356
MCIMX356AVM5B
2.0
Automotive
5284
532 MHz
-40 to 85
1
Case 5284 is RoHS-compliant, lead-free, MSL = 3, 1. See application note AN330 for details.
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Table 2 shows the functional differences between the different parts in the i.MX35 family.
Table 2. Part Descriptions
Module
MCIMX351
MCIMX355
MCIMX356
I2C (3)
yes
yes
yes
CSPI (2)
yes
yes
yes
SSI/I2S (2)
yes
yes
yes
ESAI
yes
yes
yes
SPDIF I/O
yes
yes
yes
USB HS Host
yes
yes
yes
USB OTG
yes
yes
yes
FlexCAN (2)
yes
yes
yes
MLB
yes
yes
yes
Ethernet
yes
yes
yes
1-Wire
yes
yes
yes
KPP
yes
yes
yes
SDIO/MMC (2)
yes
yes
yes
SDIO/Memory Stick
yes
yes
yes
External Memory Controller (EMC)
yes
yes
yes
JTAG
yes
yes
yes
PATA
—
yes
yes
CE-ATA
—
yes
yes
Image Processing Unit (IPU) (inversion and rotation, pre- and
post-processing, camera interface, blending, display controller)
—
yes
yes
Open VG graphics acceleration (GPU)
—
—
yes
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1.3
Block Diagram
Figure 1 shows the i.MX35 simplified interface block diagram.
NOR
Flash/
PSRAM
DDR2/SDDR
RAM
NAND
Flash
Camera
Sensor
External Memory
Interface (EMI)
Smart
DMA
LCD Display 1 External Graphics
Accelerator
LCD Display 2
Image
Processing Unit
(IPU)
ARM11
Platform
ARM1136JF-S
SPBA
VFP
ARM1136 Platform Peripherals
SSI
HS USBOTG
HS USBOTGPHY
AUDMUX
HS USBHost
FS USBPHY
L1 I/D cache
Peripherals
MSHC
ESAI
SPDIF
SSI
ASRC
L2 cache
I2C(3)
AVIC
UART(2)
MAX
CSPI
AIPS (2)
eSDHC(3)
ETM
UART
CSPI
ATA
GPU 2D
Internal
Memory
FEC
CAN(2)
ECT
MLB
IOMUX
IIM
RTICv3
GPIO(3)
RNGC
EPIT
SCC
PWM
Timers
RTC
WDOG
OWIRE
GPT
KPP
3 FuseBox
Audio/Power
Management
JTAG
Bluetooth
MMC/SDIO
or WLAN
Keypad
Connectivity
Access
Figure 1. i.MX35 Simplified Interface Block Diagram
2
Functional Description and Application Information
The MCIMX35 consists of the following major subsystems:
• ARM1136 Platform—AP domain
• SDMA Platform and EMI—Shared domain
2.1
Application Processor Domain Overview
The applications processor (AP) and its domain are responsible for running the operating system and
applications software, providing the user interface, and supplying access to integrated and external
peripherals. The AP domain is built around an ARM1136JF-S core with 16-Kbyte instruction and
16-Kbyte data L1 caches, an MMU, a 128-Kbyte L2 cache, a multiported crossbar switch, and advanced
debug and trace interfaces.
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The ARM11 core is intended to operate at a maximum frequency of 532 MHz to support the required
multimedia use cases. Furthermore, an Image Processing Unit (IPU) is integrated into the AP domain to
offload the ARM11 core from performing functions such as color space conversion, image rotation and
scaling, graphics overlay, and pre- and post-processing.
Peripheral functionality belonging to the AP domain include the user interface, connectivity, display,
security, and memory interfaces and 128 Kbytes of multipurpose SRAM.
2.2
Shared Domain Overview
The shared domain is composed of the shared peripherals, a Smart DMA Engine (SDMA) and a number
of miscellaneous modules. For maximum flexibility, some peripherals are directly accessible by the
SDMA engine.
The MCIMX35 has a hierarchical memory architecture including L1 caches and unified L2 cache. This
reduces the bandwidth demands for the external bus and external memory. The external memory
subsystem supports a flexible external memory system, including support for SDRAM (SDR, DDR2 and
Mobile DDR) and NAND Flash.
2.3
Advanced Power Management Overview
To address the continuing need to reduce power consumption, the following techniques are incorporated
in the MCIMX35:
• Clock gating
• Power gating
• Power optimized synthesis
• Well biasing
The insertion of gating into the clock paths allows unused portions of the chip to be disabled. Since static
CMOS logic consumes only leakage power, significant power savings can be realized.
“Well biasing” is applying a voltage that is greater than Vdd to the nwells and lower than Vss to the pwells.
The effect of applying this well back bias voltage reduces the subthreshold channel leakage. For the 90-nm
digital process, it is estimated that the subthreshold leakage is reduced by a factor of ten over the nominal
leakage. Additionally, the supply voltage for internal logic can be reduced from 1.4 V to 1.22 V.
2.4
ARM11 Microprocessor Core
The CPU of the i.MX35 is the ARM1136JF-S core, based on the ARM v6 architecture. This core supports
the ARM Thumb® instruction sets, features Jazelle® technology (which enables direct execution of Java
byte codes), and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit
registers.
The ARM1136JF-S processor core features are as follows:
• Integer unit with integral EmbeddedICE™ logic
• Eight-stage pipeline
• Branch prediction with return stack
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•
Low-interrupt latency
Instruction and data memory management units (MMUs), managed using micro TLB structures
backed by a unified main TLB
Instruction and data L1 caches, including a non-blocking data cache with Hit-Under-Miss
Virtually indexed/physically addressed L1 caches
64-bit interface to both L1 caches
Write buffer (bypassable)
High-speed Advanced Micro Bus Architecture (AMBA)™ L2 interface
Vector Floating Point co-processor (VFP) for 3D graphics and other floating-point applications’
hardware acceleration
ETM™ and JTAG-based debug support
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Table 3 summarizes information about the i.MX35 core.
Table 3. i.MX35 Core
Core
Acronym
ARM11 or
ARM1136
2.5
Core
Name
ARM1136
Platform
Brief Description
Integrated Memory
Includes
The ARM1136™ Platform consists of the ARM1136JF-S core, the ETM
real-time debug modules, a 6 x 5 multi-layer AHB crossbar switch (MAX), and
a Vector Floating Processor (VFP).
The i.MX35 provides a high-performance ARM11 microprocessor core and
highly integrated system functions. The ARM Application Processor (AP) and
other subsystems address the needs of the personal, wireless, and portable
product market with integrated peripherals, advanced processor core, and
power management capabilities.
• 16-Kbyte
instruction cache
• 16-Kbyte data
cache
• 128-Kbyte L2
cache
• 32-Kbyte ROM
• 128-Kbyte RAM
Module Inventory
Table 4 shows an alphabetical listing of the modules in the MCIMX35. For extended descriptions of the
modules, see the MCIMX35 reference manual.
Table 4. Digital and Analog Modules
Block
Mnemonic
1-WIRE
ASRC
ATA
Block Name
Domain 1
Subsystem
Brief Description
1-Wire
interface
ARM
ARM1136
platform
peripherals
1-Wire provides the communication line to a 1-Kbit Add-Only
Memory. The interface can send or receive 1 bit at a time.
Asynchronous
sample rate
converter
SDMA
Connectivity
peripherals
The ASRC is designed to convert the sampling rate of a signal
associated to an input clock into a signal associated to a different
output clock. It supports a concurrent sample rate conversion of
about –120dB THD+N. The sample rate conversion of each channel
is associated to a pair of incoming and outgoing sampling rates.
ATA module
SDMA
Connectivity
peripherals
The ATA block is an AT attachment host interface. Its main use is to
interface with IDE hard disk drives and ATAPI optical disk drives. It
interfaces with the ATA device over a number of ATA signals.
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Table 4. Digital and Analog Modules (continued)
Block
Mnemonic
Block Name
Domain 1
Subsystem
Brief Description
AUDMUX
Digital audio
mux
ARM
Multimedia
peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (SSIs) and
peripheral serial interfaces (audio codecs). The AUDMUX has two
sets of interfaces: internal ports to on-chip peripherals and external
ports to off-chip audio devices. Data is routed by configuring the
appropriate internal and external ports.
CAN(2)
CAN module
ARM
Connectivity
peripherals
The CAN protocol is primarily designed to be used as a vehicle serial
data bus running at 1 Mbps.
CCM
Clock control
module
ARM
Clocks
This block generates all clocks for the peripherals in the SDMA
platform. The CCM also manages ARM1136 platform low-power
modes (WAIT, STOP), disabling peripheral clocks appropriately for
power conservation, and provides alternate clock sources for the
ARM1136 and SDMA platforms.
CSPI(2)
Configurable
serial
peripheral
interface
SDMA,
ARM
Connectivity
peripherals
This module is a serial interface equipped with data FIFOs (first in
first out); each master/slave-configurable SPI module is capable of
interfacing to both serial port interface master and slave devices. The
CSPI ready (SPI_RDY) and slave select (SS) control signals enable
fast data communication with fewer software interrupts.
ECT
Embedded
cross trigger
SDMA,
ARM
Debug
ECT (embedded cross trigger) is an IP for real-time debug purposes.
It is a programmable matrix allowing several subsystems to interact
with each other. ECT receives signals required for debugging
purposes (from cores, peripherals, buses, external inputs, and so on)
and propagates them (propagation programmed through software) to
the different debug resources available within the SoC.
EMI
External
memory
interface
SDMA
External
memory
interface
The EMI module provides access to external memory for the ARM
and other masters. It is composed of the following main submodules:
M3IF—provides arbitration between multiple masters requesting
access to the external memory.
SDRAM CTRL—interfaces to mDDR, DDR2 (4-bank architecture
type), and SDR interfaces.
NANDFC—provides an interface to NAND Flash memories.
WEIM—interfaces to NOR Flash and PSRAM.
Enhanced
periodic
interrupt timer
ARM
Timer
peripherals
Each EPIT is a 32-bit “set-and-forget” timer that starts counting after
the EPIT is enabled by software. It is capable of providing precise
interrupts at regular intervals with minimal processor intervention. It
has a 12-bit prescaler to adjust the input clock frequency to the
required time setting for the interrupts, and the counter value can be
programmed on the fly.
Enhanced
serial audio
interface
SDMA
Connectivity
peripherals
The enhanced serial audio interface (ESAI) provides a full-duplex
serial port for serial communication with a variety of serial devices,
including industry-standard codecs, SPDIF transceivers, and other
DSPs. The ESAI consists of independent transmitter and receiver
sections, each section with its own clock generator.
EPIT(2)
ESAI
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Table 4. Digital and Analog Modules (continued)
Block
Mnemonic
eSDHCv2
(3)
FEC
GPIO(3)
Block Name
Domain 1
Subsystem
Brief Description
Enhanced
secure digital
host controller
ARM
Connectivity
peripherals
The eSDHCv2 consists of four main modules: CE-ATA, MMC, SD
and SDIO. CE-ATA is a hard drive interface that is optimized for
embedded applications of storage. The multi-media card (MMC) is a
universal, low-cost, data storage and communication media to
applications such as electronic toys, organizers, PDAs, and smart
phones. The secure digital (SD) card is an evolution of MMC and is
specifically designed to meet the security, capacity, performance,
and environment requirements inherent in emerging audio and video
consumer electronic devices. SD cards are categorized into Memory
and I/O. A memory card enables a copyright protection mechanism
that complies with the SDMI security standard. SDIO cards provide
high-speed data I/O (such as wireless LAN via SDIO interface) with
low power consumption.
Note: CE-ATA is not available for the MCIMX351.
Ethernet
SDMA
Connectivity
peripherals
The Ethernet media access controller (MAC) is designed to support
both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external
transceiver interface and transceiver function are required to
complete the interface to the media
General
purpose I/O
modules
ARM
Pins
Used for general purpose input/output to external ICs. Each GPIO
module supports 32 bits of I/O.
GPT
General
ARM
purpose timers
Timer
peripherals
Each GPT is a 32-bit free-running or set-and-forget mode timer with
a programmable prescaler and compare and capture registers. A
timer counter value can be captured using an external event and can
be configured to trigger a capture event on either the leading or
trailing edges of an input pulse. When the timer is configured to
operate in set-and-forget mode, it is capable of providing precise
interrupts at regular intervals with minimal processor intervention.
The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either on
an external clock or on an internal clock.
GPU2D
ARM
Graphics
processing unit
2Dv1
Multimedia
peripherals
This module accelerates OpenVG and GDI graphics.
Note: Not available for the MCIMX351.
I2C module
ARM1136
platform
peripherals
Inter-integrated circuit (I2C) is an industry-standard, bidirectional
serial bus that provides a simple, efficient method of data exchange,
minimizing the interconnection between devices. I2C is suitable for
applications requiring occasional communications over a short
distance among many devices. The interface operates at up to
100 kbps with maximum bus loading and timing. The I2C system is a
true multiple-master bus, with arbitration and collision detection that
prevent data corruption if multiple devices attempt to control the bus
simultaneously. This feature supports complex applications with
multiprocessor control and can be used for rapid testing and
alignment of end products through external connections to an
assembly-line computer.
I2C(3)
ARM
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Table 4. Digital and Analog Modules (continued)
Block
Mnemonic
IIM
Block Name
IC
identification
module
Domain 1
ARM
Subsystem
Brief Description
Security
modules
The IIM provides the primary user-visible mechanism for interfacing
with on-chip fuse elements. Among the uses for the fuses are unique
chip identifiers, mask revision numbers, cryptographic keys, and
various control signals requiring a fixed value.
IOMUX
ARM
External
signals and pin
multiplexing
Pins
Each I/O multiplexer provides a flexible, scalable multiplexing
solution with the following features:
Up to eight output sources multiplexed per pin
Up to four destinations for each input pin
Unselected input paths held at constant levels for reduced power
consumption
IPUv1
Image
ARM
processing unit
Multimedia
peripherals
The IPU supports video and graphics processing functions. It also
provides the interface for image sensors and displays. The IPU
performs the following main functions:
Preprocessing of data from the sensor or from the external system
memory
Postprocessing of data from the external system memory
Post-filtering of data from the system memory with support of the
MPEG-4 (both deblocking and deringing) and H.264 post-filtering
algorithms
Displaying video and graphics on a synchronous (dumb or
memory-less) display
Displaying video and graphics on an asynchronous (smart) display
Transferring data between IPU sub-modules and to/from the system
memory with flexible pixel reformatting
KPP
Keypad port
ARM
Connectivity
peripherals
Can be used for either keypad matrix scanning or general purpose
I/O.
MLB
Media local
bus
ARM
Connectivity
peripherals
The MLB is designed to interface to an automotive MOST ring.
OSCAUD
OSC audio
reference
oscillator
Analog
Clock
The OSCAUDIO oscillator provides a stable frequency reference for
the PLLs. This oscillator is designed to work in conjunction with an
external 24.576-MHz crystal.
OSC24M
OSC24M—24- Analog
MHz reference
oscillator
Clock
The signal from the external 24-MHz crystal is the source of the
CLK24M signal fed into USB PHY as the reference clock and to the
real time clock (RTC).
MPLL
PPLL
Digital
phase-locked
loops
SDMA
Clocks
DPLLs are used to generate the clocks:
MCU PLL (MPLL)—programmable
Peripheral PLL (PPLL)—programmable
PWM
Pulse-width
modulator
ARM
ARM1136
platform
peripherals
The pulse-width modulator (PWM) is optimized to generate sound
from stored sample audio images; it can also generate tones.
RTC
Real-time
clock
ARM
Clocks
Provides the ARM1136 platform with a clock function (days, hours,
minutes, seconds) and includes alarm, sampling timer, and minute
stopwatch capabilities.
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Table 4. Digital and Analog Modules (continued)
Block
Mnemonic
SDMA
1
Block Name
Domain 1
Subsystem
Brief Description
Smart DMA
engine
SDMA
System
controls
The SDMA provides DMA capabilities inside the processor. It is a
shared module that implements 32 DMA channels and has an
interface to connect to the ARM1136 platform subsystem, EMI
interface, and the peripherals.
SJC
Secure JTAG
controller
ARM
Pins
The secure JTAG controller (SJC) provides debug and test control
with maximum security.
SPBA
SDMA
peripheral bus
arbiter
SDMA
System
controls
The SPBA controls access to the SDMA peripherals. It supports
shared peripheral ownership and access rights to an owned
peripheral.
S/PDIF
Serial audio
interface
SDMA
Connectivity
peripherals
Sony/Philips digital transceiver interface
SSI(2)
Synchronous
SDMA,
serial interface ARM(2)
Connectivity
peripherals
The SSI is a full-duplex serial port that allows the processor
connected to it to communicate with a variety of serial protocols,
including the Freescale Semiconductor SPI standard and the I2C
sound (I2S) bus standard. The SSIs interface to the AUDMUX for
flexible audio routing.
Connectivity
peripherals
Each UART provides serial communication capability with external
devices through an RS-232 cable using the standard RS-232
non-return-to-zero (NRZ) encoding format. Each module transmits
and receives characters containing either 7 or 8 bits
(program-selectable). Each UART can also provide low-speed IrDA
compatibility through the use of external circuitry that converts
infrared signals to electrical signals (for reception) or transforms
electrical signals to signals that drive an infrared LED (for
transmission).
ARM(UA
RT1,2)
SDMA(U
ART3)
UART(3)
Universal
asynchronous
receiver/trans
mitters
USBOH
High-speed
SDMA
USB on-the-go
Connectivity
peripherals
The USB module provides high performance USB on-the-go (OTG)
functionality (up to 480 Mbps), compliant with the USB 2.0
specification, the OTG supplement, and the ULPI 1.0 low pin count
specification. The module has DMA capabilities handling data
transfer between internal buffers and system memory.
WDOG
Watchdog
modules
Timer
peripherals
Each module protects against system failures by providing a method
of escaping from unexpected events or programming errors. Once
activated, the timer must be serviced by software on a periodic basis.
If servicing does not take place, the watchdog times out and then
either asserts a system reset signal or an interrupt request signal,
depending on the software configuration.
ARM
ARM = ARM1136 platform, SDMA = SDMA platform
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3
Signal Descriptions: Special Function Related Pins
Some special functional requirements are supported in the MCIMX35 device. The details about these
special functions and the corresponding pad names are listed in Table 5.
Table 5. Special Function Related Pins
Function Name
Pad Name
Mux Mode
EXT_ARMCLK
ALT0
External clock input for ARM clock.
External Peripheral Clock
I2C1_CLK
ALT6
External peripheral clock source.
External 32-kHz Clock
CAPTURE
ALT4
CSPI1_SS1
ALT2
External clock input of 32 kHz, used when the internal
24M Oscillator is powered off, which could be
configured either from CAPTURE or CSPI1_SS1.
CLKO
ALT0
Clock-out pin from CCM, clock source is controllable
and can also be used for debug.
GPIO1_0
ALT1
TX1
ALT1
PMIC power-ready signal, which can be configured
either from GPIO1_0 or TX1.
GPIO1_1
ALT6
External ARM Clock
Clock Out
Power Ready
Tamper Detect
4
Detailed Description
Tamper-detect logic is used to issue a security
violation. This logic is activated if the tamper-detect
input is asserted. Tamper-detect logic is enabled by the
bit of IOMUXC_GPRA[2]. After enabling the logic, it is
impossible to disable it until the next reset.
Electrical Characteristics
The following sections provide the device-level and module-level electrical characteristics for the i.MX35
processor.
4.1
i.MX35 Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference
to the individual tables and sections.
Table 6. i.MX35 Chip-Level Conditions
Characteristics
Table / Location
Absolute Maximum Ratings
Table 7 on page 13
MCIMX35 Operating Ranges
Table 8 on page 13
Interface Frequency
Table 9 on page 14
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CAUTION
Stresses beyond those listed in Table 7, "Absolute Maximum Ratings," on
page 13 may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions
beyond those indicated in Table 8, "MCIMX35 Operating Ranges," on page
13 is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
Table 7. Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Supply Voltage (Core)
VDDmax1
–0.5
1.47
V
Supply Voltage (I/O)
NVCCmax
–0.5
3.6
V
Input Voltage Range
VImax
–0.5
3.6
Storage Temperature
Tstorage
ESD Damage Immunity:
–40
125
V
o
C
Vesd
V
Human Body Model (HBM)
—
20002
Machine Model (MM)
—
200
Charge Device Model (CDM)
—
5003
1
VDD is also known as QVCC.
HBM ESD classification level according to the AEC-Q100-002 standard.
3
Corner pins max. 750 V.
2
4.1.1
MCIMX35 Operating Ranges
Table 8 provides the recommended operating ranges. The term NVCC in this section refers to the
associated supply rail of an input or output.
Table 8. MCIMX35 Operating Ranges
Symbol
VDD
Parameter
Min. Typical Max. Units
Core Operating Voltage
0 < fARM < 400 MHz
1.22
—
1.47
V
Core Operating Voltage
0 < fARM < 532MHz
1.33
—
1.47
V
State Retention Voltage
1
—
—
V
NVCC_EMI1,2,3
EMI1
1.7
—
3.6
V
NVCC_CRM
WTDG, Timer, CCM, GPIO, CSPI1
1.75
—
3.6
V
NVCC_NANDF
NANDF
1.75
—
3.6
V
NVCC_ATA
ATA, USB generic
1.75
—
3.6
V
NVCC_SDIO
eSDHC1
1.75
—
3.6
V
NVCC_CSI
CSI, SDIO2
1.75
—
3.6
V
NVCC_JTAG
JTAG
1.75
—
3.6
V
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Table 8. MCIMX35 Operating Ranges (continued)
Symbol
Parameter
Min. Typical Max. Units
NVCC_LCDC
LCDC, TTM, I2C1
1.75
—
3.6
V
NVCC_MISC
I2Sx2,ESAI, I2C2, UART2, UART1, FEC
1.75
—
3.6
V
NVCC_MLB2
MLB
1.75
—
3.6
V
PHY1_VDDA
USB OTG PHY
3.17
3.3
3.43
V
USBPHY1_VDDA_BIAS
USB OTG PHY
3.17
3.3
3.43
V
USBPHY1_UPLLVDD
USB OTG PHY
3.17
3.3
3.43
V
PHY2_VDD
USB HOST PHY
3.0
3.3
3.6
V
OSC24M_VDD
OSC24M
3.0
3.3
3.6
V
OSC_AUDIO_VDD
OSC_AUDIO
3.0
3.3
3.6
V
MVDD
MPLL
1.4
—
1.65
V
PVDD
PPLL
1.4
—
1.65
V
FUSE_VDD3
Fusebox program supply voltage
3.0
3.6
3.6
V
TA
Operating Ambient Temperature Range
–40
—
85
oC
TJ
Junction Temperature Range
–40
—
105
oC
1
EMI I/O interface power supply should be set up according to external memory. For example, if using SDRAM
then NVCC_EMI1,2,3 should all be set at 3.3 V (typ.). If using MDDR or DDR2, NVC_EMI1,2,3 must be set at
1.8 V (typ.).
2 MLB interface I/O pads can be programmed to function as GPIO by setting NVCC_MLB to 1.8 or 3.3 V, but if
used as MLB pads, NVCC_MLB must be set to 2.5 V in order to be compliant with external MOST devices.
NVCC_MLB may be left floating.
3 The Fusebox read supply is connected to supply of the full speed USBPHY. FUSE_VDD is only used for
programming. It is recommended that FUSE_VDD be connected to ground when not being used for
programming.
4.1.2
Interface Frequency Limits
Table 9 provides information on interface frequency limits.
Table 9. Interface Frequency
ID
1
Parameter
JTAG TCK Frequency
Symbol
Min.
Typ.
Max.
Units
fJTAG
DC
5
10
MHz
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4.2
Power Modes
Table 10 provides descriptions of the power modes of the MCIMX35 processor.
Table 10. MCIMX35 Power Modes
Power
Mode
Wait
Doze
Stop
Description
QVCC(ARM/L2
Peripheral)
MVDD/PVDD
OSC24M_VDD
OSC_AUDO_VDD
Typ.
Max.
Typ.
Max.
Typ.
Max.
QVCC1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is active.
L2 cache is kept powered.
MCU PLL is on (400 MHz)
PER PLL is off (can be configured)
(default: 300 MHz)
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured).
.RNGC internal osc is off
TBD
TBD
TBD
TBD
TBD
TBD
QVCC1,2,3,4 = 1.1v (min.)
ARM is in wait for interrupt mode.
MAX is halted.
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is on(400 MHz)
PER PLL is off (can be configured).
(300Mhz).
Module clocks are gated off (can be
configured by CGR register).
OSC 24M is ON.
OSC audio is off (can be configured)
.RNGC internal osc is off
TBD
TBD
TBD
TBD
TBD
TBD
790 µA
TBD
40 µA
TBD
1 mA
TBD
QVCC1,2,3,4 = 1.1v (min.)
.Arm is in wait for interrupt mode.
.MAX is halted
.L2 cache is kept powered.
.L2 cache control logic off.
.AWB enabled.
.MCU PLL is off.
.PER PLL is off.
.All clocks are gated off.
.OSC 24MHz is on
.OSC audio is off
.RNGC internal osc is off
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Table 10. MCIMX35 Power Modes (continued)
Power
Mode
Static
Description
QVCC1,2,3,4 = 1.0v
.Arm is in wait for interrupt mode.
.MAX is halted
.L2 cache is kept powered.
.L2 cache control logic off.
.AWB enabled.
.MCU PLL is off.
.PER PLL is off.
.All clocks are gated off.
.OSC 24MHz is off
.OSC audio is off
.RNGC internal osc is off
QVCC(ARM/L2
Peripheral)
MVDD/PVDD
OSC24M_VDD
OSC_AUDO_VDD
Typ.
Max.
Typ.
Max.
Typ.
Max.
770 µA
TBD
50 µA
TBD
26 µA
TBD
Note: Typical column: TA = 25°C
Note: Maximum column TA = 70°C
4.3
Supply Power-Up/Power-Down Requirements and Restrictions
Any i.MX35 board design must comply with the power-up and power-down sequence guidelines as
described in this section to guarantee reliable operation of the device. Any deviation from these sequences
can result in any or all of the following situations:
• Excessive current during power-up phase
• Prevent the device from booting
• Irreversible damage to the i.MX35 processor (worst-case scenario)
4.3.1
Powering Up
The power-up sequence should be completed as follows:
1. Assert Power on Reset (POR).
2. Turn on digital logic domain and I/O power supplies VDDn and NVCCx.
3. Wait 32μs.
4. Turn on all other analog power supplies, including PHY1_VDDA, USBPHY1_VDDA_BIAS,
PHY2_VDD, USBPHY1_UPLLVDD, OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD,
and FUSEVDD (FUSEVDD is tied to GND if fuses are not being programmed).
5. Wait 100μs.
6. Negate the POR signal.
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4.3.2
Powering Down
The power-up in reverse order is recommended. However, all power supplies can be shut down at the same
time.
4.4
Thermal Characteristics
The thermal resistance characteristics for the device are given in Table 11. These values were measured
under the following conditions:
• Two-layer substrate
• Substrate solder mask thickness: 0.025 mm
• Substrate metal thicknesses: 0.016 mm
• Substrate core thickness: 0.200 mm
• Core via I.D: 0.168 mm, Core via plating 0.016 mm.
• Full array map design, but nearly all balls under die are power or ground.
• Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K
• Mold compound: k = 0.9 W/m K
Table 11. Thermal Resistance Data
Rating
Condition
Symbol
Value
Unit
Junction to Ambient1 Natural Convection
Single layer board (1s)
ReJA
53
ºC/W
Junction to Ambient1 Natural Convection
Four layer board (2s2p)
ReJA
30
ºC/W
Single layer board (1s)
ReJMA
44
ºC/W
Four layer board (2s2p)
ReJMA
27
ºC/W
—
ReJB
19
ºC/W
—
ReJCtop
10
ºC/W
ΨJT
2
ºC/W
Junction to
Ambient1
(@200 ft/min)
Junction to Ambient1 (@200 ft/min)
Junction to
Boards2
Junction to Case (Top)3
Junction to Package
Top4
Natural Convection
1
Junction-to-Ambient thermal resistance determined per JEDC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
2 Junction-to-Board thermal resistance determined per JEDC JESD51-8. Thermal test board meets JEDEC specification
for this package.
3 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature
is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4
Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, this thermal characterization parameter is
written as Psi-JT.
4.5
I/O Pad DC Electrical Characteristics
There are two main types of I/O: GPIO and DDR. The DDR pads can be configured in three different
drive-strength modes: MobileDDR, SDRAM, and DDR2. SDRAM and Mobile DDR modes can be further
customized within three drive strength levels: Nominal, High and Max. See Table 12.
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Table 12. I/O Drive Strength Modes and Levels for DDR Pads
Drive Mode
Mobile DDR
SDRAM
DDR2
Normal
High
Max
3.6 mA
7.2 mA
10.8 mA
4 mA
8 mA
12 mA
—
—
13.4 mA
Table 13 shows the DC electrical characteristics for GPIO, DDR2, mobile DDR, and SDRAM pads. The
symbol NVCC refers to the power supply voltage that feeds the I/O of the module in question. For
example, if you are concerned about the SD/MMC interface then NVCC refers to NVCC_SDIO.
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Table 13. I/O Pad DC Electrical Characteristics
Pad
GPIO
DC Electrical Characteristics
High-level output voltage
Symbol
Voh
Low-level output voltage
Vol
High-level output current for
slow mode
Ioh
High-level output current for
fast mode
Ioh
Low-level output current for
slow mode
Iol
Low-level output current for
fast mode
Iol
High-level DC Input Voltage
with 1.8V, 3.3V NVCC
(for digital cells in input mode)
VIH
Low-level DC Input Voltage
with 1.8V, 3.3V NVCC
(for digital cells in input mode
VIL
Input Hysteresis
VHYS
Test Condition
Ioh=–1mA
Ioh=spec’ed
Drive
Min.
Nom.
Max.
NVCC-0.15
0.8*NVCC
—
—
—
—
0.15
0.2*NVCC
Ioh=–1mA
Ioh=spec’ed
Drive
Voh=0.8*NVCC
Standard Drive
High Drive
Max. Drive
–2.0
–4.0
–8.0
Voh=0.8*NVCC
Standard Drive
High Drive
Max. Drive
–4.0
–6.0
–8.0
Voh=0.2*NVCC
Standard Drive
High Drive
Max. Drive
2.0
4.0
8.0
Voh=0.2*NVCC
Standard Drive
High Drive
Max. Drive
4.0
6.0
8.0
V
V
mA
—
—
mA
—
—
mA
—
—
mA
—
0.7*NVCC
—
—
NVCC
V
0.2*NVCC
V
TBD
V
—
–0.3V
—
NVCC=1.8
NVCC=2.5
NVCC=3.3
Unit
—
TBD
—
Schmitt trigger VT+
VT+
—
0.5NVCC
V
Schmitt trigger VT-
VT-
—
Pull-up resistor (22 KΩ PU)
Rpu
Vi=0
—
22
—
KΩ
Pull-up resistor (47 KΩ PU)
Rpu
Vi=0
—
47
—
KΩ
Pull-up resistor (100 KΩ PU)
Rpu
Vi=0
—
100
—
KΩ
Pull-down resistor (100 KΩ PD)
Rpd
Vi=NVCC
—
100
—
KΩ
—
—
—
0.5NVCC
V
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
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Table 13. I/O Pad DC Electrical Characteristics (continued)
Pad
DDR2
DC Electrical Characteristics
Symbol
Test Condition
Min.
Nom.
Max.
Unit
High-level output voltage
Voh
—
NVCC–0.28
—
—
V
Low-level output voltage
Vol
—
—
0.28
V
Output min. source current
Ioh
—
–13.4
—
—
mA
Output min. sink current
Iol
—
13.4
—
—
mA
DC input logic high
VIH(dc)
—
NVCC/2+0.
125
—
NVCC+0.3
V
DC input logic low
VIL(dc)
—
–0.3 V
—
NVCC/2–0.
125
V
DC input signal voltage (for
differential signal)
Vin(dc)
—
–0.3
—
NVCC+0.3
V
DC differential input voltage
Vid(dc)
—
0.25
—
NVCC+0.6
V
Termination voltage
Vtt
—
NVCC/2–0.
04
NVCC/2
NVCC/2+0.
04
V
Input current (no pull-up/down)
IIN
—
—
TBD
TBD
nA
Icc–NVCC
—
—
—
TBD
nA
Icc–vddi
—
—
—
TBD
nA
Tri-state I/O supply current
Tri-state core supply current
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Table 13. I/O Pad DC Electrical Characteristics (continued)
Pad
Mobile
DDR
DC Electrical Characteristics
Symbol
Test Condition
High-level output voltage
—
IOH = –1mA
IOH = spec’ed
Drive
Low-level output voltage
—
IOL = 1mA
IOL = spec’ed
Drive
Min.
NVCC –
0.08
0.8*NVCC
—
Nom.
Max.
—
—
—
Unit
V
V
0.08
0.2*NVCC
High-level output current
—
Voh=0.8*NVCCV –3.6
Standard Drive
–7.2
High Drive
–10.8
Max. Drive
—
—
mA
Low-level output current
—
Vol=0.2*NVCCV
Standard Drive
High Drive
Max. Drive
3.6
7.2
10.8
—
—
mA
High-Level DC CMOS input voltage VIH
—
0.7*NVCC
—
NVCC+0.3
V
Low-Level DC CMOS input voltage VIL
—
–0.3
—
0.2*NVCC
V
Differential receiver VTH+
VTH+
—
—
100
mV
Differential receiver VTH–
VTH–
—
Input current (no pull-up/ down)
IIN
VI = 0
VI=NVCC
—
—
TBD
nA
Tri-state I/O supply current
Icc–NVCC
VI = NVCC or 0
—
—
TBD
nA
Tri-state core supply current
lcc–vddi
VI = VDD or 0
—
—
TBD
nA
–100
—
mV
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
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Table 13. I/O Pad DC Electrical Characteristics (continued)
Pad
DC Electrical Characteristics
Symbol
Test Condition
Min.
Nom.
Max.
Unit
SDRAM High-level output voltage
Voh
Ioh=spec’ed
drive (Ioh=–4, –8,
–12,
–16 mA)
2.4
—
—
V
Low-level output voltage
Vol
Ioh=spec’ed
drive (Ioh=4, 8,
12, 16mA)
—
—
0.4
V
High-level output current
Ioh
Standard drive
High drive
Max. drive
–4.0
–8.0
–12.0
—
—
mA
Low-level output current e
Iol
Standard drive
High drive
Max. drive
4.0
8.0
12.0
—
—
mA
High-level DC Input Voltage
VIH
—
2.0
—
3.6
V
Low-level DC Input Voltage
VIL
—
–0.3V
—
0.8
V
Input current (no pull-up/down)
IIN
VI = 0
VI=NVCC
—
—
TBD
nA
—
—
TBD
nA
—
—
TBD
nA
Tri-state I/O supply current
Icc_ovtwdd VI = NVCC or 0
Tri-state core supply current
4.6
Icc-vddi
VI = VDD or 0
I/O Pad AC Electrical Characteristics
The load circuit for output pads and the output pad transition time waveform are shown in Figure 2 and
Figure 3.
From Output
Under Test
Test Point
CL
CL includes package, probe and jig capacitance
Figure 2. Load Circuit for Output Pad
NVCC
80%
80%
Output (at pad)
20%
20%
PA1
0V
PA1
Figure 3. Output Pad Transition Time Waveform
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4.6.1
•
•
AC Electrical Test Parameter Definitions
AC electrical characteristics in Table 14 through Table 19 are not applicable for the output open
drain pull-down driver.
The dI/dt parameter are measured with the following methodology:
— The zero voltage source is connected between pad and load capacitance.
— The current (through this source) derivative is calculated during output transitions.
Table 14. AC Electrical Characteristics of GPIO Pads in Slow Slew Rate Mode [NVCC=3.0 V–3.6 V]
Symbol
Test Condition
Min.
Rise/Fall
Typ. Rise/Fall
Max.
Rise/Fall
Fduty
—
40
—
60
Output pad slew rate (max. drive)
tps
25 pF
50 pF
0.79/1.12
0.49/0.73
1.30/1.77
0.84/1.23
2.02/2.58
1.19/1.58
Output pad slew rate (high drive)
tps
25 pF
50 pF
0.48/0.72
0.27/0.42
0.76/1.10
0.41/0.62
1.17/1.56
0.63/0.86
Output pad slew rate (standard
drive)
tps
25 pF
50 pF
0.25/0.40
0.14/0.21
0.40/0.59
0.21/0.32
0.60/0.83
0.32/0.44
Output pad di/dt (max. drive)
tdit
25 pF
50 pF
15
16
36
38
76
80
Output pad di/dt (high drive)
tdit
25 pF
50 pF
8
9
20
21
45
47
Output pad di/dt (standard
drive)
tdit
25 pF
50 pF
4
4
10
10
22
23
Parameter
Duty cycle
Table 15. AC Electrical Characteristics of GPIO Pads in Slow Slew Rate Mode [NVCC=1.65 V–1.95 V]
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
—
60
%
Output pad slew rate (max. drive)
tps
25 pF
50 pF
0.30/0.42
0.20/0.29
0.54/0.73
0.35/0.50
0.91/1.20
0.60/0.80
V/ns
Output pad slew rate (high drive)
tps
25 pF
50 pF
0.19/0.28
0.12/0.18
0.34/0.49
0.34/0.49
0.58/0/79
0.36/0.49
V/ns
Output pad slew rate (standard drive)
tps
25 pF
50 pF
0.12/0.18
0.07/0.11
0.20/0.30
0.11/0.17
0.34/0.47
0.20/0.27
V/ns
Output pad di/dt (max. drive)
tdit
25 pF
50 pF
7
7
21
22
56
58
mA/ns
Output pad di/dt (high drive)
tdit
25 pF
50 pF
5
5
14
15
38
40
mA/ns
Output pad di/dt (standard
drive)
tdit
25 pF
50 pF
2
2
7
7
18
19
mA/ns
Parameter
Duty cycle
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
23
Table 16. AC Electrical Characteristics of GPIO Pads in Fast Slew Rate Mode for [NVCC=3.0 V–3.6 V]
Symbol
Test Condition
Min.
rise/fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
—
60
%
Output pad slew rate (max. drive)
tps
25 pF
50 pF
0.96/1.40
0.54/0.83
1.54/2.10
0.85/1.24
2.30/3.00
1.26/1.70
V/ns
Output pad slew rate (high drive)
tps
25 pF
50 pF
0.76/1.10
0.41/0.64
1.19/1.71
0.63/0.95
1.78/2.39
0.95/1.30
V/ns
Output pad slew rate (standard drive)
tps
25 pF
50 pF
0.52/0.78
0.28/0.44
0.80/1.19
0.43/0.64
1.20/1.60
0.63/0.87
V/ns
Output pad di/dt (max. drive)
tdit
25 pF
50 pF
46
49
108
113
250
262
mA/ns
Output pad di/dt (high drive)
tdit
25 pF
50 pF
35
37
82
86
197
207
mA/ns
Output pad di/dt (standard
drive)
tdit
25 pF
50 pF
22
23
52
55
116
121
mA/ns
Parameter
Duty cycle
Table 17. AC Electrical Characteristics, GPIO Pads in Fast Slew Rate Mode [NVCC=1.65 V–1.95 V]
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
—
60
%
Output pad slew rate (max. drive)
tps
25 pF
50 pF
0.40/0.57
0.25/0.36
0.72/0.97
0.43/0.61
1.2/1.5
0.72/0.95
V/ns
Output pad slew rate (high drive)
tps
25 pF
50 pF
0.38/0.48
0.20/0.30
0.59/0.81
0.34/0.50
0.98/1.27
0.56/0.72
V/ns
Output pad slew rate (standard drive)
tps
25 pF
50 pF
0.23/0.32
0.13/0.20
0.40/0.55
0.23/0.34
0.66/0.87
0.38/0.52
V/ns
Output pad di/dt (max. drive)
tdit
25 pF
50 pF
7
7
43
46
112
118
mA/ns
Output pad di/dt (high drive)
tdit
25 pF
50 pF
11
12
31
33
81
85
mA/ns
Output pad di/dt (standard
drive)
tdit
25 pF
50 pF
9
10
27
28
71
74
mA/ns
Parameter
Duty cycle
Table 18. AC Electrical Characteristics of GPIO Pads in Slow Slew Rate Mode [NVCC=2.25 V–2.75 V]
Parameter
Duty cycle
Output pad slew rate (max. drive)
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
—
60
%
tps
25 pF
40 pF
50 pF
0.63/0.85
0.52/0.67
0.41/0.59
1.10/1.40
0.90/1.10
0.73/0.99
1.86/2.20
1.53/1.73
1.20/1.50
V/ns
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
24
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 18. AC Electrical Characteristics of GPIO Pads in Slow Slew Rate Mode [NVCC=2.25 V–2.75 V]
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Output pad slew rate (high drive)
tps
25 pF
40 pF
50 pF
0.40/0.58
0.33/0.43
0.25/0.37
0.71/0.98
0.56/0.70
0.43/0.60
1.16/1.40
0.93/1.07
0.68/0.90
V/ns
Output pad slew rate (standard drive)
tps
25 pF
40 pF
50 pF
0.24/0.36
0.19/0.25
0.13/0.21
0.41/0.59
0.32/0.35
0.23/0.33
0.66/0.87
0.51/0.59
0.36/0.48
V/ns
Output pad di/dt (max. drive)
tdit
25 pF
50 pF
22
23
62
65
148
151
mA/ns
Output pad di/dt (high drive)
tdit
25 pF
50 pF
15
16
42
44
102
107
mA/ns
Output pad di/dt (standard
drive)
tdit
25 pF
50 pF
7
8
21
22
52
54
mA/ns
Parameter
Units
Table 19. AC Electrical Characteristics of GPIO Pads in Fast Slew Rate Mode [NVCC=2.25 V–2.75 V]
Symbol
Test
Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Notes
Fduty
—
40
—
60
%
—
Output pad slew rate (max. drive)
tps
25 pF
40 pF
50 pF
0.84/1.10
0.68/0.83
0.58/0.72
1.45/1.80
1.14/1.34
0.86/1.10
2.40/2.80
1.88/2.06
1.40/1.70
V/ns
2
Output pad slew rate (high drive)
tps
25 pF
40 pF
50 pF
0.69/0.96
0.55/0.69
0.40/0.59
1.18/1.50
0.92/1.10
0.67/0.95
1.90/2.30
1.49/1.67
1.10/1.30
V/ns
Output pad slew rate (standard
drive)
tps
25 pF
40 pF
50 pF
0.24/0.36
0.37/0.47
0.13/0.21
0.80/1.00
0.62/0.76
0.45/0.65
1.30/1.60
1.00/1.14
0.70/0.95
V/ns
Output pad di/dt (max. drive)
tdit
25 pF
50 pF
46
49
124
131
310
324
mA/ns
Output pad di/dt (high drive)
tdit
25 pF
50 pF
33
35
89
94
290
304
mA/ns
Output pad di/dt (standard
drive)
tdit
25 pF
50 pF
28
29
75
79
188
198
mA/ns
Parameter
Duty cycle
3
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
25
4.6.2
AC Electrical Characteristics for DDR Pads (DDR2, Mobile DDR, and
SDRAM Modes)
Table 20. AC Electrical Characteristics of DDR Type IO Pads in DDR2 Mode
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
50
60
%
f
—
—
133
—
MHz
Output pad slew rate
tps
25 pF
50 pF
0.86/0.98
0.46/054
1.35/1.5
0.72/0.81
2.15/2.19
1.12/1.16
V/ns
Output pad di/dt
tdit
25 pF
50 pF
65
70
157
167
373
396
mA/ns
Parameter
Duty cycle
Clock frequency
Table 21. AC Requirements of DDR2 Pads
Parameter1
Symbol
Min.
Max.
Units
AC input logic high
VIH(ac)
NVCC/2+0.25
NVCC+0.3
V
AC input logic low
VIL(ac)
–0.3
NVCC/2–0.25
V
AC differential cross point
voltage for output2
Vox(ac)
NVCC/2–0.125
NVCC/2+0.125
V
1
The Jedec SSTL_18 specification (JESD8–15a) for a SSTL interface for class II operation supersedes
any specification in this document.
2 The typical value of Vox(ac) is expected to be about 0.5*NVCC and Vox(ac) is expected to track
variation in NVCC. Vox(ac) indicates the voltage at which the differential output signal must cross.
Cload=25 pF.
Table 22. AC Electrical Characteristics of DDR Type IO Pads in MobileDDR Mode, Fast Slew Rate
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
50
60
%
f
—
—
133
—
MHz
Output pad slew rate (max. drive)
tps
25pF
50pF
0.80/0.92
0.43/0.50
1.35/1.50
0.72/0.81
2.23/2.27
1.66/1.68
V/ns
Output pad slew rate (high drive)
tps
25pF
50pF
0.37/0.43
0.19/0.23
0.62/0.70
0.33/0.37
1.03/1.05
0.75/0.77
V/ns
Output pad slew rate (standard drive)
tps
25pF
50pF
0.18/0.22
0.10/0.12
0.31/0.35
0.16/0.18
0.51/0.53
0.38/0.39
V/ns
Output pad di/dt (max. drive)
tdit
25pF
50pF
64
69
171
183
407
432
mA/ns
Output pad di/dt (high drive)
tdit
25pF
50pF
37
39
100
106
232
246
mA/ns
Output pad di/dt (standard drive)
tdit
25pF
50pF
18
20
50
52
116
123
mA/ns
Parameter
Duty cycle
Clock frequency
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
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Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 23. AC Electrical Characteristics of DDR Type IO Pads in MobileDDR Mode, Slow Slew Rate
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
50
60
%
f
—
—
133
—
MHz
Output pad slew rate (max. drive)
tps
25pF
50pF
0.37/0.45
0.30/0.36
0.64/0.79
0.52/0.61
1.14/1.36
0.90/1.02
V/ns
Output pad slew rate (high drive)
tps
25pF
50pF
0.30/0.37
0.21/0.25
0.51/0.63
0.36/0.42
091/1.06
0.63/0.67
V/ns
Output pad slew rate (standard drive)
tps
25pF
50pF
0.22/0.26
0.13/0.16
0.37/0.44
0.23/0.26
0.65/0.72
0.39/0.40
V/ns
Output pad di/dt (max. drive)
tdit
25pF
50pF
65
70
171
183
426
450
mA/ns
Output pad di/dt (high drive)
tdit
25pF
50pF
31
33
82
87
233
245
mA/ns
Output pad di/dt (standard drive)
tdit
25pF
50pF
16
17
43
46
115
120
mA/ns
Parameter
Duty cycle
Clock frequency
Table 24. AC Electrical Characteristics of DDR Type IO Pads in SDRAM Mode, Fast Slew Rate
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
50
60
%
f
—
—
125
—
MHz
Output pad slew rate (max. drive)
tps
25pF
50pF
1.11/1.20
0.97/0.65
1.74/1.75
0.92/0.94
2.42/2.46
1.39/1.30
V/ns
Output pad slew rate (high drive)
tps
25pF
50pF
0.76/0.80
0.40/0.43
1.16/1.19
0.61/0.63
1.76/1.66
0.93/0.87
V/ns
Output pad slew rate (standard drive)
tps
25pF
50pF
0.38/0.41
0.20/0.22
0.59/0.60
0.31/0.32
0.89/0.82
0.47/0.43
V/ns
Output pad di/dt (max. drive)
tdit
25 pF
50 pF
89
94
198
209
398
421
mA/ns
Output pad di/dt (high drive)
tdit
25 pF
50 pF
59
62
132
139
265
279
mA/ns
Output pad di/dt (standard drive)
tdit
25 pF
50 pF
29
31
65
69
132
139
mA/ns
Parameter
Duty cycle
Clock frequency
Table 25. AC Electrical Characteristics of DDR Type IO Pads in MobileDDR Mode. Slow Slew Rate
Parameter
Duty cycle
Clock frequency
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Fduty
—
40
50
60
%
f
—
—
125
—
MHz
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
27
Table 25. AC Electrical Characteristics of DDR Type IO Pads in MobileDDR Mode. Slow Slew Rate
Symbol
Test Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Output pad slew rate (max. drive)
tps
25pF
50pF
1.11/1.20
0.60/0.65
1.74/1.75
0.93/0.95
2.63/2.48
1.39/1.29
V/ns
Output pad slew rate (high drive)
tps
25pF
50pF
0.75/0.81
0.40/0.43
1.16/1.18
0.62/0.64
1.76/1.65
094/0.87
V/ns
Output pad slew rate (standard drive)
tps
25pF
50pF
0.38/0.41
0.20/0.22
0.59/0.61
0.31/0.32
0.89/0.83
0.47/0.43
V/ns
Output pad di/dt (max. drive)
tdit
25 pF
50 pF
89
95
202
213
435
456
mA/ns
Output pad di/dt (high drive)
tdit
25 pF
50 pF
60
63
135
142
288
302
mA/ns
Output pad di/dt (standard drive)
tdit
25 pF
50 pF
29
31
67
70
144
150
mA/ns
Parameter
4.7
Units
Module-Level AC Electrical Specifications
This section contains the AC electrical information (including timing specifications) for different modules
of the MCIMX35. The modules are listed in alphabetical order.
4.7.1
AUDMUX Electrical Specifications
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is hence governed by the SSI module. See the electrical specification for SSI.
4.7.2
CSPI AC Electrical Specifications
The MCIMX35 provides two CSPI modules. CSPI ports are multiplexed in the MCIMX35 with other
pads. See the IOMUX chapter of the reference manual for more details.
Figure 4 and Figure 5 depict the master mode and slave mode timings of CSPI, and Table 26 lists the
timing parameters.
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
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Preliminary—Subject to Change Without Notice
Freescale Semiconductor
SPI_RDY
CS11
SSn[3:0]
CS1
CS3
CS2
CS6
CS5
CS3
CS4
SCLK
CS2
CS7 CS8
MOSI
CS9
CS10
MISO
Figure 4. CSPI Master Mode Timing Diagram
SSn[3:0]
CS1
CS3
CS2
CS5
CS6
CS4
SCLK
CS9
CS3
CS10
CS2
MISO
CS7
CS8
MOSI
Figure 5. CSPI Slave Mode Timing Diagram
Table 26. CSPI Interface Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
CS1
SCLK Cycle Time
tclk
60
—
ns
CS2
SCLK High or Low Time
tSW
30
—
ns
CS3
SCLK Rise or Fall
tRISE/FALL
—
7.6
ns
CS4
SSn[3:0] pulse width
tCSLH
30
—
ns
CS5
SSn[3:0] Lead Time (CS setup time)
tSCS
30
—
ns
CS6
SSn[3:0] Lag Time (CS hold time)
tHCS
30
—
ns
CS7
MOSI Setup Time
tSmosi
5
—
ns
CS8
MOSI Hold Time
tHmosi
5
—
ns
CS9
MISO Setup Time
tSmiso
5
—
ns
CS10
MISO Hold Time
tHmiso
5
—
ns
CS11
SPI_RDY Setup Time
tSDRY
5
—
ns
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
29
4.7.3
DPLL Electrical Specifications
There are three PLLs inside the MCIMX35, all based on the same PLL design. The reference clock for
these PLLs is normally generated from an external 24-MHz crystal connected to an internal oscillator via
EXTAL24M and XTAL24 pads. It is also possible to connect an external 24-MHz clock directly to
EXTAL24M, bypassing the internal oscillator.
DPLL specifications are listed in Table 27.
Table 27. DPLL Specifications
Parameter
Min.
Typ.
Max.
Unit
Reference Clock frequency
10
24
100
MHz
Max. allowed reference clock phase
noise
—
—
0.03
0.01
0.15
2 Tdck1
Frequency lock time (FOL mode or
non-integer MF)
—
—
80
μs
—
Phase lock time
—
—
100
μs
—
Max. allowed PL voltage ripple
—
—
150
100
150
mV
1
Comments
Fmodulation <50 kHz
50 kHz<Fmodulation 300 Hz
Fmodulation > 300 KHz
Fmodulation < 50 kHz
50 kHz < Fmodulation 300 Hz
Fmodulation > 300 KHz
There are two PLL are used in the MCIMX35, MPLL and PPLL. Both are based on same DPLL design.
4.7.4
Embedded Trace Macrocell (ETM) Electrical Specifications
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a test point
access (TPA) that supports TRACECLK frequencies up to 133 MHz.
Figure 6 depicts the TRACECLK timings of ETM, and Table 28 lists the timing parameters.
Figure 6. ETM TRACECLK Timing Diagram
Table 28. ETM TRACECLK Timing Parameters
ID
Parameter
Min.
Max.
Unit
Frequency dependent
—
ns
Tcyc
Clock period
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
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Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 28. ETM TRACECLK Timing Parameters (continued)
ID
Parameter
Min.
Max.
Unit
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Figure 7 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and
Table 29 lists the timing parameters.
Figure 7. Trace Data Timing Diagram
Table 29. ETM Trace Data Timing Parameters
ID
4.7.4.1
Parameter
Min.
Max.
Unit
Ts
Data setup
2
—
ns
Th
Data hold
1
—
ns
Half-Rate Clocking Mode
When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and
falling edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 7.
The same Ts and Th parameters from Table 29 still apply with respect to the falling edge of the
TRACECLK signal.
4.7.5
EMI Electrical Specifications
This section provides electrical parametrics and timing for the EMI module.
4.7.5.1
NAND Flash Controller Interface (NFC)
The MCIMX35 NFC supports normal timing mode, using two flash clock cycles for one access of RE and
WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 8, Figure 9,
Figure 10, and Figure 11 depict the relative timing requirements among different signals of the NFC at
module level, for normal mode, and Table 30 lists the timing parameters.
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
31
NFCLE
NF2
NF1
NF3
NF4
NFCE
NF5
NFWE
NF6
NF7
NFALE
NF8
NF9
Command
NFIO[7:0]
Figure 8. Command Latch Cycle Timing DIagram
NFCLE
NF1
NF4
NF3
NFCE
NF10
NF11
NF5
NFWE
NF7
NF6
NFALE
NF8
NF9
NFIO[7:0]
Address
Figure 9. Address Latch Cycle Timing DIagram
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
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Preliminary—Subject to Change Without Notice
Freescale Semiconductor
NFCLE
NF1
NF3
NFCE
NF10
NF11
NF5
NFWE
NF7
NF6
NFALE
NF8
NF9
NFIO[15:0]
Data to NF
Figure 10. Write Data Latch Cycle Timing DIagram
NFCLE
NFCE
NF14
NF15
NF13
NFRE
NF16
NF17
NFRB
NF12
NFIO[15:0]
Data from NF
Figure 11. Read Data Latch Cycle Timing DIagram
Table 30. NFC Timing Parameters1
ID
Parameter
Symbol
Timing
T = NFC Clock Cycle2
Example Timing for
NFC Clock ≈ 33 MHz
T = 30 ns
Min.
Max.
Min.
Max.
Unit
NF1
NFCLE Setup Time
tCLS
T–1.0 ns
—
29
—
ns
NF2
NFCLE Hold Time
tCLH
T–2.0 ns
—
28
—
ns
NF3
NFCE Setup Time
tCS
T–1.0 ns
—
29
—
ns
NF4
NFCE Hold Time
tCH
T–2.0 ns
—
28
—
ns
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
33
Table 30. NFC Timing Parameters1 (continued)
ID
Parameter
Symbol
Timing
T = NFC Clock Cycle2
Min.
1
2
Example Timing for
NFC Clock ≈ 33 MHz
T = 30 ns
Max.
Min.
T–1.5 ns
Unit
Max.
NF5
NF_WP Pulse Width
tWP
28.5
ns
NF6
NFALE Setup Time
tALS
T
—
30
—
ns
NF7
NFALE Hold Time
tALH
T–3.0 ns
—
27
—
ns
NF8
Data Setup Time
tDS
T
—
30
—
ns
NF9
Data Hold Time
tDH
T–5.0 ns
—
25
—
ns
NF10 Write Cycle Time
tWC
2T
60
ns
NF11 NFWE Hold Time
tWH
T–2.5 ns
27.5
ns
NF12 Ready to NFRE Low
tRR
6T
—
180
—
ns
NF13 NFRE Pulse Width
tRP
1.5T
—
45
—
ns
NF14 READ Cycle Time
tRC
2T
—
60
—
ns
NF15 NFRE High Hold Time
tREH
0.5T–2.5 ns
12.5
—
ns
NF16 Data Setup on READ
tDSR
N/A
10
—
ns
NF17 Data Hold on READ
tDHR
N/A
0
—
ns
The flash clock maximum frequency is 50 MHz.
Subject to DPLL jitter specification listed in Table 27, "DPLL Specifications," on page 30.
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is
approximately 33 MHz (30 ns). All timings are listed according to this NFC
clock frequency (multiples of NFC clock phases), except NF16 and NF17,
which are not NFC clock related.
4.7.5.2
Wireless External Interface Module (WEIM)
The following diagrams and tables specify the timings related to the WEIM module. All WEIM output
control signals may be asserted and deasserted by internal clock related to BCLK rising edge or falling
edge according to corresponding assertion/negation control fields. The address always begins relative to
the BCLK falling edge, but may be ended both on rising and falling edge in the muxed mode according to
control register configuration. Output data begins relative to BCLK rising edge except in muxed mode,
where both rising and falling edge may be used according to the control register configuration. Input data,
ECB_B and DTACK_B all captured according to BCLK rising edge time.
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NOTE
The DTACK_B signal can be muxed to different pins on the chip-level. In
those cases, see the system configuration section for the corresponding pin
name.
The Address and Data pin names are determined by the WEIM mode.
,
WE1
WE2
WE3
...
BCLK
WE4
WE5
WE6
WE7
WE8
WE9
WE10
WE11
WE12
WE13
WE14
WE15
WE16
WE17
Address
CSx_B
RW_B
OE_B
EBy_B
LBA_B
Output Data
Figure 12. WEIM Outputs Timing Diagram
BCLK
WE18, WE19
Input Data
WE20, WE21
WE22, WE23
ECB_B
WE24, WE25
WE26
DTACK_B
WE27
Figure 13. WEIM Inputs Timing Diagram
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Table 31. WEIM Bus Timing Parameters 1
1.8 V
ID
Parameter
Unit
Min.
Max.
WE1
BCLK Cycle time2
7.5
ns
WE2
BCLK Low Level Width2
3.0
ns
WE3
BCLK High Level Width2
3.0
ns
WE4
Clock fall to address valid
–1.0
2.0
ns
WE5
Clock rise/fall to address invalid
–1.0
2.0
ns
WE6
Clock rise/fall to CSx_B] valid
–1.0
2.0
ns
WE7
Clock rise/fall to CSx_B] invalid
–1.0
2.0
ns
WE8
Clock rise/fall to RW_B Valid
–1.0
2.0
ns
WE9
Clock rise/fall to RW_B Invalid
–1.0
2.0
ns
WE10
Clock rise/fall to OE_B Valid
–1.0
2.0
ns
WE11
Clock rise/fall to OE_B Invalid
–1.0
2.0
ns
WE12
Clock rise/fall to EBy_B Valid
–1.0
1.50
ns
WE13
Clock rise/fall to EBy_B Invalid
–1.0
1.50
ns
WE14
Clock rise/fall to LBA_B Valid
–1.0
2.0
ns
WE15
Clock rise/fall to LBA_B Invalid
–1.0
2.0
ns
WE16
Clock rise/fall to Output Data Valid
–1.0
1.501
ns
WE17
Clock rise to Output Data Invalid
–1.0
1.501
ns
WE18
Input Data Valid to Clock rise, FCE=1
1.2
ns
WE19
Input Data Valid to Clock rise, FCE=0
7.2
ns
WE20
Clock rise to Input Data Invalid, FCE=1
0.2
ns
WE21
Clock/k rise to Input Data Invalid, FCE=0
2.4
ns
WE22
ECB_B setup time, FCE=1
1.2
ns
WE23
ECB_B setup time, FCE=0
7.2
ns
WE24
ECB_B hold time, FCE=1
0.2
ns
WE25
ECB_B hold time, FCE=0
2.4
ns
WE26
DTACK_B setup time
5.4
ns
WE27
DTACK_B hold time
–3.2
ns
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1
In case of DOL=1 and BCLK 66MHz, max time for WE16 and WE17 is 2.5ns.
High is defined as 80% of signal value and low is defined as 20% of signal value.
BCLK parameters are being measured from the 50% point. i.e., high is defined as 50% of signal value
and low is defined as 50% as signal value.
Note: Test conditions are: PAD Voltage 1.7V–1.95V, Capacitance 25 pF for PADS.
Note: Recommended drive strength for all controls, address and BCLK is MAX drive.
The following diagrams give a few examples of basic WEIM accesses to external memory devices with
the timing parameters mentioned previously for specific control parameters settings.
BCLK
WE4
ADDR
Last Valid Address
WE5
Address V1
WE6
Next Address
WE7
CSx_B
RW_B
WE14
WE15
WE10
WE11
WE12
WE13
LBA_B
OE_B
EBy_B
WE18
DATA
D(V1)
WE20
Figure 14. Asynchronous Memory Read Access, WSC=1.
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BCLK
WE5
WE4
ADDR
Last Valid Address
Next Address
Address V1
WE6
WE7
WE8
WE9
CSx_B
RW_B
WE14
WE15
LBA_B
OE_B
WE12
WE13
EBy_B
WE17
WE16
DATA
D(V1)
Figure 15. Asynchronous Memory, Write Access, WSC=1, EBWA=1, EBWN=1, LBN=1.
BCLK
WE5
WE4
ADDR
Address V1
Last Valid Addr
Address V2
WE7
WE6
CSx_B
RW_B
WE14
WE15
LBA_B
WE10
WE11
WE12
WE13
OE_B
EBy_B
WE24
ECB_B
WE22
WE20
D(V1) D(V1+1)
Halfword Halfword
DATA
D(V2)
Halfword
D(V2+1)
Halfword
WE18
Figure 16. Synchronous 16-Bit Memory, Two Non-Sequential 32-Bit Read Accesses, WSC=2, SYNC=1,
DOL=0
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BCLK
WE4
ADDR
WE5
Address V1
Last Valid Addr
WE6
WE7
WE8
WE9
CSx_B
RW_B
WE14
LBA_B
OE_B
WE12
WE13
EBy_B
WE24
ECB_B
WE22
WE17
WE17
DATA
D(V2) D(V3) D(V4)
D(V1)
WE16
WE16
Figure 17. Synchronous Memory, Burst Write, BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1
BCLK
ADDR/
M_DATA
CSx_B
RW_B
Last WE4
Valid Addr
WE5
WE17
Write Data
Address V1
WE6
WE16
WE8
WE7
WE9
Write
WE14
WE15
LBA_B
OE_B
WE10
WE11
EBy_B
Figure 18. Muxed A/D Mode, Asynchronous Write Access, WSC=7, LBA=1, LBN=1, LAH=1
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BCLK
ADDR/
M_DATA
Last WE4
Valid Addr
WE6
WE20
WE5
Address V1
Read Data
WE18
CSx_B
WE7
RW_B
WE15
WE14
LBA_B
WE10
WE11
OE_B
WE12
WE13
EBy_B
Figure 19. Muxed A/D Mode, Asynchronous Read Access, WSC=7, LBA=1, LBN=1, LAH=1, OEA=7
Figure 20, Figure 21, and Table 32 help to determine timing parameters relative chip select state for
asynchronous WEIM accesses with correspondent WEIM bit fields and the timing parameters above
mentioned.
CSx_B
WE31
ADDR
Last Valid Address
WE32
Next Address
Address V1
RW_B
WE39
WE40
WE35
WE36
WE37
WE38
LBA_B
OE_B
EBy_B
WE44
DATA
D(V1)
WE43
Figure 20. Asynchronous Memory Read Access
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CSx_B
WE31
ADDR
Last Valid Address
WE32
Next Address
Address V1
WE33
WE34
WE39
WE40
WE45
WE46
RW_B
LBA_B
OE_B
EBy_B
WE42
DATA
D(V1)
WE41
Figure 21. Asynchronous Memory Write Access
Table 32. WEIM Asynchronous Timing Parameters Table Relative Chip Select
Ref
No.
Parameter
WE31
CSx_B valid to Address Valid
WE4 – WE6 – CSA × HHC 2
WE32
Address Invalid to CSx_B
invalid
WE7 – WE5 – CSN × HHC
WE33
CSx_B Valid to RW_B Valid
WE8 – WE6 + (RWA – CSA) × HHC
WE34
Determination by Synchronous
Measured Parameters 1
RW_B Invalid to CSx_B Invalid WE7 – WE9 + (RWN – CSN) × HHC
WE35
CSx_B Valid to OE_B Valid
WE10 – WE6 + (OEA – CSA) ×
HHC
WE36
OE_B Invalid to CSx_B Invalid
WE7 – WE11 + (OEN – CSN) ×
HHC
WE37
CSx_B Valid to EBy_B Valid
(Read access)
WE12 – WE6 + (EBRA – CSA) ×
HHC
WE38
EBy_B Invalid to CSx_B Invalid
(Read access)
WE7 – WE13 + (EBRN – CSN) ×
HHC
WE39
CSx_B Valid to LBA_B Valid
WE14 – WE6 + (LBA – CSA) ×
HHC
WE40
LBA_B Invalid to CSx_B Invalid
WE7 – WE15 + (LBN – CSN) ×
HHC
WE41
CSx_B Valid to Output Data
Valid
WE16 – WE6 + (1 – CSA) × HHC
WE42
CSx_B Invalid to Output Data
Invalid
WE17 – WE7 + (1 – CSN) × HHC
1.8 V
Unit
Min
Max
1.6 – CSA × HHC
–2.1 – CSN ×
HHC
ns
ns
1.9 + (RWA – CSA)
× HHC
–1.6 + (RWN –
CSN) × HHC
ns
ns
1.8 + (OEA – CSA)
× HHC
–1.3 + (OEN –
CSN) × HHC
ns
ns
1.7 + (EBRA –
CSA) × HHC
–1.8 + (EBRN –
CSN) × HHC
ns
ns
2.1 + (LBA – CSA)
× HHC
–1.5 + (LBN –
CSN) × HHC
ns
ns
2.3 + (1 – CSA) ×
HHC
–1.5 + (1 – CSN) ×
HHC
ns
ns
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Table 32. WEIM Asynchronous Timing Parameters Table Relative Chip Select (continued)
Ref
No.
1.8 V
Determination by Synchronous
Measured Parameters 1
Parameter
Unit
Min
Max
WE43
Input Data Valid to CSx_B
Invalid
WE19 + WE6 + (CSN[0] – 1 +
MAXN) × HHC 3
4.9 + (CSN[0] – 1
+ MAXN) × HHC
ns
WE44
CSx_B Invalid to Input Data
Invalid
WE21+ WE7 + (1 – CSN[0] +
MAXN) × HHC
0.7 + (1 – CSN[0] +
MAXN) × HHC
ns
WE45
CSx_B Valid to EBy_B Valid
(Write access)
WE12 – WE6 + (EBWA – CSA) ×
HHC
1.7 + (EBWA –
CSA) × HHC
ns
WE46
EBy_B Invalid to CSx_B Invalid
(Write access)
WE7 – WE13 + (EBWN – CSN) ×
HHC
–1.8 + (EBWA –
CSA) × HHC
ns
1
Parameters WE4... WE21 value see in the Table 31.
Here HHC is a half HCLK period. It is 3.75 ns in default case then HCLK is 133 MHz.
3 Here MAXN = (OEN[3:1] – CSN[3:1])*2 in case OEN[3:1] > CSN[3:1], in other cases MAXN = 0.
2
Figure 22, Figure 23, and Table 33 help to determine timing parameters relative address bus valid state for
asynchronous WEIM accesses with correspondent WEIM bit fields and the timing parameters above
mentioned.
ADDR
Last Valid Address
Next Address
Address V1
WE50
WE51
WE58
WE59
WE54
WE55
WE56
WE57
CSx_B
RW_B
LBA_B
OE_B
EBy_B
WE63
DATA
D(V1)
WE62
Figure 22. Asynchronous Memory Read Access
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ADDR
Last Valid Address
Next Address
Address V1
WE50
WE51
WE52
WE53
WE58
WE59
WE64
WE65
CSx_B
RW_B
LBA_B
OE_B
EBy_B
WE61
DATA
D(V1)
WE60
Figure 23. Asynchronous Memory Write Access
Table 33. WEIM Asynchronous Timing Parameters Table Relative Address Bus Valid
Ref No.
WE50
Determination by
Synchronous Measured
Parameters 1
Parameter
– WE4 + CSA × HHC 2
WE5 – WE7 + CSN × HHC
1.8 V
Unit
Min
1.6+ CSA × HHC
Address Valid to CSx_B valid WE6
WE51
CSx_B invalid to Address
Invalid
WE52
Address Valid to RW_B Valid
WE8 – WE4 + RWA × HHC
WE53
RW_B Invalid to Address
Invalid
WE5 – WE9 + RWN × HHC
WE54
Address Valid to OE_B Valid
WE10 – WE4 + OEA × HHC
WE55
OE_B Invalid to Address
Invalid
WE5
WE56
Address Valid to EBy_B Valid WE12 – WE4 + EBRA × HHC
(Read access)
WE57
EBy_B Invalid to Address
Invalid (Read access)
WE58
Address Valid to LBA_B Valid
WE14
WE59
LBA_B Invalid to Address
Invalid
WE5
WE60
Address Valid to Output Data
Valid
WE16
– WE4 + HHC
WE61
Address Invalid to Output
Data Invalid
WE17
– WE5 + HHC
WE62
Input Data Valid to Address
Invalid
– WE11 + OEN × HHC
WE5 – WE13 + EBRN × HHC
–1.6 + CSN × HHC
WE19 + WE4
+ (1 + MAXN) × HHC 3
ns
ns
2.2 + RWA × HHC
–1.4 + RWN × HHC
ns
ns
2.1 + OEA × HHC
–1.1 + OEN × HHC
ns
ns
2.0 + EBRA × HHC
–1.6 + EBRN × HHC
– WE4 + LBA × HHC
– WE15 + LBN × HHC
Max
ns
ns
2.4 + LBA × HHC
–1.3 + LBN × HHC
ns
ns
2.6 + HHC
ns
–1.3 + HHC
ns
4.6 + (1 + MAXN) × HHC
ns
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Table 33. WEIM Asynchronous Timing Parameters Table Relative Address Bus Valid (continued)
Ref No.
WE63
Determination by
Synchronous Measured
Parameters 1
Parameter
Address Invalid to Input Data
Invalid
1.8 V
Unit
Min
Max
WE23 – WE5
+ (MAXN – 1) × HHC
–0.4 + (MAXN – 1)
ns
2.0 + EBWA × HHC
ns
WE64
Address Valid to EBy_B
Valid (Write access)
WE12 – WE4
+ EBWA × HHC
WE65
EBy_B Invalid to Address
Invalid (Write access)
WE5 – WE13
+ EBWN × HHC
× HHC
–1.6 + EBWN × HHC
ns
1
Parameters WE4... WE21 value see in the <st-bold><f-helvetica><st-hyperlink>Table 31..
Here HHC is a half HCLK period. It is 3.75 ns in default case then HCLK is 133 MHz.
3 Here MAXN is maximum from (OEN & 4‘b1110) or (CSN & 4‘b1110).
2
4.7.5.3
4.7.5.3.1
ESDCTL Electrical Specifications
SDRAM Memory Controller
The following diagrams and tables specify the timings related to the SDRAMC module which interfaces
SDRAM.
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SD1
SDCLK
SDCLK
SD2
SD4
SD3
CS
SD5
SD4
RAS
SD5
SD4
CAS
SD4
SD5
SD5
WE
SD6
ADDR
SD7
ROW/BA
COL/BA
SD8
DQ
SD9
Data
SD4
DQM
SD5
Note:
CKE is high during the read/write cycle.
Figure 24. SDRAM Read Cycle Timing Diagram
Table 34. SDRAM Timing Parameter Table
ID
Parameter
Symbol
Min
Max
Unit
SD1
SDRAM clock high-level width
tCH
0.45
0.55
tCK
SD2
SDRAM clock low-level width
tCL
0.45
0.55
tCK
SD3
SDRAM clock cycle time
tCK
7.5
—
ns
SD4
CS, RAS, CAS, WE, DQM, CKE setup time
tCMS
2.3
—
ns
SD5
CS, RAS, CAS, WE, DQM, CKE hold time
tCMH
1.3
—
ns
SD6
Address setup time
tAS
2.4
—
ns
SD7
Address output hold time
tAH
1.4
—
ns
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Table 34. SDRAM Timing Parameter Table (continued)
ID
Parameter
Symbol
Min
Max
Unit
SD8
SDRAM access time
tAC
1.8
6.5
ns
SD9
Data out hold time
tOH
1.4
—
ns
SD1
SDCLK
SDCLK
SD2
SD3
SD4
CS
SD5
RAS
SD4
CAS
SD5
SD4
SD4
WE
SD5
SD5
SD7
SD6
ADDR
BA
COL/BA
ROW / BA
SD13
DQ
SD14
DATA
DQM
Figure 25. SDRAM Write Cycle Timing Diagram
Table 35. SDRAM Write Timing Parameter Table
ID
Parameter
Symbol
Min.
Max.
Unit
SD1
SDRAM clock high-level width
tCH
0.45
0.55
tCK
SD2
SDRAM clock low-level width
tCL
0.45
0.55
tCK
SD3
SDRAM clock cycle time
tCK
7.5
—
ns
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Table 35. SDRAM Write Timing Parameter Table (continued)
ID
Parameter
Symbol
Min.
Max.
Unit
SD4
CS, RAS, CAS, WE, DQM, CKE setup time
tCMS
2.3
—
ns
SD5
CS, RAS, CAS, WE, DQM, CKE hold time
tCMH
1.3
—
ns
SD6
Address setup time
tAS
2.4
—
ns
SD7
Address hold time
tAH
1.4
—
ns
SD13
Data setup time
tDS
2.4
—
ns
SD14
Data hold time
tDH
1.4
—
ns
4.7.5.3.2
Mobile DDR SDRAM Specific Parameters
The following diagrams and tables specify the timings related to the SDRAMC module which interfaces
with the Mobile DDR SDRAM.
DDR1
SDCLK
SDCLK
DDR2
DDR4
DDR3
CS
DDR5
DDR4
RAS
DDR5
DDR4
CAS
DDR4
DDR5
DDR5
WE
CKE
DDR8
DDR6
ADDR
DDR7
ROW/BA
COL/BA
Figure 26. Mobile DDR SDRAM Timing Diagram
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Table 36. Mobile DDR SDRAM Timing Parameter Table
ID
Parameter
Symbol
Unit
Min
Max
DDR1
SDRAM clock high-level width
tCH
0.45
0.55
tCK
DDR2
SDRAM clock low-level width
tCL
0.45
0.55
tCK
DDR3
SDRAM clock cycle time
tCK
7.5
—
ns
DDR4
CS, RAS, CAS, WE, DQM setup time
tCMS
2.3
—
ns
DDR5
CS, RAS, CAS, WE, DQM hold time
tCMH
1.3
—
ns
DDR6
Address output setup time
tAS
1.4
—
ns
DDR7
Address output hold time
tAH
1.4
—
ns
DDR8
CKE setup time
tCKS
2.5
—
ns
SDCLK
SDCLK_B
DD19
DD20
DQS (output)
DQ (output)
DQM (output)
DD17
DD17
DD18
DD17
DD18
Data
Data
Data
Data
Data
Data
Data
Data
DM
DM
DM
DM
DM
DM
DM
DM
DD18
DD17
DD18
Figure 27. Mobile DDR SDRAM Write Cycle Timing Diagram
Table 37. Mobile DDR SDRAM Write Cycle Parameter Table
ID
Parameter
Symbol
Min
Max
Unit
DD17
DQ & DQM setup time to DQS
tDS
1.2
—
ns
DD18
DQ & DQM hold time to DQS
tDH
1.2
—
ns
DD19
Write cycle DQS falling edge to SDCLK output delay time.
tDSS
0.25
—
tCK
DD20
Write cycle DQS falling edge to SDCLK output hold time.
tDSH
0.25
—
tCK
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SDCLK
SDCLK_B
DD23
DQS (input)
DD22
DD21
DQ (input)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Figure 28. Mobile DDR SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram
Table 38. Mobile DDR SDRAM Read Cycle Parameter Table
ID
Parameter
Symbol
Min
Max
Unit
DD21
DQS - DQ Skew (defines the Data valid window in
read cycles related to DQS).
tDQSQ
—
0.85
ns
DD22
DQS DQ HOLD time from DQS
tQH
2.5
—
ns
DD23
DQS output access time from SDCLK posedge
tDQSCK
2
6.5
ns
4.7.5.3.3
DDR2 SDRAM Specific Parameters
The following diagrams and tables specify the timings related to the SDRAMC module which interfaces
DDR2 SDRAM.
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DDR1
SDCLK
SDCLK
DDR2
DDR4
DDR3
CS
DDR5
DDR4
RAS
DDR5
DDR4
CAS
DDR4
DDR5
DDR5
WE
CKE
DDR4
DDR6
ADDR
DDR7
ROW/BA
COL/BA
Figure 29. DDR2 SDRAM Basic Timing Parameters
Table 39. DDR2 SDRAM Timing Parameter Table
ID
PARAMETER
Symbol
Min
Max
Unit
DDR1
SDRAM clock high-level width
tCH
0.45
0.55
tCK
DDR2
SDRAM clock low-level width
tCL
0.45
0.55
tCK
DDR3
SDRAM clock cycle time
tCK
7.5
8
ns
DDR4
CS, RAS, CAS, CKE, WE setup time
tIS
0.35
—
ns
DDR5
CS, RAS, CAS, CKE, WE hold time
tIH
0.475
—
ns
DDR6
Address output setup time
tIS
0.35
—
ns
DDR7
Address output hold time
tIH
0.475
—
ns
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SDCLK
SDCLK_B
DDR21
DDR22
DQS (output)
DDR18
DDR17
DQ (output)
DQM (output)
DDR20
DDR23
DDR17
DDR19
DDR18
Data
Data
Data
Data
Data
Data
Data
Data
DM
DM
DM
DM
DM
DM
DM
DM
DDR17
DDR18
DDR17
DDR18
Figure 30. DDR2 SDRAM Write Cycle Timing Diagram
Table 40. DDR2 SDRAM Write Cycle Parameter Table
ID
Parameter
Symbol
Min
Max
Unit
DDR17
DQ & DQM setup time to DQS
(single-ended strobe)
tDS(base)
0.025
—
ns
DDR18
DQ & DQM hold time to DQS
tDH(base)
0.025
—
ns
DDR19
Write cycle DQS falling edge to SDCLK output setup time.
tDSS
0.2
—
tCK
DDR20
Write cycle DQS falling edge to SDCLK output hold time.
tDSH
0.2
—
tCK
DDR21
DQS latching rising transitions to associated clock edges
tDQSS
-0.25
0.25
tCK
DDR22
DQS high level width
tDQSH
0.35
—
tCK
DDR23
DQS low level width
tDQSL
0.35
—
tCK
(single-ended strobe)
SDCLK
SDCLK_B
DQS (input)
DDR26
DDR25
DDR24
DQ (input)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Figure 31. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram
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Table 41. DDR2 SDRAM Read Cycle Parameter Table
ID
Parameter
DDR24 DQS - DQ Skew (defines the Data valid window in read cycles related to DQS).
DDR25 DQS DQ in HOLD time from DQS1
DDR26 DQS output access time from SDCLK posedge
Symbol
Min
Max Unit
tDQSQ
—
0.35
ns
tQH
2.925
—
ns
tDQSCK
-0.5
0.5
ns
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4.7.6
Enhanced Serial Audio Interface (ESAI) Timing Specifications
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator. Table 42 shows the interface timing values. The number field in the table refers to timing signals
found in Figure 32 and Figure 33.
Table 42. Enhanced Serial Audio Interface Timing
Characteristics1,2
No.
62
Clock cycle4
63
Clock high period
• For internal clock
Symbol
Expression2
Min.
Max.
tSSICC
4 × Tc
4 × Tc
30.0
30.0
—
—
i ck
i ck
—
2 × T c − 9.0
6
—
—
2 × Tc
15
—
2 × T c − 9.0
6
—
2 × Tc
15
—
ns
ns
• For external clock
64
Condition 3 Unit
Clock low period
• For internal clock
ns
—
• For external clock
—
65
SCKR rising edge to FSR out (bl) high
—
—
—
—
17.0
7.0
x ck
i ck a
ns
66
SCKR rising edge to FSR out (bl) low
—
—
—
—
17.0
7.0
x ck
i ck a
ns
67
SCKR rising edge to FSR out (wr) high5
—
—
—
—
19.0
9.0
x ck
i ck a
ns
68
SCKR rising edge to FSR out (wr) low 5
—
—
—
—
19.0
9.0
x ck
i ck a
ns
69
SCKR rising edge to FSR out (wl) high
—
—
—
—
16.0
6.0
x ck
i ck a
ns
70
SCKR rising edge to FSR out (wl) low
—
—
—
—
17.0
7.0
x ck
i ck a
ns
71
Data in setup time before SCKR (SCK in synchronous
mode) falling edge
—
—
12.0
19.0
—
—
x ck
i ck
ns
72
Data in hold time after SCKR falling edge
—
—
3.5
9.0
—
—
x ck
i ck
ns
73
FSR input (bl, wr) high before SCKR falling edge5
—
—
2.0
12.0
—
—
x ck
i ck a
ns
74
FSR input (wl) high before SCKR falling edge
—
—
2.0
12.0
—
—
x ck
i ck a
ns
75
FSR input hold time after SCKR falling edge
—
—
2.5
8.5
—
—
x ck
i ck a
ns
78
SCKT rising edge to FST out (bl) high
—
—
—
—
18.0
8.0
x ck
i ck
ns
79
SCKT rising edge to FST out (bl) low
—
—
—
—
20.0
10.0
x ck
i ck
ns
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Table 42. Enhanced Serial Audio Interface Timing (continued)
No.
Characteristics1,2
Symbol
Expression2
Min.
Max.
Condition 3 Unit
80
SCKT rising edge to FST out (wr) high5
—
—
—
—
20.0
10.0
x ck
i ck
ns
81
SCKT rising edge to FST out (wr) low5
—
—
—
—
22.0
12.0
x ck
i ck
ns
82
SCKT rising edge to FST out (wl) high
—
—
—
—
19.0
9.0
x ck
i ck
ns
83
SCKT rising edge to FST out (wl) low
—
—
—
—
20.0
10.0
x ck
i ck
ns
84
SCKT rising edge to data out enable from high
impedance
—
—
—
—
22.0
17.0
x ck
i ck
ns
86
SCKT rising edge to data out valid
—
—
—
—
18.0
13.0
x ck
i ck
ns
87
SCKT rising edge to data out high impedance 67
—
—
—
—
21.0
16.0
x ck
i ck
ns
89
FST input (bl, wr) setup time before SCKT falling edge5
—
—
2.0
18.0
—
—
x ck
i ck
ns
90
FST input (wl) setup time before SCKT falling edge
—
—
2.0
18.0
—
—
x ck
i ck
ns
91
FST input hold time after SCKT falling edge
—
—
4.0
5.0
—
—
x ck
i ck
ns
1
2
3
4
5
6
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
bl = bit length
wl = word length
wr = word length relative
SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
Periodically sampled and not 100% tested.
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62
63
64
SCKT
(Input/Output)
78
79
FST (Bit)
Out
82
FST (Word)
Out
83
86
86
84
87
First Bit
Data Out
Last Bit
93
89
91
FST (Bit) In
90
91
FST (Word) In
See Note
Note: In network mode, output flag transitions can occur at the start of each time slot within the
frame. In normal mode, the output flag state is asserted for the entire frame period.
Figure 32. ESAI Transmitter Timing
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62
63
64
SCKR
(Input/Output)
65
66
FSR (Bit)
Out
69
70
FSR (Word)
Out
72
71
Data In
First Bit
Last Bit
75
73
FSR (Bit)
In
74
75
FSR (Word)
In
76
77
Flags In
Figure 33. ESAI Receiver Timing
4.7.7
eSDHCv2 AC Electrical Specifications
Figure 34 depicts the timing of eSDHCv2, and Table 43 lists the eSDHCv2 timing characteristics. The
following definitions apply to values and signals described in Table 43:
• LS: low-speed mode. Low-speed card can tolerate a clock up to 400 kHz.
• FS: full-speed mode. For a full-speed MMC card, the card clock can reach 20 MHz; a full-speed
SD/SDIO card can reach 25 MHz.
• HS: high-speed mode. For a high-speed MMC card, the card clock can reach 52 MHz; SD/SDIO
can reach 50 MHz.
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SD4
SD2
SD1
SD5
SDHCx_CLK
SD3
output from eSDHCv2 to card
SDHCx_CMD
SDHCx_DAT_0
SDHCx_DAT_1
SD6
SDHCx_DAT_7
SD7
output from card to eSDHCv2
SD8
SDHCx_CMD
SDHCx_DAT_0
SDHCx_DAT_1
SDHCx_DAT_7
Figure 34. eSDHCv2 Timing
Table 43. eSDHCv2 Interface Timing Specification
ID
Parameter
Symbols Min. Max. Unit
Card Input Clock
fPP1
0
Clock frequency (SD/SDIO Full Speed/High Speed)
fPP2
0
25/50 MHz
Clock frequency (MMC Full Speed/High Speed)
fPP3
0
20/52 MHz
Clock frequency (Identification Mode)
fOD
100
400
kHz
SD2 Clock Low Time
tWL
7
—
ns
SD3 Clock High Time
tWH
7
—
ns
SD4 Clock Rise Time
tTLH
—
3
ns
SD5 Clock Fall Time
tTHL
—
3
ns
tOD
–3
3
ns
SD7 eSDHC Input Setup Time
tISU
5
—
ns
SD8 eSDHC Input Hold Time
tIH4
2.5
—
ns
SD1 Clock frequency (Low Speed)
400
kHz
eSDHC Output / Card Inputs CMD, DAT (Reference to CLK)
SD6 eSDHC Output Delay
eSDHC Input / Card Outputs CMD, DAT (Reference to CLK)
1
In low-speed mode, the card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal-speed mode for the SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
3 In normal-speed mode for MMC card, clock frequency can be any value between 0 and 20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
2
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4.7.8
Fast Ethernet Controller (FEC) AC Electrical Specifications
This section describes the electrical information of the FEC module. The FEC is designed to support both
10- and 100-Mbps Ethernet networks. An external transceiver interface and transceiver function are
required to complete the interface to the media. The FEC supports the 10/100 Mbps Media Independent
Interface (MII) using a total of 18 pins. The 10-Mbps 7-wire interface that is restricted to a 10-Mbps data
rate uses seven of the MII pins for connection to an external Ethernet transceiver.
4.7.8.1
FEC AC Timing
This section describes the AC timing specifications of the FEC. The MII signals are compatible with
transceivers operating at a voltage of 3.3 V.
4.7.8.2
MII Receive Signal Timing
The MII receive timing signals consist of FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency
must exceed twice the FEC_RX_CLK frequency. Table 44 lists MII receive channel timings.
Table 44. MII Receive Signal Timing
Characteristic1
Num
Min.
Max.
Unit
M1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
—
ns
M2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
—
ns
M3
FEC_RX_CLK pulse width high
35%
65%
FEC_RX_CLK period
M4
FEC_RX_CLK pulse width low
35%
65%
FEC_RX_CLK period
1 FEC_RX_DV,
FEC_RX_CLK, and FEC_RXD0 have the same timing when in 10 Mbps 7-wire interface mode.
Figure 35 shows the MII receive signal timings listed in Table 44.
M3
FEC_RX_CLK (input)
M4
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M1
M2
Figure 35. MII Receive Signal Timing Diagram
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4.7.8.3
MII Transmit Signal Timing
The transmitter timing signals consist of FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency. Table 45 lists MII transmit channel timings.
Table 45. MII Transmit Signal Timing
Characteristic1
Num
Min.
Max.
Unit
M5
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER
invalid
5
—
ns
M6
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER
valid
—
20
ns
M7
FEC_TX_CLK pulse width high
35%
65%
FEC_TX_CLK period
M8
FEC_TX_CLK pulse width low
35%
65%
FEC_TX_CLK period
1 FEC_TX_EN,
FEC_TX_CLK, and FEC_TXD0 have the same timing when in 10 Mbps 7-wire interface mode.
Figure 36 shows the MII transmit signal timings listed in Table 45.
M7
FEC_TX_CLK (input)
M5
M8
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M6
Figure 36. MII Transmit Signal Timing Diagram
4.7.8.4
MII Asynchronous Inputs Signal Timing
The MII asynchronous timing signals are FEC_CRS and FEC_COL. Table 46 lists MII asynchronous
inputs signal timing.
Table 46. MII Asynch Inputs Signal Timing
1
Num
Characteristic
Min.
Max.
Unit
M91
FEC_CRS to FEC_COL minimum pulse width
1.5
—
FEC_TX_CLK period
FEC_COL has the same timing in 10 Mbit 7-wire interface mode.
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Figure 37 shows MII asynchronous input timings listed in Table 46.
FEC_CRS, FEC_COL
M9
Figure 37. MII Asynch Inputs Timing Diagram
4.7.8.5
MII Serial Management Channel Timing
Serial management channel timing is accomplished using FEC_MDIO and FEC_MDC. The FEC
functions correctly with a maximum MDC frequency of 2.5 MHz. Table 47 lists MII serial management
channel timings.
The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 MII
specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz.
Table 47. MII Transmit Signal Timing
Num
Characteristic
Min.
Max.
Unit
M10
FEC_MDC falling edge to FEC_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11
FEC_MDC falling edge to FEC_MDIO output valid (max.
propagation delay)
—
5
ns
M12
FEC_MDIO (input) to FEC_MDC rising edge setup
18
—
ns
M13
FEC_MDIO (input) to FEC_MDC rising edge hold
0
—
ns
M14
FEC_MDC pulse width high
40%
60%
FEC_MDC period
M15
FEC_MDC pulse width low
40%
60%
FEC_MDC period
Figure 38 shows MII serial management channel timings listed in Table 47.
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M14
M15
FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12
M13
Figure 38. MII Serial Management Channel Timing Diagram
4.7.9
FIR Electrical Specifications
FIR implements asynchronous infrared protocols (FIR, MIR) defined by IrDA® (Infrared Data
Association). Refer to the IrDA website for details on FIR and MIR protocols.
4.7.10
FlexCAN Module AC Electrical Specifications
The electrical characteristics are related to the CAN transceiver outside the chip. For use in an application,
the MAX3051 is recommended. For details, please refer to the MAX3051 datasheetThe MCIMX35 has
two CAN modules available for systems design. TX and RX ports for both modules are multiplexed with
other I/O pads. Refer to the IOMUX chapter of the MCIMX35 Multimedia Applications Processor
Reference Manual to see which pads expose TX and RX pins; these ports are named TXCAN and
RXCAN, respectively.
4.7.11
I2C AC Electrical Specifications
This section describes the electrical information of the I2C module.
4.7.11.1
I2C Module Timing
Figure 39 depicts the timing of the I2C module. Table 48 lists the I2C module timing parameters.
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I2CLK
IC11
IC10
I2DAT
IC2
START
IC7
IC4
IC8
IC10
IC11
IC6
IC9
IC3
STOP
START
START
IC5
IC1
Figure 39. I2C Bus Timing Diagram
Table 48. I2C Module Timing Parameters
Standard Mode
ID
Fast Mode
Parameter
Unit
Min.
Max.
Min.
Max.
IC1
I2CLK cycle time
10
—
2.5
—
μs
IC2
Hold time (repeated) START condition
4.0
—
0.6
—
μs
IC3
Set-up time for STOP condition
4.0
—
0.6
—
μs
IC4
Data hold time
01
3.452
01
0.92
μs
IC5
HIGH Period of I2CLK Clock
4.0
—
0.6
—
μs
IC6
LOW Period of the I2CLK Clock
4.7
—
1.3
—
μs
IC7
Set-up time for a repeated START condition
4.7
—
0.6
—
μs
—
ns
IC8
Data set-up time
250
—
1003
IC9
Bus free time between a STOP and START condition
4.7
—
1.3
—
μs
IC10
Rise time of both I2DAT and I2CLK signals
—
1000
—
300
ns
IC11
Fall time of both I2DAT and I2CLK signals
—
300
—
300
ns
IC12
Capacitive load for each bus line (Cb)
—
400
—
400
pF
1
A device must internally provide a hold time of at least 300 ns for the I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
2
The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal.
3 A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement of set-up time (ID IC7) of 250
ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time
(ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2CLK line is released.
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4.7.12
IPU—Sensor Interfaces
4.7.12.1
Supported Camera Sensors
Table 49 lists the known supported camera sensors at the time of publication.
Table 49. Supported Camera Sensors1
Vendor
Model
Conexant
CX11646, CX204902, CX204502
Agilant
HDCP–2010, ADCS–10212, ADCS–10212
Toshiba
TC90A70
ICMedia
ICM202A, ICM1022
iMagic
IM8801
Transchip
TC5600, TC5600J, TC5640, TC5700, TC6000
Fujitsu
MB86S02A
Micron
MI-SOC–0133
Matsushita
MN39980
STMicro
W6411, W6500, W65012, W66002, W65522, STV09742
OmniVision
OV7620, OV6630, OV2640
Sharp
LZ0P3714 (CCD)
Motorola
MC30300 (Python)2, SCM200142, SCM201142, SCM221142, SCM200272
National Semiconductor
LM96182
1
Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only
camera suppliers.
2 These sensors have not been validated at the time of publication.
4.7.12.2
Functional Description
There are three timing modes supported by the IPU.
4.7.12.2.4
Pseudo BT.656 Video Mode
Smart camera sensors, which typically include image processing capability, support video mode transfer
operations. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC
signals. The timing syntax is defined by the BT.656 standard.
This operation mode follows the recommendations of the ITU BT.656 specifications. The only control
signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream.
An active line starts with a SAV code and ends with an EAV code. In some cases, digital blanking is
inserted in between EAV and SAV code. The CSI decodes and filters out the timing coding from the data
stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.
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4.7.12.2.5
Gated Clock Mode
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure 40.
Active Line
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_HSYNC
SENSB_PIX_CLK
SENSB_DATA[9:0]
invalid
invalid
1st byte
1st byte
Figure 40. Gated Clock Mode Timing Diagram
A frame starts with a rising edge on SENSB_VSYNC (all the timing corresponds to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. The pixel clock
is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
SENSB_HSYNC goes to low at the end of the line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For the next line, the SENSB_HSYNC timing repeats. For the next frame,
the SENSB_VSYNC timing repeats.
4.7.12.2.6
Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 4.7.12.2.5, “Gated Clock Mode”),
except for the SENSB_HSYNC signal, which is not used. See Figure 41. All incoming pixel clocks are
valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_PIX_CLK
SENSB_DATA[7:0]
invalid
invalid
1st byte
1st byte
Figure 41. Non-Gated Clock Mode Timing Diagram
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The timing described in Figure 41 is that of a Motorola sensor. Some other sensors may have slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.7.12.3
Electrical Characteristics
Figure 42 depicts the sensor interface timing, and Table 50 lists the timing parameters.
1/IP1
SENSB_MCLK
(Sensor Input)
SENSB_PIX_CLK
(Sensor Output)
IP3
IP2
1/IP4
SENSB_DATA,
SENSB_VSYNC,
SENSB_HSYNC
Figure 42. Sensor Interface Timing Diagram
Table 50. Sensor Interface Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
IP1
Sensor input clock frequency
Fmck
0.01
133
MHz
IP2
Data and control setup time
Tsu
5
—
ns
IP3
Data and control holdup time
Thd
3
—
ns
IP4
Sensor output (pixel) clock frequency
Fpck
0.01
133
MHz
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4.7.13
IPU—Display Interfaces
4.7.13.1
Supported Display Components
Table 51 lists the known supported display components at the time of publication.
Table 51. Supported Display Components1
Type
TFT displays
(memory-less)
Display controllers
Smart display modules
Digital video encoders
(for TV)
Vendor
Model
Sharp (HR-TFT Super
Mobile LCD family)
LQ035Q7 DB02, LM019LC1Sxx
Samsung (QCIF and
QVGA TFT modules for
mobile phones)
LTS180S1-HF1, LTS180S3-HF1, LTS350Q1-PE1,
LTS350Q1-PD1, LTS220Q1-HE12
Toshiba (LTM series)
LTM022P8062, LTM04C380K2,
LTM018A02A2, LTM020P3322, LTM021P3372, LTM019P3342,
LTM022A7832, LTM022A05ZZ2
NEC
NL6448BC20-08E, NL8060BC31-27
Epson
S1D15xxx series, S1D19xxx series, S1D13713, S1D13715
Solomon Systech
SSD1301 (OLED), SSD1828 (LDCD)
Hitachi
HD66766, HD66772
ATI
W2300
Epson
L1F10043 T2, L1F10044 T2, L1F10045 T 2, L2D220022, L2D200142,
L2F500322, L2D25001 T2
Hitachi
120 160 65K/4096 C-STN (#3284 LTD-1398-2) based on HD 66766
controller
Densitron Europe LTD
All displays with MPU 80/68K series interface and serial peripheral
interface
Sharp
LM019LC1Sxx
Sony
ACX506AKM
Analog Devices
ADV7174/7179
Crystal (Cirrus Logic)
CS49xx series
Focus
FS453/4
1
Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only
display component suppliers.
2
These display components have not been validated at the time of publication.
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4.7.13.2
4.7.13.2.7
Synchronous Interfaces
Interface to Active Matrix TFT LCD Panels, Functional Description
Figure 43 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,
signals are shown with negative polarity. The sequence of events for active matrix interface timing is as
follows:
• DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is
selected). In active mode, DISPB_D3_CLK runs continuously.
• DISPB_D3_HSYNC causes the panel to start a new line.
• DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
• DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted to the display. When disabled, the data is invalid and the trace is off.
DISPB_D3_VSYNC
DISPB_D3_HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
DISPB_D3_HSYNC
DISPB_D3_DRDY
1
2
3
m-1
m
DISPB_D3_CLK
DISPB_D3_DATA
Figure 43. Interface Timing Diagram for TFT (Active Matrix) Panels
4.7.13.2.8
Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
Figure 44 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity
of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC
and DISPB_D3_DRDY signals.
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IP7
IP6
IP9
IP10
IP8
Start of line
IP5
DISPB_D3_CLK
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_DATA
Figure 44. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 45 depicts the vertical timing (timing of one frame). All figure parameters shown are
programmable.
End of frame
Start of frame
IP13
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
IP11
IP15
IP14
IP12
Figure 45. TFT Panels Timing Diagram—Vertical Sync Pulse
Table 52 shows timing parameters of signals presented in Figure 44 and Figure 45.
Table 52. Synchronous Display Interface Timing Parameters—Pixel Level
ID
Parameter
Symbol
Value
Units
IP5
Display interface clock period
Tdicp
Tdicp1
ns
IP6
Display pixel clock period
Tdpcp
(DISP3_IF_CLK_CNT_D+1) * Tdicp
ns
IP7
Screen width
Tsw
(SCREEN_WIDTH+1) * Tdpcp
ns
IP8
HSYNC width
Thsw
(H_SYNC_WIDTH+1) * Tdpcp
ns
IP9
Horizontal blank interval 1
Thbi1
BGXP * Tdpcp
ns
IP10
Horizontal blank interval 2
Thbi2
(SCREEN_WIDTH–BGXP–FW) * Tdpcp
ns
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Table 52. Synchronous Display Interface Timing Parameters—Pixel Level (continued)
ID
1
Parameter
Symbol
Value
Units
IP11
HSYNC delay
Thsd
H_SYNC_DELAY * Tdpcp
ns
IP12
Screen height
Tsh
(SCREEN_HEIGHT+1) * Tsw
ns
IP13
VSYNC width
Tvsw
if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH+1) * Tdpcp
else
(V_SYNC_WIDTH+1) * Tsw
ns
IP14
Vertical blank interval 1
Tvbi1
BGYP * Tsw
ns
IP15
Vertical blank interval 2
Tvbi2
(SCREEN_HEIGHT – BGYP – FH) * Tsw
ns
Display interface clock period immediate value
Display interface clock period average value.
DISP3_IF_CLK_PER_WR
Tdicp = T HSP_CLK ⋅ -----------------------------------------------------------------HSP_CLK_PERIOD
Figure 46 depicts the synchronous display interface timing for access level, and Table 53 lists the timing
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
IP20
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
other controls
DISPB_D3_CLK
IP16
IP17
IP19
IP18
DISPB_DATA
Figure 46. Synchronous Display Interface Timing Diagram—Access Level
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Table 53. Synchronous Display Interface Timing Parameters—Access Level
ID
Parameter
Symbol
Typ.1
Min.
Tdicd2-Tdicu3
Max.
Units
IP16 Display interface clock low time
Tckl
Tdicd-Tdicu-1.5
IP17 Display interface clock high time
Tckh
Tdicp-Tdicd+Tdicu-1.5 Tdicp-Tdicd+Tdicu Tdicp-Tdicd+Tdicu+1.5
ns
IP18 Data setup time
Tdsu
Tdicd-3.5
Tdicu
—
ns
IP19 Data holdup time
Tdhd
Tdicp-Tdicd-3.5
Tdicp-Tdicu
—
ns
IP20 Control signals setup time to
display interface clock
Tcsu
Tdicd-3.5
Tdicu
—
ns
Tdicd-Tdicu+1.5
ns
1
The exact conditions not have been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device specific.
2
Display interface clock down time
1
2 ⋅ DISP3_IF_CLK_DOWN_WR
Tdicd = --- T HSP_CLK ⋅ ceil --------------------------------------------------------------------------------2
HSP_CLK_PERIOD
3
Display interface clock up time
2 ⋅ DISP3_IF_CLK_UP_WR
1
Tdicu = --- T HSP_CLK ⋅ ceil ---------------------------------------------------------------------HSP_CLK_PERIOD
2
where CEIL(X) rounds the elements of X to the nearest integers toward infinity.
4.7.13.3
Interface to Sharp HR-TFT Panels
Figure 47 depicts the Sharp HR-TFT panel interface timing, and Table 54 lists the timing parameters. The
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
Section 4.7.13.2.8, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.” The timing
images correspond to straight polarity of the Sharp signals.
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Horizontal timing
DISPB_D3_CLK
D1 D2
DISPB_D3_DATA
DISPB_D3_SPL
IP21
D320
1 DISPB_D3_CLK period
DISPB_D3_HSYNC
IP23
IP22
DISPB_D3_CLS
IP24
DISPB_D3_PS
IP25
IP26
DISPB_D3_REV
Example is drawn with FW+1=320 pixel/line, FH+1=240 lines.
SPL pulse width is fixed and aligned to the first data of the line.
REV toggles every HSYNC period.
Figure 47. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
Table 54. Sharp Synchronous Display Interface Timing Parameters—Pixel Level
ID
Parameter
Symbol
Value
Units
IP21
SPL rise time
Tsplr
(BGXP – 1) * Tdpcp
ns
IP22
CLS rise time
Tclsr
CLS_RISE_DELAY * Tdpcp
ns
IP23
CLS fall time
Tclsf
CLS_FALL_DELAY * Tdpcp
ns
IP24
CLS rise and PS fall time
Tpsf
PS_FALL_DELAY * Tdpcp
ns
IP25
PS rise time
Tpsr
PS_RISE_DELAY * Tdpcp
ns
IP26
REV toggle time
Trev
REV_TOGGLE_DELAY * Tdpcp
ns
4.7.13.4
Synchronous Interface to Dual-Port Smart Displays
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are
identical to parameters of the synchronous interface. See Section 4.7.13.2.8, “Interface to Active Matrix
TFT LCD Panels, Electrical Characteristics.”
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4.7.13.4.9
Interface to a TV Encoder—Functional Description
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits
D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 48 depicts the
interface timing.
• The frequency of the clock DISPB_D3_CLK is 27 MHz.
• The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.
• The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal.
It remains low for a single clock cycle.
• The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC
signal. It remains low for at least one clock cycle.
— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC
and DISPB_D3_HSYNC coincide.
— At a transition to an even field (of the same frame), they do not coincide.
• The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC
signal being high.
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DISPB_D3_CLK
DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_DRDY
DISPB_DATA
Cb
Y
Cr
Y
Cb
Y
Cr
Pixel Data Timing
DISPB_D3_HSYNC
523
524
525
1
2
3
4
5
6
10
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field
261
262
Odd Field
263
264
265
266
267
268
269
273
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field
Odd Field
Line and Field Timing - NTSC
DISPB_D3_HSYNC
621
622
623
624
625
1
2
3
4
23
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field
308
Odd Field
309
310
311
312
313
314
315
316
336
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_VSYNC
Even Field
Odd Field
Line and Field Timing - PAL
Figure 48. TV Encoder Interface Timing Diagram
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4.7.13.4.10
Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display
characteristics. See Section 4.7.13.2.8, “Interface to Active Matrix TFT LCD Panels, Electrical
Characteristics.”
4.7.13.5
4.7.13.5.11
Asynchronous Interfaces
Parallel Interfaces, Functional Description
The IPU supports the following asynchronous parallel interfaces:
• System 80 interface
— Type 1 (sampling with the chip select signal) with and without byte enable signals.
— Type 2 (sampling with the read and write signals) with and without byte enable signals.
• System 68k interface
— Type 1 (sampling with the chip select signal) with or without byte enable signals.
— Type 2 (sampling with the read and write signals) with or without byte enable signals.
For each of four system interfaces, there are three burst modes:
1. Burst mode without a separate clock—The burst length is defined by the corresponding parameters
of the IDMAC (when data is transferred from the system memory) or by the HBURST signal
(when the MCU directly accesses the display via the slave AHB bus). For system 80 and system
68k type 1 interfaces, data is sampled by the CS signal and other control signals changes only when
transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD
signals (system 80) or by the ENABLE signal (system 68k), and the CS signal stays active during
the whole burst.
2. Burst mode with the separate clock DISPB_BCLK—In this mode, data is sampled with the
DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are
changed simultaneously with data when the bus state (read, write or wait) is altered. The CS
signals and other controls move to non-active state after burst has been completed.
3. Single access mode—In this mode, slave AHB and DMA burst are broken to single accesses. The
data is sampled with CS or other controls according to the interface type as described above. All
controls (including CS) become non-active for one display interface clock after each access. This
mode corresponds to the ATI single access mode.
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 49,
Figure 50, Figure 51, and Figure 52. These timing images correspond to active-low DISPB_Dn_CS,
DISPB_Dn_WR and DISPB_Dn_RD signals.
Additionally, the IPU allows a programmable pause between two bursts. The pause is defined in the
HSP_CLK cycles. It allows the prevention of timing violation between two sequential bursts or two
accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.
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DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by CS signal
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 49. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram
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DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by WR/RD signals
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
DISPB_RD
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 50. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram
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DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Burst access mode with sampling by CS signal
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 51. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram
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DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Burst access mode with sampling by ENABLE signal
DISPB_BCLK
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Burst access mode with sampling by separate burst clock (BCLK)
DISPB_D#_CS
DISPB_PAR_RS
DISPB_WR
(READ/WRITE)
DISPB_RD
(ENABLE)
DISPB_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 52. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram
Display read operation can be performed with wait states when each read access takes up to 4 display
interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the
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DI_DISP0_TIME_CONF_3, DI_DISP1_TIME_CONF_3, DI_DISP2_TIME_CONF_3 registers.
Figure 53 shows timing of the parallel interface with read wait states.
WRITE OPERATION
READ OPERATION
DISP0_RD_WAIT_ST=00
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
DISP0_RD_WAIT_ST=01
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
DISP0_RD_WAIT_ST=10
DISPB_D#_CS
DISPB_RD
DISPB_WR
DISPB_PAR_RS
DISPB_DATA
Figure 53. Parallel Interface Timing Diagram—Read Wait States
4.7.13.5.12
Parallel Interfaces, Electrical Characteristics
Figure 54, Figure 56, Figure 55, and Figure 57 depict timing of asynchronous parallel interfaces based on
the system 80 and system 68k interfaces. Table 55 lists the timing parameters at display access level. All
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timing images are based on active low control signals (signal polarity is controlled via the
DI_DISP_SIG_POL register).
IP28, IP27
DISPB_PAR_RS
DISPB_RD (READ_L)
DISPB_DATA[17]
(READ_H)
IP35, IP33
IP36, IP34
DISPB_D#_CS
DISPB_WR (WRITE_L)
DISPB_DATA[16]
(WRITE_H)
IP31, IP29
IP32, IP30
read point
IP38
IP37
DISPB_DATA
(Input)
Read Data
IP40
IP39
DISPB_DATA
(Output)
IP46,IP44
IP47
IP45, IP43
IP42, IP41
Figure 54. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram
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IP28, IP27
DISPB_PAR_RS
DISPB_D#_CS
IP35, IP33
IP36, IP34
DISPB_RD (READ_L)
DISPB_DATA[17]
(READ_H)
DISPB_WR (WRITE_L)
DISPB_DATA[16]
(WRITE_H)
IP31, IP29
IP32, IP30
read point
IP37
DISPB_DATA
(Input)
IP38
Read Data
IP39
IP40
DISPB_DATA
(Output)
IP46,IP44
IP47
IP45, IP43
IP42, IP41
Figure 55. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram
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IP28, IP27
DISPB_PAR_RS
DISPB_RD (ENABLE_L)
DISPB_DATA[17]
(ENABLE_H)
IP35,IP33
IP36, IP34
DISPB_D#_CS
DISPB_WR
(READ/WRITE)
IP31, IP29
IP32, IP30
read point
IP37
DISPB_DATA
(Input)
IP38
Read Data
IP39
IP40
DISPB_DATA
(Output)
IP46,IP44
IP47
IP45, IP43
IP42, IP41
Figure 56. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram
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IP28, IP27
DISPB_PAR_RS
DISPB_D#_CS
IP35,IP33
IP36, IP34
DISPB_RD (ENABLE_L)
DISPB_DATA[17]
(ENABLE_H)
DISPB_WR
(READ/WRITE)
IP32, IP30
IP31, IP29
read point
IP38
IP37
DISPB_DATA
(Input)
Read Data
IP39
IP40
DISPB_DATA
(Output)
IP46,IP44
IP47
IP45, IP43
IP42, IP41
Figure 57. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram
Table 55. Asynchronous Parallel Interface Timing Parameters—Access Level
ID
Parameter
IP27 Read system cycle time
IP28 Write system cycle time
Symbol
Tcycr
Tcycw
Min.
Typ.1
Tdicpr-1.5
Tdicpr2
Tdicpw-1.5
Tdicpw3
4
Max.
5
Units
Tdicpr+1.5
ns
Tdicpw+1.5
ns
Tdicdr-Tdicur+1.5
ns
Tdicpr-Tdicdr+Tdicur+1.5
ns
IP29 Read low pulse width
Trl
Tdicdr-Tdicur-1.5
Tdicdr -Tdicur
IP30 Read high pulse width
Trh
Tdicpr-Tdicdr+Tdicur-1.5
Tdicpr-Tdicdr+
Tdicur
IP31 Write low pulse width
Twl
Tdicdw-Tdicuw-1.5
Tdicdw6-Tdicuw7 Tdicdw-Tdicuw+1.5
ns
IP32 Write high pulse width
Twh
Tdicpw-Tdicdw+
Tdicuw-1.5
Tdicpw-Tdicdw+
Tdicuw
ns
Tdicpw-Tdicdw+
Tdicuw+1.5
IP33 Controls setup time for read
Tdcsr
Tdicur-1.5
Tdicur
—
ns
IP34 Controls hold time for read
Tdchr
Tdicpr-Tdicdr-1.5
Tdicpr-Tdicdr
—
ns
IP35 Controls setup time for write
Tdcsw
Tdicuw-1.5
Tdicuw
—
ns
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Table 55. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)
ID
Parameter
Symbol
IP36 Controls hold time for write
Tdchw
8
Typ.1
Min.
Tdicpw-Tdicdw-1.5
Max.
Units
—
ns
Tdicpw-Tdicdw
9
10
Tracc
0
—
Tdrp -Tlbd -Tdicur-1.5
ns
Troh
Tdrp-Tlbd-Tdicdr+1.5
—
Tdicpr-Tdicdr-1.5
ns
IP39 Write data setup time
Tds
Tdicdw-1.5
Tdicdw
—
ns
IP40 Write data hold time
Tdh
Tdicpw-Tdicdw-1.5
Tdicpw-Tdicdw
—
ns
Tdicpr-1.5
Tdicpr
Tdicpr+1.5
ns
IP37 Slave device data delay
IP38 Slave device data hold time
8
IP41 Read
period2
Tdicpr
IP42 Write
period3
Tdicpw Tdicpw-1.5
Tdicpw
Tdicpw+1.5
ns
Tdicdr
Tdicdr-1.5
Tdicdr
Tdicdr+1.5
ns
Tdicur
Tdicur-1.5
Tdicur
Tdicur+1.5
ns
Tdicdw Tdicdw-1.5
Tdicdw
Tdicdw+1.5
ns
Tdicuw Tdicuw-1.5
Tdicuw
Tdicuw+1.5
ns
Tdrp
Tdrp+1.5
ns
IP43 Read down
time4
IP44 Read up time
IP45 Write down
IP46 Write up
5
time6
time7
IP47 Read time point
9
Tdrp
Tdrp-1.5
1The
exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device-specific.
2 Display interface clock period value for read:
Tdicpr = T
3
HSP_CLK
DISP#_IF_CLK_PER_RD
⋅ cei l ---------------------------------------------------------------HSP_CLK_PERIOD
Display interface clock period value for write:
Tdicpw = T
4
HSP_CLK
DISP#_IF_CLK_PER_WR
⋅ ceil -----------------------------------------------------------------HSP_CLK_PERIOD
Display interface clock down time for read:
1
2 ⋅ DISP#_IF_CLK_DOWN_RD
Tdicdr = --- T HSP_CLK ⋅ cei l ------------------------------------------------------------------------------2
HSP_CLK_PERIOD
5
Display interface clock up time for read:
1
2 ⋅ DISP#_IF_CLK_UP_RD
Tdicur = --- THSP_CLK ⋅ ce il -------------------------------------------------------------------2
HSP_CLK_PERIOD
6
Display interface clock down time for write:
1
2 ⋅ DISP#_IF_CLK_DOWN_WR
Tdicdw = --- T HSP_CLK ⋅ ceil --------------------------------------------------------------------------------2
HSP_CLK_PERIOD
7
Display interface clock up time for write:
1
2 ⋅ DISP#_IF_CLK_UP_WR
Tdi cuw = --- T HSP_CLK ⋅ cei l ---------------------------------------------------------------------2
HSP_CLK_PERIOD
8
This parameter is a requirement to the display connected to the IPU
9
Data read point
DISP#_READ_EN
Tdrp = T HSP_CLK ⋅ ceil -------------------------------------------------HSP_CLK_PERIOD
10
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific.
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The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD,
DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD,
DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the
DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers.
4.7.13.6
Serial Interfaces, Functional Description
The IPU supports the following types of asynchronous serial interfaces:
• 3-wire (with bidirectional data line)
• 4-wire (with separate data input and output lines)
• 5-wire type 1 (with sampling RS by the serial clock)
• 5-wire type 2 (with sampling RS by the chip select signal)
Figure 58 depicts timing of the 3-wire serial interface. The timing images correspond to active-low
DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal.
For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and
output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide
joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D
signal provided by the IPU.
Each data transfer can be preceded by an optional preamble with programmable length and contents. The
preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is
programmable. The RW bit can be disabled. The following data can consist of one word or of a whole
burst. The interface parameters are controlled by the DI_SER_DISP1_CONF and DI_SER_DISP2_CONF
Registers.
DISPB_D#_CS
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_SD_D_CLK
DISPB_SD_D
RW
Preamble
RS
D7
D6
D5
D4
D3
D2
D1
D0
Input or output data
Figure 58. 3-Wire Serial Interface Timing Diagram
Figure 59 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output
data lines both inside and outside the device.
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Write
DISPB_D#_CS
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
RS
D7
D6
D5
Preamble
D4
D3
D2
D1
D0
Output data
DISPB_SD_D
(Input)
Read
DISPB_D#_CS
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
RS
Preamble
DISPB_SD_D
(Input)
D7
D6
D5
D4
D3
D2
D1
D0
Input data
Figure 59. 4-Wire Serial Interface Timing Diagram
Figure 60 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is
added. When a burst is transmitted within a single active chip select interval, the RS can be changed at
boundaries of words.
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Write
DISPB_D#_CS
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
D7
D6
D5
Preamble
D4
D3
D2
D1
D0
Output data
DISPB_SD_D
(Input)
DISPB_SER_RS
Read
DISPB_D#_CS
1 display IF
clock cycle
1 display IF
clock cycle
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
Preamble
DISPB_SD_D
(Input)
D7
D6
D5
D4
D3
D2
D1
D0
Input data
DISPB_SER_RS
Figure 60. 5-Wire Serial Interface (Type 1) Timing Diagram
Figure 61 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is
added. When a burst is transmitted within a single active chip select interval, the RS can be changed at
boundaries of words.
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Write
1 display IF
clock cycle
DISPB_D#_CS
1 display IF
clock cycle
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
D7
D6
D5
D4
D3
D2
D1
D0
Output data
Preamble
DISPB_SD_D
(Input)
1 display IF
clock cycle
DISPB_SER_RS
Read
1 display IF
clock cycle
DISPB_D#_CS
1 display IF
clock cycle
DISPB_SD_D_CLK
DISPB_SD_D
(Output)
RW
Preamble
DISPB_SD_D
(Input)
DISPB_SER_RS
D7
D6
D5
1 display IF
clock cycle
D4
D3
D2
D1
D0
Input data
Figure 61. 5-Wire Serial Interface (Type 2) Timing Diagram
4.7.13.6.13
Serial Interfaces, Electrical Characteristics
Figure 62 depicts timing of the serial interface. Table 56 lists the timing parameters at display access level.
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IP49, IP48
DISPB_SER_RS
IP56,IP54
IP57, IP55
DISPB_SD_D_CLK
IP51, IP53
IP50, IP52
read point
IP59
IP58
DISPB_DATA
(Input)
Read Data
IP60
IP61
DISPB_DATA
(Output)
IP67,IP65
IP47
IP64, IP66
IP62, IP63
Figure 62. Asynchronous Serial Interface Timing Diagram
Table 56. Asynchronous Serial Interface Timing Parameters—Access Level
ID
Parameter
Symbol
Min.
Typ.1
Max.
Units
IP48 Read system cycle time
Tcycr
Tdicpr-1.5
Tdicpr2
Tdicpr+1.5
ns
IP49 Write system cycle time
Tcycw
Tdicpw-1.5
Tdicpw3
Tdicpw+1.5
ns
Tdicdr4-Tdicur5
Tdicdr-Tdicur+1.5
ns
Tdicpr-Tdicdr+Tdicur+1.5
ns
IP50 Read clock low pulse width
Trl
Tdicdr-Tdicur-1.5
IP51 Read clock high pulse width
Trh
Tdicpr-Tdicdr+Tdicur-1.5 Tdicpr-Tdicdr+
Tdicur
IP52 Write clock low pulse width
Twl
Tdicdw-Tdicuw-1.5
Tdicdw6-Tdicuw7 Tdicdw-Tdicuw+1.5
ns
IP53 Write clock high pulse width
Twh
Tdicpw-Tdicdw+
Tdicuw-1.5
Tdicpw-Tdicdw+
Tdicuw
ns
IP54 Controls setup time for read
Tdcsr
Tdicur-1.5
Tdicur
—
ns
IP55 Controls hold time for read
Tdchr
Tdicpr-Tdicdr-1.5
Tdicpr-Tdicdr
—
ns
IP56 Controls setup time for write
Tdcsw
Tdicuw-1.5
Tdicuw
—
ns
IP57 Controls hold time for write
Tdchw
Tdicpw-Tdicdw-1.5
Tdicpw-Tdicdw
—
ns
Tdicpw-Tdicdw+
Tdicuw+1.5
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Table 56. Asynchronous Serial Interface Timing Parameters—Access Level (continued)
ID
Parameter
Symbol
IP58 Slave device data delay8
Typ.1
Min.
Max.
Units
Tracc
0
—
Tdrp9-Tlbd10-Tdicur-1.5
ns
Troh
Tdrp-Tlbd-Tdicdr+1.5
—
Tdicpr-Tdicdr-1.5
ns
IP60 Write data setup time
Tds
Tdicdw-1.5
Tdicdw
—
ns
IP61 Write data hold time
Tdh
Tdicpw-Tdicdw-1.5
Tdicpw-Tdicdw
—
ns
Tdicpr-1.5
Tdicpr
Tdicpr+1.5
ns
IP59 Slave device data hold
IP62 Read
time8
period2
Tdicpr
IP63 Write period3
Tdicpw Tdicpw-1.5
Tdicpw
Tdicpw+1.5
ns
IP64 Read down time4
Tdicdr
Tdicdr-1.5
Tdicdr
Tdicdr+1.5
ns
Tdicur
Tdicur-1.5
Tdicur
Tdicur+1.5
ns
Tdicdw Tdicdw-1.5
Tdicdw
Tdicdw+1.5
ns
Tdicuw Tdicuw-1.5
Tdicuw
Tdicuw+1.5
ns
Tdrp
Tdrp+1.5
ns
IP65 Read up
time5
IP66 Write down
time6
IP67 Write up time7
IP68 Read time point9
Tdrp
Tdrp-1.5
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device specific.
2
Display interface clock period value for read:
Tdicpr = T
3
HSP_CLK
DISP#_IF_CLK_PER_RD
⋅ c eil ---------------------------------------------------------------HSP_CLK_PERIOD
Display interface clock period value for write:
Tdi cpw = T
4
HSP_CLK
DISP#_IF_CLK_PER_WR
⋅ ce il -----------------------------------------------------------------HSP_CLK_PERIOD
Display interface clock down time for read:
1
2 ⋅ DISP#_IF_CLK_DOWN_RD
Tdicdr = --- T HSP_CLK ⋅ cei l ------------------------------------------------------------------------------2
HSP_CLK_PERIOD
5
Display interface clock up time for read:
1
2 ⋅ DISP#_IF_CLK_UP_RD
Tdi cur = --- T HSP_CLK ⋅ cei l -------------------------------------------------------------------2
HSP_CLK_PERIOD
6
Display interface clock down time for write:
1
2 ⋅ DISP#_IF_CLK_DOWN_WR
Tdi cdw = --- T
⋅ cei l --------------------------------------------------------------------------------2 HSP_CLK
HSP_CLK_PERIOD
7
Display interface clock up time for write:
1
2 ⋅ DISP#_IF_CLK_UP_WR
Tdi cuw = --- T
⋅ ce il ---------------------------------------------------------------------2 HSP_CLK
HSP_CLK_PERIOD
8
9
This parameter is a requirement to the display connected to the IPU.
Data read point:
Tdrp = T
10
HSP_CLK
DISP#_READ_EN
⋅ cei l -------------------------------------------------HSP_CLK_PERIOD
Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a
device-level output delay, board delays, a device-level input delay, and an IPU input delay. This value is device specific.
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The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD,
DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD,
DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the
DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER registers.
4.7.14
Memory Stick Host Controller (MSHC)
Figure 63, Figure 64, and Figure 65 depict the MSHC timings, and Table 57 and Table 58 list the timing
parameters.
tSCLKc
tSCLKwh
tSCLKwl
MSHC_SCLK
tSCLKr
tSCLKf
Figure 63. MSHC_CLK Timing Diagram
tSCLKc
MSHC_SCLK
tBSsu
tBSh
MSHC_BS
tDsu
tDh
MSHC_DATA
(Output)
tDd
MSHC_DATA
(Intput)
Figure 64. Transfer Operation Timing Diagram (Serial)
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tSCLKc
MSHC_SCLK
tBSsu
tBSh
MSHC_BS
tDsu
tDh
MSHC_DATA
(Output)
tDd
MSHC_DATA
(Input)
Figure 65. Transfer Operation Timing Diagram (Parallel)
NOTE
The memory stick host controller is designed to meet the timing
requirements per Sony's Memory Stick Pro Format Specifications. Tables in
this section detail the specifications’ requirements for parallel and serial
modes, and not the i.MX35 timing.
Table 57. Serial Interface Timing Parameters1
Standards
Signal
MSHC_SCLK
MSHC_BS
Parameter
Symbol
Unit
Min.
Max.
Cycle
tSCLKc
50
—
ns
H pulse length
tSCLKwh
15
—
ns
L pulse length
tSCLKwl
15
—
ns
Rise time
tSCLKr
—
10
ns
Fall time
tSCLKf
—
10
ns
Setup time
tBSsu
5
—
ns
Hold time
tBSh
5
—
ns
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Table 57. Serial Interface Timing Parameters1 (continued)
Standards
Signal
MSHC_DATA
1
Parameter
Symbol
Unit
Min.
Max.
Setup time
tDsu
5
—
ns
Hold time
tDh
5
—
ns
Output delay time
tDd
—
15
ns
Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See
NVCC restrictions described in Table 58.
Table 58. Parallel Interface Timing Parameters1
Standards
Signal
Parameter
MSHC_SCLK
MSHC_BS
MSHC_DATA
1
Symbol
Unit
Min.
Max.
Cycle
tSCLKc
25
—
ns
H pulse length
tSCLKwh
5
—
ns
L pulse length
tSCLKwl
5
—
ns
Rise time
tSCLKr
—
10
ns
Fall time
tSCLKf
—
10
ns
Setup time
tBSsu
8
—
ns
Hold time
tBSh
1
—
ns
Setup time
tDsu
8
—
ns
Hold time
tDh
1
—
ns
Output delay time
tDd
—
15
ns
Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC
restrictions described in Table 8, "MCIMX35 Operating Ranges," on page 13.
4.7.15
MediaLB Controller Electrical Specifications
This section describes the electrical information of the MediaLB Controller module.
4.7.15.1
MediaLB Device AC Timing
Figure 66 and Figure 67 show the timing of MediaLB Controller, and Table 59 lists the MediaLB
controller timing characteristics.
MediaLB controllers configured as timing slaves use the MOST network as the PLL clocking source
during normal operation; however, brief periods of unlock can occur. During these periods of network
unlock, the PLL clocking source is switched to a local external crystal until the network relocks. The PLL
is temporarily unlocked during these periods of switching between the network and the crystal.
Specifications shown are applicable when the PLL is locked, unless otherwise specified.
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Figure 66. MediaLB Timing
Figure 67. MediaLB Pulse Width Variation Timing
Ground = 0.0V; Load Capacitance = 60pF; MediaLB speed = 256/512Fs; Fs = 48 kHz; all timing
parameters specified from the valid voltage threshold as listed below; unless otherwise noted.
Table 59. MLB 256/512Fs Timing Parameters
Parameter
Symbol
Min
MLBCLK Operating
Frequency1
fmck
11.264
Typ
Max
Units
Comment
MHz
Min: 256*fs at 44.0 kHz
Typ: 256*fs at 48.0 kHz
Typ: 512*fs at 48.0 kHz
Max: 512*fs at 48.1 kHz
Max: 512*fs PLL unlocked
12.288
24.576
24.6272
25.600
MLBCLK rise time
tmckr
3
ns
VIL TO VIH
MLB fall time
tmckf
3
ns
VIH TO VIL
MLBCLK cycle time
tmckc
ns
256*Fs
512*Fs
81
40
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Table 59. MLB 256/512Fs Timing Parameters (continued)
Parameter
Symbol
Min
Typ
MLBCLK low time
tmckl
31.5
30
MLBCLK high time
tmckh
Max
Units
Comment
37
35.5
ns
256*Fs
256*Fs PLL unlocked
14.5
14
17
16.5
ns
512*Fs
512*Fs PLL unlocked
31.5
30
38
36.5
ns
256*Fs
256*Fs PLL unlocked
14.5
14
17
16.5
ns
512*Fs
512*Fs PLL unlocked
ns pp
Note2
MLBCLK pulse width variation
tmpwv
MLBSIG/MLBDAT input valid
to MLBCLK falling
tdsmcf
1
ns
MLBSIG/MLBDAT input hold
from MLBCLK low
tdhmcf
0
ns
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0
Bus Hold Time
tmdzh
4
2
tmckl
ns
ns
Note3
1
The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state.
Pulse width variattion is measured at 1.25V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (pp)
3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
2
Ground = 0.0V; Load Capacitance = 40pF; MediaLB speed = 1024Fs; Fs = 48 kHz; all timing parameters
specified from the valid voltage threshold as listed below; unless otherwise noted.
Table 60. MLB Device 1024Fs Timing Parameters
Parameter
Symbol
Min
MLBCLK Operating
Frequency1
fmck
45.056
Typ
Max
Units
Comment
MHz
Min: 1024*fs at 44.0 kHz
Typ: 1024*fs at 48.0 kHz
Max: 1024fs*fs at 48.1 kHz
Max: 1024*fs PLL unlocked
49.152
49.2544
51.200
MLBCLK rise time
tmckr
1
ns
VIL TO VIH
MLB fall time
tmckf
1
ns
VIH TO VIL
MLBCLK cycle time
tmckc
MLBCLK low time
tmckl
MLBCLK high time
MLBCLK pulse width variation
tmckh
tmpwv
20.3
ns
6.5
6.1
7.7
7.3
ns
9.7
9.3
10.6
10.2
ns
PLL unlocked
PLL unlocked
0.7
ns pp
Note2
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Table 60. MLB Device 1024Fs Timing Parameters (continued)
Parameter
Symbol
Min
Typ
Max
Units
MLBSIG/MLBDAT input valid
to MLBCLK falling
tdsmcf
1
ns
MLBSIG/MLBDAT input hold
from MLBCLK low
tdhmcf
0
ns
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0
Bus Hold Time
tmdzh
2
tmckl
Comment
ns
Note3
ns
1
The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state.
Pulse width variattion is measured at 1.25V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (pp)
3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
2
4.7.16
1-Wire Timing Specifications
Figure 68 depicts the RPP timing, and Table 61 lists the RPP timing parameters.
1-WIRE Tx
“Reset Pulse”
DS2502 Tx
“Presence Pulse”
OW2
1-Wire bus
(BATT_LINE)
OW3
OW1
OW4
Figure 68. Reset and Presence Pulses (RPP) Timing Diagram
Table 61. RPP Sequence Delay Comparisons Timing Parameters
ID
Parameters
Symbol
Min.
Typ.
Max.
Units
OW1
Reset Time Low
tRSTL
480
511
—
µs
OW2
Presence Detect High
tPDH
15
—
60
µs
OW3
Presence Detect Low
tPDL
60
—
240
µs
OW4
Reset Time High
tRSTH
480
512
—
µs
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Figure 69 depicts write 0 sequence timing, and Table 62 lists the timing parameters.
OW6
1-Wire bus
(BATT_LINE)
OW5
Figure 69. Write 0 Sequence Timing Diagram
Table 62. WR0 Sequence Timing Parameters
ID
Parameter
OW5
Write 0 Low Time
OW6
Transmission Time Slot
Symbol
Min.
Typ.
Max.
Units
tWR0_low
60
100
120
µs
tSLOT
OW5
117
120
µs
Figure 70 shows write 1 sequence timing, Figure 71 depicts the read sequence timing, and Table 63 lists
the timing parameters.
OW8
1-Wire bus
(BATT_LINE)
OW7
Figure 70. Write 1 Sequence Timing Diagram
OW8
1-Wire bus
(BATT_LINE)
OW7
OW9
Figure 71. Read Sequence Timing Diagram
Table 63. WR1 /RD Timing Parameters
ID
4.7.17
Parameter
Symbol
Min.
Typ.
Max.
Units
OW7
Write 1 / Read Low Time
tLOW1
1
5
15
µs
OW8
Transmission Time Slot
tSLOT
60
117
120
µs
OW9
Release Time
tRELEASE
15
—
45
µs
Parallel ATA Module AC Electrical Specifications
The parallel ATA module can work on PIO/multiword DMA/ultra-DMA transfer modes. Each transfer
mode has a different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100 MBps.
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The parallel ATA module interface consists of a total of 29 pins. Some pins act on different function in
different transfer mode. There are various requirements for timing relationships among the function pins,
in compliance with the ATA/ATAPI-6 specification, and these requirements are configurable by the ATA
module registers.
4.7.17.1
General Timing Requirements
Table 64 and Figure 72 define the AC characteristics of the interface signals on all data transfer modes.
Table 64. AC Characteristics of All Interface Signals
1
ID
PARAMETER
SYMBOL
Min.
Max.
UNIT
SI1
Rising edge slew rate for any signal on the ATA
interface1
Srise1
—
1.25
V/ns
SI2
Falling edge slew rate for any signal on the ATA
interface1
Sfall1
—
1.25
V/ns
SI3
Host interface signal capacitance at the host
connector
Chost
—
20
pF
SRISE and SFALL meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with
all capacitive loads from 15 pF through 40 pF, where all signals have the same capacitive load value.
ATA Interface Signals
SI2
SI1
Figure 72. ATA Interface Signals Timing Diagram
4.7.17.2
ATA Electrical Specifications (ATA Bus, Bus Buffers)
This section discusses ATA parameters. For a detailed description, refer to the ATA-6 specification.
The user needs to use level shifters for 3.3-V or 5.0-V compatibility on the ATA interface.
The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors
make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast
UDMA mode operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Few vendors of bus buffers specify slew rate of the outgoing signals.
When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a
direction control signal is needed. This direction control signal is ata_buffer_en. When it is high, the bus
should drive from host to device. When it is low, the bus should drive from device to host. Steering of the
signal is such that contention on the host and device tri-state buses is always avoided.
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4.7.17.3
Timing Parameters
In the timing equations, some timing parameters are used. These parameters depend on the implementation
of the ATA interface on silicon, the bus buffer used, the cable delay, and the cable skew. Table 65 shows
ATA timing parameters.
Table 65. ATA Timing Parameters
Name
T
Value/
Contributing Factor1
Description
Bus clock period (ipg_clk_ata)
ti_ds
ti_dh
peripheral clock
frequency
Set-up time ata_data to ata_iordy edge (UDMA-in only)
UDMA0
UDMA1
UDMA2, UDMA3
UDMA4
UDMA5
15 ns
10 ns
7 ns
5 ns
4 ns
hold time ata_iordy edge to ata_data (UDMA-in only)
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA5
5.0 ns
4.6 ns
tco
propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
ata_buffer_en
12.0 ns
tsu
set-up time ata_data to bus clock L-to-H
8.5 ns
tsui
set-up time ata_iordy to bus clock H-to-L
8.5 ns
thi
hold time ata_iordy to bus clock H to L
2.5 ns
tskew1 Max. difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
7 ns
tskew2 Max. difference in buffer propagation delay for any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
transceiver
tskew3 Max. difference in buffer propagation delay for any of following signals ata_iordy, ata_data
(read)
transceiver
tbuf
Max. buffer propagation delay
transceiver
tcable1 cable propagation delay for ata_data
cable
tcable2 cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack
cable
tskew4 Max. difference in cable propagation delay between ata_iordy and ata_data (read)
cable
tskew5 Max. difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
cable
tskew6 Max. difference in cable propagation delay without accounting for ground bounce
cable
1
Values provided where applicable.
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4.7.17.4
PIO Mode Timing
Figure 73 shows timing for PIO read, and Table 66 lists the timing parameters for PIO read.
Figure 73. PIO Read Timing Diagram
Table 66. PIO Read Timing Parameters
ATA
Parameter
Parameter from Figure 73
Value
Controlling
Variable
t1
t1
t1 (min.) = time_1 * T - (tskew1 + tskew2 + tskew5)
time_1
t2
t2r
t2 min.) = time_2r * T - (tskew1 + tskew2 + tskew5)
time_2r
t9
t9
t9 (min.) = time_9 * T - (tskew1 + tskew2 + tskew6)
time_3
t5
t5
t5 (min.) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
If not met, increase
time_2
t6
t6
0
tA
tA
tA (min.) = (1.5 + time_ax) * T - (tco + tsui + tcable2 + tcable2 + 2*tbuf)
trd
trd1
t0
—
—
trd1 (max.) = (–trd) + (tskew3 + tskew4)
trd1 (min.) = (time_pio_rdx – 0.5)*T – (tsu + thi)
(time_pio_rdx – 0.5) * T > tsu + thi + tskew3 + tskew4
t0 (min.) = (time_1 + time_2 + time_9) * T
time_ax
time_pio_rdx
time_1, time_2r, time_9
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Figure 74 shows timing for PIO write, and Table 67 lists the timing parameters for PIO write.
Figure 74. PIO Write Timing Diagram
Table 67. PIO Write Timing Parameters
ATA
Parameter
Parameter
from
Figure 74
t1
t1
t2
t2w
t9
t9
t9 (min.) = time_9 * T – (tskew1 + tskew2 + tskew6)
t3
—
t3 (min.) = (time_2w – time_on)* T – (tskew1 + tskew2 +tskew5)
t4
t4
t4 (min.) = time_4 * T – tskew1
time_4
tA
tA
tA = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf)
time_ax
t0
—
t0(min.) = (time_1 + time_2 + time_9) * T
—
—
Avoid bus contention when switching buffer on by making ton long enough.
—
—
—
Avoid bus contention when switching buffer off by making toff long enough.
—
Value
t1 (min.) = time_1 * T – (tskew1 + tskew2 + tskew5)
t2 (min.) = time_2w * T – (tskew1 + tskew2 + tskew5)
Controlling
Variable
time_1
time_2w
time_9
If not met, increase
time_2w
time_1, time_2r,
time_9
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Figure 75 shows timing for MDMA read, Figure 76 shows timing for MDMA write, and Table 68 lists the
timing parameters for MDMA read and write.
Figure 75. MDMA Read Timing Diagram
Figure 76. MDMA Write Timing Diagram
Table 68. MDMA Read and Write Timing Parameters
ATA
Parameter
Parameter
from
Figure 75,
Figure 76
tm, ti
tm
tm (min.) = ti (min.) = time_m * T – (tskew1 + tskew2 + tskew5)
time_m
td
td, td1
td1.(min.) = td (min.) = time_d * T – (tskew1 + tskew2 + tskew6)
time_d
tk
tk
tk.(min.) = time_k * T – (tskew1 + tskew2 + tskew6)
time_k
t0
—
t0 (min.) = (time_d + time_k) * T
tg(read)
tgr
tgr (min.-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
tgr.(min.-drive) = td – te(drive)
tf(read)
tfr
tfr (min.-drive) = 0
tg(write)
—
tg (min.-write) = time_d * T – (tskew1 + tskew2 + tskew5)
time_d
tf(write)
—
tf (min.-write) = time_k * T – (tskew1 + tskew2 + tskew6)
time_k
tL
—
tL (max.) = (time_d + time_k–2)*T – (tsu + tco + 2*tbuf + 2*tcable2)
Value
Controlling
Variable
time_d, time_k
time_d
—
time_d, time_k
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Table 68. MDMA Read and Write Timing Parameters (continued)
ATA
Parameter
Parameter
from
Figure 75,
Figure 76
tn, tj
tkjn
tn= tj= tkjn = (max.(time_k,. time_jn) * T – (tskew1 + tskew2 + tskew6)
—
ton
toff
ton = time_on * T – tskew1
toff = time_off * T – tskew1
4.7.17.5
Value
Controlling
Variable
time_jn
—
UDMA-In Timing
Figure 77 shows timing when the UDMA-in transfer starts, Figure 78 shows timing when the UDMA-in
host terminates transfer, Figure 79 shows timing when the UDMA-in device terminates transfer, and
Table 69 lists the timing parameters for the UDMA-in burst.
Figure 77. UDMA-In Transfer Starts Timing Diagram
Figure 78. UDMA-In Host Terminates Transfer Timing Diagram
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Figure 79. UDMA-In Device Terminates Transfer Timing Diagram
Table 69. UDMA-In Burst Timing Parameters
ATA
Parameter
Parameter
from
Figure 77,
Figure 78,
Figure 79
tack
tack
tack (min.) = (time_ack * T) – (tskew1 + tskew2)
time_ack
tenv
tenv
tenv (min.) = (time_env * T) – (tskew1 + tskew2)
tenv (max.) = (time_env * T) + (tskew1 + tskew2)
time_env
tds
tds1
tds – (tskew3) – ti_ds > 0
tdh
tdh1
tdh – (tskew3) –ti_dh > 0
tcyc
tc1
(tcyc – tskew) > T
trp
trp
trp (min.) = time_rp * T – (tskew1 + tskew2 + tskew6)
time_rp
—
tx11
(time_rp * T) – (tco + tsu + 3T + 2 *tbuf + 2*tcable2) > trfs (drive)
time_rp
tmli
tmli1
tmli1 (min.) = (time_mlix + 0.4) * T
time_mlix
tzah
tzah
tzah (min.) = (time_zah + 0.4) * T
time_zah
tdzfs
tdzfs
tdzfs = (time_dzfs * T) – (tskew1 + tskew2)
time_dzfs
tcvh
tcvh
tcvh = (time_cvh *T) – (tskew1 + tskew2)
time_cvh
—
ton
toff
ton = time_on * T – tskew1
toff = time_off * T – tskew1
Description
Controlling Variable
tskew3, ti_ds, ti_dh
should be low enough
T big enough
—
1
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
2. Make ton and toff big enough to avoid bus contention.
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4.7.17.6
UDMA-Out Timing
Figure 80 shows timing when the UDMA-out transfer starts, Figure 81 shows timing when the UDMA-out
host terminates transfer, Figure 82 shows timing when the UDMA-out device terminates transfer, and
Table 70 lists the timing parameters for the UDMA-out burst.
Figure 80. UDMA-Out Transfer Starts Timing Diagram
Figure 81. UDMA-Out Host Terminates Transfer Timing Diagram
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Figure 82. UDMA-Out Device Terminates Transfer Timing Diagram
Table 70. UDMA-Out Burst Timing Parameters
ATA
Parameter
Parameter
from
Figure 80,
Figure 81,
Figure 82
tack
tack
tack (min.) = (time_ack * T) – (tskew1 + tskew2)
time_ack
tenv
tenv
tenv (min.) = (time_env * T) – (tskew1 + tskew2)
tenv (max.) = (time_env * T) + (tskew1 + tskew2)
time_env
tdvs
tdvs
tdvs = (time_dvs * T) – (tskew1 + tskew2)
time_dvs
tdvh
tdvh
tdvs = (time_dvh * T) – (tskew1 + tskew2)
time_dvh
tcyc
tcyc
tcyc = time_cyc * T – (tskew1 + tskew2)
time_cyc
t2cyc
—
t2cyc = time_cyc * 2 * T
time_cyc
trfs1
trfs
trfs = 1.6 * T + tsui + tco + tbuf + tbuf
—
tdzfs
tss
tss
tmli
tdzfs_mli
tli
Value
tdzfs = time_dzfs * T – (tskew1)
tss = time_ss * T – (tskew1 + tskew2)
Controlling
Variable
—
time_dzfs
time_ss
tdzfs_mli =max. (time_dzfs, time_mli) * T – (tskew1 + tskew2)
—
tli1
tli1 > 0
—
tli
tli2
tli2 > 0
—
tli
tli3
tli3 > 0
—
tcvh
tcvh
tcvh = (time_cvh *T) – (tskew1 + tskew2)
—
ton
toff
ton = time_on * T – tskew1
toff = time_off * T – tskew1
time_cvh
—
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4.7.18
Parallel Interface (ULPI) Timing
Electrical and timing specifications of the parallel interface are presented in the subsequent sections.
Table 71. Signal Definitions—Parallel Interface
Name
Direction
USB_Clk
USB_Data[7:0]
USB_Dir
USB_Stp
Signal Description
In
Interface clock. All interface signals are synchronous to the clock.
I/O
Bidirectional data bus, driven low by the link during idle. Bus ownership
is determined by Dir.
In
Direction. Control the direction of the data bus.
Stop. The link asserts this signal for 1 clock cycle to stop the data
stream currently on the bus.
Out
USB_Nxt
Next. The PHY asserts this signal to throttle the data.
In
USB_Clk
US15
US16
USB_Stp
US15
US16
USB_Data
US17
US17
USB_Dir/Nxt
Figure 83. USB Transmit/Receive Waveform in Parallel Mode
Table 72. USB Timing Specification in VP_VM Unidirectional Mode
ID
Parameter
Min.
Max.
Unit
Conditions /
Reference Signal
US15
USB_TXOE_B
—
6.0
ns
10 pF
US16
USB_DAT_VP
—
0.0
ns
10 pF
US17
USB_SE0_VM
—
9.0
ns
10 pF
4.7.19
PWM Electrical Specifications
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
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being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin. The modulated signal of the module is observed at this pin. It can be viewed as a clock signal whose
period and duty cycle can be varied with different settings of the PWM. The smallest period is two ipg_clk
periods with duty cycle of 50 percent.
4.7.20
SJC Electrical Specifications
This section details the electrical characteristics for the SJC module. Figure 84 depicts the SJC test clock
input timing. Figure 85 depicts the SJC boundary scan timing, Figure 86 depicts the SJC test access port,
Figure 87 depicts the SJC TRST timing, and Table 73 lists the SJC timing parameters.
SJ1
SJ2
TCK
(Input)
SJ2
VM
VIH
VM
VIL
SJ3
SJ3
Figure 84. Test Clock Input Timing Diagram
TCK
(Input)
VIH
VIL
SJ4
Data
Inputs
SJ5
Input Data Valid
SJ6
Data
Outputs
Output Data Valid
SJ7
Data
Outputs
SJ6
Data
Outputs
Output Data Valid
Figure 85. Boundary Scan (JTAG) Timing Diagram
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TCK
(Input)
VIH
VIL
SJ8
TDI
TMS
(Input)
SJ9
Input Data Valid
SJ10
TDO
(Output)
Output Data Valid
SJ11
TDO
(Output)
SJ10
TDO
(Output)
Output Data Valid
Figure 86. Test Access Port Timing Diagram
TCK
(Input)
SJ13
TRST
(Input)
SJ12
Figure 87. TRST Timing Diagram
Table 73. SJC Timing Parameters
All Frequencies
ID
Parameter
Unit
Min.
Max.
1001
—
ns
SJ1
TCK cycle time
SJ2
TCK clock pulse width measured at VM 2
40
—
ns
SJ3
TCK rise and fall times
—
3
ns
SJ4
Boundary scan input data set-up time
10
—
ns
SJ5
Boundary scan input data hold time
50
—
ns
SJ6
TCK low to output data valid
—
50
ns
SJ7
TCK low to output high impedance
—
50
ns
SJ8
TMS, TDI data set-up time
10
—
ns
SJ9
TMS, TDI data hold time
50
—
ns
SJ10
TCK low to TDO data valid
—
44
ns
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Table 73. SJC Timing Parameters (continued)
All Frequencies
ID
Parameter
Unit
Min.
Max.
—
44
ns
SJ11
TCK low to TDO high impedance
SJ12
TRST assert time
100
—
ns
SJ13
TRST set-up time to TCK low
40
—
ns
1
On cases where SDMA TAP is put in the chain, the max. TCK frequency is limited by max. ratio of 1:8 of SDMA core frequency
to TCK limitation. This implies max. frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
2
VM - mid point voltage
4.7.21
SPDIF Timing
As SPDIF data is sent using biphase marking code. When encoding, the SPDIF data signal is modulated
to the clock that is twice the bitrate of the data signal.
Figure 88 shows the SRCK timing, when SPDIF works in the Rx mode, where SRCK stands for the
modulating Rx clock. Figure 89 shows the STCLK timing when SPDIF works in the Tx mode, where
STCLK stands for the modulating Tx clock.
Table 74. SPDIF Timing
All Frequency
Characteristics
Symbol
Unit
Min.
Max.
SPDIFIN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
SPDIFOUT output (Load = 50pf)
• Skew
• Transition Rising
• Transition Falling
—
—
—
—
—
—
1.5
24.2
31.3
ns
SPDIFOUT1 output (Load = 30pf)
• Skew
• Transition Rising
• Transition Falling
—
—
—
—
—
—
1.5
13.6
18.0
ns
SRCK period
srckp
40.0
—
ns
SRCK high period
srckph
16.0
—
ns
SRCK low period
srckpl
16.0
—
ns
STCLK period
stclkp
40.0
—
ns
STCLK high period
stclkph
16.0
—
ns
STCLK low period
stclkpl
16.0
—
ns
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srckp
srckpl
SRCK
(Output)
srckph
VM
VM
Figure 88. SRCK Timing
Figure 89. STCLK Timing
stclkp
stclkpl
STCLK
(Input)
4.7.22
VM
stclkph
VM
SSI Electrical Specifications
This section describes the electrical information of SSI. Note the following pertaining to timing
information:
• All of the timing for the SSI is given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)
and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or
the frame sync STFS/SRFS shown in the tables and in the figures.
• All timing is on AUDMUX signals when SSI is being used for data transfer.
• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
• For internal frame sync operation using the external clock, the FS timing will be the same as that
of Tx Data (for example, during AC97 mode of operation).
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4.7.22.1
SSI Transmitter Timing with Internal Clock
Figure 90 depicts the SSI transmitter timing with internal clock, and Table 75 lists the timing parameters.
SS1
SS3
SS5
SS2
SS4
AD1_TXC
(Output)
SS8
SS6
AD1_TXFS (bl)
(Output)
SS10
SS12
AD1_TXFS (wl)
(Output)
SS14
SS15
SS16
SS18
SS17
AD1_TXD
(Output)
SS43
SS19
SS42
AD1_RXD
(Input)
Note: SRXD Input in Synchronous mode only
SS1
SS3
SS5
SS4
SS2
DAM1_T_CLK
(Output)
SS6
SS8
DAM1_T_FS (bl)
(Output)
SS10
SS12
DAM1_T_FS (wl)
(Output)
SS14
SS15
SS16
SS18
SS17
DAM1_TXD
(Output)
SS43
SS42
SS19
DAM1_RXD
(Input)
Note: SRXD Input in Synchronous mode only
Figure 90. SSI Transmitter with Internal Clock Timing Diagram
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Table 75. SSI Transmitter with Internal Clock Timing Parameters
ID
Parameter
Min.
Max.
Unit
Internal Clock Operation
SS1
(Tx/Rx) CK clock period
81.4
—
ns
SS2
(Tx/Rx) CK clock high period
36.0
—
ns
SS3
(Tx/Rx) CK clock rise time
—
6
ns
SS4
(Tx/Rx) CK clock low period
36.0
—
ns
SS5
(Tx/Rx) CK clock fall time
—
6
ns
SS6
(Tx) CK high to FS (bl) high
—
15.0
ns
SS8
(Tx) CK high to FS (bl) low
—
15.0
ns
SS10
(Tx) CK high to FS (wl) high
—
15.0
ns
SS12
(Tx) CK high to FS (wl) low
—
15.0
ns
SS14
(Tx/Rx) Internal FS rise time
—
6
ns
SS15
(Tx/Rx) Internal FS fall time
—
6
ns
SS16
(Tx) CK high to STXD valid from high impedance
—
15.0
ns
SS17
(Tx) CK high to STXD high/low
—
15.0
ns
SS18
(Tx) CK high to STXD high impedance
—
15.0
ns
SS19
STXD rise/fall time
—
6
ns
10.0
—
ns
Synchronous Internal Clock Operation
SS42
SRXD setup before (Tx) CK falling
SS43
SRXD hold after (Tx) CK falling
0
—
ns
SS52
Loading
—
25
pF
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4.7.22.2
SSI Receiver Timing with Internal Clock
Figure 91 depicts the SSI receiver timing with internal clock, and Table 76 lists the timing parameters.
SS1
SS3
SS5
SS2
SS4
AD1_TXC
(Output)
SS9
SS7
AD1_TXFS (bl)
(Output)
SS11
SS13
AD1_TXFS (wl)
(Output)
SS20
SS21
AD1_RXD
(Input)
SS51
SS47
SS48
SS49
SS50
AD1_RXC
(Output)
SS1
SS3
SS5
SS2
SS4
DAM1_T_CLK
(Output)
SS7
DAM1_T_FS (bl)
(Output)
SS9
SS11
SS13
DAM1_T_FS (wl)
(Output)
SS20
SS21
DAM1_RXD
(Input)
SS47
SS48
SS51
SS50
SS49
DAM1_R_CLK
(Output)
Figure 91. SSI Receiver with Internal Clock Timing Diagram
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Table 76. SSI Receiver with Internal Clock Timing Parameters
ID
Parameter
Min.
Max.
Unit
Internal Clock Operation
SS1
(Tx/Rx) CK clock period
81.4
—
ns
SS2
(Tx/Rx) CK clock high period
36.0
—
ns
SS3
(Tx/Rx) CK clock rise time
—
6
ns
SS4
(Tx/Rx) CK clock low period
36.0
—
ns
SS5
(Tx/Rx) CK clock fall time
—
6
ns
SS7
(Rx) CK high to FS (bl) high
—
15.0
ns
SS9
(Rx) CK high to FS (bl) low
—
15.0
ns
SS11
(Rx) CK high to FS (wl) high
—
15.0
ns
SS13
(Rx) CK high to FS (wl) low
—
15.0
ns
SS20
SRXD setup time before (Rx) CK low
10.0
—
ns
SS21
SRXD hold time after (Rx) CK low
0
—
ns
15.04
—
ns
Oversampling Clock Operation
SS47
Oversampling clock period
SS48
Oversampling clock high period
6
—
ns
SS49
Oversampling clock rise time
—
3
ns
SS50
Oversampling clock low period
6
—
ns
SS51
Oversampling clock fall time
—
3
ns
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4.7.22.3
SSI Transmitter Timing with External Clock
Figure 92 depicts the SSI transmitter timing with external clock, and Table 77 lists the timing parameters.
SS22
SS23
SS25
SS26
SS24
AD1_TXC
(Input)
SS27
SS29
AD1_TXFS (bl)
(Input)
SS33
SS31
AD1_TXFS (wl)
(Input)
SS39
SS37
SS38
AD1_TXD
(Output)
SS45
SS44
AD1_RXD
(Input)
SS46
Note: SRXD Input in Synchronous mode only
SS22
SS26
SS23
SS24
SS25
DAM1_T_CLK
(Input)
SS27
SS29
DAM1_T_FS (bl)
(Input)
SS33
SS31
DAM1_T_FS (wl)
(Input)
SS39
SS37
SS38
DAM1_TXD
(Output)
SS44
SS45
DAM1_RXD
(Input)
Note: SRXD Input in Synchronous mode only
SS46
Figure 92. SSI Transmitter with External Clock Timing Diagram
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Table 77. SSI Transmitter with External Clock Timing Parameters
ID
Parameter
Min.
Max.
Unit
External Clock Operation
SS22
(Tx/Rx) CK clock period
81.4
—
ns
SS23
(Tx/Rx) CK clock high period
36.0
—
ns
SS24
(Tx/Rx) CK clock rise time
—
6.0
ns
SS25
(Tx/Rx) CK clock low period
36.0
—
ns
SS26
(Tx/Rx) CK clock fall time
—
6.0
ns
SS27
(Tx) CK high to FS (bl) high
—10.0
15.0
ns
SS29
(Tx) CK high to FS (bl) low
10.0
—
ns
SS31
(Tx) CK high to FS (wl) high
–10.0
15.0
ns
SS33
(Tx) CK high to FS (wl) low
10.0
—
ns
SS37
(Tx) CK high to STXD valid from high
impedance
—
15.0
ns
SS38
(Tx) CK high to STXD high/low
—
15.0
ns
SS39
(Tx) CK high to STXD high impedance
—
15.0
ns
Synchronous External Clock Operation
SS44
SRXD setup before (Tx) CK falling
10.0
—
ns
SS45
SRXD hold after (Tx) CK falling
2.0
—
ns
SS46
SRXD rise/fall time
—
6.0
ns
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4.7.22.4
SSI Receiver Timing with External Clock
Figure 93 depicts the SSI receiver timing with external clock, and Table 78 lists the timing parameters.
SS22
SS26
SS24
SS25
SS23
AD1_TXC
(Input)
SS30
SS28
AD1_TXFS (bl)
(Input)
SS32
AD1_TXFS (wl)
(Input)
SS34
SS35
SS41
SS36
SS40
AD1_RXD
(Input)
SS22
SS24
SS26
SS23
SS25
DAM1_T_CLK
(Input)
SS30
SS28
DAM1_T_FS (bl)
(Input)
SS32
DAM1_T_FS (wl)
(Input)
SS34
SS35
SS41
SS36
SS40
DAM1_RXD
(Input)
Figure 93. SSI Receiver with External Clock Timing Diagram
Table 78. SSI Receiver with External Clock Timing Parameters
ID
Parameter
Min.
Max.
Unit
External Clock Operation
SS22
(Tx/Rx) CK clock period
81.4
—
ns
SS23
(Tx/Rx) CK clock high period
36.0
—
ns
SS24
(Tx/Rx) CK clock rise time
—
6.0
ns
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Table 78. SSI Receiver with External Clock Timing Parameters (continued)
ID
4.7.23
Parameter
Min.
Max.
Unit
SS25
(Tx/Rx) CK clock low period
36.0
—
ns
SS26
(Tx/Rx) CK clock fall time
—
6.0
ns
SS28
(Rx) CK high to FS (bl) high
–10.0
15.0
ns
SS30
(Rx) CK high to FS (bl) low
10.0
—
ns
SS32
(Rx) CK high to FS (wl) high
–10.0
15.0
ns
SS34
(Rx) CK high to FS (wl) low
10.0
—
ns
SS35
(Tx/Rx) External FS rise time
—
6.0
ns
SS36
(Tx/Rx) External FS fall time
—
6.0
ns
SS40
SRXD setup time before (Rx) CK low
10.0
—
ns
SS41
SRXD hold time after (Rx) CK low
2.0
—
ns
UART Electrical
This section describes the electrical information of the UART module.
4.7.23.1
4.7.23.1.14
UART RS-232 Serial Mode Timing
UART Transmitter
Figure 94 depicts the transmit timing of UART in RS-232 serial mode, with 8 data bit/1 stop bit format.
Table 79 lists the UART RS-232 serial mode transmit timing characteristics.
UA1
TXD
(output)
Start
Bit
Possible
Parity
Bit
UA1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Par Bit STOP
BIT
UA1
Next
Start
Bit
UA1
Figure 94. UART RS-232 Serial Mode Transmit Timing Diagram
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Table 79. RS-232 Serial Mode Transmit Timing Parameters
ID
UA1
1
2
Parameter
Transmit Bit Time
Symbol
Min.
Max.
Units
tTbit
1/Fbaud_rate1 Tref_clk2
1/Fbaud_rate +
Tref_clk
-
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
4.7.23.1.15
UART Receiver
Figure 95 depicts the RS-232 serial mode receive timing, with 8 data bit/1 stop bit format. Table 80 lists
serial mode receive timing characteristics.
UA2
RXD
(input)
Start
Bit
Possible
Parity
Bit
UA2
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Par Bit STOP
BIT
UA2
Next
Start
Bit
UA2
Figure 95. UART RS-232 Serial Mode Receive Timing Diagram
Table 80. RS-232 Serial Mode Receive Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
UA2
Receive Bit Time1
tRbit
1/Fbaud_rate2 1/(16*Fbaud_rate)
1/Fbaud_rate +
1/(16*Fbaud_rate)
-
1
Note: The UART receiver can tolerate 1/(16*Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must
not exceed 3/(16*Fbaud_rate).
2 F
baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.7.23.2
UART IrDA Mode Timing
The following subsections give the UART transmit and receive timings in IrDA mode.
4.7.23.2.16
UART IrDA Mode Transmitter
Figure 96 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 81 lists
the transmit timing characteristics.
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UA3
UA4
UA3
UA3
UA3
TXD
(output)
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Possible
Parity
Bit
Bit 7
STOP
BIT
Figure 96. UART IrDA Mode Transmit Timing Diagram
Table 81. IrDA Mode Transmit Timing Parameters
1
2
ID
Parameter
Symbol
Min.
Max.
Units
UA3
Transmit Bit Time in IrDA mode
tTIRbit
1/Fbaud_rate1 Tref_clk2
1/Fbaud_rate + Tref_clk
-
UA4
Transmit IR Pulse Duration
tTIRpulse
(3/16)*(1/Fbaud_rate)
- Tref_clk
(3/16)*(1/Fbaud_rate)
+ Tref_clk
-
Fbaud_rate : Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk : The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
4.7.23.2.17
UART IrDA Mode Receiver
Figure 97 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 82 lists the
receive timing characteristics.
UA5
UA6
UA5
UA5
UA5
RXD
(input)
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Possible
Parity
Bit
STOP
BIT
Figure 97. UART IrDA Mode Receive Timing Diagram
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Table 82. IrDA Mode Receive Timing Parameters
ID
Parameter
UA5
Receive Bit Time1 in IrDA mode
UA6
Receive IR Pulse Duration
Symbol
Min.
Max.
Units
tRIRbit
1/Fbaud_rate2 1/(16*Fbaud_rate)
1/Fbaud_rate +
1/(16*Fbaud_rate)
-
tRIRpulse
1.41 us
(5/16)*(1/Fbaud_rate)
-
1
Note: The UART receiver can tolerate 1/(16*Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must
not exceed 3/(16*Fbaud_rate).
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.7.24
USB Electrical Specifications
In order to support four different serial interfaces, the USB serial transceiver can be configured to operate
in one of four modes:
• DAT_SE0 bidirectional, 3-wire mode
• DAT_SE0 unidirectional, 6-wire mode
• VP_VM bidirectional, 4-wire mode
• VP_VM unidirectional, 6-wire mode
4.7.24.1
DAT_SE0 Bidirectional Mode
Table 83. Signal Definitions - DAT_SE0 Bidirectional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out
In
TX data when USB_TXOE_B is low
Differential RX data when USB_TXOE_B is high
USB_SE0_VM
Out
In
SE0 drive when USB_TXOE_B is low
SE0 RX indicator when USB_TXOE_B is high
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Transmit
US3
USB_TXOE_B
USB_DAT_VP
US1
USB_SE0_VM
US2
US4
Figure 98. USB Transmit Waveform in DAT_SE0 Bidirectional Mode
Receive
USB_TXOE_B
USB_DAT_VP
US7
US8
USB_SE0_VM
Figure 99. USB Receive Waveform in DAT_SE0 Bidirectional Mode
Table 84. Signal Definitions—DAT_SE0 Bidirectional Mode
No.
Parameter
Signal Name
Direction
Min.
Max.
Unit
Conditions /
Reference
Signal
US1
TX Rise/Fall Time
USB_DAT_VP
Out
—
5.0
ns
50 pF
US2
TX Rise/Fall Time
USB_SE0_VM
Out
—
5.0
ns
50 pF
US3
TX Rise/Fall Time
USB_TXOE_B
Out
—
5.0
ns
50 pF
US4
TX Duty Cycle
USB_DAT_VP
Out
49.0
51.0
%
—
US7
RX Rise/Fall Time
USB_DAT_VP
In
—
3.0
ns
35 pF
US8
RX Rise/Fall Time
USB_SE0_VM
In
—
3.0
ns
35 pF
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4.7.24.2
DAT_SE0 Unidirectional Mode
Table 85. Signal Definitions - DAT_SE0 Unidirectional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out
TX data when USB_TXOE_B is low
USB_SE0_VM
Out
SE0 drive when USB_TXOE_B is low
USB_VP1
In
Buffered data on DP when USB_TXOE_B is high
USB_VM1
In
Buffered data on DM when USB_TXOE_B is high
USB_RCV
In
Differential RX data when USB_TXOE_B is high
Transmit
US11
USB_TXOE_B
USB_DAT_VP
US9
USB_SE0_VM
US10
US12
Figure 100. USB Transmit Waveform in DAT_SE0 Unidirectional Mode
Receive
USB_TXOE_B
USB_VP1
USB_RCV
US15/US17
US16
USB_VM1
Figure 101. USB Receive Waveform in DAT_SE0 Unidirectional Mode
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Table 86. USB Port Timing Specification in DAT_SE0 Unidirectional Mode
No.
Parameter
Signal Name
Signal
Source
Min.
Max.
Unit
Condition /
Reference Signal
US9
TX Rise/Fall Time USB_DAT_VP
Out
—
5.0
ns
50 pF
US10
TX Rise/Fall Time USB_SE0_VM
Out
—
5.0
ns
50 pF
US11
TX Rise/Fall Time USB_TXOE_B
Out
—
5.0
ns
50 pF
US12
TX Duty Cycle
Out
49.0
51.0
%
—
US15
RX Rise/Fall Time USB_VP1
In
—
3.0
ns
35 pF
US16
RX Rise/Fall Time USB_VM1
In
—
3.0
ns
35 pF
US17
RX Rise/Fall Time USB_RCV
In
—
3.0
ns
35 pF
4.7.24.3
USB_DAT_VP
VP_VM Bidirectional Mode
Table 87. Signal Definitions—VP_VM Bidirectional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
USB_DAT_VP
Out (Tx)
In (Rx)
TX VP data when USB_TXOE_B is low
RX VP data when USB_TXOE_B is high
USB_SE0_VM
Out (Tx)
In (Rx)
TX VM data when USB_TXOE_B low
RX VM data when USB_TXOE_B high
USB_RCV
Transmit enable, active low
In
Differential RX data
Transmit
US20
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US18
US21
US19
US22
US22
Figure 102. USB Transmit Waveform in VP_VM Bidirectional Mode
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Receive
US26
USB_DAT_VP
USB_SE0_VM
US27
US28
USB_RCV
US29
Figure 103. USB Receive Waveform in VP_VM Bidirectional Mode
Table 88. USB Port Timing Specification in VP_VM Bidirectional Mode
No.
Parameter
Signal Name
Direction
Min.
Max.
Unit
Condition /
Reference Signal
US18
TX Rise/Fall Time
USB_DAT_VP
Out
-
5.0
ns
50 pF
US19
TX Rise/Fall Time
USB_SE0_VM
Out
-
5.0
ns
50 pF
US20
TX Rise/Fall Time
USB_TXOE_B
Out
-
5.0
ns
50 pF
US21
TX Duty Cycle
USB_DAT_VP
Out
49.0
51.0
%
-
US22
TX Overlap
USB_SE0_VM
Out
-3.0
+3.0
ns
USB_DAT_VP
US26
RX Rise/Fall Time
USB_DAT_VP
In
-
3.0
ns
35 pF
US27
RX Rise/Fall Time
USB_SE0_VM
In
-
3.0
ns
35 pF
US28
RX Skew
USB_DAT_VP
In
-4.0
+4.0
ns
USB_SE0_VM
US29
RX Skew
USB_RCV
In
-6.0
+2.0
ns
USB_DAT_VP
4.7.24.4
VP_VM Unidirectional Mode
Table 89. Signal Definitions—VP_VM Unidirectional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out
TX VP data when USB_TXOE_B is low
USB_SE0_VM
Out
TX VM data when USB_TXOE_B is low
USB_VP1
In
RX VP data when USB_TXOE_B is high
USB_VM1
In
RX VM data when USB_TXOE_B is high
USB_RCV
In
Differential RX data
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Transmit
US32
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US30
US33
US31
US34
US34
Figure 104. USB Transmit Waveform in VP_VM Unidirectional Mode
Receive
USB_TXOE_B
USB_VP1
US38
USB_VM1
US40
US39
USB_RCV
US41
Figure 105. USB Receive Waveform in VP_VM Unidirectional Mode
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Table 90. USB Timing Specification in VP_VM Unidirectional Mode
No.
Parameter
Signal
Direction
Min.
Max.
Unit
Conditions /
Reference Signal
US30
TX Rise/Fall Time
USB_DAT_VP
Out
-
5.0
ns
50 pF
US31
TX Rise/Fall Time
USB_SE0_VM
Out
-
5.0
ns
50 pF
US32
TX Rise/Fall Time
USB_TXOE_B
Out
-
5.0
ns
50 pF
US33
TX Duty Cycle
USB_DAT_VP
Out
49.0
51.0
%
-
US34
TX Overlap
USB_SE0_VM
Out
-3.0
+3.0
ns
USB_DAT_VP
US38
RX Rise/Fall Time
USB_VP1
In
-
3.0
ns
35 pF
US39
RX Rise/Fall Time
USB_VM1
In
-
3.0
ns
35 pF
US40
RX Skew
USB_VP1
In
-4.0
+4.0
ns
USB_VM1
US41
RX Skew
USB_RCV
In
-6.0
+2.0
ns
USB_VP1
5
Package Information and Pinout
This section includes the following:
• Pin/contact assignment information
• Mechanical package drawing
5.1
MAPBGA Production Package 1568-01, 17 x 17 mm, 0.8 Pitch
See Figure 106 for the package drawing and dimensions of the production package.
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5.2
Production Package Outline Drawing
Figure 106. Production Package: Mechanical Drawing
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5.2.1
MAPBGA Signal Assignments
Table 91 lists MAPBGA signals alphabetized by signal name. Table 92 shows the signal assignment on
the MCIMX35 ball map.
Table 91. Signal Ball Map Locations
Signal ID
A0
A1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A2
A20
A21
A22
A23
A24
A25
A3
A4
A5
A6
A7
A8
A9
ATA_BUFF_EN1
ATA_CS01
ATA_CS11
ATA_DA01
ATA_DA11
ATA_DA21
ATA_DATA01
ATA_DATA11
ATA_DATA101
ATA_DATA111
ATA_DATA121
ATA_DATA131
ATA_DATA141
ATA_DATA151
ATA_DATA21
ATA_DATA3
Ball Location
Signal ID
Ball Location
A5
D7
F15
D5
F6
B3
D14
D15
D13
D12
E11
D11
E7
D10
E10
D9
E9
D8
E8
C6
D6
B5
C5
A4
B4
A3
T5
V7
T7
R4
V1
R5
Y5
W5
V3
Y2
U3
W2
W1
T4
V5
U5
ATA_DATA71
Y3
U4
W3
Y6
W6
V6
T3
V2
U6
T6
E14
W10
U9
V12
E16
Y10
T10
V10
T12
L16
F17
E19
B20
C19
E18
F19
V16
T15
W16
V15
U14
Y16
U15
W17
V14
W15
Y15
T14
V9
W9
W8
T8
ATA_DATA81
ATA_DATA91
ATA_DIOR1
ATA_DIOW1
ATA_DMACK1
ATA_DMARQ1
ATA_INTRQ1
ATA_IORDY 1
ATA_RESET_B1
BCLK
BOOT_MODE0
BOOT_MODE1
CAPTURE
CAS
CLK_MODE0
CLK_MODE1
CLKO
COMPARE
CONTRAST1
CS0
CS1
CS2
CS3
CS4
CS5
CSI_D101
CSI_D111
CSI_D121
CSI_D131
CSI_D141
CSI_D151
CSI_D81
CSI_D91
CSI_HSYNC1
CSI_MCLK1
CSI_PIXCLK1
CSI_VSYNC1
CSPI1_MISO
CSPI1_MOSI
CSPI1_SCLK
CSPI1_SPI_RDY
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Freescale Semiconductor
Table 91. Signal Ball Map Locations (continued)
Signal ID
Ball Location
Signal ID
Ball Location
ATA_DATA4
ATA_DATA5
ATA_DATA6
CTS2
D0
D1
D10
D11
D12
D13
D14
D15
D2
D3
D3_CLS1
D3_DRDY1
D3_FPSHIFT 1
D3_HSYNC1
D3_REV1
D3_SPL1
D3_VSYNC1
D4
D5
D6
D7
D8
D9
DE_B
DQM0
DQM1
DQM2
DQM3
EB0
EB1
ECB
EXT_ARMCLK
EXTAL_AUDIO
EXTAL24M
FEC_COL
FEC_CRS
FEC_MDC
FEC_MDIO
FEC_RDATA0
FEC_RDATA1
FEC_RDATA2
FEC_RDATA3
Y4
W4
V4
G5
A2
D4
D2
E6
E3
F5
D1
E2
B2
E5
L17
L20
L15
L18
M17
M18
M19
C3
B1
D3
C2
C1
E4
W19
B19
D17
D16
C18
F18
F16
D19
V8
W20
T20
P3
N5
R1
P1
P2
N2
M3
N1
CSPI1_SS0
CSPI1_SS1
CTS1
FEC_TDATA0
FEC_TDATA1
FEC_TDATA2
FEC_TDATA3
FEC_TX_CLK
FEC_TX_EN
FEC_TX_ERR
FSR
FST
FUSE_VDD
FUSE_VSS
GPIO1_0
GPIO1_1
GPIO2_0
GPIO3_0
HCKR
HCKT
I2C1_CLK
I2C1_DAT
I2C2_CLK
I2C2_DAT
LBA
LD01
LD11
LD101
LD111
LD121
LD131
LD141
LD151
LD161
LD171
LD181
LD191
LD21
LD201
LD211
LD221
LD231
LD31
LD41
LD51
LD61
Y8
U8
R3
P5
M4
M5
L6
P4
T1
N4
K5
J1
P13
M11
T11
Y11
U11
V11
K2
J5
M20
N17
L3
M1
D20
F20
G18
H20
J18
J16
J19
J17
J20
K14
K19
K18
K20
G17
K16
K17
K15
L19
G16
G19
H16
H18
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
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Preliminary—Subject to Change Without Notice
131
Table 91. Signal Ball Map Locations (continued)
Signal ID
FEC_RX_CLK
FEC_RX_DV
FEC_RX_ERR
MA10
MGND
MLB_CLK
MLB_DAT
MLB_SIG
MVDD
NF_CE0
NFALE
NFCLE
NFRB
NFRE_B
NFWE_B
NFWP_B
NGND_ATA
NGND_ATA
NGND_ATA
NGND_CRM
NGND_CSI
NGND_EMI1
NGND_EMI1
NGND_EMI1
NGND_EMI2
NGND_EMI3
NGND_EMI3
NGND_JTAG
NGND_LCDC
NGND_LCDC
NGND_MISC
NGND_MISC
NGND_MLB
NGND_NFC
NGND_SDIO
NVCC_ATA
NVCC_ATA
NVCC_ATA
NVCC_ATA
NVCC_CRM
NVCC_CSI
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
Ball Location
R2
T2
N3
C4
N11
W13
Y13
W12
P11
G3
F2
E1
F3
F1
G2
F4
M9
P9
L10
L11
N10
H8
H10
J10
J11
J12
K12
M13
K11
L12
M7
K8
M10
K9
N12
N6
P6
P7
P8
R9
R11
G7
G8
G9
H9
F10
Signal ID
1
LD7
LD81
LD91
NVCC_EMI2
NVCC_EMI2
NVCC_EMI2
NVCC_EMI3
NVCC_JTAG
NVCC_LCDC
NVCC_LCDC
NVCC_LCDC
NVCC_LCDC
NVCC_MISC
NVCC_MISC
NVCC_MISC
NVCC_MLB
NVCC_NFC
NVCC_NFC
NVCC_NFC
NVCC_SDIO
OE
OSC_AUDIO_VDD
OSC_AUDIO_VSS
OSC24M_VDD
OSC24M_VSS
PGND
PHY1_VDDA
PHY1_VDDA
PHY1_VSSA
PHY1_VSSA
PHY2_VDD
PHY2_VSS
POR_B
POWER_FAIL
PVDD
RAS
RESET_IN_B
RTCK
RTS1
RTS2
RW
RXD1
RXD2
SCK4
SCK5
SCKR
Ball Location
G20
H17
H19
G12
F13
F14
G14
P16
H14
J14
L14
M14
K6
K7
L8
R10
G6
H6
H7
P14
E20
V20
U19
T19
T18
M12
M15
N20
N16
P20
R13
P12
W11
Y9
N13
E15
U10
U18
U1
G1
C20
U2
H3
L4
L5
K3
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Freescale Semiconductor
Table 91. Signal Ball Map Locations (continued)
Signal ID
Ball Location
Signal ID
Ball Location
NVCC_EMI1
NVCC_EMI1
NVCC_EMI1
SD1_CLK
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD10
SD11
SD12
SD13
SD14
SD15
SD16
SD17
SD18
SD19
SD2
SD2_CLK
SD2_CMD
SD2_DATA0
SD2_DATA1
SD2_DATA2
SD2_DATA3
SD20
SD21
SD22
SD23
SD24
SD25
SD26
SD27
SD28
SD29
SD3
SD30
SD31
SD4
SD5
SD6
SD7
SD8
SD9
SDBA0
G10
F11
G11
V18
Y19
R14
U16
W18
V17
A15
B15
C13
B14
A14
B13
C12
C11
A12
B12
B18
W14
U13
V13
T13
Y14
U12
B11
A11
C10
B10
A9
C9
B9
A8
B8
C8
C16
A7
B7
A18
C15
A17
B16
C14
A16
A6
SCKT
SD0
SD1
SDCLK
SDCLK_B
SDQS0
SDQS1
SDQS2
SDQS3
SDWE
SJC_MOD
SRXD4
SRXD5
STXD4
STXD5
STXFS4
STXFS5
TCK
TDI
TDO
TEST_MODE
TMS
TRSTB
TTM_PAD
TX0
TX1
TX2_RX3
TX3_RX2
TX4_RX1
TX5_RX0
TXD1
TXD2
USBOTG_OC
USBOTG_PWR
USBPHY1_DM
USBPHY1_DP
USBPHY1_RREF
USBPHY1_UID
USBPHY1_UPLLGND
USBPHY1_UPLLVDD
USBPHY1_UPLLVDD
USBPHY1_VBUS
USBPHY1_VDDA_BIAS
USBPHY1_VSSA_BIAS
USBPHY2_DM
USBPHY2_DP
J4
C17
A19
E12
E13
B17
A13
A10
C7
G15
U17
L1
K4
M2
K1
L2
J6
R17
P15
R15
Y7
R16
T16
M16
G4
H1
H5
J2
H4
J3
R6
H2
U7
W7
N19
P19
R19
N18
N14
N15
P17
P18
R20
R18
Y17
Y18
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
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Preliminary—Subject to Change Without Notice
133
Table 91. Signal Ball Map Locations (continued)
1
Signal ID
Ball Location
Signal ID
Ball Location
SDBA1
SDCKE0
SDCKE1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
B6
D18
E17
L7
N7
R7
F8
R8
F9
F12
R12
G13
H15
J15
A1
Y1
J8
M8
N8
J9
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSTBY
WDOG_RST
XTAL_AUDIO
XTAL24M
M6
F7
J7
L9
N9
K10
P10
H11
H12
H13
J13
K13
L13
T17
A20
Y20
T9
Y12
V19
U20
Not available for the MCIMX351.
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Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 92. Ball Map—17 x 17, 0.8 mm Pitch1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
VSS
D0
A9
A7
A0
SDBA
0
SD30
SD27
SD24
SDQ
S2
SD21
SD18
SDQ
S1
SD14
SD10
SD9
SD6
SD4
SD1
VSS
A
B
D5
D2
A13
A8
A5
SDBA
1
SD31
SD28
SD26
SD23
SD20
SD19
SD15
SD13
SD11
SD7
SDQ
S0
SD2
DQM
0
CS2
B
C
D8
D7
D4
MA10
A6
A3
SDQ
S3
SD29
SD25
SD22
SD17
SD16
SD12
SD8
SD5
SD3
SD0
DQM
3
CS3
RW
C
D
D14
D10
D6
D1
A11
A4
A1
A24
A22
A20
A19
A17
A16
A14
A15
DQM
2
DQM
1
SDCK
E0
ECB
LBA
D
E
NFCL
E
D15
D12
D9
D3
D11
A2
A25
A23
A21
A18
SDCL
K
SDCL
K_B
BCLK
RAS
CAS
SDCK
E1
CS4
CS1
OE
E
F
NFRE
_B
NFAL
E
NFRB
NFW
P_B
D13
A12
VDD
VDD
VDD
NVC
C_EM
I1
NVC
C_EM
I1
VDD
NVC
C_EM
I2
NVC
C_EM
I2
A10
EB1
CS0
EB0
CS5
LD0
F
G
RTS2
NFW
E_B
NF_C
E0
TX0
CTS2
NVC
C_NF
C
NVC
C_EM
I1
NVC
C_EM
I1
NVC
C_EM
I1
NVC
C_EM
I1
NVC
C_EM
I1
NVC
C_EM
I2
VDD
NVC
C_EM
I3
SDW
E
LD3
LD2
LD1
LD4
LD7
G
H
TX1
TXD2
RXD2
TX4_
RX1
TX2_
RX3
NVC
C_NF
C
NVC
C_NF
C
NGN
D_EM
I1
NVC
C_EM
I1
NGN
D_EM
I1
VSS
VSS
VSS
NVC
C_LC
DC
VDD
LD5
LD8
LD6
LD9
LD10
H
J
FST
TX3_
RX2
TX5_
RX0
SCKT
HCKT
STXF
S5
VDD
VSS
VSS
NGN
D_EM
I1
NGN
D_EM
I2
NGN
D_EM
I3
VSS
NVC
C_LC
DC
VDD
LD12
LD14
LD11
LD13
LD15
J
K
STXD
5
HCK
R
SCKR
SRXD
5
FSR
NVC
C_MI
SC
NVC
C_MI
SC
NGN
D_MI
SC
NGN
D_NF
C
VSS
NGN
D_LC
DC
NGN
D_EM
I3
VSS
LD16
LD22
LD20
LD21
LD18
LD17
LD19
K
L
SRXD
4
STXF
S4
I2C2_
CLK
SCK4
SCK5
FEC_
TDAT
A3
VDD
NVC
C_MI
SC
VSS
NGN
D_AT
A
NGN
D_CR
M
NGN
D_LC
DC
VSS
NVC
C_LC
DC
D3_F
PSHI
FT
CON
TRAS
T
D3_C
LS
D3_H
SYNC
LD23
D3_D
RDY
L
M
I2C2_
DAT
STXD
4
FEC_
RDAT
A2
FEC_
TDAT
A1
FEC_
TDAT
A2
VDD
NGN
D_MI
SC
VSS
NGN
D_AT
A
NGN
D_ML
B
FUSE
_VSS
PGN
D
NGN
D_JT
AG
NVC
C_LC
DC
PHY1
_VDD
A
TTM_
PAD
D3_R
EV
D3_S
PL
D3_V
SYNC
I2C1_
CLK
M
N
FEC_
RDAT
A3
FEC_
RDAT
A1
FEC_
RX_E
RR
FEC_
TX_E
RR
FEC_
CRS
NVC
C_AT
A
VDD
VSS
VSS
NGN
D_CS
I
MGN
D
NGN
D_SD
IO
PVDD
USBP
HY1_
UPLL
GND
USBP
HY1_
UPLL
VDD
PHY1
_VSS
A
I2C1_
DAT
USBP
HY1_
UID
USBP
HY1_
DM
PHY1
_VDD
A
N
P
FEC_
MDIO
FEC_
RDAT
A0
FEC_
COL
FEC_
TX_C
LK
FEC_
TDAT
A0
NVC
C_AT
A
NVC
C_AT
A
NVC
C_AT
A
NGN
D_AT
A
VSS
MVD
D
PHY2
_VSS
FUSE
_VDD
NVC
C_SD
IO
TDI
NVC
C_JT
AG
USBP
HY1_
UPLL
VDD
USBP
HY1_
VBUS
USBP
HY1_
DP
PHY1
_VSS
A
P
R
FEC_
MDC
FEC_
RX_C
LK
CTS1
ATA_
DA0
ATA_
DA2
TXD1
VDD
VDD
NVC
C_CR
M
NVC
C_ML
B
NVC
C_CS
I
VDD
PHY2
_VDD
SD1_
DATA
0
TDO
TMS
TCK
USBP
HY1_
VSSA
_BIA
S
USBP
HY1_
RREF
USBP
HY1_
VDDA
_BIA
S
R
T
FEC_
TX_E
N
FEC_
RX_D
V
ATA_
DMA
RQ
ATA_
DATA
15
ATA_
BUFF
_EN
ATA_
RESE
T_B
ATA_
CS1
CSPI
1_SPI
_RDY
VSTB
Y
CLK_
MOD
E1
GPIO
1_0
COM
PARE
SD2_
DATA
1
CSI_
VSYN
C
CSI_
D11
TRST
B
VSS
OSC2
4M_V
SS
OSC2
4M_V
DD
EXTA
L24M
T
U
RTS1
RXD1
ATA_
DATA
12
ATA_
DATA
8
ATA_
DATA
3
ATA_I
ORDY
USB
OTG_
OC
CSPI
1_SS
1
BOOT
_MO
DE1
RESE
T_IN_
B
GPIO
2_0
SD2_
DATA
3
SD2_
CMD
CSI_
D14
CSI_
D8
SD1_
DATA
1
SJC_
MOD
RTCK
OSC_
AUDI
O_VS
S
XTAL
24M
U
V
ATA_
DA1
ATA_I
NTR
Q
ATA_
DATA
10
ATA_
DATA
6
ATA_
DATA
2
ATA_
DMA
CK
ATA_
CS0
EXT_
ARM
CLK
CSPI
1_MI
SO
CLKO
GPIO
3_0
CAPT
URE
SD2_
DATA
0
CSI_
HSYN
C
CSI_
D13
CSI_
D10
SD1_
DATA
3
SD1_
CLK
XTAL
_AUD
IO
OSC_
AUDI
O_VD
D
V
W
ATA_
DATA
14
ATA_
DATA
13
ATA_
DATA
9
ATA_
DATA
5
ATA_
DATA
1
ATA_
DIOW
USB
OTG_
PWR
CSPI
1_SC
LK
CSPI
1_MO
SI
BOOT
_MO
DE0
POR_
B
MLB_
SIG
MLB_
CLK
SD2_
CLK
CSI_
MCLK
CSI_
D12
CSI_
D9
SD1_
DATA
2
DE_B
EXTA
L_AU
DIO
W
Y
VSS
ATA_
DATA
11
ATA_
DATA
7
ATA_
DATA
4
ATA_
DATA
0
ATA_
DIOR
TEST
_MO
DE
CSPI
1_SS
0
POW
ER_F
AIL
CLK_
MOD
E0
GPIO
1_1
WDO
G_RS
T
MLB_
DAT
SD2_
DATA
2
CSI_
PIXC
LK
CSI_
D15
USBP
HY2_
DM
USBP
HY2_
DP
SD1_
CMD
VSS
Y
See Table 91 for pins unavailable in the MCIMX351 SoC.
MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1
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Preliminary—Subject to Change Without Notice
135
6
Product Documentation
All related product documentation for the i.MX35 processor is located at http://www.freescale.com/imx.
7
Revision History
Table 93 shows the revision history of this document.
Table 93. MCIMX35 Data Sheet Revision History
Revision
Number
Date
Substantive Change(s)
1
12/2008
• Section 4.3.1, “Powering Up”: In the power-up sequence, inserted the step, “Wait 32 μs,” after step 2,
and inserted as the second-to-last step, “Wait 100 μs.”
• Section 4.7, “Module-Level AC Electrical Specifications”: Updated NFC, SDRAM and mDDR SDRAM
timing. Inserted DDR2 SDRAM timing.
0
10/2008
Initial public release
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Document Number: MCIMX35SR2AEC
Rev. 1
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Preliminary—Subject to Change Without Notice
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