CY7C1371S
18-Mbit (512K × 36) Flow-Through SRAM
with NoBL™ Architecture
18-Mbit (512K × 36) Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
■
No Bus Latency (NoBL) architecture eliminates dead cycles
between write and read cycles
■
Supports up to 133-MHz bus operations with zero wait states
■
Data is transferred on every clock
■
Pin-compatible and functionally equivalent to ZBT™ devices
■
Internally self-timed output buffer control to eliminate the need
to use OE
■
Registered inputs for flow through operation
■
Byte Write capability
■
3.3 V/2.5 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■
Clock Enable (CEN) pin to enable clock and suspend operation
■
Synchronous self-timed writes
■
Asynchronous Output Enable
■
Available in JEDEC-standard Pb-free 100-pin TQFP, and non
Pb-free 119-ball BGA
■
Three chip enables for simple depth expansion
■
Automatic Power down feature available using ZZ mode or CE
deselect
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
Burst Capability – linear or interleaved burst order
■
Low standby power
The CY7C1371S is a 3.3 V, 512K × 36 Synchronous flow through
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations with no wait state insertion.
The CY7C1371S is equipped with the advanced No Bus Latency
(NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This
feature dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent Write-Read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Description
133 MHz
Unit
Maximum Access Time
6.5
ns
Maximum Operating Current
210
mA
Maximum CMOS Standby Current
70
mA
Cypress Semiconductor Corporation
Document Number: 001-43826 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 18, 2016
CY7C1371S
Logic Block Diagram – CY7C1371S
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW B
BW C
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
BW D
WE
OE
CE1
CE2
CE3
ZZ
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
DQP C
DQP D
E
E
READ LOGIC
SLEEP
CONTROL
Document Number: 001-43826 Rev. *F
Page 2 of 29
CY7C1371S
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Burst Read Accesses .................................................. 7
Single Write Accesses ................................................. 7
Burst Write Accesses .................................................. 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10
Disabling the JTAG Feature ...................................... 10
Test Access Port (TAP) ............................................. 10
PERFORMING A TAP RESET .................................. 10
TAP REGISTERS ...................................................... 10
TAP Instruction Set ................................................... 10
TAP Controller State Diagram ....................................... 12
TAP Controller Block Diagram ...................................... 13
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 14
3.3 V TAP AC Test Conditions ....................................... 15
3.3 V TAP AC Output Load Equivalent ......................... 15
2.5 V TAP AC Test Conditions ....................................... 15
2.5 V TAP AC Output Load Equivalent ......................... 15
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 15
Document Number: 001-43826 Rev. *F
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Identification Codes ....................................................... 16
Boundary Scan Order .................................................... 17
Maximum Ratings ........................................................... 18
Operating Range ............................................................. 18
Electrical Characteristics ............................................... 18
Capacitance .................................................................... 19
Thermal Resistance ........................................................ 19
AC Test Loads and Waveforms ..................................... 19
Switching Characteristics .............................................. 20
Switching Waveforms .................................................... 21
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagrams .......................................................... 25
Acronyms ........................................................................ 27
Document Conventions ................................................. 27
Units of Measure ....................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
Page 3 of 29
CY7C1371S
Pin Configurations
A
42
43
44
45
46
47
48
49
50
NC/72M
A
A
A
A
A
A
A
41
NC/36M
40
37
A0
VSS
36
A1
VDD
35
A
39
34
A
NC/144M
33
A
38
32
NC/288M
31
Document Number: 001-43826 Rev. *F
81
A
82
A
83
A
84
ADV/LD
90
85
VSS
91
OE
VDD
92
86
CE3
93
CEN
BWA
94
WE
BWB
95
88
BWC
96
CLK
BWD
97
89
CE1
CE2
A
98
87
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1371S
A
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 4 of 29
CY7C1371S
Pin Configurations (continued)
Figure 2. 119-ball BGA (14 × 22 × 2.4 mm) pinout
CY7C1371S (512K × 36)
A
1
VDDQ
2
A
3
A
4
A
5
A
6
A
7
VDDQ
B
C
NC/576M
NC/1G
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
D
E
DQC
DQC
DQPC
DQC
VSS
VSS
NC
CE1
VSS
VSS
DQPB
DQB
DQB
DQB
F
VDDQ
DQC
VSS
VSS
DQB
VDDQ
G
H
J
K
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
NC
VSS
BWB
VSS
NC
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
BWA
VSS
DQA
DQA
DQA
VDDQ
VSS
DQA
DQA
L
DQD
DQD
M
VDDQ
DQD
BWD
VSS
N
DQD
DQD
VSS
OE
A
WE
VDD
CLK
NC
CEN
A1
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC/144M
A
MODE
VDD
NC
A
NC/288M
T
U
NC
VDDQ
NC/72M
TMS
A
TDI
A
TCK
A
TDO
NC/36M
NC
ZZ
VDDQ
Document Number: 001-43826 Rev. *F
Page 5 of 29
CY7C1371S
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the
Synchronous CLK. A[1:0] are fed to the two-bit burst counter.
InputByte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the
BWA, BWB,
BWC, BWD Synchronous rising edge of CLK.
WE
InputWrite Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
Synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH
Synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a
new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select/deselect the device.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select/deselect the device.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select/deselect the device.
OE
Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block inside
InputAsynchronou the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
s
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
CEN
InputClock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the Clock signal is masked. While deasserting CEN does not deselect the
device, use CEN to extend the previous cycle when required.
ZZ
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with
InputAsynchronou data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an internal
pull down.
s
DQs
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and
DQP[A:D] are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the device
is deselected, regardless of the state of OE.
DQPX
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs.
Synchronous
MODE
VDD
VDDQ
VSS
TDO
Input Strap
Pin
Mode Input. Selects the Burst Order of the Device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved
burst sequence.
Power Supply Power Supply Inputs to the Core of the Device.
I/O Power
Supply
Ground
Power Supply for the I/O Circuitry.
Ground for the Device.
JTAG serial Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature
output
is not being used, this pin must be left unconnected. This pin is not available on TQFP packages.
Synchronous
Document Number: 001-43826 Rev. *F
Page 6 of 29
CY7C1371S
Pin Definitions (continued)
Name
I/O
Description
TDI
JTAG serial Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available
input
Synchronous on TQFP packages.
TMS
JTAG serial Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Synchronous
TCK
JTAGClock
Clock Input to the JTAG Circuitry. If the JTAG feature is not being used, this pin must be connected
to VSS. This pin is not available on TQFP packages.
NC
–
No Connects. Not internally connected to the die. NC/(36M, 72M, 144M, 288M, 576M, 1G) are address
expansion pins and are not internally connected to the die.
Functional Overview
The CY7C1371S is a synchronous flow through burst SRAM
designed specifically to eliminate wait states during Write-Read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the Clock Enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns
(133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the Write Enable (WE). BWX can be used to conduct byte write
operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD must be driven LOW after the device has been
deselected to load a new address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied at
clock rise:
■
CEN is asserted LOW
■
CE1, CE2, and CE3 are ALL asserted active
■
The Write Enable input signal WE is deasserted HIGH
■
ADV/LD is asserted LOW.
The address presented to the address inputs is latched into the
Address Register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
Document Number: 001-43826 Rev. *F
device to drive out the requested data. On the subsequent clock,
another operation (Read/Write/Deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output is tri-stated immediately.
Burst Read Accesses
The CY7C1371S has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
Reads without reasserting the address inputs. ADV/LD must be
driven LOW to load a new address into the SRAM, as described
in the Single Read Accesses section. The sequence of the burst
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst
counter regardless of the state of chip enable inputs or WE. WE
is latched at the beginning of a burst cycle. Therefore, the type
of access (Read or Write) is maintained throughout the burst
sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address bus is
loaded into the Address Register. The write signals are latched
into the Control Logic block. The data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for byte write operations, see truth table for details)
inputs is latched into the device and the write is complete.
Additional accesses (Read/Write/Deselect) can be initiated on
this cycle.
The data written during the Write operation is controlled by BWX
signals. The CY7C1371S provides byte write capability that is
described in the truth table. Asserting the Write Enable input
(WE) with the selected Byte Write Select input selectively writes
to only the desired bytes. Bytes not selected during a byte write
operation remains unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included to greatly simplify
Read/Modify/Write sequences, which can be reduced to simple
byte write operations.
Page 7 of 29
CY7C1371S
Because the CY7C1371S is a common I/O device, data must not
be driven into the device while the outputs are active. The Output
Enable (OE) can be deasserted HIGH before presenting data to
the DQs and DQPX inputs. Doing so tri-states the output drivers.
As a safety precaution, DQs and DQPX are automatically
tri-stated during the data portion of a write cycle, regardless of
the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
Burst Write Accesses
00
01
10
11
The CY7C1371S has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
Write operations without reasserting the address inputs. ADV/LD
must be driven LOW to load the initial address, as described in
the Single Write Access section. When ADV/LD is driven HIGH
on the subsequent clock rise, the Chip Enables (CE1, CE2, and
CE3) and WE inputs are ignored and the burst counter is
incremented. The correct BWX inputs must be driven in each
cycle of the burst write, to write the correct bytes of data.
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1:A0
Linear Burst Address Table
(MODE = GND)
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
80
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-43826 Rev. *F
Page 8 of 29
CY7C1371S
Truth Table
The truth table for CY7C1371S follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
Deselect Cycle
None
H
X
X
L
L
X
X
X
L
L–>H
Tri-State
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L–>H
Tri-State
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L–>H
Tri-State
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L–>H
Tri-State
Read Cycle (Begin Burst)
External
L
H
L
L
L
H
X
L
L
L–>H Data Out (Q)
Next
X
X
X
L
H
X
X
L
L
L–>H Data Out (Q)
External
L
H
L
L
L
H
X
H
L
L–>H
Tri-State
Next
X
X
X
L
H
X
X
H
L
L–>H
Tri-State
External
L
H
L
L
L
L
L
X
L
L–>H Data In (D)
Write Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L–>H Data In (D)
NOP/Write Abort (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L–>H
Tri-State
Write Abort (Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L–>H
Tri-State
Current
X
X
X
L
X
X
X
X
H
L–>H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Partial Truth Table for Read/Write
Function (CY7C1371S) [1, 2, 8]
WE
BWA
BWB
BWC
BWD
Read
H
X
X
X
X
Write No bytes written
L
H
H
H
H
Write Byte A – (DQA and DQPA)
L
L
H
H
H
Write Byte B – (DQB and DQPB)
L
H
L
H
H
Write Byte C – (DQC and DQPC)
L
H
H
L
H
Write Byte D – (DQD and DQPD)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = 0 signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired byte write selects
are asserted, see truth table for details.
2. Write is defined by BWX, and WE. See truth table for Read/Write.
3. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
4. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CEN = H, inserts wait states.
6. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE is
inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is based on which byte write is active.
Document Number: 001-43826 Rev. *F
Page 9 of 29
CY7C1371S
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1371S incorporates a serial boundary scan test
access port (TAP).This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic
levels.
The CY7C1371S contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
must be left unconnected. Upon power up, the device is up in a
reset state which does not interfere with the operation of the
device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 12. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Identification Codes on page 16).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
scans data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register.
Document Number: 001-43826 Rev. *F
Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 13. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 16.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Identification Codes on page 16. Three of these instructions are
listed as RESERVED and must not be used. The other five
instructions are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller is moved
into the Update-IR state.
Page 10 of 29
CY7C1371S
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the shift-DR controller state.
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is supplied a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO balls when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High Z
state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
Document Number: 001-43826 Rev. *F
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells prior to the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #85
(for 119-ball BGA package). When this scan cell, called the
“extest output bus tri-state,” is latched into the preload register
during the “Update-DR” state in the TAP controller, it directly
controls the state of the output (Q-bus) pins, when the EXTEST
is entered as the current instruction. When HIGH, it enables the
output buffers to drive the output bus. When LOW, this bit places
the output bus into a High Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is preset HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 11 of 29
CY7C1371S
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
0
1
EXIT1-DR
0
1
0
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 001-43826 Rev. *F
Page 12 of 29
CY7C1371S
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
Selection
Circuitry
TDO
31 30 29 . . . 2 1 0
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TAP CONTROLLER
TMS
Document Number: 001-43826 Rev. *F
Page 13 of 29
CY7C1371S
TAP Timing
Figure 3. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
Parameter [9, 10]
Description
Min
Max
Unit
Clock
tTCYC
TCK Clock Cycle Time
50
–
ns
tTF
TCK Clock Frequency
–
20
MHz
tTH
TCK Clock HIGH time
20
–
ns
tTL
TCK Clock LOW time
20
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
tTMSS
TMS Setup to TCK Clock Rise
5
–
ns
tTDIS
TDI Setup to TCK Clock Rise
5
–
ns
tCS
Capture Setup to TCK Rise
5
–
ns
tTMSH
TMS Hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
Output Times
Setup Times
Hold Times
Notes
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document Number: 001-43826 Rev. *F
Page 14 of 29
CY7C1371S
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse level ................................................. VSS to 2.5 V
Input rise and fall times ...................................................1 ns
Input rise and fall time ....................................................1 ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels ...................................... .1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [11]
Description
VOH1
Output HIGH Voltage
VOH2
Output HIGH Voltage
Conditions
Min
Max
Unit
IOH = –4.0 mA
VDDQ = 3.3 V
2.4
–
V
IOH = –1.0 mA
VDDQ = 2.5 V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
VDDQ = 3.3 V
–
0.4
V
VOL1
Output LOW Voltage
IOL = 8.0 mA
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
2.0
VDD + 0.3
V
VIH
Input HIGH Voltage
VDDQ = 3.3 V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VIL
Input LOW Voltage
VDDQ = 3.3 V
–0.5
0.7
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
IX
Input Load Current
GND < VIN < VDDQ
Note
11. All voltages referenced to VSS (GND).
Document Number: 001-43826 Rev. *F
Page 15 of 29
CY7C1371S
Identification Register Definitions
CY7C1371S
(512K × 36)
Instruction Field
Revision Number (31:29)
000
Device Depth (28:24)
01011
Description
Describes the version number
Reserved for internal use
Device Width (23:18)
001001
Defines memory type and architecture
Cypress Device ID (17:12)
100101
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
ID Register Presence Indicator (0)
1
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction
3
Bypass
1
ID
32
Boundary Scan Order (119-ball BGA package)
85
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to High Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 001-43826 Rev. *F
Page 16 of 29
CY7C1371S
Boundary Scan Order
119-ball BGA [12, 13]
Bit #
Ball ID
Bit #
1
H4
T4
23
2
24
3
T5
25
4
T6
26
5
R5
6
L5
7
8
Ball ID
Bit #
Ball ID
Bit #
Ball ID
F6
45
G4
67
L1
E7
46
A4
68
M2
D7
47
G3
69
N1
H7
48
C3
70
P1
27
G6
49
B2
71
K1
28
E6
50
B3
72
L2
R6
29
D6
51
A3
73
U6
30
C7
52
C2
74
N2
P2
9
R7
31
B7
53
A2
75
R3
10
T7
32
C6
54
B1
76
T1
11
P6
33
A6
55
C1
77
R1
12
N7
34
C5
56
D2
78
T2
13
M6
35
B5
57
E1
79
L3
14
L7
36
G5
58
F2
80
R2
15
K6
37
B6
59
G1
81
T3
16
P7
38
D4
60
H2
82
L4
17
N6
39
B4
61
D1
83
N4
18
L6
40
F4
62
E2
84
P4
19
K7
41
M4
63
G2
85
Internal
20
J5
42
A5
64
H1
21
H6
43
K4
65
J3
22
G7
44
E4
66
2K
Notes
12. Balls which are NC (No Connect) are pre-set LOW.
13. Bit# 85 is pre-set HIGH.
Document Number: 001-43826 Rev. *F
Page 17 of 29
CY7C1371S
Maximum Ratings
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch up Current .................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V
Range
Ambient
Temperature
Commercial
0 °C to +70 °C
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
VDD
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [14, 15]
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
[14]
Test Conditions
Min
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
for 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
2.0
VDD + 0.3
V
for 2.5 V I/O
1.7
VDD + 0.3
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
VIH
Input HIGH Voltage
VIL
Input LOW Voltage [14]
–0.3
0.7
V
IX
Input Leakage Current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input Current of MODE
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
Input Current of ZZ
IDD
[16]
for 3.3 V I/O
Input = VSS
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5 ns cycle,
133 MHz
–
210
mA
ISB1
Automatic CE Power down
Current – TTL Inputs
VDD = Max, Device Deselected, 7.5 ns cycle,
VIN VIH or VIN VIL,
133 MHz
f = fMAX, inputs switching
–
140
mA
ISB2
Automatic CE Power down
Current – CMOS Inputs
VDD = Max, Device Deselected, 7.5 ns cycle,
VIN 0.3V or VIN > VDD – 0.3 V, 133 MHz
f = 0, inputs static
–
70
mA
ISB3
Automatic CE Power down
Current – CMOS Inputs
VDD = Max, Device Deselected, 7.5 ns cycle,
VIN 0.3 V or VIN > VDDQ – 0.3 V, 133 MHz
f = fMAX, inputs switching
–
130
mA
ISB4
Automatic CE Power down
Current – TTL Inputs
VDD = Max, Device Deselected, 7.5 ns cycle,
VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz
f = 0, inputs static
–
80
mA
Notes
14. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
15. TPower up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
16. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-43826 Rev. *F
Page 18 of 29
CY7C1371S
Capacitance
Parameter [17]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/Output capacitance
100-pin TQFP 119-ball BGA
Package
Package
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
Unit
5
8
pF
5
8
pF
5
8
pF
Thermal Resistance
Parameter [17]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
100-pin TQFP 119-ball BGA
Package
Package
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, according to
EIA/JESD51.
Unit
28.66
23.8
C/W
4.08
6.2
C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1ns
1ns
(c)
(b)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 1538
VT = 1.25 V
(a)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
1ns
1ns
(c)
Note
17. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-43826 Rev. *F
Page 19 of 29
CY7C1371S
Switching Characteristics
Over the Operating Range
Parameter [18, 19]
Description
tPOWER[20]
133 MHz
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock Cycle Time
7.5
–
ns
tCH
Clock HIGH
2.1
–
ns
tCL
Clock LOW
2.1
–
ns
Output Times
tCDV
Data Output Valid After CLK Rise
–
6.5
ns
tDOH
Data Output Hold After CLK Rise
2.0
–
ns
2.0
–
ns
–
4.0
ns
–
3.2
ns
0
–
ns
–
4.0
ns
[21, 22, 23]
tCLZ
Clock to Low Z
tCHZ
Clock to High Z [21, 22, 23]
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
OE LOW to Output Low Z
[21, 22, 23]
OE HIGH to Output High Z
[21, 22, 23]
Setup Times
tAS
Address Setup Before CLK Rise
1.5
–
ns
tALS
ADV/LD Setup Before CLK Rise
1.5
–
ns
tWES
WE, BWX Setup Before CLK Rise
1.5
–
ns
tCENS
CEN Setup Before CLK Rise
1.5
–
ns
tDS
Data Input Setup Before CLK Rise
1.5
–
ns
tCES
Chip Enable Setup Before CLK Rise
1.5
–
ns
tAH
Address Hold After CLK Rise
0.5
–
ns
tALH
ADV/LD Hold After CLK Rise
0.5
–
ns
tWEH
WE, BWX Hold After CLK Rise
0.5
–
ns
tCENH
CEN Hold After CLK Rise
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.5
–
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
–
ns
Hold Times
Notes
18. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
19. Test conditions shown in (a) of Figure 4 on page 19 unless otherwise noted.
20. This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD(minimum) initially, before a read or write operation can be initiated.
21. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 19. Transition is measured ±200 mV from steady-state voltage.
22. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z
prior to Low Z under the same system conditions.
23. This parameter is sampled and not 100% tested.
Document Number: 001-43826 Rev. *F
Page 20 of 29
CY7C1371S
Switching Waveforms
Figure 5. Read/Write Waveforms [24, 25, 26]
1
2
3
t CYC
4
5
A3
A4
6
7
8
9
A5
A6
A7
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW X
A1
ADDRESS
t AS
A2
t CDV
t AH
t DOH
t CLZ
DQ
D(A1)
t DS
D(A2)
Q(A3)
D(A2+1)
t OEV
Q(A4+1)
Q(A4)
t OELZ
W RITE
D(A1)
W RITE
D(A2)
D(A5)
Q(A6)
D(A7)
W RITE
D(A7)
DESELECT
t OEHZ
t DH
OE
COM M AND
t CHZ
BURST
W RITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
t DOH
W RITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
24. For this waveform ZZ is tied LOW.
25. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 001-43826 Rev. *F
Page 21 of 29
CY7C1371S
Switching Waveforms (continued)
Figure 6. NOP, STALL AND DESELECT Cycles [27, 28, 29]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A5
t CHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
t DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Notes
27. For this waveform ZZ is tied LOW.
28. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
29. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 001-43826 Rev. *F
Page 22 of 29
CY7C1371S
Switching Waveforms (continued)
Figure 7. ZZ Mode Timing [30, 31]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
30. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
31. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-43826 Rev. *F
Page 23 of 29
CY7C1371S
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available.For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
Package
Diagram
Ordering Code
Part and Package Type
CY7C1371S-133AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1371S-133BGC
51-85115 119-ball BGA (14 × 22 × 2.4 mm)
Operating
Range
Commercial
Ordering Code Definitions
CY
7
C 1371 S - 133 XX
X
C
Temperature Range:
C = Commercial
Pb-free
Package Type: XX = A or BG
A = 100-pin TQFP
BG = 119-ball BGA
Frequency Range: 133 MHz
Die Revision
Part Identifier: 1371 = FT, 512Kb × 36 (18 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-43826 Rev. *F
Page 24 of 29
CY7C1371S
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 001-43826 Rev. *F
Page 25 of 29
CY7C1371S
Package Diagrams (continued)
Figure 9. 119-ball BGA (14 × 22 × 2.4 mm) BG119 Package Outline, 51-85115
51-85115 *D
Document Number: 001-43826 Rev. *F
Page 26 of 29
CY7C1371S
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BGA
Ball Grid Array
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
I/O
Input/Output
MHz
megahertz
JTAG
Joint Test Action Group
µA
microampere
LSB
Least Significant Bit
mA
milliampere
MSB
Most Significant Bit
mm
millimeter
OE
Output Enable
ms
millisecond
SRAM
Static Random Access Memory
mV
millivolt
TAP
Test Access Port
ns
nanosecond
TCK
Test Clock
TMS
Test Mode Select
TDI
Test Data-In
TDO
Test Data-Out
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 001-43826 Rev. *F
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 27 of 29
CY7C1371S
Document History Page
Document Title: CY7C1371S, 18-Mbit (512K × 36) Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-43826
Rev.
ECN No.
Issue Date
Orig. of
Change
**
1898286
See ECN
VKN /
AESA
New data sheet.
*A
2082246
See ECN
JASM
Changed status from Preliminary to Final.
*B
2897885
03/23/10
NJY
Updated Ordering Information (Removed inactive parts).
Updated Package Diagrams.
*C
3203729
03/23/2011
NJY
Updated Ordering Information (Updated part numbers) and added Ordering
Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated to new template.
*D
3571224
04/03/2012
PRIT
Updated Features (Removed 165-ball FBGA package and Pb-free 119-ball
BGA related information).
Updated Functional Description (Removed CY7C1373S related information,
removed the Note For best practices or recommendations, please refer to the
Cypress application note AN1064, SRAM System Design Guidelines on
www.cypress.com.” and its reference).
Updated Selection Guide (Removed 100 MHz frequency related information).
Removed Logic Block Diagram – CY7C1373S.
Updated Pin Configurations (Removed CY7C1373S related information, and
165-ball FBGA package related information).
Updated Functional Overview (Removed CY7C1373S related information).
Updated Truth Table (Removed CY7C1373S related information).
Removed Partial Truth Table for Read/Write (Corresponding to CY7C1373S).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed CY7C1373S
related information).
Updated Identification Register Definitions (Removed CY7C1373S related
information).
Updated Scan Register Sizes (Removed 165-ball FBGA package related
information and removed Bit Size (× 18) column).
Removed Boundary Scan Order (Corresponding to 165-ball FBGA package).
Updated Operating Range (Removed Industrial Temperature range).
Updated Electrical Characteristics (Removed 100 MHz frequency related
information).
Updated Capacitance (Removed 165-ball FBGA package related information).
Updated Thermal Resistance (Removed 165-ball FBGA package related
information).
Updated Switching Characteristics (Removed 100 MHz frequency related
information).
Updated Package Diagrams (Removed 165-ball FBGA package related
information).
Replaced all instances of IO with I/O across the document.
*E
3978170
04/22/2013
PRIT
Updated Package Diagrams:
spec 51-85115 – Changed revision from *C to *D.
Completing Sunset Review.
*F
5181234
03/18/2016
PRIT
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
Document Number: 001-43826 Rev. *F
Description of Change
Page 28 of 29
CY7C1371S
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
Wireless/RF
cypress.com/psoc
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2008-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-43826 Rev. *F
Revised March 18, 2016
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc.
Page 29 of 29