TI1 ISO7310CDR Robust emc, low power, single channel digital isolator Datasheet

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ISO7310C, ISO7310FC
SLLSEI8D – JUNE 2014 – REVISED APRIL 2015
ISO7310x Robust EMC, Low Power, Single Channel Digital Isolator
1 Features
3 Description
•
•
•
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ISO7310x provide galvanic isolation up to 3000 VRMS
for 1 minute per UL and 4242 VPK per VDE. These
devices have one isolated channel comprised of a
logic input and output buffer separated by a silicon
dioxide (SiO2) insulation barrier. Used in conjunction
with isolated power supplies, ISO7310x prevent noise
currents on a data bus or other circuit from entering
the local ground and interfering with or damaging
sensitive circuitry. These devices have integrated
noise filters for harsh industrial environment where
short noise pulses may be present at the device input
pins. ISO7310x have TTL input thresholds and
operate from 3 V to 5.5 V supply levels. Through
innovative chip design and layout techniques,
electromagnetic compatibility of ISO7310x has been
significantly enhanced to enable system-level ESD,
EFT, Surge and Emissions compliance.
1
•
•
•
•
•
•
•
•
•
Signaling Rate: 25 Mbps
Integrated Noise Filter at the Input
Default Output 'High' and 'Low' Options
Low Power Consumption: Typical ICC
– 1.9 mA at 1 Mbps, 3.8 mA at 25 Mbps (5V
Supplies)
– 1.4 mA at 1 Mbps, 2.6 mA at 25 Mbps (3.3V
Supplies)
Low Propagation Delay: 32 ns Typical (5V
Supplies)
3.3 V and 5 V Level Translation
Wide TA Range Specified: –40°C to 125°C
65 KV/μs Transient Immunity, Typical (5V
Supplies)
Robust Electromagnetic Compatibility (EMC)
– System-level ESD, EFT, and Surge Immunity
– Low Emissions
Isolation Barrier Life: > 25 Years
Operates from 3.3 V and 5 V Supplies
Narrow Body SOIC-8 Package
Safety and Regulatory Approvals:
– 4242 VPK Isolation per DIN V VDE V 0884-10
and DIN EN 61010-1
– 3000 VRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A,
IEC 60950-1 and IEC 61010-1 End Equipment
Standards
– CQC Certification per GB4943.1-2011
Device Information(1)
PART NUMBER
ISO7310C
ISO7310FC
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4,90mm x 3,91mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCC2
VCC1
Isolation
Capacitor
IN
OUT
GND1
GND2
2 Applications
•
Opto-Coupler Replacement in:
– Industrial FieldBus
– ProfiBus
– ModBus
– DeviceNet™ Data Buses
– Servo Control Interface
– Motor Control
– Power Supplies
– Battery Packs
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7310C, ISO7310FC
SLLSEI8D – JUNE 2014 – REVISED APRIL 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5
5
5
5
6
6
7
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
15
Applications and Implementation ...................... 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 PCB Material ......................................................... 19
11.2 Layout Guidelines ................................................. 19
11.3 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1 Trademarks ........................................................... 20
12.2 Electrostatic Discharge Caution ............................ 20
12.3 Glossary ................................................................ 20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision C (March 2015) to Revision D
Page
•
Added "and DINEN 61010-1" to the 4242 VPK in the Features .............................................................................................. 1
•
Deleted "(Approval Pending)" from the CSA Component Acceptance list item in the Features ............................................ 1
•
Deleted IEC from the section title: Insulation and Safety-Related Specifications for D-8 Package .................................... 12
•
Changed the CTI Test Conditions in Insulation and Safety-Related Specifications for D-8 Package ................................ 12
•
Changed VISO Test Condition in the Insulation Characteristics table .................................................................................. 13
•
Changed column CSA in the Regulatory Information table.................................................................................................. 13
Changes from Revision B (September 2014) to Revision C
Page
•
Changed Features From: Integrated Noise Filter on the Input pin To: Integrated Noise Filter at the Input........................... 1
•
Added Features - Default Output 'High' and 'Low' Options .................................................................................................... 1
•
Changed the DIN V VDE 0884-10 To: DIN V VDE V 0884-10 in the Features ..................................................................... 1
•
Changed Features From: 3 KVRMS Isolation To: 3000 VRMS Isolation .................................................................................... 1
•
Added "(Approval Pending)" to the CSA Component Acceptance list item in the Features .................................................. 1
•
Changed Features From: GB4943.1-2011 CQC Certification To: CQC Certification per GB4943.1-2011............................ 1
•
Changed the Simplified Schematic: GND1 To: GNDI and GND2 To GNDO......................................................................... 1
•
Changed the Handling Ratings to ESD Ratings table and updated guidelines ..................................................................... 5
•
Changed the CTI MIN value in Insulation and Safety-Related Specifications for D-8 Package From: >400 V To: 400 V .. 12
•
Added "DT1" to the Minimum internal gap in Insulation and Safety-Related Specifications for D-8 Package ................... 12
•
Changed the DTI MIN value in Insulation and Safety-Related Specifications for D-8 Package From: 0.014 mm To:
13 µM.................................................................................................................................................................................... 12
•
Changed the RIO Test Condition in Insulation and Safety-Related Specifications for D-8 Package From: TA < 100°C
To: TA = 25°C ....................................................................................................................................................................... 12
•
Changed the RIO Test Condition in Insulation and Safety-Related Specifications for D-8 Package From: TA ≤ max
To: TA = 125°C ..................................................................................................................................................................... 12
•
Changed DIN V VDE 0884-10 To: DIN V VDE V 0884-10 in the Insulation Characteristics .............................................. 13
•
Added VIOSM to the Insulation Characteristics table ............................................................................................................ 13
2
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•
Changed RS Test Conditions in Insulation Characteristics From: TS To: TS = 150°C ......................................................... 13
•
Changed the Regulatory Information table, VDE Certified From: DIN V VDE 0884-10 To: DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07 ............................................................................ 13
•
Changed the Regulatory Information table, deleted (Approval Pending) statement ............................................................ 13
•
Changed the Regulatory Information table, CQC Certified number From: CQC14001109540 To: CQC15001121656 ...... 13
•
Changed title From: " IEC Safety Limiting Values" To: Safety Limiting Values .................................................................. 14
•
Changed Table 2 Header information to include device number for the OUT column. Added Note 3. .............................. 15
•
Changed Figure 14 to include a diode at VCC1 on the Input circuit ...................................................................................... 15
•
Changed Figure 15 .............................................................................................................................................................. 16
•
Added Figure 16 .................................................................................................................................................................. 17
Changes from Revision A (July 2014) to Revision B
Page
•
Added device ISO7310FC ..................................................................................................................................................... 1
•
Changed Feature From: 4242 VPK Isolation per DIN EN 60747-5-5 (VDE 0884-5) To: 4242 VPK Isolation per DIN V
VDE 0884-10 .......................................................................................................................................................................... 1
•
Deleted "All Agencies Approvals Planned" from the Features Safety and Regulatory Approvals: ........................................ 1
•
Replaced Figure 10 ............................................................................................................................................................. 10
•
Changed DIN EN 60747-5-5 To: DIN V VDE 0884-10 in the Insulation Characteristics .................................................... 13
•
Changed DIN EN 60747-5-5 (VDE 0884-5) To: DIN V VDE 0884-10 in the Regulatory Information table ......................... 13
•
Added a NOTE in the Application Information section ........................................................................................................ 16
Changes from Original (March 2014) to Revision A
Page
•
Changed from a 1 page Product Preview to the full data sheet ............................................................................................ 1
•
Added Features - GB4943.1-2011 CQC Certification ........................................................................................................... 1
•
Changed the Description to include: "Through innovative chip design..." .............................................................................. 1
•
Changed the Simplified Schematic ........................................................................................................................................ 1
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ISO7310C, ISO7310FC
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5 Pin Configuration and Functions
VCC1
1
IN
2
VCC1
3
GND1
4
Isolation
D PACKAGE
(TOP VIEW)
8
VCC2
7
GND2
6
OUT
5
GND2
Pin Functions
PIN
NAME
VCC1
NUMBER
I/O
DESCRIPTION
1, 3
–
Power supply, VCC1
2
I
Input
GND1
4
–
Ground connection for VCC1
GND2
5, 7
–
Ground connection for VCC2
OUT
6
O
Output
VCC2
8
–
Power supply, VCC2
IN
4
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Supply voltage (2)
Voltage
(2)
MIN
MAX
VCC1 , VCC2
–0.5
6
IN, OUT
–0.5 VCC+0.5 (3)
Output current
IO
Junction temperature
TJ
Storage temperature
Tstg
(1)
–65
UNIT
V
V
±15
mA
150
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
Maximum voltage must not exceed 6 V.
(2)
(3)
6.2 ESD Ratings
MAX
VESD
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
TYP
MAX
Supply voltage
IOH
High-level output current
IOL
Low-level output current
VIH
High-level input voltage
2
5.5
V
VIL
Low-level input voltage
0
0.8
V
tui
Input pulse duration
1 / tui
Signaling rate
25
Mbps
136
°C
125
°C
TJ
(1)
TA
(1)
3
5.5
UNIT
VCC1, VCC2
–4
4
40
Junction temperature
-40
mA
ns
0
Ambient temperature
V
mA
25
To maintain the recommended operating conditions for TJ, see the Thermal Information table.
6.4 Thermal Information
D PACKAGE
THERMAL METRIC (1)
(8) PINS
RθJA
Junction-to-ambient thermal resistance
119.9
RθJCtop
Junction-to-case (top) thermal resistance
65.2
RθJB
Junction-to-board thermal resistance
61.3
ψJT
Junction-to-top characterization parameter
19.3
ψJB
Junction-to-board characterization parameter
60.7
RθJCbot
Junction-to-case (bottom) thermal resistance
N/A
PD
Maximum power dissipation
PD1
Power dissipation by Side-1
PD2
Power dissipation by Side-2
(1)
UNIT
°C/W
34
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 12.5 MHz 50% duty-cycle square wave
7.9
mW
26.1
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 9
TEST CONDITIONS
VCC2 – 0.5
4.7
IOH = –20 μA; see Figure 9
VCC2 – 0.1
5
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IN = VCC
IIL
Low-level input current
IN = 0 V
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 11.
MAX
V
IOL = 4 mA; see Figure 9
0.2
0.4
IOL = 20 μA; see Figure 9
0
0.1
480
V
mV
10
μA
μA
–10
25
UNIT
65
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
Supply current for VCC1 and VCC2
ICC2
ICC1
ICC2
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
10 Mbps
CL = 15pF
25 Mbps
CL = 15pF
0.3
0.6
1.6
2.4
0.5
1
2.2
3.2
0.8
1.3
3
4.2
mA
6.6 Switching Characteristics
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(pp)
(2)
TEST CONDITIONS
See Figure 9
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
6
TYP
MAX
20
32
58
ns
4
ns
24
ns
Part-to-part skew time
tr
(1)
(2)
MIN
2.5
See Figure 9
See Figure 10
UNIT
ns
2
ns
7.5
μs
Also known as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.7 Electrical Characteristics
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 9
TEST CONDITIONS
VCC2 – 0.5
3
IOH = –20 μA; see Figure 9
VCC2 – 0.1
3.3
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IN = VCC
IIL
Low-level input curre
IN = 0 V
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 11
MAX
UNIT
V
IOL = 4 mA; see Figure 9
0.2
0.4
IOL = 20 μA; see Figure 9
0
0.1
450
V
mV
10
μA
μA
-10
25
50
kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement)
ICC1
DC to 1 Mbps
ICC2
ICC1
Supply current for VCC1 and VCC2
ICC2
ICC1
ICC2
DC Input: VI = VCC or 0 V,
AC Input: CL = 15pF
10 Mbps
CL = 15pF
25 Mbps
CL = 15pF
0.2
0.4
1.2
1.8
0.3
0.5
1.6
2.2
0.5
0.8
2.1
3
mA
6.8 Switching Characteristics
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(pp)
(2)
TEST CONDITIONS
See Figure 9
TYP
MAX
22
36
67
ns
3.5
ns
28
ns
Part-to-part skew time
tr
Output signal rise time
tf
Output signal fall time
tfs
Fail-safe output delay time from input power loss
(1)
(2)
MIN
See Figure 9
See Figure 10
3.2
UNIT
ns
2.7
ns
7.4
μs
Also known as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.9 Typical Characteristics
3.5
2.5
2
1.5
1
0.5
ICC1 atat3.3
ICC2
5 VV
2.5
2
1.5
1
0.5
0
0
0
5
10
15
20
25
Data Rate (Mbps)
TA = 25°C
0
6
10
15
20
Data Rate (Mbps)
CL = 15 pF
TA = 25°C
25
C014
CL = No Load
Figure 2. Supply Current vs Data Rate (with No Load)
0.9
VCC at
VV
VCC
at 53.3
Low-Level Output Voltage (V)
VCC =at3.3
VCC
5 VV
5
5
C014
Figure 1. Supply Current vs Data Rate (with 15 pF Load)
High-Level Output Voltage (V)
ICC1
ICC2 atat53.3
V V
ICC2 atat3.3
ICC1
5 VV
ICC1 atat53.3
V V
ICC2
3
Supply Current (mA)
3
Supply Current (mA)
3.5
ICC1
ICC2 atat53.3
V V
ICC1
5 VV
ICC2 atat3.3
ICC2
ICC1 atat53.3
V V
ICC1 atat3.3
ICC2
5 VV
4
3
2
1
VCC
3.3VV
V
CC atat3.3
0.8
V
VCC
CC atat55VV
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
±15
±10
0
±5
High-Level Output Current (mA)
0
TA = 25°C
43
VCC
Rising
V
CC Rising
C014
tpHLtphl3.3
at 3.3 V
tpLHtphl5v
at 3.3 V
tpHLtplh3.3
at 5 V
tpLHtplh55v
at 5 V
41
V
VCC
Falling
CC Falling
Propagation Delay Time (ns)
Power Supply Undervoltage Threshold (V)
15
Figure 4. Low-Level Output Voltage vs Low-Level Output
Current
2.5
2.46
2.44
2.42
2.4
2.38
2.36
39
37
35
33
31
29
27
25
2.34
±40
±20
0
20
40
60
80
Free-Air Temperature (oC)
100
120
140
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±40
±5
30
65
Free-Air Temperature (oC)
C014
Figure 5. Power Supply Undervoltage Threshold vs Free-Air
Temperature
8
10
TA = 25°C
Figure 3. High-Level Output Voltage vs High-level Output
Current
2.48
5
Low-Level Output Current (mA)
C014
100
135
C014
Figure 6. Propagation Delay Time vs Free-Air Temperature
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Typical Characteristics (continued)
240
tGStgs3.3
at 5 V
tGStpgs5v
at 3.3 V
27
220
Pk-Pk Output Jitter (ps)
Input Glitch Suppression Time (ns)
29
25
23
21
19
17
200
180
160
140
Output Jitter at 3.3 V
120
15
Output Jitter at 5 V
100
±40
±5
30
65
100
Free-Air Temperature (oC)
135
0
5
10
15
20
Data Rate (Mbps)
C014
25
C014
TA = 25°C
Figure 7. Input Glitch Suppression Time vs Free-Air
Temperature
Figure 8. Output Jitter vs Data Rate
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Isolation Barrier
7 Parameter Measurement Information
IN
Input
Generator
(1)
VI
50 W
VCC1
VI
OUT
VO
50%
50%
0V
CL
tPLH
(2)
tPHL
90%
10%
50%
VO
50%
VOH
VOL
tr
tf
(1)
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
(2)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Switching Characteristic Test Circuit and Voltage Waveforms
VI
IN = 0 V (ISO7310C)
IN = VCC (ISO7310FC)
A.
VCC
ISOLATION BARRIER
VCC
IN
2.7 V
VI
OUT
0V
t fs
VO
fs high
VO
CL
NOTE A
VOH
50%
fs low V
OL
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
S1
IN
C = 0.1 μ F ±1%
Isolation Barrier
VCC1
GND1
VCC2
C = 0.1 μ F ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
(1)
CL
VOH or VOL
–
GND2
+ VCM –
(1)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Common-Mode Transient Immunity Test Circuit
10
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8 Detailed Description
8.1 Overview
The isolator in Figure 12 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25
Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter
gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which
then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can
be either above or below the common mode voltage VREF depending on whether the input bit transitioned from
0 to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic
(DCL) at the output of the HF channel comparator measures the durations between signal transients. If the
duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency
signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
8.2 Functional Block Diagram
Isolation Barrier
OSC
Low ± Frequency
Channel
(DC...100 kbps)
PWM
VREF
LPF
0
Polarity and
Threshold Selection
IN
OUT
1 S
High ± Frequency
Channel
(100 kbps ...25 Mbps )
VREF
DCL
Polarity and Threshold Selection
Figure 12. Conceptual Block Diagram of a Digital Capacitive Isolator
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter
(LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
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8.3 Feature Description
PRODUCT
ISO7310C
ISO7310FC
(1)
RATED ISOLATION
3000 VRMS / 4242 VPK
MAX DATA RATE
(1)
DEFAULT OUTPUT
High
25 Mbps
Low
See the Regulatory Information section for detailed Isolation Ratings
8.3.1 High Voltage Feature Description
8.3.1.1 Insulation and Safety-Related Specifications for D-8 Package
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4
mm
L(I02)
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
4
mm
CTI
Tracking resistance (comparative
tracking index)
DIN EN 60112 (VDE 0303-11); IEC 60112
DTI
Minimum internal gap (internal
clearance)
Distance through the insulation
RIO
Isolation resistance, input to
output (1)
CIO
Isolation capacitance, input to
output (1)
CI
Input capacitance (2)
(1)
(2)
400
V
13
µm
VIO = 500 V, TA = 25°C
>1012
Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
Ω
VIO = 0.4 sin (2πft), f = 1 MHz
0.5
pF
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
1.6
pF
All pins on each side of the barrier tied together creating a two-terminal device.
Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
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8.3.1.2 Insulation Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER (1)
SPECIFICATION
UNIT
VIOWM
Maximum isolation working voltage
TEST CONDITIONS
400
VRMS
VIORM
Maximum repetitive peak voltage per
DIN V VDE V 0884-10
566
VPK
Input-to-output test voltage per
DIN V VDE V 0884-10
VPR
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
680
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
906
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
1062
VPK
VIOTM
Maximum transient overvoltage per
DIN V VDE V 0884-10
VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
4242
VPK
VIOSM
Maximum surge isolation voltage per
DIN V VDE V 0884-10
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 x VIOSM = 7800 VPK (qualification)
6000
VPK
VISO
Withstand isolation voltage per UL 1577
VTEST = VISO = 3000 VRMS, t = 60 sec
(qualification);
VTEST = 1.2 x VISO = 3600 VRMS, t = 1 sec (100%
production)
3000
VRMS
RS
Insulation resistance
VIO = 500 V at TS = 150°C
>109
Ω
Pollution degree
(1)
2
Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
Basic isolation group
Installation classification
TEST CONDITIONS
SPECIFICATION
Material group
II
Rated mains voltage ≤ 150 VRMS
I–IV
Rated mains voltage ≤ 300 VRMS
I–III
8.3.1.3 Regulatory Information
VDE
CSA
Certified according to DIN V VDE
V 0884-10 (VDE V 088410):2006-12 and DIN EN 610101 (VDE 0411-1):2011-07
Approved under CSA
Component Acceptance Notice
5A, IEC 60950-1, and IEC
61010-1
Basic Insulation
Maximum Transient Overvoltage,
4242 VPK;
Maximum Surge Isolation
Voltage, 6000 VPK;
Maximum Repetitive Peak
Voltage, 566 VPK
400 VRMS Basic Insulation and
200 VRMS Reinforced Insulation
working voltage per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed.+A1+A2;
Single protection, 3000 VRMS
300 VRMS Basic Insulation
working voltage per CSA
61010-1-12 and IEC 61010-1
3rd Ed.
Certificate number: 40016131
Master contract number:
220991
(1)
UL
CQC
Recognized under UL 1577
Component Recognition
Program
File number: E181974
Certified according to GB4943.12011
(1)
Basic Insulation, Altitude ≤ 5000 m,
Tropical Climate, 250 VRMS
maximum working voltage
Certificate number:
CQC15001121656
Production tested ≥ 3600 VRMS for 1 second in accordance with UL 1577.
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8.3.1.4 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output, or supply
current
TS
Maximum case temperature
TEST CONDITIONS
MIN
TYP
MAX
RθJA = 119.9 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
190
RθJA = 119.9 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
290
150
UNIT
mA
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolut Maximun
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
Safety Limiting Current (mA)
350
VCC1 = VCC2 = 3.6 V
300
250
200
VCC1 = VCC2 = 5.5 V
150
100
50
0
0
50
100
150
200
Case Temperature (oC)
C004
Figure 13. θJC Thermal Derating Curve per DIN V VDE 0884-10
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8.4 Device Functional Modes
Table 2. Function Table (1)
(1)
(2)
(3)
VCC1
VCC2
PU
PU
OUT
IN
ISO7310C
ISO7310FC
H
H
H
L
L
L
Open
H (2)
L (3)
PD
PU
X
H (2)
L (3)
X
PD
X
Undetermined
Undetermined
PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H = High level; L = Low level
In fail-safe condition, output defaults to high level
In fail-safe condition, output defaults to low level
8.4.1 Device I/O Schematics
Input (ISO7310C)
VCC1
VCC1
VCC1
VCC1
5 PA
500 Q
IN
Output
VCC2
40 Q
OUT
Input (ISO7310FC)
VCC1
VCC1
VCC1
500 Q
IN
5 PA
Figure 14. Device I/O Schematics
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
ISO7310x use single-ended TTL-logic switching technology. The supply voltage range is from 3 V to 5.5 V for
both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (i.e. μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Application
ISO7310 can be used with Texas Instruments’ microcontroller, CAN transceiver, transformer driver, and lowdropout voltage regulator to create an Isolated CAN Interface as shown in Figure 15.
VS
10 F
3.3V
2
Vcc
D2
1:2.2 MBR0520L
3
1
SN6501
10F 0.1F
D1
GND
4
IN
OUT
ISO 5V
5
TPS76350
3
1
EN
GND
10F
2
MBR0520L
GND
5
ISO-BARRIER
5,7
GND2
(See Note 1)
0.1F
6
8
6MHz
18pF
18pF
40 12(1) 3
37
9(1)
RST
VDD VDDA VBAT
VDDC
25
30
CAN0Rx
OSC0 STELLARIS
26
31
OSC1 LM3S5Y36 CAN0Tx
7
LDO GND GNDA WAKE
0.1F
10(1)
4
(See Note 1)
(1)
32
OUT ISO7310 IN
VCC2
0.1F
0.1F
4
GND1
VCC1
0.1F
3
2
1,3
4
1
0.1F
1,3
VCC1
0.1F
VCC2
8
2 IN ISO7310 OUT 6
GND1
GND2
4
5,7
VCC
S 8
RXD
10 (opt)
CANH
7
6
CANL
Vref 5
SN65HVD1050
TXD
GND
2
10 (opt)
SM712
4.7nF/
2kV
Multiple pins and capacitors omitted for clarity purpose.
Figure 15. Isolated CAN Interface
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Typical Supply Current Equations
At VCC1 = VCC2 = 5 V
• ICC1 = 0.30517 + (0.01983 x f)
• ICC2 = 1.40021 + (0.02879 x f) + (0.0021 x f x CL)
At VCC1 = VCC2 = 3.3 V
• ICC1 = 0.18133 + (0.01166 x f)
• ICC2 = 1.053 + (0.01607 x f) + (0.001488 x f x CL)
ICC1 and ICC2 are typical supply currents measured in mA, f is data rate measured in Mbps, CL is the capacitive
load measured in pF.
9.2.2 Detailed Design Procedure
Unlike optocouplers, which need external components to improve performance, provide bias, or limit current,
ISO7310x only need two external bypass capacitors to operate.
VCC1
VCC2
2 mm
max.
from
VCC1
0.1mF
1
8
2 mm
max.
from
VCC2
0.1mF
2 IN
7
6
3
OUT
4
5
INPUT
OUTPUT
GND1
GND2
Figure 16. Typical ISO7310 Circuit Hook-up
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7310x
incorporate many chip-level design improvements for overall system robustness. Some of these improvements
include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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Typical Application (continued)
9.2.3 Application Performance Curves
Typical eye diagrams of ISO7310x below indicate very low jitter and wide open eye at the maximum data rate of
25 Mbps.
Figure 17. Eye Diagram at 25 Mbps, 5V and 25°C
Figure 18. Eye Diagram at 25 Mbps, 3.3V and 25°C
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at
input and output supply pins (VCC1 & VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 datasheet (SLLSEA0) .
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11 Layout
11.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics.
11.2 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 19). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.
11.3 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces , pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 19. Recommended Layer Stack
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12 Device and Documentation Support
12.1 Trademarks
DeviceNet is a trademark of Texas Instruments.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Isolation Glossary, SLLA353
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4
5
B
.150-.157
[3.81-3.98]
NOTE 4
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
.041
[1.04]
DETAIL A
TYPICAL
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
SEE
DETAILS
SYMM
1
8X (.055)
[1.4]
SEE
DETAILS
SYMM
1
8
8X (.024)
[0.6]
8
SYMM
5
4
6X (.050 )
[1.27]
8X (.024)
[0.6]
SYMM
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
.0028 MAX
[0.07]
ALL AROUND
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
1
6X (.050 )
[1.27]
1
8
8X (.024)
[0.6]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SYMM
SYMM
5
4
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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13-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7310CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7310C
ISO7310CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7310C
ISO7310FCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7310FC
ISO7310FCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7310FC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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13-Apr-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7310CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7310FCDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7310CDR
SOIC
D
8
2500
367.0
367.0
38.0
ISO7310FCDR
SOIC
D
8
2500
367.0
367.0
38.0
Pack Materials-Page 2
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