IDT IDT70825L45PF High-speed 8k x 16 sequential access random access memory (saramâ ¢) Datasheet

HIGH-SPEED 8K x 16
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM™)
IDT70825S/L
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 8K x 16 Sequential Access Random Access Memory
(SARAM™)
- Sequential Access from one port and standard Random
Access from the other port
- Separate upper-byte and lower-byte control of the
Random Access Port
• High-speed operation
- 20ns tAA for random access port
- 20ns tCD for sequential port
- 25ns clock cycle time
• Architecture based on Dual-Port RAM cells
• Electrostatic discharge > 2001V, Class II
• Compatible with Intel BMIC and 82430 PCI Set
• Width and Depth Expandable
• Sequential side
- Address based flags for buffer control
- Pointer logic supports two internal buffers
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in 80-pin TQFP and 84-pin PGA
• Military product compliant to MIL-STD-883.
• Industrial temperature range (–40°C to +85°C) is available,
tested to military electrical specifications.
The IDT70825 is a high-speed 8K x 16-bit Sequential
Access Random Access Memory (SARAM). The SARAM
offers a single-chip solution to buffer data sequentially on one
port, and be accessed randomly (asynchronously) through
the other port. The device has a Dual-Port RAM based
architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with
counter sequencing for the sequential (synchronous) access
port.
Fabricated using CMOS high-performance technology,
this memory device typically operates on less than 900mW of
power at maximum high-speed clock-to-data and Random
Access. An automatic power down feature, controlled by CE,
permits the on-chip circuitry of each port to enter a very low
standby power mode.
The IDT70825 is packaged in a 80-pin Thin Plastic Quad
Flatpack (TQFP) or 84-pin Ceramic Pin Grid Array (PGA).
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0-12
13
SCLK
R/
LSB
Random
Access
Port
Controls
Sequential
Access
Port
Controls
MSB
8K X 16
Memory
Array
16
I/O0-15
SR/
16
DataR
DataL
1
2
Reg.
16
SI/O0-15
13
13
AddrL
AddrR
13
RST
13
13
Pointer/
Counter
13
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
13
1
COMPARATOR
2
3016 drw 01
The IDT logo is a registered trademark and SARAM is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.31
OCTOBER 1996
DSC-3016/6
1
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SI/O2
SI/O3
VCC
SI/O4
SI/O5
SI/O6
SI/O7
GND
SI/O8
SI/O9
SI/O10
SI/O11
VCC
SI/O12
SI/O13
SI/O14
SI/O15
GND
N/C
A12
PIN CONFIGURATIONS(1,2)
INDEX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
59
2
58
3
SI/O1
SI/O0
GND
N/C
4
57
W
5
RST
6
56
55
SLD
7
54
SSTRT2
SSTRT1
8
SCE
SR/
53
10
11
13
SOE
SCLK
GND
51
50
49
TQFP
TOP
VIEW(3)
12
CNTEN
52
IDT70825
PN80-1
9
GND
GND
48
14
47
15
46
45
16
EOB2
EOB1
VCC
I/O0
44
18
43
LB
UB
19
42
R/
66
60
VCC
64
I/O2
67
EOB1
62
58
55
59
56
I/O0 EOB2
NC
54
51
48
46
65
SOE
57
49
50
47
RST SLD SCE
53
44
72
76
33
73
I/O8
32
28
I/O10 I/O11 VCC
79
26
80
82
7
CMD
NC
1
2
I/O15 GND
84
3
W
NC
R/
A
B
4
OE
UB
C
5
6
LB
CE
8
11
VCC
10
A0
9
VCC
15
12
23
A2
14
A4
13
A7
16
20
22
A10
18
A12
19
05
27
04
25
03
24
GND
02
21
A5
A3
A6
A8
A9
A11
E
F
G
H
J
K
L
D
06
30
A1
INDEX
07
36
NC SI/O15
17
08
34
SI/O14 SI/O13
83
I/O14
29
09
37
SI/O12 VCC SI/O11
I/O12 I/O13
81
31
10
39
SI/O9 SI/O10 SI/O6
84-PIN PGA
TOP VIEW(3)
78
77
35
11
40
SI/O8 SI/O7 GND
IDT70825
G84-3
74
I/O5
NC
SI/O4 SI/O5
I/O6 GND
70
I/O9
42
SI/O2 VCC
38
71
75
43
41
52
SCLK GND SSTRT1
VCC
I/O7
GND
SI/O0 SI/O1 SI/O3
68
I/O4
3016 drw 02
45
GND CNTEN GND SSTRT2 SR/W NC
I/O3 GND
69
W
OE
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
61
I/O1
CMD
CE
17
I/O1
GND
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
VCC
I/O12
I/O13
I/O14
I/O15
GND
63
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
VCC
VCC
A1
A0
1
01
3016 drw 03
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.31
2
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS: RANDOM ACCESS PORT
SYMBOL
A0-A12
NAME
I/O(1)
DESCRIPTION
Address Lines
I
Address inputs to access the 8192-word (16 bit) memory array.
I/O0-I/O15 Inputs/Outputs
I
Random access data inputs/outputs for 16-bit wide data.
CE
Chip Enable
I
When CE is LOW, the random access port is enabled. When CE is HIGH, the random access
port is disabled into power-down mode and the I/O outputs are in the high-impedance state. All
data is retained during CE = VIH, unless it is altered by the sequential port. CE and CMD may not
be LOW at the same time.
CMD
Control Register
Enable
I
When CMD is LOW, Address lines A0-A2, R/W, and inputs/outputs I/O0-I/O11, are used to
access the control register, the flag register, and the start and end of buffer registers. CMD and
CE may not be LOW at the same time.
R/W
Read/Write Enable
I
If CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the
array when R/W is HIGH. If CE is HIGH and CMD is LOW, R/W is used to access the buffer command registers. CE and CMD may not be LOW at the same time.
OE
Output Enable
I
When OE is LOW and R/W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O
outputs are in the high-impedance state.
Lower Byte, Upper
Byte Enables
I
When LB is LOW, I/O0-I/O7 are accessible for read and write operations. When LB is HIGH, I/O0I/O7 are tri-stated and blocked during read and write operations. UB controls access for I/O8I/O15 in the same manner and is asynchronous from LB.
,
LB UB
VCC
Power Supply
Seven +5V power supply pins. All Vcc pins must be connected to the same +5V VCC supply.
GND
Ground
Ten Ground pins. All Ground pins must be connected to the same Ground supply.
3016 tbl 01
PIN DESCRIPTIONS: SEQUENTIAL ACCESS PORT
SYMBOL
NAME
SI/O0-15 Inputs
I/O(1)
I/O
DESCRIPTION
Sequential data inputs/outputs for 16-bit wide data.
SCLK
Clock
I
SI/O0-SI/O15, SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK.
Also, the sequential access port address pointer increments by 1 on each LOW-to-HIGH
transition of SCLK when CNTEN is LOW.
SCE
Chip Enable
I
When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of
SCLK. When SCE is HIGH, the sequential access port is disabled into powered-down mode on
the LOW-to-HIGH transition of SCLK, and the SI/O outputs are in the high-impedance state. All
data is retained, unless altered by the random access port.
CNTEN
Counter Enable
I
When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK.
This function is independant of SCE.
SR/W
Read/Write Enable
I
When SR/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of
SCLK. When SR/W is HIGH, and SCE and SOE are LOW, a read cycle is initiated on the
LOW-to-HIGH transition of SCLK. Termination of a Write cycle is done on the Low-to-High
transistion of SCLK if SR/W or SCE is High.
SLD
Address Pointer
Load Control
I
When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer
changes. When SLD is LOW, data on the inputs SI/O0-SI/O11 is loaded into a data-in register
on the LOW-to-HIGH transition of SCLK. On the cycle following SLD, the address pointer
changes to the address location contained in the data-in register. SSTRT1 and SSTRT2 may
not be LOW while SLD is LOW or during the cycle following SLD.
Load Start of
Address Register
I
When SSTRT1 or SSTRT2 is LOW, the start of address register #1 or #2 is loaded into the
address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in
internal registers. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle
following SLD.
End of Buffer Flag
O
EOB1 or EOB2 is output LOW when the address pointer is incremented to match the address
stored in the end of buffer registers. The flags can be cleared by either asserting RST LOW or
by writing zero into bit 0 and/or bit 1 of the control register at address 101. EOB1 and EOB2 are
dependent on separate internal registers, and therefore separate match addresses.
SOE
Output Enable
I
SOE
RST
Reset
I
When RST is LOW, all internal registers are set to their default state, the address pointer is set
to zero and the EOB1 and EOB2 flags are set HIGH. RST is asynchronous to SCLK.
SSTRT
SSTRT
EOB
EOB
1,
2
1,
2
controls the data outputs and is independent of SCLK. When SOE is LOW, output buffers
and the sequentially addressed data is output. When SOE is HIGH, the SI/O output bus is in
the high-impedance state. SOE is asynchronous to SCLK.
NOTE:
1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.
3016 tbl 02
6.31
3
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
Rating
Commercial
Military
–0.5 to +7.0
Operating
Temperature
0 to +70
–55 to +125
TBIAS
Temperature
Under Bias
–55 to +125
–65 to +135
°C
TSTG
Storage
Temperature
–55 to +125
–65 to +150
°C
IOUT
DC Output
Current
50
50
mA
TA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Unit
Terminal Voltage –0.5 to +7.0
with Respect
to GND
MILITARY AND COMMERCIAL TEMPERATURE RANGES
V
Grade
°C
Ambient
Temperature
GND
VCC
Military
–55°C to +125°C
0V
5.0V ± 10%
Commercial
0°C to +70°C
0V
5.0V ± 10%
3016 tbl 04
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
NOTES:
3016 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc
+ 0.5V.
Parameter
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
V
VCC
Supply Voltage
GND
Supply Voltage
0
0
VIH
Input High Voltage
2.2
—
6.0(2)
V
Input Low Voltage
–0.5(1)
—
0.8
V
VIL
NOTES:
1. VIL > –1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
3016 tbl 05
CAPACITANCE(1)
(TA = +25°C, F = 1.0MHz)TQFP ONLY
Conditions(2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output
Capacitance
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
NOTES:
3016 tbl 06
1. This parameter is determined by device characterization, but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
Symbol
Parameter
Test Conditions
IDT70825S
Min.
Max.
IDT70825L
Min.
Max.
Unit
|ILI|
Input Leakage Current(1)
VCC = Max. VIN = GND to VCC
—
5.0
—
1.0
µA
|ILO|
Output Leakage Current
VCC = Max. CE and SCE = VIH
VOUT = GND to VCC
—
5.0
—
1.0
µA
VOL
Output Low Voltage
IOL = 4mA, VCC = Min.
—
0.4
—
0.4
V
VOH
Output High Voltage
IOH = –4mA, VCC = Min.
2.4
—
2.4
—
V
3016 tbl 07
NOTE:
1. At Vcc ≤ 2.0V input leakages are undefined.
6.31
4
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Test
Condition
Parameter
Version
Dynamic Operating
Current
CE
= VIL, Outputs
Open, SCE = VIL(5)
MIL.
(Both Ports Active)
f = fMAX(3)
COM’L. S
L
Standby Current
(Both Ports - TTL Level
SCE
MIL.
Inputs)
f = fMAX(3)
Standby Current
(One Port - TTL Level
70825X35
70825X45
Typ.(2) Max. Typ.(2) Max. Unit
—
—
—
—
—
—
—
—
160
160
400
340
155
155
400
340
180
180
380
330
170
170
360
310
160
160
340
290
155
155
340
290
S
L
—
—
—
—
—
—
—
—
20
20
85
65
16
16
85
65
COM’L. S
L
25
25
70
50
25
25
70
50
20
20
70
50
16
16
70
50
CE
MIL.
—
—
——
—
—
—
—
95
95
290
250
90
90
290
250
Input)
Open, f = fMAX(3)
COM’L. S
L
115
115
260
230
105
105
250
220
95
95
240
210
90
90
240
210
Full Standby Current
(Both Ports - CMOS
Both Ports CE and
MIL.
(6,7)
SCE ≥ VCC - 0.2V
S
L
—
—
—
—
—
—
—
—
1.0
0.2
30
10
1.0
0.2
30
10
Level Inputs)
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V, f = 0(4)
COM’L. S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
Full Standby Current
(One Port - CMOS
Level Inputs)
One Port CE or
(6)
SCE ≥ VCC - 0.2V
Outputs Open
MIL.
—
—
—
—
—
—
—
—
90
90
260
215
85
85
260
215
110
240
100
230
90
220
85
220
110
200
100
190
90
180
85
180
and CE > VIH(7)
CMD = VIH
or SCE = VIH
Active Port Outputs
S
L
70825X20
70825X25
Com'l. Only Com'l. Only
Typ.(2) Max. Typ.(2)Max.
S
L
S
L
(Active port), f = fMAX(3) COM’L. S
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
L
mA
mA
mA
mA
mA
NOTES:
3016 tbl 08
1. "X" in part number indicates power rating (S or L).
2. VCC = 5V, Ta = +25°C; guaranteed by device characterization but not production tested.
3. At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. SCE may transition, but is Low (SCE=VIL) when clocked in by SCLK.
6. SCE may be ≤ 0.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown.
7. If one port is enabled (either CE or SCE = Low) then the other port is disabled (SCE or CE = High, respectively). CMOS High > Vcc - 0.2V and
Low < 0.2V, and TTL High = VIH and Low = VIL.
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L VERSION ONLY) (VLC < 0.2V, VHC > VCC - 0.2V)
Symbol
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Test Condition
VCC = 2V
CE
= VHC
VIN = VHC or = VLC
tCDR(3)
tR
(3)
SCE
Operation Recovery Time
CMD
= VHC
NOTES :
1. TA = +25°C, VCC = 2V; guaranteed by device characterization but not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by device characterization, but is not production tested.
4. To initiate data retention, SCE = VIH must be clocked in.
6.31
Typ.(1)
Max.
Unit
2.0
—
—
V
MIL.
—
100
4000
µA
COM’L.
—
100
1500
= VHC(4) when SCLK=
Chip Deselect to Data Retention Time
Min.
0
—
—
tRC(2)
—
—
ns
ns
3016 tbl 09
5
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION AND POWER DOWN/UP WAVEFORM (RANDOM AND SEQUENTIAL PORT) (1,2)
DATA RETENTION MODE
VDR ≥ 2V
4.5V
VCC
4.5V
tCDR
tR
VDR
CE
VIH
VIH
SCLK
SCE
tPD
tPU
ICC
ISB
NOTES :
1. SCE is synchronized to the sequential clock input.
2. CMD > VCC - 0.2V.
3016 drw 04
ISB
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
347Ω
30pF
347Ω
3016 drw 05
5pF
3016 drw 06
Figure 2. Output Test Load (for tCLZ, tBLZ, tOLZ, tCHZ,
tBHZ, tOHZ, tWHZ, tCKHZ, and tCKLZ)
Including scope and jig.
Figure 1. AC Output Test Load
8
7
6
tAA/tCD/tEB 5
(Typical, ns)
4
3
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
2
GND to 3.0V
1
3ns Max.
Input Timing Reference Levels
1.5V
-1
Output Reference Levels
1.5V
-2
Figures 1, 2, and 3
-3
AC Test Load
10pF is the I/O
capacitance of
this device, and
30pF is the AC
Test Load
capacitance.
20 40 60 80 100 120 140 160 180 200
CAPACITANCE (pF)
3016 drw 07
3016 tbl 10
Figure 3. Lumped Capacitance Load Typical Derating Curve
6.31
6
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – RANDOM ACCESS READ AND WRITE (1,2)
Inputs/Outputs
CE
CMD
R/W
OE
LB
MODE
UB
I/O0-I/O7
I/O8-I/O-
L
H
H
L
L
L
DATAOUT
DATAOUT
L
H
H
L
L
H
DATAOUT
High-Z
Read both Bytes.
Read lower Byte only.
L
H
H
L
H
L
High-Z
DATAOUT
Read upper Byte only.
L
H
L
H(3)
L
L
DATAIN
DATAIN
Write to both Bytes.
L
H
L
H(3)
L
H
DATAIN
High-Z
Write to lower Byte only.
L
H
L
H(3)
H
L
High-Z
DATAIN
Write to upper Byte only.
H
H
X
X
X
X
High-Z
High-Z
Both Bytes deselected and powered down.
L
H
H
H
X
X
High-Z
High-Z
Outputs disabled but not powered down.
L
H
X
X
H
H
High-Z
High-Z
Both Bytes deselected but not powered down.
H
L
L
H(3)
L(4)
L(4)
DATAIN
DATAIN
Write I/O0-I/O12 to the Buffer Command Register.
H
L
H
L
L(4)
L(4)
DATAOUT
DATAOUT
Read contents of the Buffer Command Register via I/O0-I/O12.
3016 tbl 11
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2. RST, SCE, CNTEN, SR/W, SLD, SSTRT1, SSTRT2, SCLK, SI/O0-SI/O15, EOB1, EOB2, and SOE are unrelated to the random access port control and
operation.
3. If OE = VIL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven.
4. Byte operations to control register using UB and LB separately are also allowed.
TRUTH TABLE II – SEQUENTIAL READ (1,2,3,6,8)
Inputs/Outputs
SCLK SCE
MODE
CNTEN SR/W EOB1 EOB2 SOE
SI/O
Counter Advanced Sequential Read with EOB1 reached.
L
L
H
LOW
LAST
L
[EOB1]
L
H
H
LAST
LAST
L
[EOB1 - 1] Non-Counter Advanced Sequential Read, without EOB1 reached.
L
L
H
LAST
LOW
L
[EOB2]
L
H
H
LAST
LAST
L
[EOB2 - 1] Non-Counter Advanced Sequential Read without EOB2 reached.
L
L
H
LOW
LOW
H
HIGH-Z
Counter Advanced Sequential Read with EOB2 reached.
Counter Advanced Sequential Non-Read with EOB1 and EOB2
reached.
3016 tbl 12
TRUTH TABLE III – SEQUENTIAL WRITE (1,2,3,4,5,6,7,8)
Inputs/Outputs
MODE
SCLK SCE CNTEN SR/W EOB1 EOB2 SOE
SI/O
L
H
L
LAST LAST
H
SI/OIN Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached
L
L
L
LOW
LOW
H
SI/OIN Counter Advanced Sequential Write with EOB1 and EOB2 reached.
H
H
X
LAST LAST
X
High-Z No Write or Read due to Sequential port Deselect. No counter advance.
H
L
X
NEXT NEXT
X
High-Z No Write or Read due to Sequential port Deselect. Conter does advance.
3016 tbl 13
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance. LOW = VOL.
2. RST, SLD, SSTRT1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations.
3. CE, OE, R/W, CMD, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently
with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. SOE must be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising
edge of the clock during the cycle in which SR/W = VIL.
5. SI/OIN refers to SI/O0-SI/O15 inputs.
6. "LAST" refers to the previous value still being output, no change.
7. Termination of a write is done on the Low-to-High transition of SCLK if SR/W or SCE is High.
8. When CLKEN=Low, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter
Enable Cycle after Reset, Read (and write) Cycle".
6.31
7
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE IV – SEQUENTIAL ADDRESS POINTER OPERATIONS (1,2,3,4,5)
Inputs/Outputs
SLD SSTRT1 SSTRT 2 SOE
SCLK
H
L
H
X
H
H
L
X
L
H
H
H(6)
MODE
Start address for Buffer #1 loaded into Address Pointer.
Start address for Buffer #2 loaded into Address Pointer.
Data on SI/O0-SI/O12 loaded into Address Pointer.
NOTES:
3016 tbl 14
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2. RST is continuously HIGH. The conditions of SCE, CNTEN, and SR/W are unrelated to the sequential address pointer operations.
3. CE, OE, R/W, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently with
the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.
5. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address
is not incremented during the two cycles.
6. SOE may be LOW with SCE deselect or in the write mode using SR/W.
ADDRESS POINTER LOAD CONTROL (SLD)
In SLD mode, there is an internal delay of one cycle before
the address pointer changes in the cycle following SLD. When
SLD is LOW, data on the inputs SI/O0-SI/O12 is loaded into a
data-in register on the LOW-to-HIGH transition of SCLK. On
the cycle following SLD, the address pointer changes to the
address location contained in the data-in register. SSTRT1,
SSTRT2 may not be low while SLD is LOW, or during the cycle
following SLD. The SSTRT1 and SSTRT2 require only one
clock cycle, since these addresses are pre-loaded in the
registers already.
SLD MODE (1)
SLD
(1)
SCLK
B
A
ADDRIN
SI/O0-11
C
DATAOUT
SSTRT1,2
3016 drw 08
NOTE:
1. At SCLK edge (A), SI/O0-SI/O12 data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e.
address pointer changes). At SCLK edge (A), SSTRT1 and SSTRT2 must be high to ensure for proper sequential address pointer loading. At SCLK edge
(B), SLD and SSTRT1,2 must be high to ensure for proper sequential address pointer loading. For SSTRT1 or SSTRT2, the data to be read will be ready
for edge (B), while data will not be ready at edge (B) when SLD is used, but will be ready at edge (C).
SEQUENTIAL LOAD OF ADDRESS INTO POINTER/COUNTER (1)
MSB
15
14
13
12 ------------------------------------------------------------------------------------------------------------ 0
H
H
H
H
Address Loaded into Pointer
LSB SI/O BITS
3016 drw 09
NOTE:
1. "H" = VIH for the SI/O intput state.
6.31
8
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Reset (RST)
Setting RST LOW resets the control state of the SARAM.
functions asynchronously of SCLK, (i.e. not registered).
The default states after a reset operation are as follows:
RST
Register
Contents
Address Pointer
0
EOB Flags
Cleared to High state
Buffer Flow Mode
BUFFER CHAINING
Start Address Buffer #1
0
End Address Buffer #1
4095
(4K)
Start Address Buffer #2
4096
(4K+1)
End Address Buffer #2
8191
(8K)
Registered State
SCE
(1)
= VIH, SR/W = VIL
3016 tbl 15
BUFFER COMMAND MODE (CMD)
Buffer Command Mode (CMD) allows the random access
port to control the state of the two buffers. Address pins A0-A2
and I/O pins I/O0-I/O12 are used to access the start of buffer
and the end of buffer addresses and to set the flow control
mode of each buffer. The Buffer Command Mode also allows
reading and clearing the status of the EOB flags. Seven
different CMD cases are available depending on the conditions of A0-A2 and R/W. Address bits A3-A12 and data I/O bits
I/O13-I/O15 are not used during this operation.
RANDOM ACCESS PORT CMD MODE(1)
Case #
A2-A0
R/W
DESCRIPTIONS
1
000
0 (1)
Write (read) the start address of Buffer #1 through I/O0-I/O12.
2
001
0 (1)
Write (read) the end address of Buffer #1 through I/O0-I/O12.
3
010
0 (1)
Write (read) the start address of Buffer #2 through I/O0-I/O12.
4
011
0 (1)
Write (read) the end address of Buffer #2 through I/O0-I/O12.
5
100
0 (1)
6
101
0
7
101
1
8
110/111
(X)
Write (read) flow control register
Write only – clear EOB1 and/or EOB2 flag
Read only – flag status register
(Reserved)
NOTE:
1. R/W input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
3016 tbl 16
CASES 1 THROUGH 4: START AND END OF BUFFER REGISTER DESCRIPTION(1,2)
MSB
15
14
13
12 ------------------------------------------------------------------------------------------------------------ 0
H
H
H
Address Loaded into Buffer
LSB I/O BITS
NOTES:
3016 drw 10
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.
2. A write into the buffer occurs when R/W = VIL and a read when R/W = VIH. EOB1/SOB1 and EOB2/SOB2 are chosen through address A0-A2 while CMD
= VIL and CE = VIH.
CASE 5: BUFFER FLOW MODES
Within the SARAM, the user can designate one of four
buffer flow modes for each buffer. Each buffer flow mode
defines a unique set of actions for the sequential port address
pointer and EOB flags. In BUFFER CHAINING mode, after the
address pointer reaches the end of the buffer, it sets the
corresponding EOB flag and continues from the start address
of the other buffer. In STOP mode, the address pointer stops
incrementing after it reaches the end of the buffer. In LINEAR
mode, the address pointer ignores the end of buffer address
and increments past it, but sets the EOB flag. MASK mode is
the same as LINEAR mode except EOB flags are not set.
6.31
9
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FLOW CONTROL REGISTER DESCRIPTION(1,2)
0
15
MSB
H
H
H
H
H
H
H
H
H
H
H
4
3
2
Counter Release
(STOP Mode Only)
1
0
LSB I/O BITS
Buffer #1 flow control
NOTES:
Buffer #2 flow control
3016 drw 11
1. "H" = VOH for I/O in the output state and "Don't Cares"' for I/O in the input state.
2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs
asynchronously of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled
by CNTEN. The pointer is also released by RST, SLD, SSTRT1 and SSTRT2 operations.
FLOW CONTROL BITS
Flow Control Bits
Bit 1 & Bit 0
(Bit 3 & Bit 2)
Mode
00
BUFFER
CHAINING
Functional Description
01
EOB1 (EOB2) is asserted (Active Low output) when the pointer matches the end address of Buffer
#1 (Buffer #2). The pointer value is changed to the start address of Buffer #2 (Buffer #1).(1,3)
EOB1 (EOB2) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2).
The address pointer will stop incrementing when it reaches the next address (EOB address + 1), if
CNTEN is Low on the next clock's rising edge. Otherwise, the address pointer will stop incrementing on
EOB. Sequential write operations are inhibited after the address pointer is stopped. The pointer can be
STOP
released by bit 4 of the flow control register. (1,2,4)
10
EOB1 (EOB2) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2).
LINEAR
The pointer keeps incrementing for further operations.(1)
11
EOB1 (EOB2) is not asserted when the pointer reaches the end address of Buffer #1 (Buffer #2),
MASK
although the flag status bits will be set. The pointer keeps incrementing for further operations.
3016 tbl 17
NOTES:
1. EOB1 and EOB2 may be asserted (set) at the same time, if both end addresses have been loaded with the same value.
2. CMD Flow Control bits are unchanged, the count does not continue advancement.
3. If EOB1 and EOB2 are equal, then the pointer will jump to the start of Buffer #1.
4. If counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK otherwise
the flow control will remain in the STOP mode.
CASES 6 AND 7: FLAG STATUS REGISTER BIT DESCRIPTION(1)
0
15
MSB
H
H
H
H
H
H
H
H
H
H
H
H
NOTE:
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.
H
H
1
0
LSB I/O BITS
End of buffer flag for Buffer #1
End of buffer flag for Buffer #2
3016 drw 12
CASE 6: FLAG STATUS REGISTER WRITE CONDITIONS(1)
Flag Status Bit 0, (Bit 1)
Functional Description
0
Clears Buffer Flag EOB1, (EOB2).
1
No change to the Buffer Flag.(2)
NOTES:
3016 tbl 18
1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be cleared while the second is left alone or cleared.
2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0).
CASE 7: FLAG STATUS REGISTER READ CONDITIONS
Flag Status Bit 0, (Bit 1) Functional Description
0
1
EOB1 (EOB2) flag has not been set, the
Pointer has not reached the End of the
Buffer.
EOB1 (EOB2) flag has been set, the
Pointer has reached the End of the Buffer.
3016 tbl 19
6.31
10
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CASES 8 AND 9: (RESERVED)
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (2,3)
Symbol
Parameter
IDT70825X20
IDT70825X25
Com'l. Only
Com'l. Only
Min.
Max.
Min.
IDT70825X35
Max.
Min.
IDT70825X45
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
—
25
—
35
—
45
—
ns
tAA
Address Access Time
—
20
—
25
—
35
—
45
ns
tACE
Chip Enable Access Time
—
20
—
25
—
35
—
45
ns
tBE
Byte Enable Access Time
—
20
—
25
—
35
—
45
ns
tOE
Output Enable Access Time
—
10
—
10
—
15
—
20
ns
tOH
Output Hold from Address Change
3
—
3
—
3
—
3
—
ns
tCLZ
Chip Select Low-Z Time(1)
3
—
3
—
3
—
3
—
ns
tBLZ
Byte Enable Low-Z Time(1)
3
—
3
—
3
—
3
—
ns
tOLZ
Output Enable Low-Z Time(1)
2
—
2
—
2
—
2
—
ns
tCHZ
Chip Select High-Z
Time(1)
—
10
—
12
—
15
—
15
ns
tBHZ
Byte Enable High-Z Time(1)
—
10
—
12
—
15
—
15
ns
tOHZ
Output Enable High-Z
Time(1)
—
9
—
11
—
15
—
15
ns
tPU
Chip Select Power-Up Time
0
—
0
—
0
—
0
—
ns
tPD
Chip Select Power-Down Time
—
20
—
25
—
35
—
45
ns
3016 tbl 20
NOTES:
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3. CMD access follows standard timing listed for both read and write accesses, ( CE = VIH when CMD = VIL ) or ( CMD = VIH when CE = VIL ).
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (2,4)
Symbol
Parameter
IDT70825X20
IDT70825X25
Com'l. Only
Com'l. Only
IDT70825X35
IDT70825X45
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
20
—
25
—
35
—
45
—
ns
tCW
Chip Select to End-of-Write
15
—
20
—
25
—
30
—
ns
End-of-Write(3)
tAW
Address Valid to
15
—
20
—
25
—
30
—
ns
tAS
Address Set-up Time
0
—
0
—
0
—
0
—
ns
tWP
Write Pulse Width(3)
13
—
20
—
25
—
30
—
ns
tBP
Byte Enable Pulse Width(3)
15
—
20
—
25
—
30
—
ns
tWR
Write Recovery Time
0
—
0
—
0
—
0
—
ns
Time(1)
tWHZ
Write Enable Output High-Z
—
10
—
12
—
15
—
15
ns
tDW
Data Set-up Time
13
—
15
—
20
—
25
—
ns
tDH
Data Hold Time
0
—
0
—
0
—
0
—
ns
tOW
Output Active from End-of-Write
3
—
3
—
3
—
3
—
ns
NOTES:
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
drivers to turn off and on the data to be placed on the bus for the required tDW. If OE is HIGH during the R/W controlled write cycle, this requirement does
not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degradation to tCW timing.
4. CMD access follows standard timing listed for both read and write accesses, ( CE = VIH when CMD = VIL ) or ( CMD = VIH when CE = VIL ).
3016 tbl 21
6.31
11
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RANDOM ACCESS PORT WAVEFORM: READ CYCLES (1,2)
tRC
ADDR
tAA
tOH
(2)
tACS
tCHZ
tCLZ
,
tBHZ
tBE
tBLZ
tOE
tOHZ
tOLZ
I/OOUT
Valid Data Out
3016 drw 13
NOTES:
1. R/W is HIGH for Read cycle.
2. Address valid prior to or coincident with CE transition LOW; otherwise tAA is the limiting parameter.
RANDOM ACCESS PORT WAVEFORM: READ CYCLES BUFFER COMMAND MODE
tRC
ADDR
tAA
(1)
tOH
tACS
tCHZ
tCLZ
,
tBHZ
tBE
tBLZ
tOE
tOLZ
tOHZ
I/OOUT
Valid Data Out
3016 drw 14
NOTE:
1. CE = VIH when
CMD = VIL.
6.31
12
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
W CONTROLLED TIMING)
RANDOM ACCESS PORT WAVEFORM: WRITE CYCLE NO.1 (R/
(1,6)
tWC
ADDR
tAW
W
R/
tWP
tAS
(8)
CE, LB, UB
(2)
tWR
(3)
(5)
tDH
tDW
I/OIN
Valid Data In
OE
tOHZ
tWHZ
I/OOUT
Data Out
(4)
Data Out
tACS
tBE
(4)
tOW
3016 drw 15
RANDOM ACCESS PORT WAVEFORM: WRITE CYCLE NO.2
(CE , LB, AND/OR UB CONTROLLED TIMING) (1,6,7)
tWC
ADDR
tAW
(8)
CE, LB, UB
(5)
tAS
tWR
tCW (2)
tBP (2)
W
R/
tDW
I/OIN
(3)
tDH
Valid Data
3016 drw 16
NOTES:
1. R/W, CE, or LB and UB must be inactive during all address transitions.
2. A write occurs during the overlap of R/W = VIL, CE = VIL and LB = VIL and/or UB = VIL.
3. tWR is measured from the earlier of CE (and LB and/or UB) or R/W going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and the input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
drivers to turn off and on the data to be placed on the bus for the required tDW. If OE is HIGH during the R/W controlled write cycle, this requirement does
not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degregation to tCW timing.
7. I/OOUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8. CMD access follows the standard CE access described above. If CMD = VIL, then CE must = VIH or, when CE = VIL, CMD must = VIH.
6.31
13
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(2)
IDT70825X20
Com'l. Only
Symbol
Parameter
IDT70825X25
IDT70825X35
IDT70825X45
Com'l. Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tCYC
Sequential Clock Cycle Time
25
—
30
—
40
—
50
—
ns
tCH
Clock Pulse High
10
—
12
—
15
—
18
—
ns
tCL
Clock Pulse Low
10
—
12
—
15
—
18
—
ns
tES
Count Enable and Address Pointer Set-up Time
5
—
5
—
6
—
6
—
ns
tEH
Count Enable and Address Pointer Hold Time
2
—
2
—
2
—
2
—
ns
8
—
10
—
15
—
20
ns
—
2
—
2
—
2
—
ns
tSOE
Output Enable to Data Valid
—
tOLZ
Output Enable Low-Z Time(1)
2
tOHZ
Output Enable High-Z
Time(1)
tCD
Clock to Valid Data
—
9
—
11
—
15
—
15
ns
—
20
—
25
—
35
—
45
ns
tCKHZ
Clock High-Z
Time(1)
—
12
—
14
—
17
—
20
ns
tCKLZ
Clock Low-Z Time(1)
3
—
3
—
3
—
3
—
ns
tEB
Clock to EOB
—
13
—
15
—
18
—
23
ns
3016 tbl 22
NOTES:
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part numbers indicates power rating (S or L).
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(1)
IDT70825X20
Com'l. Only
Symbol
Parameter
IDT70825X25
IDT70825X35
IDT70825X45
Com'l. Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
—
50
—
ns
WRITE CYCLE
tCYC
Sequential Clock Cycle Time
25
—
30
—
40
tFS
Flow Restart Time
13
—
15
—
20
—
20
—
ns
tWS
Chip Select and Read/Write Set-up Time
5
—
5
—
6
—
6
—
ns
tWH
Chip Select and Read/Write Hold Time
2
—
2
—
2
—
2
—
ns
tDS
Input Data Set-up Time
5
—
5
—
6
—
6
—
ns
tDH
Input Data Hold Time
2
—
2
—
2
—
2
—
ns
NOTE:
1. "X" in part numbers indicates power rating (S or L).
3016 tbl 23
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(1)
Symbol
Parameter
IDT70825X20
IDT70825X25
Com'l. Only
Com'l. Only
IDT70825X35
IDT70825X45
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
RESET CYCLE
tRSPW
Reset Pulse Width
13
—
15
—
20
—
20
—
ns
tWERS
Write Enable High to Reset High
10
—
10
—
10
—
10
—
ns
tRSRC
Reset High to Write Enable Low
10
—
10
—
10
—
10
—
ns
tRSFV
Reset High to Flag Valid
15
—
20
—
25
—
25
—
ns
NOTE:
1. "X" in part numbers indicates power rating (S or L).
3016 tbl 24
6.31
14
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT WAVEFORM: WRITE, POINTER LOAD, NON-INCREMENTING READ
tCYC
tCH
tCL
SCLK
tEH
tES
CNTEN
(2)
(3)
tEH
tES
SLD
(1)
tDS
tDH
SI/OIN
Dx
HIGH IMPEDANCE
A0
tWS
tWS
tWH
tWH
W
SR/
tWS
tWS
SCE
tWH
tWH
tCSZ
tCKHZ
tCD
SOE
tSOE
tOLZ
SI/OOUT
tOHZ
D0
D0
D0
tCKLZ
3016 drw 17
SEQUENTIAL PORT WAVEFORM: WRITE, POINTER LOAD, BURST READ
tCH
tCYC
tCL
SCLK
tES
CNTEN
tEH
(3)
(2)
tEH
tES
SLD
(1)
tDS
tDS
tDH
SI/OIN
Dx
tWS
tWH
W
HIGH IMPEDANCE
A0
tWS
tDH
D2
tWH
SR/
tWS
SCE
tWH
tWS
tWH
tCD
SOE
tSOE
tOHZ
tOLZ
SI/OOUT
D0
tCKLZ
D1
(2)
3016 drw 18
NOTES:
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
6.31
15
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT WAVEFORM: READ STRT/EOB FLAG TIMING
tCH
tCYC
tCL
SCLK
tES
CNTEN
tEH
(4)
tES
(2)
tEH
SSTRT1/2
(1)
tDS
SI/OIN
HIGH IMPEDANCE
D3
Dx
tWS
tWS
tWH
W
tDH
tWH
SR/
tWS
SCE
SOE
tWS
tWH
tWH
(3)
tCD
tSOE
tOHZ
tOLZ
SI/OOUT
EOB1/2
(5)
D0
D1
D2
(2)
tCKLZ
tEB
3016 drw 19
NOTES:
1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be High on Power-Up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within
that cycle. If SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a Read. SOE may be used to control
the bus contention and permit a Write on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT .
5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.31
16
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT WAVEFORM: WRITE CYCLES
tCYC
tCH
tCL
SCLK
tES
CNTEN
tES
tEH
(4)
(3)
tEH
tES
SLD
(1)
tDS
SI/OIN
tEH
Dx
tWS
W
tDH
A0
tDS
tDS
tDH
tDH
HIGH IMPEDANCE
D0
tWS
tWH
D1
tWH
SR/
(4)
tWS
SCE
tWS
tWH
tWH
tCKHZ
tCD
SOE
(5)
SI/OOUT
D0
tOHZ
HIGH IMPEDANCE
D0
3016 drw 20
tCKLZ
SEQUENTIAL PORT WAVEFORM: BURST WRITE CYCLES
tCYC
tCH
tCL
SCLK
tES
CNTEN
(3)
tES
(1)
tDS
Dx
tWS
SR/
W
A0
tDS
D1
D0
tWS
tWH
tDH
tDH
D2
tWH
(5)
tWS
SCE
(2)
tEH
SLD
SI/OIN
tEH
tWS
tWH
tWH
SOE
(5)
tCKLZ
tCD
SI/OOUT
HIGH IMPEDANCE
D2
30916 drw 21
NOTES :
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incrementing on cycle immediately following SLD even if CNTEN is Low.
4. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
5. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.31
17
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT WAVEFORM: WRITE CYCLES (STRT/EOB FLAG TIMING)
tCH
tCL
SCLK
tES
CNTEN
tEH
(2)
(4)
tES
tEH
SSTRT1/2
(1)
tDS
tDH
SI/OIN
Dx
D0
D1
D3
HIGH IMPEDANCE
tWS
tWS
tWH
tWH
W
D2
SR/
(5)
tWS
tWS
SCE
tWH
tWH
(3)
SOE
(6)
tCKLZ
tCD
SI/OOUT
HIGH IMPEDANCE
D3
EOB1/2
tEB
3016 drw 22
NOTES:
1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be High on Power-Up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within
that cycle. If SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a Read. SOE may be used to control
the bus contention and permit a Write on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.31
18
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL COUNTER ENABLE CYCLE AFTER RESET, WRITE CYCLE(2, 4, 6)
SCLK
(2)
SI/OIN
D0
D1
D2
D3
D4
3016 drw 23
SEQUENTIAL COUNTER ENABLE CYCLE AFTER RESET, READ CYCLE(2, 4)
SCLK
SR/
(3)
(5)
SI/OOUT
D0
(5)
D1
D2
D3
3016 drw 24
NOTES:
1. 'D0' represents data input for Address=0, 'D1' represents data input for Address=1, etc.
1. If CNTEN=VIL then 'D1' would be written into 'A1' at this point.
3. Data output is available at a tCD after the SR/W=VIH is clocked. The RST sets SR/W=Low internally and therefore disables the output until the next clock.
4. SCE=VIL throughout all cycles.
5. If CNTEN=VIL then 'D1' would be clocked out (read) at this point.
6. SR/W=VIL.
6.31
19
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RANDOM ACCESS PORT WAVEFORM: RESET TIMING
tRSPW
tRSRC
R/ , SR/
or
(4)
+ )
(
tWERS
tRSFV
1/2
Flag Valid
3016 drw 25
RANDOM ACCESS PORT WAVEFORM: RESTART TIMING OF SEQUENTIAL PORT (1)
0.5 x tCYC
tFS
SCLK
R/
(2)
2-5ns
6-7ns
CLR (3)
Block
(Internal Signal)
3016 drw 26
NOTES:
1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5).
2. "0" is written to Bit 4 from the random port at address [A2 - A0] = 100, when CMD = VIL and CE = VIH. The device is in the Buffer Command Mode
(see Case 5).
3. CLR is an internal signal only and is shown for reference only.
4. Sequential port must also prohibit SR/W or SCE from being low for tWERS and tRSRC periods, or SCLK must not toggle from Low-to-High until after tRSRC.
6.31
20
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
B
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
G
PF
84-pin PGA (G84-3)
80-pin TQFP (PN80-1)
20
25
35
45
Commercial Only
Commercial Only
S
L
Standard Power
Low Power
70825
128K (8K x 16) Sequential Access Random Access
Memory
Speed in nanoseconds
3016 drw 27
6.31
21