ON MC74AC74 Dual d-type positive edge-triggered flip-flop Datasheet

MC74AC74, MC74ACT74
Dual D-Type Positive
Edge-Triggered Flip-Flop
The MC74AC74/74ACT74 is a dual D−type flip−flop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold
voltage has been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next rising edge
of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
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MARKING
DIAGRAMS
14
14
SOIC−14
D SUFFIX
CASE 751A
xxx74G
AWLYWW
1
1
14
Features
• Outputs Source/Sink 24 mA
• ′ACT74 Has TTL Compatible Inputs
• These are Pb−Free Devices
xxx
74
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
14
1
VCC
CD2
D2
CP2
SD2
Q2
Q2
14
13
12
11
10
9
8
CD1
D1
Q1
CP1 SD1 Q1
xxx
= AC or ACT
A
= Assembly Location
WL or L = Wafer Lot
Y
= Year
WW or W = Work Week
G or G
= Pb−Free Package
SD2
CP2
Q2
D2 CD2 Q2
(Note: Microdot may be in either location)
1
2
3
4
5
6
7
CD1
D1
CP1
SD1
Q1
Q1
GND
ORDERING INFORMATION
Figure 1. Pinout: 14−Lead Packages Conductors
(Top View)
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
PIN ASSIGNMENT
PIN
FUNCTION
D1, D2
Data Inputs
CP1, CP2
Clock Pulse Inputs
CD1, CD2
Direct Clear Inputs
SD1, SD2
Direct Set Inputs
Q1, Q1, Q2,
Q2
Outputs
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 8
1
Publication Order Number:
MC74AC74/D
MC74AC74, MC74ACT74
TRUTH TABLE (Each Half)
Inputs
Outputs
SD
CD
CP
D
Q
Q
L
H
L
H
H
H
H
L
L
H
H
H
X
X
X
X
X
X
H
L
X
H
L
H
H
L
Q0
L
H
H
L
H
Q0
NOTE:
L
Q1
SD1
D1
Q1
CD1
CP1
Q2
SD2
D2 CP2
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial;
= LOW-to-HIGH Clock Transition
Q0(Q0) = Previous Q(Q) before LOW-to-HIGH
Transition of Clock
Q2
CD2
Figure 2. Logic Symbol
SD
D
Q
CP
Q
CD
NOTE:
This diagram is provided only for the understanding of
logic operations and should not be used to estimate
propagation delays.
Figure 3. Logic Diagram
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2
MC74AC74, MC74ACT74
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
*0.5 to )7.0
V
*0.5 v VI v VCC )0.5
V
*0.5 v VO v VCC )0.5
V
DC Input Diode Current
$20
mA
IOK
DC Output Diode Current
$50
mA
IO
DC Output Sink/Source Current
$50
mA
ICC
DC Supply Current per Output Pin
$50
mA
IGND
DC Ground Current per Output Pin
$50
mA
TSTG
Storage Temperature Range
*65 to )150
°C
TL
Lead temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction temperature under Bias
)150
°C
qJA
Thermal Resistance (Note 2)
SOIC
TSSOP
125
170
°C/W
PD
Power Dissipation in Still Air at 85°C
SOIC
TSSOP
125
170
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 2000
> 200
> 1000
V
ILatch−Up
Latch−Up Performance
Above VCC and Below GND at 85°C (Note 6)
$100
mA
VCC
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
(Note 1)
Level 1
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
Vin, Vout
DC Input Voltage, Output Voltage (Ref. to GND)
tr, tf
Input Rise and Fall Time (Note )
′AC Devices except Schmitt Inputs
Min
Typ
Max
′AC
2.0
5.0
6.0
′ACT
4.5
5.0
5.5
0
−
VCC
VCC @ 3.0 V
−
150
−
VCC @ 4.5 V
−
40
−
VCC @ 5.5 V
−
25
−
VCC @ 4.5 V
−
10
−
VCC @ 5.5 V
−
8.0
−
−
−
140
Unit
V
V
ns/V
tr, tf
Input Rise and Fall Time (Note )
′ACT Devices except Schmitt Inputs
TJ
Junction Temperature (PDIP)
TA
Operating Ambient Temperature Range
−40
25
85
°C
IOH
Output Current − High
−
−
−24
mA
IOL
Output Current − Low
−
−
24
mA
ns/V
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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3
MC74AC74, MC74ACT74
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74AC
74AC
TA = +25°C
TA =
−40°C to
+85°C
Typ
VIH
VIL
VOH
VOL
Guaranteed Limits
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1 V
or VCC − 0.1 V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1 V
or VCC − 0.1 V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
5.5
−
±0.1
5.5
−
5.5
5.5
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
IOLD
†Minimum Dynamic
Output Current
ICC
Conditions
Minimum High Level
Input Voltage
IIN
IOHD
Unit
Maximum Quiescent
Supply Current
IOUT = −50 mA
*VIN = VIL or VIH
−12 mA
IOH
−24 mA
−24 mA
V
IOUT = 50 mA
V
V
*VIN = VIL or VIH
12 mA
IOL
24 mA
24 mA
±1.0
mA
VI = VCC, GND
−
75
mA
VOLD = 1.65 V Max
−
−
−75
mA
VOHD = 3.85 V Min
−
4.0
40
mA
VIN = VCC or GND
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
AC CHARACTERISTICS
Symbol
VCC*
(V)
Parameter
74AC
74AC
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
fmax
Maximum Clock
Frequency
3.3
5.0
100
140
125
160
−
−
95
125
−
−
MHz
3−3
tPLH
Propagation Delay
CDn or SDn to Qn or Qn
3.3
5.0
5.0
3.5
8.0
6.0
12.5
9.0
4.0
3.0
13.0
10.0
ns
3−6
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
3.3
5.0
4.0
3.0
10.5
8.0
12.0
9.5
3.5
2.5
13.5
10.5
ns
3−6
tPLH
Propagation Delay
CPn to Qn or Qn
3.3
5.0
4.5
3.5
8.0
6.0
13.5
10.0
4.0
3.0
16.0
10.5
ns
3−6
tPHL
Propagation Delay
CPn to Qn or Qn
3.3
5.0
3.5
2.5
8.0
6.0
14.0
10.0
3.5
2.5
14.5
10.5
ns
3−6
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
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4
MC74AC74, MC74ACT74
AC OPERATING REQUIREMENTS
Symbol
VCC*
(V)
Parameter
Typ
74AC
74AC
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Guaranteed Minimum
ts
Set-up Time, HIGH or LOW
Dn to CPn
3.3
5.0
1.5
1.0
4.0
3.0
4.5
3.0
ns
3−9
th
Hold Time, HIGH or LOW
Dn to CPn
3.3
5.0
−2.0
−1.5
0.5
0.5
0.5
0.5
ns
3−9
tw
CPn or CDn or SDn
Pulse Width
3.3
5.0
3.0
2.5
5.5
4.5
7.0
5.0
ns
3−6
trec
Recovery TIme
CDn or SDn to CP
3.3
5.0
−2.5
−2.0
0
0
0
0
ns
3−9
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
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5
MC74AC74, MC74ACT74
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74ACT
74ACT
TA = +25°C
TA =
−40°C to
+85°C
Typ
Guaranteed Limits
Unit
Conditions
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
VOUT = 0.1 V
or VCC − 0.1 V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
VOUT = 0.1 V
or VCC − 0.1 V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
4.5
5.5
−
−
3.86
4.86
3.76
4.76
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
4.5
5.5
−
−
0.36
0.36
0.44
0.44
V
*VIN = VIL or VIH
24 mA
IOL
24 mA
VOL
Maximum Low Level
Output Voltage
IOUT = −50 mA
*VIN = VIL or VIH
−24 mA
IOH
−24 mA
V
IOUT = 50 mA
V
IIN
Maximum Input
Leakage Current
5.5
−
±0.1
±1.0
mA
VI = VCC, GND
DICCT
Additional Max. ICC/Input
5.5
0.6
−
1.5
mA
VI = VCC − 2.1 V
IOLD
†Minimum Dynamic
Output Current
5.5
−
−
75
mA
VOLD = 1.65 V Max
5.5
−
−
−75
mA
VOHD = 3.85 V Min
5.5
−
4.0
40
mA
VIN = VCC or GND
IOHD
ICC
Maximum Quiescent
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS
Symbol
VCC*
(V)
Parameter
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
fmax
Maximum Clock
Frequency
5.0
145
210
−
125
−
MHz
3−3
tPLH
Propagation Delay
CDn or SDn to Qn or Qn
5.0
3.0
5.5
9.5
2.5
10.5
ns
3−6
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
5.0
3.0
6.0
10.0
3.0
11.5
ns
3−6
tPLH
Propagation Delay
CPn to Qn or Qn
5.0
4.0
7.5
11.0
4.0
13.0
ns
3−6
tPHL
Propagation Delay
CPn to Qn or Qn
5.0
3.5
6.0
10.0
3.0
11.5
ns
3−6
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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6
MC74AC74, MC74ACT74
AC OPERATING REQUIREMENTS
Symbol
VCC*
(V)
Parameter
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Typ
Unit
Fig.
No.
Guaranteed Minimum
ts
Set-up Time, HIGH or LOW
Dn to CPn
5.0
1.0
3.0
3.5
ns
3−9
th
Hold Time, HIGH or LOW
Dn to CPn
5.0
−0.5
1.0
1.0
ns
3−9
tw
CPn or CDn or SDn
Pulse Width
5.0
3.0
5.0
6.0
ns
3−6
trec
Recovery TIme
CDn or SDn to CP
5.0
−2.5
0
0
ns
3−9
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
35
pF
VCC = 5.0 V
ORDERING INFORMATION
Package
Shipping†
MC74AC74DG
SOIC−14
(Pb−Free)
55 Units/Rail
MC74AC74DR2G
SOIC−14
(Pb−Free)
2500/Tape & Reel
MC74AC74DTR2G
TSSOP−14
(Pb−Free)
2500/Tape & Reel
MC74ACT74DG
SOIC−14
(Pb−Free)
55 Units/Rail
MC74ACT74DR2G
SOIC−14
(Pb−Free)
2500/Tape & Reel
MC74ACT74DTR2G
TSSOP−14
(Pb−Free)
2500/Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MC74AC74, MC74ACT74
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
MC74AC74, MC74ACT74
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25
(0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74AC74, MC74ACT74
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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Phone: 81−3−5817−1050
www.onsemi.com
10
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC74AC74/D
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