M66255FP
8192 × 10-Bit Line Memory (FIFO)
REJ03F0249-0200
Rev.2.00
Sep 14, 2007
Description
The M66255FP is a high-speed line memory with a FIFO (First In First Out) structure of 8192-word × 10-bit
configuration which uses high-performance silicon gate CMOS process technology.
It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between
devices with different data processing throughput.
Features
•
•
•
•
•
•
•
Memory configuration:
8192 words × 10 bits (dynamic memory)
High-speed cycle:
30 ns (Min)
High-speed access:
25 ns (Max)
Output hold:
5 ns (Min)
Fully independent, asynchronous write and read operations
Variable length delay bit
Output:
3 states
Application
Digital photocopiers, high-speed facsimile, laser beam printers.
Block Diagram
Data input
D0 to D9
Data output
Q0 to Q9
15 16 17 18 19 24 25 26 27 28
1
2 3 4
WCK 20
Write
clock input
VCC 21
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 1 of 13
Memory array of
8192-word × 10-bit
configuration
Read control circuit
Write
reset input
Output buffer
Read address counter
WRES 22
Write address counter
WE 23
Write
enable input
Write control circuit
Input buffer
5 10 11 12 13 14
6 RE
Read
enable input
7 RRES
Read
reset input
9 RCK
Read
clock input
8 GND
M66255FP
Pin Arrangement
M66255FP
Data output
Read enable input
Read reset input
Read clock input
Data output
Q0
Q1
Q2
Q3
Q4
RE
RRES
GND
RCK
Q5
Q6
Q7
Q8
Q9
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
D0
D1
D2
D3
D4
WE
WRES
VCC
WCK
D5
D6
D7
D8
D9
(Top view)
Outline: PRSP0028DB-B (28P2W-C)
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 2 of 13
Data input
Write enable input
Write reset input
Write clock input
Data input
M66255FP
Absolute Maximum Ratings
(Ta = 0 to 70°C, unless otherwise noted)
Item
Supply voltage
Symbol
VCC
Input voltage
Output voltage
VI
VO
Power dissipation
Storage temperature
Pd
Tstg
Note:
*
Ratings
−0.5 to +7.0
Unit
V
−0.5 to VCC + 0.5
−0.5 to VCC + 0.5
V
V
825*
−65 to 150
mW
°C
Conditions
A value based on GND pin
Ta = 25°C
Ta ≥ 40°C are derated at −9.7 mW / °C
Recommended Operating Conditions
Min
Typ
Max
Unit
Supply voltage
Supply voltage
Item
VCC
GND
Symbol
4.5
5
0
5.5
V
V
Operating ambient temperature
Topr
0
70
°C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V)
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
"H" input voltage
"L" input voltage
VIH
VIL
2.0
0.8
V
V
"H" output voltage
"L" output voltage
VOH
VOL
VCC − 0.8
0.55
V
V
IOH = −4 mA
IOL = 4 mA
"H" input current
IIH
1.0
µA
VI = VCC
"L" input current
IIL
−1.0
µA
VI = GND
Off state "H" output current
Off state "L" output current
IOZH
IOZL
5.0
−5.0
µA
µA
VO = VCC
VO = GND
Operating mean current
dissipation
ICC
150
mA
Input capacitance
CI
10
pF
VI = VCC, GND, Output open
tWCK, tRCK = 30 ns
f = 1 MHz
Off state output capacitance
CO
15
pF
f = 1 MHz
WE, WRES, WCK,
RE, RRES, RCK,
D0 to D9
WE, WRES, WCK,
RE, RRES, RCK,
D0 to D9
Function
When write enable input WE is "L", the contents of data inputs D0 to D9 are written into memory in synchronization
with rise edge of write clock input WCK. At this time, the write address counter is also incremented simultaneously.
The write functions given below are also performed in synchronization with rise edge of WCK.
When WE is "H", a write operation to memory is inhibited and the write address counter is stopped.
When write reset input WRES is "L", the write address counter is initialized.
When read enable input RE is "L", the contents of memory are output to data outputs Q0 to Q9 in synchronization with
rise edge of read clock input RCK. At this time, the read address counter is also incremented simultaneously.
The read functions given below are also performed in synchronization with rise edge of RCK.
When RE is "H", a read operation from memory is inhibited and the read address counter is stopped. The outputs are in
the high impedance state.
When read reset input RRES is "L", the read address counter is initialized.
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 3 of 13
M66255FP
Switching Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V)
Item
Symbol
Access time
tAC
Min
Typ
Max
25
Unit
ns
Output hold time
Output enable time
tOH
tOEN
5
5
25
ns
ns
Output disable time
tODIS
5
25
ns
Timing Conditions
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted)
Min
Typ
Max
Unit
Write clock (WCK) cycle
Write clock (WCK) "H" pulse width
Item
tWCK
tWCKH
Symbol
30
12
ns
ns
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
tWCKL
tRCK
12
30
ns
ns
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
tRCKH
tRCKL
12
12
ns
ns
Input data setup time to WCK
Input data hold time to WCK
tDS
tDH
5
5
ns
ns
Reset setup time to WCK or RCK
Reset hold time to WCK or RCK
tRESS
tRESH
5
5
ns
ns
Reset nonselect setup time to WCK or RCK
Reset nonselect hold time to WCK or RCK
tNRESS
tNRESH
5
5
ns
ns
WE setup time to WCK
WE hold time to WCK
tWES
tWEH
5
5
ns
ns
WE nonselect setup time to WCK
WE nonselect hold time to WCK
tNWES
tNWEH
5
5
ns
ns
RE setup time to RCK
RE hold time to RCK
tRES
tREH
5
5
ns
ns
RE nonselect setup time to RCK
RE nonselect hold time to RCK
tNRES
tNREH
5
5
ns
ns
Input pulse rise/fall time
Data hold time*
tr, tf
tH
20
20
ns
ms
Notes: Perform reset operation after turning on power supply.
* For 1-line access, the following should be satisfied:
WE "H" level period ≤ 20 ms − 8192 tWCK − WRES "L" level period
RE "H" level period ≤ 20 ms − 8192 tRCK − RRES "L" level period
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 4 of 13
M66255FP
Test Circuit
VCC
RL = 1 kΩ
Qn
SW1
CL = 30 pF: tAC, tOH
Qn
SW2
CL = 5 pF: tOEN, tODIS
RL = 1 kΩ
Input pulse level:
0 to 3 V
Input pulse rise/fall time: 3 ns
Decision voltage input:
1.3 V
Decision voltage output:
1.3 V (However, tODIS (LZ) is 10% of output amplitude and tODIS (HZ) is 90% of that for
decision)
The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe.
Parameter
SW1
SW2
tODIS (LZ)
tODIS (HZ)
Closed
Open
Open
Closed
tOEN (ZL)
tOEN (ZH)
Closed
Open
Open
Closed
tODIS/tOEN Test Condition
3V
RCK
1.3 V
1.3 V
GND
3V
RE
GND
tODIS (HZ)
tOEN (ZH)
VOH
90%
1.3 V
Qn
tODIS (LZ)
Qn
tOEN (ZL)
1.3 V
10%
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 5 of 13
VOL
M66255FP
Operating Timing
Write Cycle
Cycle n
Cycle n + 1
Cycle n + 2
Disable cycle
Cycle n + 3
Cycle n + 4
WCK
tWCKH tWCKL tWEH tNWES
tWCK
tNWEH tWES
WE
tDS tDH
Dn
tDS tDH
(n)
(n + 1)
(n + 2)
(n + 4)
(n + 3)
WRES = "H"
Write Reset Cycle
Cycle n − 1
Cycle n
tWCK
tNRESH tRESS
Reset cycle
Cycle 0
Cycle 1
Cycle 2
WCK
tRESH tNRESS
WRES
Dn
tDS tDH
tDS tDH
(n − 1)
(n)
(0)
(1)
(2)
WE = "L"
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 6 of 13
M66255FP
Matters that Needs Attention when WCK Stops
n cycle
n + 1 cycle
n cycle
Disable cycle
WCK
tWCK
tNWES
WE
Dn
tDS tDH
tDS tDH
(n)
(n)
Period for writing data (n)
into memory
Period for writing data (n)
into memory
WRES = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level
period of n + 1 cycle. The writing operation is complete at the falling edge after n + 1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n + 1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 7 of 13
M66255FP
Read Cycle
Cycle n
Cycle n + 1
Cycle n + 2
tRCK
tRCKH tRCKL
tREH tNRES
Disable cycle
Cycle n + 3
Cycle n + 4
RCK
tNREH
tRES
tAC
RE
tODIS
Qn
(n)
(n + 1)
tOEN
HIGH-Z
(n + 2)
(n + 3)
(n + 4)
tOH
RRES = "H"
Read Reset Cycle
Cycle n − 1
Cycle n
tRCK
tNRESH tRESS
Reset cycle
Cycle 0
Cycle 1
Cycle 2
RCK
tRESH tNRESS
RRES
tAC
Qn
(n − 1)
(n)
(0)
(0)
(0)
(1)
tOH
RE = "L"
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 8 of 13
(2)
M66255FP
Variable Length Delay Bits
1-line (8192 Bits) Delay
A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output
from memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
Cycle 0
Cycle 1
Cycle 8190 Cycle 8191
Cycle 2
Cycle 8192 Cycle 8193 Cycle 8194
(0')
(1')
(2')
WCK
RCK
tRESS tRESH
WRES
RRES
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
(8189)
(8190)
(0')
(8191)
tAC
8192 cycles
(2')
(3')
(1)
(2)
(3)
tOH
(0)
Qn
(1')
WE, RE = "L"
N-bit Delay Bit
(Making a reset at a cycle corresponding to delay length)
Cycle 0
Cycle 1
Cycle n − 2 Cycle n − 1
Cycle 2
Cycle n
(0')
Cycle n + 1 Cycle n + 2 Cycle n + 3
(2')
(3')
(1')
WCK
RCK
tRESS tRESH
tRESS tRESH
WRES
RRES
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
m cycles
Qn
(n − 3)
(n − 2)
(n − 1)
tAC
(0')
(1')
(2')
(3')
(1)
(2)
(3)
tOH
(0)
WE, RE = "L"
m≥3
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 9 of 13
M66255FP
N-bit Delay 2
(Sliding WRES and RRES at a cycle corresponding to delay length)
Cycle 0
Cycle 1
Cycle n − 2 Cycle n − 1
Cycle 2
Cycle n + 1 Cycle n + 2 Cycle n + 3
Cycle n
WCK
RCK
tRESS tRESH
WRES
tRESS tRESH
RRES
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
(n − 2)
(n − 1)
(n)
(0)
Qn
(n + 2)
(n + 3)
(1)
(2)
(3)
tOH
tAC
m cycles
(n + 1)
WE, RE = "L"
m≥3
N-bit Delay 3
(Disabling RE at a cycle corresponding to delay length)
Cycle 0
Cycle 1
Cycle n − 1
Cycle 2
Cycle n
Cycle n + 1 Cycle n + 2 Cycle n + 3
WCK
RCK
tRESS tRESH
WRES
RRES
tNREH tRES
RE
tDS tDH
Dn
(0)
tDS tDH
(1)
(2)
m cycles
(n − 2)
(n − 1)
(n)
tAC
(n + 1)
(n + 2)
(n + 3)
(1)
(2)
(3)
tOH
HIGH-Z
Qn
(0)
WE, RE = "L"
m≥3
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 10 of 13
M66255FP
Shortest Read of Data "n" Written in Cycle n
(Cycle n − 1 on read side should be started after end of cycle n + 1 on write side)
When the start of cycle n − 1 on read side is earlier than the end of cycle n + 1 on write side, output Qn of cycle n
becomes invalid.
In the figure shown below, the read of cycle n − 1 is invalid.
Cycle n + 1
Cycle n
Cycle n + 2
Cycle n + 3
WCK
(n)
Dn
Cycle n − 2
(n + 1)
(n + 2)
Cycle n − 1
(n + 3)
Cycle n
RCK
Invalid
Qn
(n)
Longest Read of Data "n" Written in Cycle n: 1-line Delay
(Cycle n <1>* on read side should be started when cycle n <2>* on write is started)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle
<2>* overlap each other.
Cycle n <1>*
Cycle 0 <2>*
Cycle n <2>*
WCK
Dn
(n − 1) <1>*
(n) <1>*
Cycle n <0>*
(0) <2>*
Cycle 0 <1>*
(n − 1) <2>*
(n) <2>*
Cycle n <1>*
RCK
Qn
(n − 1) <0>*
(n) <0>*
Note: <0>*, <1>* and <2>* indicates a line value.
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 11 of 13
(0) <1>*
(n − 1) <1>*
(n) <1>*
M66255FP
Application Example
Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction
Q0
to
Q9
×2
1-line
delay
Subtractor
2N − (A + B)
B
Line (n + 1)
image data
D0
to
D9
M66255
Q0
to
Q9
Corrected
image data
×K
A
Line (n − 1)
image data
1-line
delay
Adder
A+B
D0
to
D9
Secondary scanning
direction
Adder
N + K {2N − (A + B) }
N
Line n image data
M66255
Primary scanning
direction
A
Line (n − 1)
N
Line n
B
Line (n + 1)
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 12 of 13
N' = N + K { (N − A) + (N − B) }
= N + K {2N − (A + B)}
K: Laplacian coefficient
M66255FP
Package Dimensions
JEITA Package Code
P-SOP28-8.4x17.5-1.27
RENESAS Code
PRSP0028DB-B
Previous Code
28P2W-C
MASS[Typ.]
0.6g
E
15
*1
HE
28
F
A2
1
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
A1
14
Index mark
c
Reference
Symbol
D
A
L
*2
e
y
*3
bp
Detail F
D
E
A2
A1
A
bp
c
HE
e
y
L
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 13 of 13
Dimension in Millimeters
Min Nom Max
17.3 17.5 17.7
8.2 8.4 8.6
2.0
0.05
2.4
0.35 0.4 0.5
0.13 0.15 0.2
0°
10°
11.63 11.93 12.23
1.07 1.27 1.47
0.15
0.8 1.0 1.2
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