Freescale MC68HC708AS48CFN Advance information Datasheet

Advance Information
This document contains information on a new product.
Specifications and information herein are subject to change without notice.
A G R E E M E N T
MC68HC708AS48
N O N - D I S C L O S U R E
HC08
R E Q U I R E D
Order this document by
MC68HC708AS48/D
Rev. 4.0
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Advance Information
Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
©Motorola, Inc., 1999
Advance Information
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Advance Information — MC68HC708AS48
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . 27
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 41
Section 3. Random-Access Memory (RAM) . . . . . . . . . 55
Section 4. Erasable Programmable Read-Only
Memory (EPROM/OTPROM) . . . . . . . . . . . . . . . . . 57
Section 5. Configuration Register (CONFIG) . . . . . . . . . 63
Section 6. Electrically Erasable Programmable
ROM (EEPROM). . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Section 7. Central Processor Unit (CPU) . . . . . . . . . . . . 79
Section 8. Clock Generator Module (CGM) . . . . . . . . . 97
Section 9. System Integration Module (SIM) . . . . . . . . 125
Section 10. Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . 149
Section 11. Break Module (Break) . . . . . . . . . . . . . . . . 155
Section 12. Monitor ROM (MON) . . . . . . . . . . . . . . . . . 161
Section 13. Computer Operating Properly (COP) . . . 171
Section 14. External Interrupt . . . . . . . . . . . . . . . . . . . . 177
Section 15. Input/Output (I/O) Ports . . . . . . . . . . . . . . 185
Section 16. Timer Interface (TIM) . . . . . . . . . . . . . . . . . 211
Section 17. Serial Communications Interface (SCI) . . 243
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Advance Information
List of Sections
3
List of Sections
Section 18. Serial Peripheral Interface (SPI) . . . . . . . . 283
Section 19. Analog-to-Digital Converter (ADC) . . . . . 317
Section 20. Byte Data Link Controller–Digital
(BDLC–D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Section 21. Electrical Specifications . . . . . . . . . . . . . . 377
Section 22. Mechanical Specifications . . . . . . . . . . . . 391
Section 23. Ordering Information . . . . . . . . . . . . . . . . . 393
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MOTOROLA
Advance Information — MC68HC708AS48
Table of Contents
Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.5.1
Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . .33
1.5.2
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . .34
1.5.3
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .34
1.5.4
External Interrupt Pin (IRQ/VPP) . . . . . . . . . . . . . . . . . . . . .34
1.5.5
Analog Power Supply Pin (VDDA/VDDAREF). . . . . . . . . . . . .34
1.5.6
Analog Ground Pin (VSSA/VREFL) . . . . . . . . . . . . . . . . . . . .34
1.5.7
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . .35
1.5.8
Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . .35
1.5.9
Port B I/O Pins (PTB7/ATD7–PTB0/ATD0). . . . . . . . . . . . .35
1.5.10
Port C I/O Pins (PTC5–PTC0). . . . . . . . . . . . . . . . . . . . . . .35
1.5.11
Port D I/O Pins (PTD7/ATD15–PTD0/ATD8) . . . . . . . . . . .35
1.5.12
Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . .36
1.5.13
Port F I/O Pins (PTF4–PTF0/TCH2) . . . . . . . . . . . . . . . . . .36
1.5.14
Port G I/O Pins (PTG2–PTG0) . . . . . . . . . . . . . . . . . . . . . .36
1.5.15
J1850 Transmit Pin Digital (BDTxD) . . . . . . . . . . . . . . . . . .36
1.5.16
J1850 Receive Pin Digital (BDRxD) . . . . . . . . . . . . . . . . . .36
Section 2. Memory Map
2.1
2.2
2.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
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Section 3. Random-Access Memory (RAM)
3.1
3.2
3.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Section 4. Erasable Programmable Read-Only Memory
(EPROM/OTPROM)
4.1
4.2
4.3
4.4
4.5
4.6
4.6.1
4.6.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
EPROM/OTPROM Control Register. . . . . . . . . . . . . . . . . . . . .59
EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . . .60
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Section 5. Configuration Register (CONFIG)
5.1
5.2
5.3
5.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Section 6. Electrically Erasable Programmable ROM
(EEPROM)
6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . .68
EEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . . . . . .72
EEPROM Redundant Mode . . . . . . . . . . . . . . . . . . . . . . . .73
EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .73
EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . .74
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6.4.7
6.4.8
6.4.8.1
6.4.8.2
EEPROM Non-Volatile Register and
EEPROM Array Configuration Register . . . . . . . . . . . . .76
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Section 7. Central Processor Unit (CPU)
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.5
7.6
7.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .87
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .87
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7.8
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Section 8. Clock Generator Module (CGM)
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.4.1
Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.4.2
Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .101
8.4.2.1
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.4.2.2
Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . .103
8.4.2.3
Manual and Automatic PLL Bandwidth Modes . . . . . . .103
8.4.2.4
Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . .105
8.4.2.5
Special Programming Exceptions . . . . . . . . . . . . . . . . .107
8.4.3
Base Clock Selector Circuit. . . . . . . . . . . . . . . . . . . . . . . .107
8.4.4
CGM External Connections. . . . . . . . . . . . . . . . . . . . . . . .108
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8.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
8.5.1
Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . .109
8.5.2
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . .109
8.5.3
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . .109
8.5.4
Analog Power Pin (VDDA/VDDAREF). . . . . . . . . . . . . . . . . .110
8.5.5
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . .110
8.5.6
Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . .110
8.5.7
CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . .110
8.5.8
CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . .110
8.6
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8.6.1
PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.6.2
PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .114
8.6.3
PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . .116
8.7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
8.8
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.9
CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .119
8.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .119
8.10.1
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . .119
8.10.2
Parametric Influences on Reaction Time . . . . . . . . . . . . .121
8.10.3
Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . .122
8.10.4
Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . .123
Section 9. System Integration Module (SIM)
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
9.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .129
9.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
9.3.2
Clock Startup from POR or LVI Reset. . . . . . . . . . . . . . . .129
9.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . .130
9.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .130
9.4.1
External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . .132
9.4.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.4.2.2
Computer Operating Properly (COP) Reset . . . . . . . . .134
9.4.2.3
Illegal Opcode Reset. . . . . . . . . . . . . . . . . . . . . . . . . . .134
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9.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . .134
9.4.2.5
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . .134
9.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . .135
9.5.2
SIM Counter During Stop Mode Recovery . . . . . . . . . . . .135
9.5.3
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . .135
9.6
Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . .136
9.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
9.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9.6.1.2
SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
9.6.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.6.3
Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.6.4
Status Flag Protection in Break Mode. . . . . . . . . . . . . . . .140
9.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
9.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
9.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
9.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
9.8.1
SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . .144
9.8.2
Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9.8.3
SIM Break Flag Control Register. . . . . . . . . . . . . . . . . . . .147
Section 10. Low-Voltage Inhibit (LVI)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
10.4.1
Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
10.4.2
Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . .151
10.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
10.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
10.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
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Section 11. Break Module (Break)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.4.1
Flag Protection During Break Interrupts . . . . . . . . . . . . . .157
11.4.2
CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . .158
11.4.3
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .158
11.4.4
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .158
11.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
11.5.1
Break Status and Control Register . . . . . . . . . . . . . . . . . .159
11.5.2
Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . .160
11.6 Wait or Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Section 12. Monitor ROM (MON)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
12.4.1
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .164
12.4.2
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
12.4.3
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
12.4.4
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
12.4.5
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12.4.6
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Section 13. Computer Operating Properly (COP)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.1
CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.2
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.3
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.4
Internal Reset Resources . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.5
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
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13.4.6
COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.7
COPL (COP Long Timeout) . . . . . . . . . . . . . . . . . . . . . . .175
13.5 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
13.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
13.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
13.9 COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . .176
Section 14. External Interrupt
14.1
14.2
14.3
14.4
14.5
14.6
14.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .182
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .182
Section 15. Input/Output (I/O) Ports
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
15.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
15.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
15.3.2
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .189
15.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.4.2
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .192
15.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
15.5.1
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
15.5.2
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .195
15.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
15.6.1
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
15.6.2
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . .199
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15.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
15.7.1
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
15.7.2
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . .203
15.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
15.8.1
Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
15.8.2
Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . .206
15.9 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
15.9.1
Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
15.9.2
Data Direction Register G . . . . . . . . . . . . . . . . . . . . . . . . .209
Section 16. Timer Interface (TIM)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
16.4.1
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . .216
16.4.2
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
16.4.3
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
16.4.3.1
Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . .218
16.4.3.2
Buffered Output Compare. . . . . . . . . . . . . . . . . . . . . . .219
16.4.4
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . .220
16.4.4.1
Unbuffered PWM Signal Generation. . . . . . . . . . . . . . .221
16.4.4.2
Buffered PWM Signal Generation. . . . . . . . . . . . . . . . .222
16.4.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
16.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
16.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
16.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
16.7 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .226
16.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
16.8.1
TIM Clock Pin (PTD6/ATD14/TCLK) . . . . . . . . . . . . . . . . .227
16.8.2
TIM Channel I/O Pins (PTF3/TCH5–PTF0/TCH2,
PTE3/TCH1–PTE2/TCH0) . . . . . . . . . . . . . . . . . . . . . .227
16.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
16.9.1
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .228
16.9.2
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .231
16.9.3
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .232
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16.9.4
16.9.5
TIM Channel Status and Control Registers. . . . . . . . . . . .233
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .238
Section 17. Serial Communications Interface (SCI)
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
17.4.1
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.4.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.4.3
Character Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.4.4
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . .249
17.4.5
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
17.4.6
Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
17.4.7
Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . .253
17.4.8
Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
17.4.9
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
17.4.10 Character Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
17.4.11 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
17.4.12 Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
17.4.13 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
17.4.14 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
17.5 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
17.5.1
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
17.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
17.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
17.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .263
17.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
17.8.1
PTE0/TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . .264
17.8.2
PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . .264
17.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
17.9.1
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .265
17.9.2
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .269
17.9.3
SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .271
17.9.4
SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
17.9.5
SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
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17.9.6
17.9.7
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .280
Section 18. Serial Peripheral Interface (SPI)
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
18.4 Pin Name and Register Name Conventions . . . . . . . . . . . . . .285
18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
18.5.1
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
18.5.2
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
18.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
18.6.1
Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . .290
18.6.2
Transmission Format When CPHA = 0 . . . . . . . . . . . . . . .291
18.6.3
Transmission Format When CPHA = 1 . . . . . . . . . . . . . . .292
18.6.4
Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . .294
18.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
18.7.1
Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
18.7.2
Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
18.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
18.9 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .301
18.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
18.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
18.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
18.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
18.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .305
18.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
18.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . .306
18.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . .307
18.13.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
18.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
18.13.5 VSS (Clock Ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
18.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
18.14.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
18.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .312
18.14.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
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Section 19. Analog-to-Digital Converter (ADC)
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
19.4.1
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
19.4.2
Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
19.4.3
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
19.4.4
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .321
19.4.5
Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . .321
19.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
19.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
19.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
19.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
19.7.1
ADC Analog Power Pin (VDDAREF)/ADC
Voltage Reference Pin (VREFH) . . . . . . . . . . . . . . . . . .322
19.7.2
ADC Analog Ground Pin (VSSA)/ADC
Voltage Reference Low Pin (VREFL). . . . . . . . . . . . . . .323
19.7.3
ADC Voltage In (ADCVIN). . . . . . . . . . . . . . . . . . . . . . . . .323
19.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
19.8.1
ADC Status and Control Register . . . . . . . . . . . . . . . . . . .324
19.8.2
ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
19.8.3
ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . .327
Section 20. Byte Data Link Controller–Digital (BDLC–D)
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
20.4.1
BDLC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . .334
20.4.1.1
Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
20.4.1.2
Reset Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
20.4.1.3
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
20.4.1.4
BDLC Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
20.4.1.5
BDLC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
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20.4.1.6
Digital Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . .336
20.4.1.7
Analog Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . .336
20.5 BDLC MUX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
20.5.1
Rx Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
20.5.1.1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
20.5.1.2
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
20.5.2
J1850 Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
20.5.3
J1850 VPW Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
20.5.4
J1850 VPW Valid/Invalid Bits and Symbols . . . . . . . . . . .346
20.5.5
Message Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
20.6 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
20.6.1
Protocol Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
20.6.2
Rx and Tx Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . .353
20.6.3
Rx and Tx Shadow Registers . . . . . . . . . . . . . . . . . . . . . .354
20.6.4
Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . .354
20.6.5
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
20.6.5.1
4X Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
20.6.5.2
Receiving a Message in Block Mode . . . . . . . . . . . . . .355
20.6.5.3
Transmitting a Message in Block Mode . . . . . . . . . . . .355
20.6.5.4
J1850 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
20.6.5.5
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
20.7 BDLC CPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
20.7.1
BDLC Analog and Roundtrip Delay. . . . . . . . . . . . . . . . . .358
20.7.2
BDLC Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . .360
20.7.3
BDLC Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . .363
20.7.4
BDLC State Vector Register . . . . . . . . . . . . . . . . . . . . . . .371
20.7.5
BDLC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
20.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
20.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
20.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
Section 21. Electrical Specifications
21.1
21.2
21.3
21.4
21.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .379
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . .380
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21.6
21.7
21.8
21.9
21.10
21.11
21.12
21.13
21.14
21.15
21.16
21.17
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing . . . . .383
CGM Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .386
CGM Component Information. . . . . . . . . . . . . . . . . . . . . . . . .386
CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . .387
Timer Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .388
Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
BDLC Transmitter VPW Symbol Timings . . . . . . . . . . . . . . . .388
BDLC Receiver VPW Symbol Timings . . . . . . . . . . . . . . . . . .389
BDLC Transmitter DC Electrical Characteristics . . . . . . . . . .390
BDLC Receiver DC Electrical Characteristics . . . . . . . . . . . .390
Section 22. Mechanical Specifications
22.1
22.2
22.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
52-Pin Plastic Leaded Chip
Carrier Package (Case 778) . . . . . . . . . . . . . . . . . . . . . . .392
Section 23. Ordering Information
23.1
23.2
23.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
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Title
1-1
1-2
1-3
1-4
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
52-Pin PLCC Assignments (Top View) . . . . . . . . . . . . . . . .31
64-Pin QFP Assignments (Top View). . . . . . . . . . . . . . . . . .32
Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Control, Status, and Data Registers. . . . . . . . . . . . . . . . . . .45
4-1
EPROM/OTPROM Control Register (EPMCR) . . . . . . . . . .59
5-1
Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . .64
6-1
6-2
6-3
EEPROM Control Register (EECR) . . . . . . . . . . . . . . . . . . .74
EEPROM Array Control Register (EEACR) . . . . . . . . . . . . .76
EEPROM Non-Volatile Register (EENVR) . . . . . . . . . . . . . .76
7-1
7-2
7-3
7-4
7-5
7-6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .85
8-1
8-2
8-3
8-4
8-5
8-6
8-7
CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
CGM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .101
CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . .109
CGM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .111
PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . .112
PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . .114
PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . .116
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R E Q U I R E D
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A G R E E M E N T
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N O N - D I S C L O S U R E
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N O N - D I S C L O S U R E
A G R E E M E N T
Figure
Title
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
SIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .128
CGM Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . .132
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Interrupt Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . .138
Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . .139
Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . .142
Wait Recovery from Internal Reset . . . . . . . . . . . . . . . . . .142
Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .143
Stop Mode Recovery from Interrupt or Break. . . . . . . . . . .143
SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . .144
SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . .146
SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .147
10-1
10-2
10-3
LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .150
LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .151
LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . .152
11-1
11-2
11-3
11-4
11-5
Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . .157
Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .157
Break Status and Control Register (BRKSCR) . . . . . . . . .159
Break Address Register (BRKH) . . . . . . . . . . . . . . . . . . . .160
Break Address Register (BRKL). . . . . . . . . . . . . . . . . . . . .160
12-1
12-2
12-3
12-4
12-5
Monitor Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Monitor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . .165
Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Break Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
13-1
13-2
COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
COP I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .172
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—
Page
13-3
COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . .175
14-1
14-2
14-3
14-4
IRQ Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
IRQ I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .179
IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .180
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . .183
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
15-13
15-14
15-15
15-16
15-17
15-18
15-19
15-20
15-21
15-22
I/O Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . .186
Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .188
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . .189
Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .191
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . .192
Port B I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . .194
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . .195
Port C I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . .197
Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . .199
Port D I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . .201
Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . .203
Port E I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . .205
Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . .206
Port F I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Port G Data Register (PTG) . . . . . . . . . . . . . . . . . . . . . . . .208
Data Direction Register G (DDRG) . . . . . . . . . . . . . . . . . .209
Port G I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
16-1
16-2
16-3
16-4
16-5
16-6
TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . .214
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . .220
TIM Status and Control Register (TSC) . . . . . . . . . . . . . . .229
TIM Counter Registers (TCNTH and TCNTL) . . . . . . . . . .231
TIM Counter Modulo Registers
(TMODH and TMODL) . . . . . . . . . . . . . . . . . . . . . . . . .232
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Title
N O N - D I S C L O S U R E
Figure
R E Q U I R E D
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Figure
N O N - D I S C L O S U R E
A G R E E M E N T
16-7
Title
16-8
16-9
TIM Channel Status
and Control Registers (TSC0–TSC5) . . . . . . . . . . . . . .233
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
TIM Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . . . .239
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
17-13
17-14
17-15
17-16
SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .246
SCI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .247
SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Transmitter I/O Register Summary. . . . . . . . . . . . . . . . . . .251
SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .255
SCI Receiver I/O Register Summary . . . . . . . . . . . . . . . . .256
Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .258
SCI Control Register 1 (SCC1) . . . . . . . . . . . . . . . . . . . . .266
SCI Control Register 2 (SCC2) . . . . . . . . . . . . . . . . . . . . .269
SCI Control Register 3 (SCC3) . . . . . . . . . . . . . . . . . . . . .272
SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . .274
Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .277
SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . .278
SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . .279
SCI BAUD Rate Register 1 (SCBR) . . . . . . . . . . . . . . . . . .280
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .286
SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .287
Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . .288
Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . .291
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . .293
Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . .295
Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . .297
Clearing SPRF When OVRF Interrupt Is Not Enabled . . . .298
SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . .301
SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . .302
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . .310
SPI Status and Control Register (SPSCR). . . . . . . . . . . . .313
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . .316
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20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
BDLC Input/Output (I/O) Register Summary . . . . . . . . . . .333
BDLC Operating Modes State Diagram . . . . . . . . . . . . . . .334
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . .338
J1850 Bus Message Format (VPW). . . . . . . . . . . . . . . . . .340
J1850 VPW Symbols with Nominal Symbol Times . . . . . .344
J1850 VPW Received Passive Symbol Times . . . . . . . . . .347
J1850 VPW Received Passive
EOF and IFS Symbol Times . . . . . . . . . . . . . . . . . . . . .348
J1850 VPW Received Active Symbol Times . . . . . . . . . . .349
J1850 VPW Received BREAK Symbol Times . . . . . . . . . .350
J1850 VPW Bitwise Arbitrations. . . . . . . . . . . . . . . . . . . . .351
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . .353
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
BDLC Analog and Roundtrip Delay Register (BARD) . . . .358
BDLC Control Register 1 (BCR1) . . . . . . . . . . . . . . . . . . . .360
BDLC Control Register 2 (BCR2) . . . . . . . . . . . . . . . . . . . .363
Types of In-Frame Response (IFR) . . . . . . . . . . . . . . . . . .367
BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . .371
BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . .373
MOTOROLA
SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384
SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
BDLC Variable Pulse Width Modulation (VPW)
Symbol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
Rev. 4.0
Advance Information
List of Figures
23
A G R E E M E N T
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
ADC Status and Control Register (ADSCR). . . . . . . . . . . .324
ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . .327
ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . .327
21-1
21-2
21-3
—
Page
19-1
19-2
19-3
19-4
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
20-21
MC68HC708AS48
Title
N O N - D I S C L O S U R E
Figure
R E Q U I R E D
List of Figures
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
List of Figures
Advance Information
24
MC68HC708AS48 — Rev. 4.0
List of Figures
MOTOROLA
Advance Information — MC68HC708AS48
List of Tables
Table
Title
1-1
1-2
External Pins Summary .........................................................37
Clock Source Summary..........................................................39
2-1
Vector Addresses ..................................................................53
6-1
6-2
6-3
EEPROM Program/Erase Cycling Reduction.........................71
EEPROM Array Address Blocks.............................................72
EEPROM Program/Erase Mode Select..................................75
7-1
7-2
Instruction Set Summary ........................................................88
Opcode Map ...........................................................................96
8-1
VCO Frequency Multiplier (N) Selection...............................116
9-1
9-2
Signal Name Conventions ....................................................128
PIN Bit Set Timing ................................................................131
10-1
LVIOUT Bit Indication ...........................................................152
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
Mode Selection ....................................................................164
Mode Differences .................................................................165
READ (Read Memory) Command ........................................167
WRITE (Write Memory) Command.......................................168
IREAD (Indexed Read) Command .......................................168
IWRITE (Indexed Write) Command......................................169
READSP (Read Stack Pointer) Command...........................169
RUN (Run User Program) Command...................................170
Monitor Baud Rate Selection................................................170
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Page
List of Tables
List of Tables
25
List of Tables
Table
Title
15-1
15-2
15-3
15-4
15-5
15-6
15-7
Port A Pin Functions.............................................................190
Port B Pin Functions.............................................................193
Port C Pin Functions.............................................................196
Port D Pin Functions.............................................................200
Port E Pin Functions.............................................................204
Port F Pin Functions .............................................................207
Port G Pin Functions ............................................................210
16-1
16-2
Prescaler Selection...............................................................230
Mode, Edge, and Level Selection.........................................237
17-1
17-2
17-3
17-4
17-5
17-6
17-7
Start Bit Verification ..............................................................259
Data Bit Recovery.................................................................259
Stop Bit Recovery.................................................................260
Character Format Selection..................................................268
SCI Baud Rate Prescaling....................................................280
SCI Baud Rate Selection......................................................281
SCI Baud Rate Selection Examples .....................................282
18-1
18-2
18-3
18-4
18-5
Pin Name Conventions.........................................................285
I/O Register Addresses ........................................................285
SPI Interrupts........................................................................300
SPI Configuration .................................................................309
SPI Master Baud Rate Selection ..........................................315
19-1
19-2
Mux Channel Select .............................................................326
ADC Clock Divide Ratio........................................................328
20-1
20-2
20-3
20-4
20-5
BDLC J1850 Bus Error Summary.........................................357
BDLC Transceiver Delay .....................................................360
BDLC Rate Selection............................................................362
BDLC Transmit In-Frame Response
Control Bit Priority Encoding............................................366
BDLC Interrupt Sources .......................................................371
23-1
MC Order Numbers ..............................................................393
List of Tables
26
Page
MC68HC708AS48 — Rev. 4.0
List of Tables
MOTOROLA
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.4
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.5.1
Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . .33
1.5.2
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . .34
1.5.3
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .34
1.5.4
External Interrupt Pin (IRQ/VPP) . . . . . . . . . . . . . . . . . . . . .34
1.5.5
Analog Power Supply Pin (VDDA/VDDAREF). . . . . . . . . . . . .34
1.5.6
Analog Ground Pin (VSSA/VREFL) . . . . . . . . . . . . . . . . . . . .34
1.5.7
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . .35
1.5.8
Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . .35
1.5.9
Port B I/O Pins (PTB7/ATD7–PTB0/ATD0). . . . . . . . . . . . .35
1.5.10
Port C I/O Pins (PTC5–PTC0). . . . . . . . . . . . . . . . . . . . . . .35
1.5.11
Port D I/O Pins (PTD7/ATD15–PTD0/ATD8) . . . . . . . . . . .35
1.5.12
Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . .36
1.5.13
Port F I/O Pins (PTF4–PTF0/TCH2) . . . . . . . . . . . . . . . . . .36
1.5.14
Port G I/O Pins (PTG2–PTG0) . . . . . . . . . . . . . . . . . . . . . .36
1.5.15
J1850 Transmit Pin Digital (BDTxD) . . . . . . . . . . . . . . . . . .36
1.5.16
J1850 Receive Pin Digital (BDRxD) . . . . . . . . . . . . . . . . . .36
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
General Description
27
R E Q U I R E D
1.1 Contents
A G R E E M E N T
Section 1. General Description
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
1.2 Introduction
The MC68HC708AS48 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
1.3 Features
Features of the MC68HC708AS48 include:
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
General Description
•
High-performance M68HC08 architecture
•
Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
•
8.4-MHz internal bus frequency
•
49,152 bytes of on-chip UV erasable programmable read-only
memory (EPROM) or one-time programmable read-only memory
(OTPROM)
•
On-chip programming firmware for use with host personal
computer
•
EPROM/OTPROM data security1
•
640 bytes of on-chip electrically erasable programmable read-only
memory (EEPROM)
•
1,536 bytes of on-chip RAM
•
Serial peripheral interface module (SPI)
•
Serial communications interface module (SCI)
•
16-bit, 6-channel timer interface module (TIM)
•
Clock generator module (CGM)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
Advance Information
28
MC68HC708AS48 — Rev. 4.0
General Description
MOTOROLA
•
8-bit, 15-channel in 52-pin plastic leaded chip carrier (PLCC), or
16-channel in 64-pin quad flat pack (QFP) analog-to-digital
converter module (ADC)
•
SAE J1850 byte data link controller digital module (BDLC-D)
•
System protection features
– Computer operating properly (COP) with optional reset
– Low-voltage detection with optional reset
R E Q U I R E D
General Description
MCU Block Diagram
A G R E E M E N T
– Illegal opcode detection with optional reset
– Illegal address detection with optional reset
•
Low-power design (fully static with stop and wait modes)
•
Master reset pin and power-on reset
•
Enhanced HC05 programming model
•
Extensive loop control functions
•
16 addressing modes (eight more than the HC05)
•
16-bit index register and stack pointer
•
Memory-to-memory data transfers
•
Fast 8 × 8 multiply instruction
•
Fast 16/8 divide instruction
•
Binary-coded decimal (BCD) instructions
•
Optimization for controller applications
•
C language support
N O N - D I S C L O S U R E
Features of the CPU08 include:
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC708AS48.
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
Advance Information
General Description
29
BREAK
MODULE
PTA
CONTROL AND STATUS REGISTERS — 62 BYTES
PTB
ANALOG-TO-DIGITAL CONVERTER
MODULE
PTB7/ATD7–PTB0/ATD0
PTC
ARITHMETIC/LOGIC
UNIT (ALU)
PTA7–PTA0
PTC5–PTC3
PTC2/MCLK
PTC1–PTC0
DDRC
CPU
REGISTERS
VREFH
USER EPROM — 49,152 BYTES
(PTC5: 64-PIN PACKAGE ONLY)
LOW-VOLTAGE INHIBIT
MODULE
PTD7/ATD15
PTD6/ATD14/TCLK
PTD5/ATD13–PTD3/ATD11
PTD2/ATD10
PTD1/ATD9–PTD0/ATD8
USER RAM — 1536 BYTES
General Description
MONITOR ROM — 224 BYTES
PTD
COMPUTER OPERATING PROPERLY
MODULE
DDRD
USER EEPROM — 640 BYTES
(PTD7/ATD15: 64-PIN PACKAGE ONLY)
TIMER INTERFACE
MODULE
SYSTEM INTEGRATION
MODULE
BYTE DATA LINK CONTROLLER
DIGITAL MODULE
MOTOROLA
MC68HC708AS48 — Rev. 4.0
IRQ/VPP
IRQ
MODULE
POWER-ON RESET
MODULE
VSS
VDD
VDDA/VDDAREF
VSSA/VREFL
BDRxD
BDTxD
DDRG
RST
DDRF
SERIAL PERIPHERAL INTERFACE
MODULE
PTE
PTF4
PTF3/TCH5
PTF2/TCH4
PTF1/TCH3
PTF0/TCH2
(PTF4: 64-PIN PACKAGE ONLY)
PTF
CLOCK GENERATOR
MODULE
SERIAL COMMUNICATIONS INTERFACE
MODULE
PTG
OSC1
OSC2
CGMXFC
DDRE
USER EPROM VECTOR SPACE — 36 BYTES
PTE7/SPSCK
PTE6/MOSI
PTE5/MISO
PTE4/SS
PTE3/TCH1
PTE2/TCH0
PTE1/RxD
PTE0/TxD
PTG2-PTG0
(PTG: 64-PIN PACKAGE ONLY)
POWER
Figure 1-1. MCU Block Diagram
General Description
Advance Information
30
INTERNAL BUS
M68HC08 CPU
R E Q U I R E D
DDRA
A G R E E M E N T
DDRB
N O N - D I S C L O S U R E
R E Q U I R E D
General Description
Pin Assignments
1.5 Pin Assignments
VREFH
PTD6/ATD14/TCLK
PTD5/ATD13
50
49
48
IRQ/VPP
46
PTD3/ATD11
9
45
PTD2/ATD10
RST
10
44
PTD1/ATD9
PTF0/TCH2
11
43
PTD0/ATD8
PTF1/TCH3
12
42
PTB7/ATD7
PTF2/TCH4
13
41
PTB6/ATD6
PTF3/TCH5
14
40
PTB5/ATD5
BDRxD
15
39
PTB4/ATD4
BDTxD
16
38
PTB3/ATD3
PTE0/TxD
17
37
PTB2/ATD2
PTE1/RxD
18
36
PTB1/ATD1
PTE2/TCH0
19
35
PTB0/ATD0
34
21
22
23
24
25
26
27
28
29
30
31
32
33
PTE5/MISO
PTE6/MOSI
PTE7/SPSCK
VSS
VDD
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
20
PTE4/SS
PTE3/TCH1
A G R E E M E N T
47
8
N O N - D I S C L O S U R E
PTC4
PTD4/ATD12
VDDA/VDDAREF
OSC2
2
51
OSC1
3
VSSA/VREFL
PTC0
4
52
PTC1
5
CGMXFC
PTC2/MCLK
6
1
PTC3
7
Figure 1-2 shows the 52-pin PLCC assignments.
PTA7
Figure 1-2. 52-Pin PLCC Assignments (Top View)
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
Advance Information
General Description
31
R E Q U I R E D
General Description
PTC1
PTC0
OSC1
OSC2
CGMXFC
VSSA/VREFL
VDDA/VDDAREF
VREFH
PTD7/ATD15
PTD6/ATD14/TCLK
PTD5/ATD13
PTD4/ATD12
61
60
59
58
57
56
55
54
53
52
51
50
NC
PTC2/MCLK
62
49
PTC3
1
48
NC
PTB7/ATD7
BDRxD
9
40
PTB6/ATD6
BDTxD
10
39
PTB5/ATD5
NC
11
38
PTB4/ATD4
NC
12
37
PTB3/ATD3
PTE0/TxD
13
36
PTB2/ATD2
PTE1/RxD
14
35
PTB1/ATD1
PTE2/TCH0
15
34
PTB0/ATD0
33
PTA7
PTA6 32
PTE4/SS 17
PTE3/TCH1 16
31
41
PTA5
8
30
PTF4
PTA4
PTD0/ATD8
29
42
PTA3
7
28
PTF3/TCH5
PTA2
PTD1/ATD9
27
43
PTA1
6
26
PTF2/TCH4
PTA0
NC
25
44
PTG2
5
24
PTF1/TCH3
PTG1
NC
23
45
PTG0
4
22
PTF0/TCH2
VDD
PTD2/ATD10
21
46
VSS
3
20
RST
PTE7/SPSCK
PTD3/ATD11
19
47
PTE6/MOSI
2
18
IRQ/VPP
PTE5/MISO
N O N - D I S C L O S U R E
A G R E E M E N T
PTC4
63
64 PTC5
Figure 1-3 shows the 64-pin QFP assignments.
Figure 1-3. 64-Pin QFP Assignments (Top View)
Advance Information
32
MC68HC708AS48 — Rev. 4.0
General Description
MOTOROLA
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-4
shows. Place the C1 bypass capacitor as close to the MCU as possible.
Use a high-frequency-response ceramic capacitor for C1. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high current levels.
MCU
VDD
VSS
C1
0.1 µF
+
C2
VDD
NOTE: Component values shown represent typical applications.
Figure 1-4. Power Supply Bypassing
VSS is also the ground for the port output buffers and the ground return
for the serial clock in the serial peripheral interface module (SPI). (See
Section 18. Serial Peripheral Interface (SPI).)
NOTE:
MC68HC708AS48
MOTOROLA
—
VSS must be grounded for proper MCU operation.
Rev. 4.0
Advance Information
General Description
33
A G R E E M E N T
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
N O N - D I S C L O S U R E
1.5.1 Power Supply Pins (VDD and VSS)
R E Q U I R E D
General Description
Pin Assignments
A G R E E M E N T
R E Q U I R E D
General Description
1.5.2 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. (See Section 8. Clock Generator Module (CGM).)
1.5.3 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. (See Section 9. System
Integration Module (SIM) for more information.)
1.5.4 External Interrupt Pin (IRQ/VPP)
IRQ/VPP is an asynchronous external interrupt pin. IRQ/VPP is also the
EPROM/OTPROM programming power pin. (See Section 14. External
Interrupt and Section 4. Erasable Programmable Read-Only
Memory (EPROM/OTPROM).)
N O N - D I S C L O S U R E
1.5.5 Analog Power Supply Pin (VDDA/VDDAREF)
VDDA/VDDAREF is the power supply pin for the analog portion of the chip.
These modules are the analog-to-digital converter (ADC) and the clock
generator module (CGM). (See Section 8. Clock Generator Module
(CGM) and Section 19. Analog-to-Digital Converter (ADC).)
1.5.6 Analog Ground Pin (VSSA/VREFL)
The VSSA/VREFL analog ground pin is used only for the ground
connections for the analog sections of the circuit and should be
decoupled as per the VSS digital ground pin. The analog sections consist
of a clock generator module (CGM) and an analog-to-digital converter
(ADC). VSSA/VREFL is also the lower reference supply for the ADC. (See
Section 8. Clock Generator Module (CGM)
and Section 19. Analog-to-Digital Converter (ADC).)
Advance Information
34
MC68HC708AS48 — Rev. 4.0
General Description
MOTOROLA
CGMXFC is an external filter capacitor connection for the CGM. (See
Section 8. Clock Generator Module (CGM).)
1.5.8 Port A Input/Output (I/O) Pins (PTA7–PTA0)
PTA7–PTA0 are general-purpose bidirectional I/O port pins. (See
Section 15. Input/Output (I/O) Ports.)
1.5.9 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0)
Port B is an 8-bit special function port that shares all eight pins with the
analog-to-digital converter (ADC). (See Section 19. Analog-to-Digital
Converter (ADC) and Section 15. Input/Output (I/O) Ports.)
1.5.10 Port C I/O Pins (PTC5–PTC0)
PTC5–PTC3 and PTC1–PTC0 are general-purpose bidirectional I/O
port pins. PTC2/MCLK is a special function port that shares its pin with
the system clock. PTC5 is only available with the 64-pin QFP package.
(See Section 15. Input/Output (I/O) Ports.)
1.5.11 Port D I/O Pins (PTD7/ATD15–PTD0/ATD8)
Port D is a 8-bit special function port that shares all of its pins with the
analog-to-digital converter module (ADC) and one of its pins with the
timer interface module (TIM). PTD7/ATD15 is only available with the
64-pin QFP package. (See Section 16. Timer Interface (TIM), Section
19. Analog-to-Digital Converter (ADC), and
Section 15. Input/Output (I/O) Ports.).
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
Advance Information
General Description
35
N O N - D I S C L O S U R E
1.5.7 External Filter Capacitor Pin (CGMXFC)
A G R E E M E N T
R E Q U I R E D
General Description
Pin Assignments
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
General Description
1.5.12 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD)
Port E is an 8-bit special function port that shares two of its pins with the
timer interface module (TIM), four of its pins with the serial peripheral
interface module (SPI), and two of its pins with the serial communication
interface module (SCI). (See Section 17. Serial Communications
Interface (SCI), Section 18. Serial Peripheral Interface (SPI), Section
16. Timer Interface (TIM), and Section 15. Input/Output (I/O) Ports.)
1.5.13 Port F I/O Pins (PTF4–PTF0/TCH2)
Port F is a 5-bit special function port that shares four of its pins with the
timer interface module (TIM). (See Section 16. Timer Interface (TIM)
and Section 15. Input/Output (I/O) Ports.). PTF4 is only available in
the 64-pin QFP package.
1.5.14 Port G I/O Pins (PTG2–PTG0)
PTG2-PTG0 are general-purpose bidirectional I/O pins. Port G is only
available in the 64-pin QFP package. (See Section 15. Input/Output
(I/O) Ports.)
1.5.15 J1850 Transmit Pin Digital (BDTxD)
BDTxD is a serial digital output data physical interface to the J1850.
(See Section 20. Byte Data Link Controller–Digital (BDLC–D)).
1.5.16 J1850 Receive Pin Digital (BDRxD)
BDRxD is a serial digital input data physical interface from the J1850.
(See Section 20. Byte Data Link Controller–Digital (BDLC–D)).
Advance Information
36
MC68HC708AS48 — Rev. 4.0
General Description
MOTOROLA
R E Q U I R E D
General Description
Pin Assignments
Function
Driver Type
Hysteresis
Reset State
PTA7–PTA0
General-Purpose I/O
Dual State
No
Input, Hi-Z
PTB7/ATD7–
PTB0/ATD0
General-Purpose I/O
ADC Channel
Dual State
No
Input, Hi-Z
PTC5–PTC3
General-Purpose I/O
Dual State
No
Input, Hi-Z
PTC2/MCLK
General-Purpose I/O
Bus Clock Output
Dual State
No
Input, Hi-Z
PTC1–PTC0
General-Purpose I/O
Dual State
No
Input, Hi-Z
PTD7/ATD15
General-Purpose I/O
Dual State
No
Input, Hi-Z
PTD6/ATD14/TCLK
General-Purpose I/O
ADC Channel/Timer
External Input Clock
Dual State
No
Input, Hi-Z
PTD5/ATD13–
PTD3/ATD11
General-Purpose I/O
ADC Channel
Dual State
No
Input, Hi-Z
PTD2/ATD10
General-Purpose Input
ADC Channel
N/A
No
Input, Hi-Z
PTD1/ATD9PTD0/ATD8
General-Purpose I/O
ADC Channel
Dual State
No
Input, Hi-Z
PTE7/SPSCK
General-Purpose I/O
SPI Clock
Dual State
Open Drain
Yes
Input, Hi-Z
PTE6/MOSI
General-Purpose I/O
SPI Data Path
Dual State
Open Drain
Yes
Input, Hi-Z
PTE5/MISO
General-Purpose I/O
SPI Data Path
Dual State
Open Drain
Yes
Input, Hi-Z
PTE4/SS
General-Purpose I/O
SPI Slave Select
Dual State
Yes
Input, Hi-Z
PTE3/TCH1
General-Purpose I/O
Timer Channel 1
Dual State
Yes
Input, Hi-Z
PTE2/TCH0
General-Purpose I/O
Timer Channel 0
Dual State
Yes
Input, Hi-Z
PTE1/RxD
General-Purpose I/O
SCI Receive Data
Dual State
Yes
Input, Hi-Z
PTE0/TxD
General-Purpose I/O
SCI Transmit Data
Dual State
Yes
Input, Hi-Z
PTF4
General-Purpose I/O
Dual State
No
Input, Hi-Z
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
N O N - D I S C L O S U R E
Pin Name
A G R E E M E N T
Table 1-1. External Pins Summary
Advance Information
General Description
37
R E Q U I R E D
General Description
N O N - D I S C L O S U R E
A G R E E M E N T
Table 1-1. External Pins Summary (Continued)
Pin Name
Function
Driver Type
Hysteresis
Reset State
PTF3/TCH5
General-Purpose I/O
Timer Channel 5
Dual State
Yes
Input, Hi-Z
PTF2/TCH4
General-Purpose I/O
Timer Channel 4
Dual State
Yes
Input, Hi-Z
PTF1/TCH3
General-Purpose I/O
Timer Channel 3
Dual State
Yes
Input, Hi-Z
PTF0/TCH2
General-Purpose I/O
Timer Channel 2
Dual State
Yes
Input, Hi-Z
PTG2-PTG0
General-Purpose I/O
Dual State
Yes
Input, Hi-Z
VDD
Chip Power Supply
N/A
N/A
N/A
VSS
Chip Ground
N/A
N/A
N/A
VDDA/VDDAREF
Analog Power Supply
(CGM and ADC)
N/A
N/A
N/A
VSSA/VREFL
Analog Ground
A/D Reference Voltage
N/A
N/A
N/A
VREFH
A/D Reference Voltage
N/A
N/A
N/A
OSC1
External Clock In
N/A
N/A
Input, Hi-Z
OSC2
External Clock Out
N/A
N/A
Output
CGMXFC
PLL Loop Filter Cap
N/A
N/A
N/A
IRQ/VPP
External Interrupt Request
EPROM Programming
Voltage
N/A
N/A
Input, Hi-Z
RST
Reset
N/A
N/A
Output Low
BDRxD
BDLC-Digital Serial Input
N/A
No
Input, Hi-Z
BDTxD
BDLC-Digital Serial Output
Output
No
Output Low
Advance Information
38
MC68HC708AS48 — Rev. 4.0
General Description
MOTOROLA
R E Q U I R E D
General Description
Pin Assignments
Clock Source
ADC
CGMXCLK or Bus Clock
BDLC
CGMXCLK
COP
CGMXCLK
CPU
Bus Clock
EEPROM
Internal RC Oscillator or Bus Clock
SPI
Bus Clock/SPSCK
SCI
CGMXCLK
TIM
Bus Clock or PTD6/ATD14/TCLK
SIM
CGMOUT and CGMXCLK
IRQ
Bus Clock
BRK
Bus Clock
LVI
Bus Clock
CGM
OSC1 and OSC2
N O N - D I S C L O S U R E
Module
A G R E E M E N T
Table 1-2. Clock Source Summary
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
Advance Information
General Description
39
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
General Description
Advance Information
40
MC68HC708AS48 — Rev. 4.0
General Description
MOTOROLA
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
2.3
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
2.2 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in Figure 2-1, includes:
•
49,152 bytes of user EPROM or OTPROM
•
1,536 bytes of RAM
•
640 bytes of EEPROM
•
36 bytes of user-defined vectors
•
224 bytes of monitor ROM
These definitions apply to the memory map representation of reserved
and unimplemented locations.
•
Reserved — Accessing a reserved location can have
unpredictable effects on MCU operation.
•
Unimplemented — Accessing an unimplemented location
causes an illegal address reset if illegal address resets are
enabled.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Memory Map
41
R E Q U I R E D
2.1 Contents
A G R E E M E N T
Section 2. Memory Map
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
R E Q U I R E D
Memory Map
$0000
↓
I/O REGISTERS — 62 BYTES
($000B & $000F ARE RESERVED)
$003F
$0040
↓
UNIMPLEMENTED — 16 BYTES
$004F
$0050
A G R E E M E N T
↓
RAM — 1,536 BYTES
$064F
$0650
↓
UNIMPLEMENTED — 432 BYTES
$07FF
$0800
↓
EEPROM — 640 BYTES
$0A7F
$0A80
N O N - D I S C L O S U R E
↓
UNIMPLEMENTED — 13,184 BYTES
$3DFF
$3E00
↓
EPROM — 49,152 BYTES
($AE00-$FDFF FOR 20,480 BYTES)
$FDFF
$FE00
SIM BREAK STATUS REGISTER (SBSR)
$FE01
SIM RESET STATUS REGISTER (SRSR)
$FE02
RESERVED
$FE03
SIM BREAK FLAG CONTROL REGISTER (SBFCR)
$FE04
RESERVED
$FE05
RESERVED
$FE06
RESERVED
$FE07
EPROM CONTROL REGISTER (EPMCR)
Figure 2-1. Memory Map
Advance Information
42
MC68HC708AS48 — Rev. 4.0
Memory Map
MOTOROLA
RESERVED
$FE09
RESERVED
$FE0A
RESERVED
$FE0B
RESERVED
$FE0C
BREAK ADDRESS REGISTER HIGH (BRKH)
$FE0D
BREAK ADDRESS REGISTER LOW (BRKL)
$FE0E
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0F
LVI STATUS REGISTER (LVISR)
A G R E E M E N T
$FE08
R E Q U I R E D
Memory Map
Introduction
$FE10
↓
RESERVED — 12 BYTES
$FE1B
$FE1C
EEPROM NON-VOLATILE REGISTER (EENVR)
$FE1D
EEPROM CONTROL REGISTER (EECR)
$FE1E
RESERVED
$FE1F
EEPROM ARRAY CONFIGURATION REGISTER (EEACR)
$FE20
↓
MONITOR ROM — 224 BYTES
N O N - D I S C L O S U R E
$FEFF
$FF00
↓
UNIMPLEMENTED — 192 BYTES
$FFBF
$FFC0
↓
RESERVED — 28 BYTES
$FFDB
$FFDC
↓
INTERRUPT AND RESET VECTORS — 36 BYTES
$FFFF
Figure 2-1. Memory Map (Continued)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Memory Map
43
2.3 Input/Output (I/O) Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the
control, status, and data registers. Additional I/O registers have these
addresses:
A G R E E M E N T
R E Q U I R E D
Memory Map
•
$FE00, SIM break status register, SBSR
•
$FE01, SIM reset status register, SRSR
•
$FE03, SIM break flag control register, SBFCR
•
$FE07, EPROM control register, EPMCR
•
$FE0C and $FE0D, break address registers, BRKH and BRKL
•
$FE0E, break status and control register, BRKSCR
•
$FE0F, LVI status register, LVISR
•
$FE1C, EEPROM non-volatile register, EENVR
•
$FE1D, EEPROM control register, EECR
•
$FE1F, EEPROM array configuration register, EEACR
•
$FFFF, COP control register, COPCTL
N O N - D I S C L O S U R E
Following the registers in Figure 2-2, Table 2-1 is a list of vector
locations.
Advance Information
44
MC68HC708AS48 — Rev. 4.0
Memory Map
MOTOROLA
Read:
Port A Data Register
(PTA) Write:
See page 188.
Reset:
$0000
Read:
Port B Data Register
(PTB) Write:
See page 191.
Reset:
$0001
Read:
Port C Data Register
(PTC) Write:
See page 194.
Reset:
$0002
Read:
Port D Data Register
(PTD) Write:
See page 197.
Reset:
$0003
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD1
PTD0
Unaffected by Reset
PTB7
0
0
R
R
PTD7
PTB4
PTB3
PTC5
PTC4
PTC3
PTD6
PTD5
PTD4
PTD3
PTD2
R
Unaffected by Reset
Read:
Data Direction Register D
DDRD7
(DDRD) Write:
See page 199.
Reset:
0
$0008
PTB5
Unaffected by Reset
Read:
Data Direction Register C
MCLKEN
(DDRC) Write:
See page 195.
Reset:
0
Read:
Port E Data Register
(PTE) Write:
See page 201.
Reset:
PTB6
Unaffected by Reset
Read:
Data Direction Register B
DDRB7
(DDRB) Write:
See page 192.
Reset:
0
$0005
$0007
6
Read:
Data Direction Register A
DDRA7
(DDRA) Write:
See page 189.
Reset:
0
$0004
$0006
Bit 7
PTE7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD1
DDRD0
0
0
0
0
0
0
0
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
0
R
0
R
Unaffected by Reset
R
= Reserved
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Memory Map
45
A G R E E M E N T
Register Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Memory Map
Input/Output (I/O) Section
R E Q U I R E D
Memory Map
Addr.
$0009
$000A
Register Name
Read:
Port F Data Register
(PTF) Write:
See page 205.
Reset:
Read:
Port G Data Register
(PTG) Write:
See page 208.
Reset:
Bit 7
6
5
0
0
0
R
R
R
4
3
2
1
Bit 0
PTF4
PTF3
PTF2
PTF1
PTF0
PTG2
PTG1
PTG0
Unaffected by Reset
0
0
0
0
0
R
R
R
R
R
Unaffected by Reset
A G R E E M E N T
$000B
$000C
$000D
$000E
Reserved
Read:
Data Direction Register E
DDRE7
(DDRE) Write:
See page 203.
Reset:
0
Read:
Data Direction Register F
(DDRF) Write:
See page 206.
Reset:
Read:
Data Direction Register G
(DDRG) Write:
See page 209.
Reset:
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
0
0
R
R
R
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
DDRG2
DDRG1
DDRG0
0
0
0
0
0
0
0
0
N O N - D I S C L O S U R E
$000F
$0010
$0011
$0012
Reserved
SPI Control Register Read:
(SPCR)
Write:
See page 310.
Reset:
Read:
SPI Status and Control
Register (SPSCR) Write:
See page 313.
Reset:
Read:
SPI Data Register
(SPDR) Write:
See page 316.
Reset:
SPRIE
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
0
0
1
0
1
0
0
0
OVRF
MODF
SPTE
R
R
R
MODFEN
SPR1
SPR0
SPRF
R
ERRIE
0
0
0
0
1
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Indeterminate after Reset
R
= Reserved
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)
Advance Information
46
MC68HC708AS48 — Rev. 4.0
Memory Map
MOTOROLA
$0014
$0015
$0016
$0017
$0018
$0019
$001A
Bit 7
6
5
4
3
2
1
Bit 0
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
T8
R
R
ORIE
NEIE
FEIE
PEIE
Read:
SCI Control Register 1
LOOPS
(SCC1) Write:
See page 266.
Reset:
0
Read:
SCI Control Register 2
(SCC2) Write:
See page 269.
Reset:
Read:
SCI Control Register 3
(SCC3) Write:
See page 272.
Reset:
R8
U
U
0
0
0
0
0
0
Read:
SCI Status Register 1
(SCS1) Write:
See page 274.
Reset:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
R
R
R
R
R
R
R
R
1
1
0
0
0
0
0
0
Read:
SCI Status Register 2
(SCS2) Write:
See page 278.
Reset:
0
0
0
0
0
0
BKF
RPF
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
SCI Data Register
(SCDR) Write:
See page 279.
Reset:
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Read:
SCI Baud Rate Register
(SCBR) Write:
See page 280.
Reset:
0
0
R
R
0
Read:
IRQ Status and Control
Register (ISCR) Write:
See page 183.
Reset:
R
Unaffected by Reset
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
0
0
0
0
0
IRQF
0
R
R
R
R
R
ACK
IMASK
MODE
0
0
0
0
0
0
0
0
1
1
1
1
R
R
R
R
1
1
1
1
$001B
$001C
A G R E E M E N T
$0013
Register Name
Reserved
Read:
PLL Control Register
(PCTL) Write:
See page 112.
Reset:
PLLIE
0
R
PLLF
R
PLLON
BCS
1
0
0
= Reserved
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Memory Map
47
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Memory Map
Input/Output (I/O) Section
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Memory Map
Addr.
$001D
$001E
$001F
$0020
Register Name
Read:
PLL Bandwidth Control
Register (PBWC) Write:
See page 114.
Reset:
Read:
PLL Programming Register
(PPG) Write:
See page 116.
Reset:
Read:
Configuration Register
(CONFIG) Write:
See page 64.
Reset:
Read:
TIM Status and Control
Register (TSC) Write:
See page 229.
Reset:
Bit 7
AUTO
6
LOCK
R
5
4
ACQ
XLD
$0023
$0024
$0025
$0026
2
1
Bit 0
0
0
0
0
R
R
R
R
0
0
0
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
0
1
1
0
0
1
1
0
R
R
COPL
STOP
COPD
R
R
R
PS2
PS1
PS0
LVIRSTD LVIPWRD SSREC
R
R
R
Unaffected by Reset
TOF
0
0
TOIE
TSTOP
0
1
0
0
TRST
R
0
0
0
0
0
$0021
$0022
3
Reserved
Read:
TIM Counter Register High
(TCNTH) Write:
See page 231.
Reset:
Bit 15
14
13
12
11
10
9
Bit 8
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
TIM Counter Register Low
(TCNTL) Write:
See page 231.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
Read:
TIM Modulo Register High
(TMODH) Write:
See page 232.
Reset:
Read:
TIM Modulo Register Low
(TMODL) Write:
See page 232.
Reset:
Read:
TIM Channel 0 Status and
Control Register (TSC0) Write:
See page 233.
Reset:
CH0F
0
0
R
= Reserved
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
Advance Information
48
MC68HC708AS48 — Rev. 4.0
Memory Map
MOTOROLA
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
Read:
TIM Channel 0 Register High
(TCH0H) Write:
See page 239.
Reset:
Read:
TIM Channel 0 Register Low
(TCH0L) Write:
See page 239.
Reset:
Read:
TIM Channel 1 Status and
Control Register (TSC1) Write:
See page 233.
Reset:
Read:
TIM Channel 1 Register High
(TCH1H) Write:
See page 239.
Reset:
Read:
TIM Channel 1 Register Low
(TCH1L) Write:
See page 239.
Reset:
Read:
TIM Channel 2 Status and
Control Register (TSC2) Write:
See page 233.
Reset:
Read:
TIM Channel 2 Register High
(TCH2H) Write:
See page 239.
Reset:
Read:
TIM Channel 2 Register Low
(TCH2L) Write:
See page 239.
Reset:
Read:
TIM Channel 3 Status and
Control Register (TSC3) Write:
See page 233.
Reset:
TIM Channel 3 Register High Read:
(TCH3H)
Write:
See page 239.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH1F
0
CH1IE
0
R
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH2F
CH2IE
MS2B
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH3F
0
CH3IE
0
R
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Indeterminate after Reset
R
= Reserved
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Memory Map
49
A G R E E M E N T
$0027
Register Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Memory Map
Input/Output (I/O) Section
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Memory Map
Addr.
Register Name
$0031
Read:
TIM Channel 3 Register Low
(TCH3L) Write:
See page 239.
Reset:
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
Read:
TIM Channel 4 Status and
Control Register (TSC4) Write:
See page 233.
Reset:
Read:
TIM Channel 4 Register High
(TCH4H) Write:
See page 239.
Reset:
Read:
TIM Channel 4 Register Low
(TCH4L) Write:
See page 239.
Reset:
Read:
TIM Channel 5 Status and
Control Register (TSC5) Write:
See page 233.
Reset:
Read:
TIM Channel 5 Register High
(TCH5H) Write:
See page 239.
Reset:
Read:
TIM Channel 5 Register Low
(TCH5L) Write:
See page 239.
Reset:
Read:
ADC Status and Control
Register (ADSCR) Write:
See page 324.
Reset:
Read:
ADC Data Register
(ADR) Write:
See page 327.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Indeterminate after Reset
CH4F
CH4IE
MS4B
MS4A
ELS4B
ELS4A
TOV4
CH4MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH5F
0
CH5IE
0
R
MS5A
ELS5B
ELS5A
TOV5
CH5MAX
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
COCO
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
0
0
1
1
1
1
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R
R
R
R
R
R
R
R
Indeterminate after Reset
R
= Reserved
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)
Advance Information
50
MC68HC708AS48 — Rev. 4.0
Memory Map
MOTOROLA
$003A
Read:
ADC Input Clock Register
(ADICLK) Write:
See page 327.
Reset:
$003B
Read:
BDLC Analog and Roundtrip
Delay Register (BARD) Write:
See page 358.
Reset:
Read:
BDLC Control Register 1
(BCR1) Write:
See page 360.
Reset:
$003C
Read:
BDLC State Vector Register
(BSVR) Write:
See page 371.
Reset:
Read:
BDLC Data Register
(BDR) Write:
See page 373.
Reset:
$003F
$FE00
$FE01
6
5
4
3
2
1
Bit 0
ADIV2
ADIV1
ADIV0
ADICLK
0
0
0
0
R
R
R
R
0
0
0
0
0
0
0
0
ATE
RXPOL
0
0
R
R
BO3
BO2
BO1
BO0
1
1
0
0
0
1
1
1
IMSG
CLKS
R1
R0
0
0
R
R
IE
WCM
1
1
1
0
0
0
0
0
DLOOP
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
1
0
0
0
0
0
0
0
0
I3
I2
I1
I0
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
R
SBSW
R
Read:
BDLC Control Register 2
ALOOP
(BCR2) Write:
See page 363.
Reset:
1
$003D
$003E
Bit 7
Read:
SIM Break Status Register
(SBSR) Write:
See page 144.
Reset:
Read:
SIM Reset Status Register
(SRSR) Write:
See page 146.
Reset:
$FE03
$FE07
Read:
SIM Break Flag Control
Register (SBFCR) Write:
See page 147.
Reset:
Read:
EPROM Control Register
(EPMCR) Write:
See page 59.
Reset:
Indeterminate after Reset
R
R
R
R
R
0
POR
PIN
COP
ILOP
ILAD
0
LVI
0
R
R
R
R
R
R
R
R
1
X
0
0
0
0
X
0
BCFE
R
R
R
R
R
R
R
0
0
0
0
0
R
R
R
R
R
0
0
0
0
0
0
R
= Reserved
U = Unaffected
ELAT
0
0
R
0
EPGM
0
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
A G R E E M E N T
Register Name
Advance Information
Memory Map
51
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Memory Map
Input/Output (I/O) Section
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Memory Map
Addr.
$FE0C
$FE0D
$FE0E
$FE0F
Register Name
Read:
Break Address Register High
(BRKH) Write:
See page 160.
Reset:
Read:
Break Address Register Low
(BRKL) Write:
See page 160.
Reset:
Read:
Break Status and Control
Register (BRKSCR) Write:
See page 159.
Reset:
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
0
0
0
0
0
0
0
R
R
R
R
EEBP2
EEBP1
EEBP0
Read: LVIOUT
LVI Status Register
(LVISR) Write:
R
See page 152.
Reset:
0
Read:
EEPROM Non-Volatile Register
$FE1C
(EENVR) Write:
See page 76.
Reset:
$FE1D
Bit 7
EERA
Bits 7, 3, 2, 1, and 0 programmed value or 1 in the erased state.
Read:
EEPROM Control Register
EEBCLK
(EECR) Write:
See page 74.
Reset:
0
0
R
EEOFF
0
0
$FE1E
$FE1F
$FFFF
LVISTOP LVILCK
EERAS1 EERAS0
0
EELAT
0
EEPGM
R
0
0
0
0
Reserved
Read:
EEPROM Array Control
Register (EEACR) Write:
See page 76.
Reset:
EERA
R
R
R
R
EEBP2
EEBP1
EEBP0
R
R
R
R
R
R
R
R
Bits 7, 3, 2, 1, and 0 load their contents from the EENVR register at reset.
Read:
COP Control Register
(COPCTL) Write:
See page 175.
Reset:
Low Byte of Reset Vector
Clear COP Counter
Unaffected by Reset
R
= Reserved
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8)
Advance Information
52
MC68HC708AS48 — Rev. 4.0
Memory Map
MOTOROLA
R E Q U I R E D
Memory Map
Input/Output (I/O) Section
Table 2-1. Vector Addresses
$FFDC
BDLC Vector (High)
$FFDD
BDLC Vector (Low)
$FFDE
ADC Vector (High)
$FFDF
ADC Vector (Low)
$FFE0
SCI Transmit Vector (High)
$FFE1
SCI Transmit Vector (Low)
$FFE2
SCI Receive Vector (High)
$FFE3
SCI Receive Vector (Low)
$FFE4
SCI Error Vector (High)
$FFE5
SCI Error Vector (Low)
$FFE6
SPI Transmit Vector (High)
$FFE7
SPI Transmit Vector (Low)
$FFE8
SPI Receive Vector (High)
$FFE9
SPI Receive Vector (Low)
$FFEA
TIM Overflow Vector (High)
$FFEB
TIM Overflow Vector (Low)
$FFEC
TIM Channel 5 Vector (High)
$FFED
TIM Channel 5 Vector (Low)
$FFEE
TIM Channel 4 Vector (High)
$FFEF
TIM Channel 4 Vector (Low)
$FFF0
TIM Channel 3 Vector (High)
$FFF1
TIM Channel 3 Vector (Low)
$FFF2
TIM Channel 2 Vector (High)
$FFF3
TIM Channel 2 Vector (Low)
$FFF4
TIM Channel 1 Vector (High)
$FFF5
TIM Channel 1 Vector (Low)
$FFF6
TIM Channel 0 Vector (High)
$FFF7
TIM Channel 0 Vector (Low)
$FFF8
PLL Vector (High)
$FFF9
PLL Vector (Low)
$FFFA
IRQ Vector (High)
$FFFB
IRQ Vector (Low)
$FFFC
SWI Vector (High)
$FFFD
SWI Vector (Low)
$FFFE
Reset Vector (High)
$FFFF
Reset Vector (Low)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
A G R E E M E N T
Vector
N O N - D I S C L O S U R E
High
Priority
Low
Address
Advance Information
Memory Map
53
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Memory Map
Advance Information
54
MC68HC708AS48 — Rev. 4.0
Memory Map
MOTOROLA
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.2 Introduction
This section describes the 1,536 bytes of random-access memory
(RAM).
3.3 Functional Description
Addresses $0050–$064F are RAM locations. The location of the stack
RAM is programmable. The 16-bit stack pointer allows the stack to be
anywhere in the 1,536-byte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 176 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for input/output (I/O) control and user data or code. When the stack
pointer is moved from its reset location at $00FF, direct addressing
mode instructions can access all page zero RAM locations efficiently.
Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Random-Access Memory (RAM)
55
R E Q U I R E D
3.1 Contents
A G R E E M E N T
Section 3. Random-Access Memory (RAM)
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
R E Q U I R E D
Random-Access Memory (RAM)
NOTE:
For M68HC05, M6805, and M146805 compatibility, the H register is not
stacked.
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
Be careful when using nested subroutines. The CPU could overwrite
data in the RAM during a subroutine or during the interrupt stacking
operation.
N O N - D I S C L O S U R E
A G R E E M E N T
NOTE:
Advance Information
56
MC68HC708AS48 — Rev. 4.0
Random-Access Memory (RAM)
MOTOROLA
4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
4.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.4
EPROM/OTPROM Control Register. . . . . . . . . . . . . . . . . . . . .59
4.5
EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . . .60
4.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
N O N - D I S C L O S U R E
4.2 Introduction
This section describes the 49,152 bytes of user non-volatile memory
(EPROM/OTPROM) and 36 bytes of user vectors.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Erasable Programmable Read-Only Memory (EPROM/OTPROM)
R E Q U I R E D
Section 4. Erasable Programmable Read-Only Memory
(EPROM/OTPROM)
A G R E E M E N T
Advance Information — MC68HC708AS48
Advance Information
57
4.3 Functional Description
The user EPROM/OTPROM consists of 49,152 bytes of user
EPROM/OTPROM from addresses $3E00-$FDFF and 36 bytes of user
interrupt and reset vector EPROM/OTPROM from addresses
$FFFC–$FFFF. See Figure 2-1. Memory Map.
NOTE:
A G R E E M E N T
R E Q U I R E D
Erasable Programmable Read-Only Memory
Security has been incorporated into the MC68HC708AS48 to prevent
external viewing of the EPROM/OTPROM contents. This feature
ensures that customer-developed software remains proprietary.1
N O N - D I S C L O S U R E
The MC68HC708AS48 with a quartz window (engineering samples
only) has 49,152 user bytes and 36 vector bytes of erasable,
programmable ROM (EPROM). The quartz window allows EPROM
erasure by exposure to ultraviolet light. In the MC68HC708AS48CFN,
without the quartz window, the EPROM cannot be erased and serves as
49,152 user bytes and 36 vector bytes of one-time programmable ROM
(OTPROM). An unprogrammed or erased location reads as $00. The
following addresses are user EPROM/OTPROM locations:
•
$3E00–$FDFF
•
$FFDC–$FFFF (These locations are reserved for user-defined
interrupt and reset vectors.)
Programming tools are available from Motorola. Contact your local
Motorola representative for more information.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
Advance Information
58
MC68HC708AS48 — Rev. 4.0
Erasable Programmable Read-Only Memory (EPROM/OTPROM)
MOTOROLA
R E Q U I R E D
Erasable Programmable Read-Only Memory (EPROM/OTPROM)
EPROM/OTPROM Control Register
4.4 EPROM/OTPROM Control Register
The EPROM control register controls EPROM/OTPROM
programming.
Bit 7
6
5
4
3
0
0
0
0
0
2
1
0
ELAT
Write:
R
R
R
R
R
Reset:
0
0
0
0
0
R
Bit 0
EPGM
R
0
0
0
= Reserved
Figure 4-1. EPROM/OTPROM Control Register (EPMCR)
ELAT — EPROM/OTPROM Latch Control Bit
This read/write bit latches the address and data buses for
programming the EPROM/OTPROM. Clearing ELAT also clears the
EPGM bit. EPROM/OTPROM data cannot be read when ELAT is set.
1 = Buses configured for EPROM/OTPROM programming
0 = Buses configured for normal operation
EPGM — EPROM/OTPROM Program Control Bit
This read/write bit applies the programming voltage from the IRQ/VPP
pin to the EPROM/OTPROM. To write to the EPGM bit, the ELAT bit
must be set already. Reset clears the EPGM bit.
1 = EPROM/OTPROM programming power switched on
0 = EPROM/OTPROM programming power switched off
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Erasable Programmable Read-Only Memory (EPROM/OTPROM)
Advance Information
59
A G R E E M E N T
Read:
$FE07
N O N - D I S C L O S U R E
Address:
4.5 EPROM/OTPROM Programming
The unprogrammed state is a 0. Programming changes the state to a 1.
Use the following procedure to program a byte of EPROM/OTPROM:
1. Apply VPP to the IRQ/VPP pin. See Section 14. External Interrupt
for application information on how to use this pin.
2. Set the ELAT bit.
NOTE:
A G R E E M E N T
R E Q U I R E D
Erasable Programmable Read-Only Memory
Writing logic 1s to both the ELAT and EPGM bits with a single instruction
sets only the ELAT bit. EPGM must be set by a separate instruction in
the programming sequence.
3. Write to any user EPROM/OTPROM address.
NOTE:
Writing to an invalid address prevents the programming voltage from
being applied.
4. Set the EPGM bit.
5. Wait for a time, tEPGM.
6. Clear the ELAT and EPGM bits.
N O N - D I S C L O S U R E
Setting the ELAT bit configures the address and data buses to latch data
for programming the array. Only data written to a valid EPROM address
will be latched. Attempts to read any other valid EPROM address after
step 2 will read the latched data written in step 3. Further writes to valid
EPROM addresses after the first write (step 3) are ignored.
The EPGM bit cannot be set if the ELAT bit is cleared. This is to ensure
a proper programming sequence. If EPGM is set and a valid EPROM
write occurs, VPP will be applied to the user EPROM array. When the
EPGM bit is cleared, the program voltage is removed from the array.
Advance Information
60
MC68HC708AS48 — Rev. 4.0
Erasable Programmable Read-Only Memory (EPROM/OTPROM)
MOTOROLA
4.6 Low-Power Modes
The WAIT and STOP instructions can put the MCU in low-power standby
modes.
4.6.1 Wait Mode
A G R E E M E N T
The WAIT instruction does not affect the EPROM.
R E Q U I R E D
Erasable Programmable Read-Only Memory (EPROM/OTPROM)
Low-Power Modes
4.6.2 Stop Mode
N O N - D I S C L O S U R E
The STOP instruction reduces the EPROM power consumption to a
minimum. If STOP occurs while EPROM programming is in progress,
high voltage will be removed from the array and the EPGM bit will be
cleared. To resume programming, clear the ELAT bit and follow the
steps shown in 4.5 EPROM/OTPROM Programming.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Erasable Programmable Read-Only Memory (EPROM/OTPROM)
Advance Information
61
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Erasable Programmable Read-Only Memory
Advance Information
62
MC68HC708AS48 — Rev. 4.0
Erasable Programmable Read-Only Memory (EPROM/OTPROM)
MOTOROLA
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.4
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.2 Introduction
This section describes the configuration register (CONFIG) in the
MC68HC708AS48.
5.3 Functional Description
The configuration register options are connections which allow the user
to customize the MCU. The options control the enable or disable of the
following functions:
•
Resets caused by the LVI module
•
Power to the LVI module
•
Stop mode recovery time (32 CGMXCLK cycles or 4096
CGMXCLK cycles)
•
COP timeout period (8,176 CGMXCLK cycles or 262,128
CGMXCLK cycles)
•
STOP instruction
•
Computer operating properly module (COP)
The configuration register ($001F) is used in the initialization of various
options. The configuration register can only be written once after each
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Configuration Register (CONFIG)
63
R E Q U I R E D
5.1 Contents
A G R E E M E N T
Section 5. Configuration Register (CONFIG)
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
A G R E E M E N T
R E Q U I R E D
Configuration Register (CONFIG)
reset. All of the configuration bits are cleared with reset. Since the
various options affect the operation of the MCU it is recommended that
this register be written immediately after reset. For compatibility, a write
to the ROM version of this MCU at this location will have no effect. The
configuration register may be read at any time.
NOTE:
The configuration register will allow only one write between resets.
5.4 Configuration Register
Address:
$001F
Bit 7
6
R
R
Read:
5
4
LVIRSTD LVIPWRD
Write:
R
Reset:
R
3
2
1
Bit 0
SSREC
COPL
STOP
COPD
R
R
R
R
Unaffected by Reset
R
= Reserved
Figure 5-1. Configuration Register (CONFIG)
LVIPWRD— LVI Power Disable Bit
N O N - D I S C L O S U R E
LVIPWRD disables the LVI module. (See Section 10. Low-Voltage
Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. (See
Section 10. Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. (See
16.6.2 Stop Mode.)
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
Advance Information
64
MC68HC708AS48 — Rev. 4.0
Configuration Register (CONFIG)
MOTOROLA
NOTE:
R E Q U I R E D
Configuration Register (CONFIG)
Configuration Register
If using an external crystal oscillator, do not set the SSREC bit.
COPL— COP Long Timeout Bit
COPL selects the long COP timeout period. (See Section 13.
Computer Operating Properly (COP).)
1 = COP timeout period is 262,128 CGMXCLK cycles
0 = COP timeout period is 8,176 CGMXCLK cycles
STOP — STOP Instruction Enable Bit
A G R E E M E N T
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
N O N - D I S C L O S U R E
COPD disables the COP module. (See Section 13. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Configuration Register (CONFIG)
65
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Configuration Register (CONFIG)
Advance Information
66
MC68HC708AS48 — Rev. 4.0
Configuration Register (CONFIG)
MOTOROLA
Section 6. Electrically Erasable Programmable ROM
(EEPROM)
R E Q U I R E D
Advance Information — MC68HC708AS48
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
6.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
6.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
6.4.1
EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . .68
6.4.2
EEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.4.3
EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . . . . . .72
6.4.4
EEPROM Redundant Mode . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.5
EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.6
EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . .74
6.4.7
EEPROM Non-Volatile Register and EEPROM
Array Configuration Register . . . . . . . . . . . . . . . . . . . . .76
6.4.8
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.4.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.4.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
MC68HC708AS48 — Rev. 4.0
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Electrically Erasable Programmable ROM (EEPROM)
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N O N - D I S C L O S U R E
6.2
A G R E E M E N T
6.1 Contents
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Electrically Erasable Programmable ROM
6.2 Introduction
This section describes the 640 bytes of electrically erasable
programmable ROM (EEPROM).
6.3 Features
•
Byte, block, or bulk erasable
•
Non-volatile redundant array option
•
Non-volatile block protection option
•
Non-volatile MCU configuration bits
•
On-chip charge pump for programming/erasing
6.4 Functional Description
Addresses $0800–$0A7F are EEPROM locations. 640 bytes of
EEPROM can be programmed or erased without an external voltage
supply. The EEPROM has a lifetime of 10,000 write-erase cycles in the
non-redundant mode. Reliability (data retention) is further extended if
the redundancy option is selected. EEPROM cells are protected with a
non-volatile, 128-byte, block protection option. These options are stored
in the EEPROM non-volatile register (EENVR) and are loaded into the
EEPROM array configuration register (EEACR) after reset or a read of
EENVR. The EEPROM array can also be disabled to reduce current.
6.4.1 EEPROM Programming
The unprogrammed state is a logic 1. Programming changes the state
to a logic 0. Only valid EEPROM bytes in the non-protected blocks and
EENVR can be programmed. When the array is configured in the
redundant mode, programming the first 128 bytes ($0800–$087F) will
also program the last 128 bytes ($0A00–$0A7F) with the same data.
Programming the EEPROM in the non-redundant mode is
recommended. Program the data to both locations before entering the
redundant mode.
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Electrically Erasable Programmable ROM (EEPROM)
MOTOROLA
R E Q U I R E D
Electrically Erasable Programmable ROM (EEPROM)
Functional Description
Follow this procedure to program a byte of EEPROM. Refer to 21.6
Control Timing for timing values.
1. Clear EERAS1 and EERAS0 and set EELAT in the EECR
($FE1D). Set value of tEEPGM. (See Notes a and b.)
2. Write the desired data to any user EEPROM address.
3. Set the EEPGM bit. (See Note c.)
4. Wait for a time, tEEPGM, to program the byte.
7. Clear EELAT bits. (See Note d.)
8. Repeat steps 1 through 7 for more EEPROM programming.
NOTES:
a. EERAS1 and EERAS0 must be cleared for programming.
Otherwise, you will be in erase mode.
b. Setting the EELAT bit configures the address and data buses
to latch data for programming the array. Only data with a valid
EEPROM address will be latched. If another consecutive valid
EEPROM write occurs, this address and data will override the
previous address and data. Any attempts to read other
EEPROM data will read the latched data. If EELAT is set,
other writes to the EECR will be allowed after a valid
EEPROM write.
c.
The EEPGM bit cannot be set if the EELAT bit is cleared and
a non-EEPROM write has occurred. This is to ensure proper
programming sequence. When EEPGM is set, the on-board
charge pump generates the program voltage and applies it to
the user EEPROM array. When the EEPGM bit is cleared, the
program voltage is removed from the array and the internal
charge pump is turned off.
d. Any attempt to clear both EEPGM and EELAT bits with a
single instruction will clear only EEPGM to allow time for
removal of high voltage from the EEPROM array.
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Electrically Erasable Programmable ROM (EEPROM)
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N O N - D I S C L O S U R E
6. Wait for the programming voltage time to fall, tEEFPV.
A G R E E M E N T
5. Clear the EEPGM bit.
6.4.2 EEPROM Erasing
The unprogrammed state is a logic 1. Only the valid EEPROM bytes in
the non-protected blocks and EENVR can be erased. When the array is
configured in the redundant mode, erasing the first 128 bytes
($0800–$087F) will also erase the last 128 bytes ($0A00–$0A7F).
Follow this procedure to erase EEPROM. Refer to 21.6 Control Timing
for timing values.
1. Clear/set EERAS1 and EERAS0 to select byte/block/bulk erase,
and set EELAT in EECTL. Set value of tEEBYT/tEEBLOCK/tEEBULK.
(See Note a.)
A G R E E M E N T
R E Q U I R E D
Electrically Erasable Programmable ROM
2. Write any data to the desired address for byte erase, to any
address in the desired block for block erase, or to any array
address for bulk erase.
3. Set the EEPGM bit. (See Note b.)
4. Wait for a time, tEEPGM, to program the byte.
5. Clear EEPGM bit.
6. Wait for the erasing voltage time to fall, tEEFPV).
7. Clear EELAT bits. (See Note c.)
N O N - D I S C L O S U R E
8. Repeat steps 1 through 7 for more EEPROM byte/block erasing.
EEBPx bit must be cleared to erase EEPROM data in the corresponding
block. If any EEBPx is set, the corresponding block cannot be erased
and bulk erase mode does not apply.
NOTES:
a. Setting the EELAT bit configures the address and data buses
to latch data for erasing the array. Only valid EEPROM
addresses with their data will be latched. If another
consecutive valid EEPROM write occurs, this address and
data will override the previous address and data. In block
erase mode, any EEPROM address in the block can be used
in step 2. All locations within this block will be erased. In bulk
erase mode, any EEPROM address can be used to erase the
whole EEPROM. EENVR is not affected with block or bulk
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MC68HC708AS48 — Rev. 4.0
Electrically Erasable Programmable ROM (EEPROM)
MOTOROLA
b. To ensure proper erasing sequence, the EEPGM bit cannot
be set if the EELAT bit is cleared and a non-EEPROM write
has occurred. Once EEPGM is set, the type of erase mode
cannot be modified. If EEPGM is set, the on-board charge
pump generates the erase voltage and applies it to the user
EEPROM array. When the EEPGM bit is cleared, the erase
voltage is removed from the array and the internal charge
pump is turned off.
c.
Any attempt to clear both EEPGM and EELAT bits with a
single instruction will clear only EEPGM to allow time for
removal of high voltage from the EEPROM array.
N O N - D I S C L O S U R E
In general, all bits should be erased before being programmed.
However, if program/erase cycling is of concern, the following procedure
can be used to minimize bit cycling in each EEPROM byte. If any bit in
a byte must be changed from a 0 to a 1, the byte needs to be erased
before programming. Table 6-1 summarizes the conditions for erasing
before programming.
Table 6-1. EEPROM Program/Erase Cycling Reduction
EEPROM Data To Be
Programmed
EEPROM Data Before
Programming
Erase Before
Programming?
0
0
No
0
1
No
1
0
Yes
1
1
No
MC68HC708AS48 — Rev. 4.0
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Electrically Erasable Programmable ROM (EEPROM)
A G R E E M E N T
erase. Any attempts to read other EEPROM data will read the
latched data. If EELAT is set, other writes to the EECR will be
allowed after a valid EEPROM write.
R E Q U I R E D
Electrically Erasable Programmable ROM (EEPROM)
Functional Description
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R E Q U I R E D
Electrically Erasable Programmable ROM
6.4.3 EEPROM Block Protection
The 640 bytes of EEPROM are divided into two 256-byte blocks and one
128-byte block. Each of these blocks can be protected separately by the
EEBPx bit. Any attempt to program or erase memory locations within the
protected block will not allow the program/erase voltage to be applied to
the array. Table 6-2 shows the address ranges within the blocks.
A G R E E M E N T
Table 6-2. EEPROM Array Address Blocks
Block Number (EEBPx)
Address Range
EEBP0
$0800–$08FF
EEBP1
$0900–$09FF
EEBP2
$0A00–$0A7F
If the EEBPx bit is set, that corresponding address block is protected.
These bits are effective after a reset or a read to the EENVR register.
The block protect configuration can be modified by erasing/
programming the corresponding bits in the EENVR register and then
reading the EENVR register.
N O N - D I S C L O S U R E
In redundant mode EEBP2 will have no meaning.
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Electrically Erasable Programmable ROM (EEPROM)
MOTOROLA
NOTE:
Before entering redundant mode, program the EEPROM in
non-redundant mode.
6.4.5 EEPROM Configuration
The EEPROM non-volatile register (EENVR) contains configurations
concerning block protection and redundancy. EENVR is physically
located on the bottom of the EEPROM array. The contents are
non-volatile and are not modified by reset. On reset, this special register
loads the EEPROM configuration into a corresponding volatile EEPROM
array configuration register (EEACR). Thereafter, all reads to the
EENVR will reload EEACR.
The EEPROM configuration can be changed by programming/erasing
the EENVR like a normal EEPROM byte. The new array configuration
will take effect with a system reset or a read of the EENVR.
MC68HC708AS48 — Rev. 4.0
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Electrically Erasable Programmable ROM (EEPROM)
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A G R E E M E N T
To extend the EEPROM data retention, the array can be placed in
redundant mode. In this mode, the first 128 bytes of user EEPROM array
are mapped to the last 128 bytes. Reading, programming and erasing of
the first 128 EEPROM bytes ($0800–$087F) will physically affect two
bytes of EEPROM. Addressing the last 128 bytes will not be recognized.
Block protection still applies but EEBP2 is meaningless.
N O N - D I S C L O S U R E
6.4.4 EEPROM Redundant Mode
R E Q U I R E D
Electrically Erasable Programmable ROM (EEPROM)
Functional Description
R E Q U I R E D
Electrically Erasable Programmable ROM
6.4.6 EEPROM Control Register
This read/write register controls programming/erasing of the array.
Address:
$FE1D
Bit 7
Read:
6
Write:
A G R E E M E N T
4
3
2
EEOFF
EERAS1
EERAS0
EELAT
0
EEBCLK
Reset:
5
R
0
Bit 0
0
R
0
1
EEPGM
R
0
0
0
0
0
0
= Reserved
Figure 6-1. EEPROM Control Register (EECR)
EEBCLK — EEPROM Bus Clock Enable Bit
This read/write bit determines which clock will be used to drive the
internal charge pump for programming/erasing. Reset clears this bit.
1 = Bus clock drives charge pump.
0 = Internal RC oscillator drives charge pump.
NOTE:
Use the internal RC oscillator for applications in the 3 to 5 V range.
N O N - D I S C L O S U R E
EEOFF — EEPROM Power Down Bit
This read/write bit disables the EEPROM module for lower power
consumption. Any attempts to access the array will give unpredictable
results. Reset clears this bit.
1 = Disable EEPROM array
0 = Enable EEPROM array
NOTE:
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74
The EEPROM requires a recovery time, tEEOFF, to stabilize after clearing
the EEOFF bit. Refer to 21.6 Control Timing for timing values.
MC68HC708AS48 — Rev. 4.0
Electrically Erasable Programmable ROM (EEPROM)
MOTOROLA
R E Q U I R E D
Electrically Erasable Programmable ROM (EEPROM)
Functional Description
EERAS1:EERAS0 — EEPROM Erase Bits
These read/write bits set the programming/erasing modes. Reset
clears these bits.
EERAS1
EERA0
MODE
0
0
0
Byte Program
0
0
1
Byte Erase
0
1
0
Block Erase
0
1
1
Bulk Erase
1
X
X
No Erase/Program
X = don’t care
EELAT — EEPROM Latch Control Bit
This read/write bit latches the address and data buses for
programming the EEPROM array. EELAT can not be cleared if
EEPGM is still set. Reset clears this bit.
1 = Buses configured for EEPROM programming
0 = Buses configured for normal read operation
EEPGM — EEPROM Program/Erase Enable Bit
This read/write bit enables the internal charge pump and applies the
programming/erasing voltage to the EEPROM array if the EELAT bit
is set and a write to a valid EEPROM location has occurred. Reset
clears the EEPGM bit.
1 = EEPROM programming/erasing power switched on
0 = EEPROM programming/erasing power switched off
NOTE:
Writing logic 0s to both the EELAT and EEPGM bits with a single
instruction will clear only EEPGM. This is to allow time for the removal of
high voltage.
MC68HC708AS48 — Rev. 4.0
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Electrically Erasable Programmable ROM (EEPROM)
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N O N - D I S C L O S U R E
EEBPx
A G R E E M E N T
Table 6-3. EEPROM Program/Erase Mode Select
6.4.7 EEPROM Non-Volatile Register and EEPROM Array Configuration Register
These registers configure the EEPROM array blocks for programming
purposes. EEACR loads its contents from the EENVR register at reset
and upon any read of the EENVR register.
Address:
A G R E E M E N T
R E Q U I R E D
Electrically Erasable Programmable ROM
$FE1F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
EERA
R
R
R
R
EEBP2
EEBP1
EEBP0
Write:
R
R
R
R
R
R
R
R
EENVR
R
R
R
EENVR
EENVR
EENVR
EENVR
R
= Reserved
Figure 6-2. EEPROM Array Control Register (EEACR)
Address:
$FE1C
Bit 7
6
5
4
3
2
1
Bit 0
EERA
R
R
R
R
EEBP2
EEBP1
EEBP0
PV
R
R
R
PV
PV
PV
PV
Read:
Write:
Reset:
N O N - D I S C L O S U R E
R
= Reserved
PV = Programmed value or 1 in the erased state.
Figure 6-3. EEPROM Non-Volatile Register (EENVR)
EERA — EEPROM Redundant Array Bit
This programmable/erasable/readable bit in EENVR and read-only bit
in EEACR configures the array in redundant mode. Reset loads
EERA from EENVR to EEACR.
1 = EEPROM array in redundant mode configuration
0 = EEPROM array in normal mode configuration
EEBP2:EEBP0 — EEPROM Block Protection Bits
These programmable/erasable/readable bits in EENVR and
read-only bits in EEACR select blocks of EEPROM array from being
programmed or erased. Reset loads EEBP[2:0] from EENVR to
EEACR. See 6.4.3 EEPROM Block Protection.
1 = EEPROM array block protected
0 = EEPROM array block unprotected
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Electrically Erasable Programmable ROM (EEPROM)
MOTOROLA
6.4.8.1 Wait Mode
The WAIT instruction does not affect the EEPROM. It is possible to
program the EEPROM while the MCU is in wait mode. However, if the
EEPROM is inactive, power can be reduced by setting the EEOFF bit
before executing the WAIT instruction.
6.4.8.2 Stop Mode
The STOP instruction reduces the EEPROM power consumption to a
minimum. The STOP instruction should not be executed while the high
voltage is turned on (EEPGM = 1).
If stop mode is entered while program/erase is in progress, high voltage
will be turned off automatically. However, the EEPGM bit will remain set.
When stop mode is terminated and if EEPGM is still set, the high voltage
will be turned back on automatically. Program/erase time will need to be
extended if program/erase is interrupted by entering stop mode.
The module requires a recovery time, tEESTOP, to stabilize after leaving
stop mode (see 21.6 Control Timing). Attempts to access the array
during the recovery time will result in unpredictable behavior.
MC68HC708AS48 — Rev. 4.0
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Electrically Erasable Programmable ROM (EEPROM)
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A G R E E M E N T
The following subsections describe the low-power modes.
N O N - D I S C L O S U R E
6.4.8 Low-Power Modes
R E Q U I R E D
Electrically Erasable Programmable ROM (EEPROM)
Functional Description
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Electrically Erasable Programmable ROM
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MOTOROLA
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
7.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.4.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.4.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
7.4.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.4.4
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
7.4.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.6
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.7
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7.8
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7.2 Introduction
This section describes the central processor unit (CPU). The M68HC08
CPU is an enhanced and fully object-code-compatible version of the
M68HC05 CPU. The CPU08 Reference Manual (Motorola document
number CPU08RM/AD) contains a description of the CPU instruction
set, addressing modes, and architecture.
MC68HC708AS48 — Rev. 4.0
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Central Processor Unit (CPU)
79
R E Q U I R E D
7.1 Contents
A G R E E M E N T
Section 7. Central Processor Unit (CPU)
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
7.3 Features
Features of the CPU include:
•
Fully upward, object-code compatibility with the M68HC05 Family
•
16-bit stack pointer with stack manipulation instructions
•
16-bit index register with X-register manipulation instructions
•
8-MHz CPU internal bus frequency
•
64-Kbyte program/data memory space
•
16 addressing modes
•
Memory-to-memory data moves without using accumulator
•
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
•
Enhanced binary coded decimal (BCD) data handling
•
Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64 Kbytes
•
Low-power stop mode and wait mode
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Central Processor Unit (CPU)
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MC68HC708AS48 — Rev. 4.0
Central Processor Unit (CPU)
MOTOROLA
7.4 CPU Registers
Figure 7-1 shows the five CPU registers. CPU registers are not part of
the memory map.
7
0
ACCUMULATOR (A)
15
0
H
X
INDEX REGISTER (H:X)
0
15
A G R E E M E N T
STACK POINTER (SP)
0
PROGRAM COUNTER (PC)
7
0
V 1 1 H I N Z C
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 7-1. CPU Registers
7.4.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by Reset
Figure 7-2. Accumulator (A)
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Central Processor Unit (CPU)
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N O N - D I S C L O S U R E
15
R E Q U I R E D
Central Processor Unit (CPU)
CPU Registers
7.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
A G R E E M E N T
R E Q U I R E D
Central Processor Unit (CPU)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Read:
Write:
Reset:
X = Indeterminate
Figure 7-3. Index Register (H:X)
N O N - D I S C L O S U R E
The index register can serve also as a temporary data storage location.
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MC68HC708AS48 — Rev. 4.0
Central Processor Unit (CPU)
MOTOROLA
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 7-4. Stack Pointer (SP)
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct
address (page zero) space. For correct operation, the stack pointer must
point only to RAM locations.
MC68HC708AS48 — Rev. 4.0
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Central Processor Unit (CPU)
83
A G R E E M E N T
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
N O N - D I S C L O S U R E
7.4.3 Stack Pointer
R E Q U I R E D
Central Processor Unit (CPU)
CPU Registers
7.4.4 Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
A G R E E M E N T
R E Q U I R E D
Central Processor Unit (CPU)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Read:
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
N O N - D I S C L O S U R E
Figure 7-5. Program Counter (PC)
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MC68HC708AS48 — Rev. 4.0
Central Processor Unit (CPU)
MOTOROLA
7.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
5
4
3
2
1
Bit 0
V
1
1
H
I
N
Z
C
X
1
1
X
1
X
X
X
Read:
R E Q U I R E D
Central Processor Unit (CPU)
CPU Registers
Reset:
X = Indeterminate
Figure 7-6. Condition Code Register (CCR)
V — Overflow Flag Bit
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
A G R E E M E N T
Write:
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an ADD or ADC operation. The
half-carry flag is required for binary coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C flags
to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask Bit
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
MC68HC708AS48 — Rev. 4.0
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Central Processor Unit (CPU)
85
N O N - D I S C L O S U R E
H — Half-Carry Flag Bit
R E Q U I R E D
Central Processor Unit (CPU)
NOTE:
To maintain M68HC05 compatibility, the upper byte of the index register
(H) is not stacked automatically. If the interrupt service routine modifies
H, then the user must stack and unstack H using the PSHH and PULH
instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A G R E E M E N T
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative Flag Bit
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero Flag Bit
N O N - D I S C L O S U R E
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag Bit
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
Advance Information
86
MC68HC708AS48 — Rev. 4.0
Central Processor Unit (CPU)
MOTOROLA
7.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Motorola document number
CPU08RM/AD) for a description of the instructions and addressing
modes and more detail about CPU architecture.
7.6 CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. See Section 11. Break Module (Break). The
program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor
mode).
N O N - D I S C L O S U R E
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
A G R E E M E N T
R E Q U I R E D
Central Processor Unit (CPU)
Arithmetic/Logic Unit (ALU)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Central Processor Unit (CPU)
87
N O N - D I S C L O S U R E
A G R E E M E N T
7.7 Instruction Set Summary
Table 7-1 provides a summary of the M68HC08 instruction set.
Description
V H I N Z C
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
A ← (A) + (M) + (C)
Add with Carry
IMM
DIR
EXT
↕ ↕ – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
IMM
DIR
EXT
↕ ↕ – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry
AIS #opr
Add Immediate Value (Signed) to SP
SP ← (SP) + (16 « M)
– – – – – – IMM
AIX #opr
Add Immediate Value (Signed) to H:X
H:X ← (H:X) + (16 « M)
A ← (A) & (M)
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
Arithmetic Shift Left
(Same as LSL)
C
b7
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
Arithmetic Shift Right
BCC rel
Branch if Carry Bit Clear
b7
ff
ee ff
A7
ii
2
– – – – – – IMM
AF
ii
2
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
0
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
38 dd
48
58
68 ff
78
9E68 ff
4
1
1
4
3
5
C
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
37 dd
47
57
67 ff
77
9E67 ff
4
1
1
4
3
5
b0
b0
PC ← (PC) + 2 + rel ? (C) = 0
Advance Information
88
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
A ← (A) + (M)
Logical AND
ff
ee ff
Cycles
Operation
Effect on
CCR
Opcode
Source
Form
Operand
Table 7-1. Instruction Set Summary (Sheet 1 of 8)
Address
Mode
R E Q U I R E D
Central Processor Unit (CPU)
– – – – – – REL
24
ff
ee ff
rr
3
MC68HC708AS48 — Rev. 4.0
Central Processor Unit (CPU)
MOTOROLA
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? (Z) = 1
– – – – – – REL
27
rr
3
BGE opr
Branch if Greater Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
– – – – – – REL
90
rr
3
BGT opr
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 – – – – – – REL
92
rr
3
BHCC rel
Branch if Half Carry Bit Clear
PC ← (PC) + 2 + rel ? (H) = 0
– – – – – – REL
28
rr
3
BHCS rel
Branch if Half Carry Bit Set
PC ← (PC) + 2 + rel ? (H) = 1
– – – – – – REL
29
rr
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
– – – – – – REL
22
rr
3
BHS rel
Branch if Higher or Same
(Same as BCC)
PC ← (PC) + 2 + rel ? (C) = 0
– – – – – – REL
24
rr
3
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
– – – – – – REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
– – – – – – REL
2E
rr
3
(A) & (M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
A5
B5
C5
D5
E5
F5
9EE5
9ED5
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
93
rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
BLE opr
Branch if Less Than or Equal To
(Signed Operands)
BLO rel
Branch if Lower (Same as BCS)
BLS rel
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 – – – – – – REL
3
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25
rr
3
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
– – – – – – REL
23
rr
3
BLT opr
Branch if Less Than (Signed Operands)
PC ← (PC) + 2 + rel ? (N ⊕ V) =1
– – – – – – REL
91
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? (I) = 0
– – – – – – REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? (N) = 1
– – – – – – REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? (I) = 1
– – – – – – REL
2D
rr
3
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Central Processor Unit (CPU)
89
A G R E E M E N T
Mn ← 0
DIR (b0)
DIR (b1)
DIR (b2)
(b3)
– – – – – – DIR
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
N O N - D I S C L O S U R E
V H I N Z C
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 2 of 8)
R E Q U I R E D
Central Processor Unit (CPU)
Instruction Set Summary
N O N - D I S C L O S U R E
A G R E E M E N T
Description
V H I N Z C
Cycles
Operation
Effect on
CCR
Opcode
Source
Form
Operand
Table 7-1. Instruction Set Summary (Sheet 3 of 8)
Address
Mode
R E Q U I R E D
Central Processor Unit (CPU)
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? (Z) = 0
– – – – – – REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? (N) = 0
– – – – – – REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel
– – – – – – REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
(b3)
– – – – – ↕ DIR
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
– – – – – – REL
21
rr
3
PC ← (PC) + 3 + rel ? (Mn) = 1
DIR (b0)
DIR (b1)
DIR (b2)
(b3)
– – – – – ↕ DIR
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
(b3)
– – – – – – DIR
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
– – – – – – REL
AD
rr
4
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
IMM
– – – – – – IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
BRCLR n,opr,rel Branch if Bit n in M Clear
BRN rel
Branch Never
BRSET n,opr,rel Branch if Bit n in M Set
BSET n,opr
Set Bit n in M
BSR rel
Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel Compare and Branch if Equal
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
PC ← (PC) + 3 + rel ? (Mn) = 0
PC ← (PC) + 2
CLC
Clear Carry Bit
C←0
– – – – – 0 INH
98
1
CLI
Clear Interrupt Mask
I←0
– – 0 – – – INH
9A
2
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
0 – – 0 1 – INH
IX1
IX
SP1
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
Clear
Advance Information
90
3F dd
4F
5F
8C
6F ff
7F
9E6F ff
3
1
1
1
3
2
4
MC68HC708AS48 — Rev. 4.0
Central Processor Unit (CPU)
MOTOROLA
Compare A with M
Complement (One’s Complement)
CPHX #opr
CPHX opr
Compare H:X with M
Compare X with M
DAA
Decimal Adjust A
Decrement
DIV
Divide
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Exclusive OR M with A
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
0 – – ↕ ↕ 1 INH
IX1
IX
SP1
33 dd
43
53
63 ff
73
9E63 ff
(H:X) – (M:M + 1)
↕ – – ↕ ↕ ↕ IMM
DIR
65
75
ii ii+1
dd
3
4
(X) – (M)
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
U – – ↕ ↕ ↕ INH
72
(A)10
DBNZ opr,rel
DBNZA rel
DBNZX rel
Decrement and Branch if Not Zero
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
A1
B1
C1
D1
E1
F1
9EE1
9ED1
(A) – (M)
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
DIR
PC ← (PC) + 2 + rel ? (result) ≠ 0
INH
PC ← (PC) + 2 + rel ? (result) ≠ 0
– – – – – – INH
PC ← (PC) + 3 + rel ? (result) ≠ 0
IX1
PC ← (PC) + 2 + rel ? (result) ≠ 0
IX
PC ← (PC) + 4 + rel ? (result) ≠ 0
SP1
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
↕ – – ↕ ↕ – INH
IX1
IX
SP1
A ← (H:A)/(X)
H ← Remainder
– – – – ↕ ↕ INH
52
A ← (A ⊕ M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
9EE8
9ED8
MC68HC708AS48 — Rev. 4.0
MOTOROLA
3B
4B
5B
6B
7B
9E6B
ii
dd
hh ll
ee ff
ff
ff
ee ff
ff
ee ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5
2
dd rr
rr
rr
ff rr
rr
ff rr
3A dd
4A
5A
6A ff
7A
9E6A ff
5
3
3
5
4
6
4
1
1
4
3
5
7
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
Advance Information
Central Processor Unit (CPU)
91
A G R E E M E N T
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
N O N - D I S C L O S U R E
V H I N Z C
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 4 of 8)
R E Q U I R E D
Central Processor Unit (CPU)
Instruction Set Summary
N O N - D I S C L O S U R E
A G R E E M E N T
Description
V H I N Z C
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Load A from M
LDHX #opr
LDHX opr
Load H:X from M
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
DIR
INH
↕ – – ↕ ↕ – INH
IX1
IX
SP1
PC ← Jump Address
DIR
EXT
– – – – – – IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
DIR
EXT
– – – – – – IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
A ← (M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
H:X ← (M:M + 1)
0 – – ↕ ↕ – IMM
DIR
45
55
ii jj
dd
3
4
X ← (M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
AE
BE
CE
DE
EE
FE
9EEE
9EDE
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
0
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
38 dd
48
58
68 ff
78
9E68 ff
4
1
1
4
3
5
C
DIR
INH
↕ – – 0 ↕ ↕ INH
IX1
IX
SP1
34 dd
44
54
64 ff
74
9E64 ff
4
1
1
4
3
5
Jump
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
Increment
Jump to Subroutine
Load X from M
Logical Shift Left
(Same as ASL)
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
Logical Shift Right
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move
MUL
Unsigned multiply
C
b7
b0
0
b7
b0
3C dd
4C
5C
6C ff
7C
9E6C ff
H:X ← (H:X) + 1 (IX+D, DIX+)
DD
0 – – ↕ ↕ – DIX+
IMD
IX+D
4E
5E
6E
7E
X:A ← (X) × (A)
– 0 – – – 0 INH
42
(M)Destination ← (M)Source
Advance Information
92
Cycles
Operation
Effect on
CCR
Operand
Source
Form
Opcode
Table 7-1. Instruction Set Summary (Sheet 5 of 8)
Address
Mode
R E Q U I R E D
Central Processor Unit (CPU)
ff
ee ff
dd dd
dd
ii dd
dd
4
1
1
4
3
5
5
4
4
4
5
MC68HC708AS48 — Rev. 4.0
Central Processor Unit (CPU)
MOTOROLA
Negate (Two’s Complement)
NOP
NSA
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
30 dd
40
50
60 ff
70
9E60 ff
4
1
1
4
3
5
No Operation
None
– – – – – – INH
9D
1
Nibble Swap A
A ← (A[3:0]:A[7:4])
– – – – – – INH
62
3
A ← (A) | (M)
IMM
DIR
EXT
0 – – ↕ ↕ – IX2
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
9EEA
9EDA
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M
PSHA
Push A onto Stack
Push (A); SP ← (SP) – 1
– – – – – – INH
87
2
PSHH
Push H onto Stack
Push (H); SP ← (SP) – 1
– – – – – – INH
8B
2
PSHX
Push X onto Stack
Push (X); SP ← (SP) – 1
– – – – – – INH
89
2
PULA
Pull A from Stack
SP ← (SP + 1); Pull (A)
– – – – – – INH
86
2
PULH
Pull H from Stack
SP ← (SP + 1); Pull (H)
– – – – – – INH
8A
2
PULX
Pull X from Stack
SP ← (SP + 1); Pull (X)
– – – – – – INH
88
2
C
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
39 dd
49
59
69 ff
79
9E69 ff
4
1
1
4
3
5
DIR
INH
↕ – – ↕ ↕ ↕ INH
IX1
IX
SP1
36 dd
46
56
66 ff
76
9E66 ff
4
1
1
4
3
5
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Rotate Left through Carry
b7
b0
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
Rotate Right through Carry
RSP
Reset Stack Pointer
SP ← $FF
– – – – – – INH
9C
1
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕ ↕ ↕ ↕ ↕ ↕ INH
80
7
RTS
Return from Subroutine
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
– – – – – – INH
81
4
C
b7
b0
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Central Processor Unit (CPU)
93
A G R E E M E N T
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
N O N - D I S C L O S U R E
V H I N Z C
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 6 of 8)
R E Q U I R E D
Central Processor Unit (CPU)
Instruction Set Summary
N O N - D I S C L O S U R E
A G R E E M E N T
Description
V H I N Z C
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
Subtract with Carry
SEC
Set Carry Bit
SEI
Set Interrupt Mask
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
STHX opr
Store H:X in M
STOP
Enable IRQ Pin; Stop Oscillator
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Store X in M
Subtract
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
C←1
– – – – – 1 INH
99
1
I←1
– – 1 – – – INH
9B
2
M ← (A)
DIR
EXT
IX2
0 – – ↕ ↕ – IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
(M:M + 1) ← (H:X)
0 – – ↕ ↕ – DIR
35
I ← 0; Stop Oscillator
– – 0 – – – INH
8E
M ← (X)
DIR
EXT
IX2
0 – – ↕ ↕ – IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
IMM
DIR
EXT
↕ – – ↕ ↕ ↕ IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
– – 1 – – – INH
83
9
A ← (A) – (M) – (C)
A ← (A) – (M)
ii
dd
hh ll
ee ff
ff
Cycles
Operation
Effect on
CCR
Operand
Source
Form
Opcode
Table 7-1. Instruction Set Summary (Sheet 7 of 8)
Address
Mode
R E Q U I R E D
Central Processor Unit (CPU)
ff
ee ff
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
ff
ee ff
3
4
4
3
2
4
5
dd
4
1
ff
ee ff
ff
ee ff
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
SWI
Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
Transfer A to CCR
CCR ← (A)
↕ ↕ ↕ ↕ ↕ ↕ INH
84
2
TAX
Transfer A to X
X ← (A)
– – – – – – INH
97
1
TPA
Transfer CCR to A
A ← (CCR)
– – – – – – INH
85
1
Advance Information
94
MC68HC708AS48 — Rev. 4.0
Central Processor Unit (CPU)
MOTOROLA
Test for Negative or Zero
TSX
Transfer SP to H:X
TXA
Transfer X to A
TXS
Transfer H:X to SP
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
(A) – $00 or (X) – $00 or (M) – $00
DIR
INH
0 – – ↕ ↕ – INH
IX1
IX
SP1
H:X ← (SP) + 1
– – – – – – INH
95
2
A ← (X)
– – – – – – INH
9F
1
(SP) ← (H:X) – 1
– – – – – – INH
94
2
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
n
opr
PC
PCH
PCL
REL
rel
rr
SP1
SP2
SP
U
V
X
Z
&
|
⊕
()
–( )
#
«
←
?
:
↕
—
3D dd
4D
5D
6D ff
7D
9E6D ff
3
1
1
3
2
4
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
N O N - D I S C L O S U R E
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
7.8 Opcode Map
The opcode map is provided in Table 7-2.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Central Processor Unit (CPU)
A G R E E M E N T
V H I N Z C
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 7-1. Instruction Set Summary (Sheet 8 of 8)
R E Q U I R E D
Central Processor Unit (CPU)
Opcode Map
95
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
MSB
Branch
REL
DIR
INH
3
4
0
2
3
4
5
6
7
8
9
A
B
C
MOTOROLA
MC68HC708AS48 — Rev. 4.0
1
2
5
BRSET0
3 DIR
5
BRCLR0
3 DIR
5
BRSET1
3 DIR
5
BRCLR1
3 DIR
5
BRSET2
3 DIR
5
BRCLR2
3 DIR
5
BRSET3
3 DIR
5
BRCLR3
3 DIR
5
BRSET4
3 DIR
5
BRCLR4
3 DIR
5
BRSET5
3 DIR
5
BRCLR5
3 DIR
5
BRSET6
3 DIR
5
BRCLR6
3 DIR
5
BRSET7
3 DIR
5
BRCLR7
3 DIR
4
BSET0
2 DIR
4
BCLR0
2 DIR
4
BSET1
2 DIR
4
BCLR1
2 DIR
4
BSET2
2 DIR
4
BCLR2
2 DIR
4
BSET3
2 DIR
4
BCLR3
2 DIR
4
BSET4
2 DIR
4
BCLR4
2 DIR
4
BSET5
2 DIR
4
BCLR5
2 DIR
4
BSET6
2 DIR
4
BCLR6
2 DIR
4
BSET7
2 DIR
4
BCLR7
2 DIR
3
BRA
2 REL
3
BRN
2 REL
3
BHI
2 REL
3
BLS
2 REL
3
BCC
2 REL
3
BCS
2 REL
3
BNE
2 REL
3
BEQ
2 REL
3
BHCC
2 REL
3
BHCS
2 REL
3
BPL
2 REL
3
BMI
2 REL
3
BMC
2 REL
3
BMS
2 REL
3
BIL
2 REL
3
BIH
2 REL
5
6
1
NEGX
1 INH
4
CBEQX
3 IMM
7
DIV
1 INH
1
COMX
1 INH
1
LSRX
1 INH
4
LDHX
2 DIR
1
RORX
1 INH
1
ASRX
1 INH
1
LSLX
1 INH
1
ROLX
1 INH
1
DECX
1 INH
3
DBNZX
2 INH
1
INCX
1 INH
1
TSTX
1 INH
4
MOV
2 DIX+
1
CLRX
1 INH
4
NEG
2
IX1
5
CBEQ
3 IX1+
3
NSA
1 INH
4
COM
2 IX1
4
LSR
2 IX1
3
CPHX
3 IMM
4
ROR
2 IX1
4
ASR
2 IX1
4
LSL
2 IX1
4
ROL
2 IX1
4
DEC
2 IX1
5
DBNZ
3 IX1
4
INC
2 IX1
3
TST
2 IX1
4
MOV
3 IMD
3
CLR
2 IX1
SP1
IX
9E6
7
Control
INH
INH
8
9
Register/Memory
IX2
SP2
IMM
DIR
EXT
A
B
C
D
9ED
4
SUB
3 EXT
4
CMP
3 EXT
4
SBC
3 EXT
4
CPX
3 EXT
4
AND
3 EXT
4
BIT
3 EXT
4
LDA
3 EXT
4
STA
3 EXT
4
EOR
3 EXT
4
ADC
3 EXT
4
ORA
3 EXT
4
ADD
3 EXT
3
JMP
3 EXT
5
JSR
3 EXT
4
LDX
3 EXT
4
STX
3 EXT
4
SUB
3 IX2
4
CMP
3 IX2
4
SBC
3 IX2
4
CPX
3 IX2
4
AND
3 IX2
4
BIT
3 IX2
4
LDA
3 IX2
4
STA
3 IX2
4
EOR
3 IX2
4
ADC
3 IX2
4
ORA
3 IX2
4
ADD
3 IX2
4
JMP
3 IX2
6
JSR
3 IX2
4
LDX
3 IX2
4
STX
3 IX2
5
SUB
4 SP2
5
CMP
4 SP2
5
SBC
4 SP2
5
CPX
4 SP2
5
AND
4 SP2
5
BIT
4 SP2
5
LDA
4 SP2
5
STA
4 SP2
5
EOR
4 SP2
5
ADC
4 SP2
5
ORA
4 SP2
5
ADD
4 SP2
IX1
SP1
IX
E
9EE
F
LSB
1
Central Processor Unit (CPU)
0
Read-Modify-Write
INH
IX1
D
E
F
4
1
NEG
NEGA
2 DIR 1 INH
5
4
CBEQ CBEQA
3 DIR 3 IMM
5
MUL
1 INH
4
1
COM
COMA
2 DIR 1 INH
4
1
LSR
LSRA
2 DIR 1 INH
4
3
STHX
LDHX
2 DIR 3 IMM
4
1
ROR
RORA
2 DIR 1 INH
4
1
ASR
ASRA
2 DIR 1 INH
4
1
LSL
LSLA
2 DIR 1 INH
4
1
ROL
ROLA
2 DIR 1 INH
4
1
DEC
DECA
2 DIR 1 INH
5
3
DBNZ DBNZA
3 DIR 2 INH
4
1
INC
INCA
2 DIR 1 INH
3
1
TST
TSTA
2 DIR 1 INH
5
MOV
3 DD
3
1
CLR
CLRA
2 DIR 1 INH
INH Inherent
REL Relative
IMM Immediate
IX
Indexed, No Offset
DIR Direct
IX1 Indexed, 8-Bit Offset
EXT Extended
IX2 Indexed, 16-Bit Offset
DD Direct-Direct
IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
3
NEG
NEG
3 SP1 1 IX
6
4
CBEQ
CBEQ
4 SP1 2 IX+
2
DAA
1 INH
5
3
COM
COM
3 SP1 1 IX
5
3
LSR
LSR
3 SP1 1 IX
4
CPHX
2 DIR
5
3
ROR
ROR
3 SP1 1 IX
5
3
ASR
ASR
3 SP1 1 IX
5
3
LSL
LSL
3 SP1 1 IX
5
3
ROL
ROL
3 SP1 1 IX
5
3
DEC
DEC
3 SP1 1 IX
6
4
DBNZ
DBNZ
4 SP1 2 IX
5
3
INC
INC
3 SP1 1 IX
4
2
TST
TST
3 SP1 1 IX
4
MOV
2 IX+D
4
2
CLR
CLR
3 SP1 1 IX
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
7
3
RTI
BGE
1 INH 2 REL
4
3
RTS
BLT
1 INH 2 REL
3
BGT
2 REL
9
3
SWI
BLE
1 INH 2 REL
2
2
TAP
TXS
1 INH 1 INH
1
2
TPA
TSX
1 INH 1 INH
2
PULA
1 INH
2
1
PSHA
TAX
1 INH 1 INH
2
1
PULX
CLC
1 INH 1 INH
2
1
PSHX
SEC
1 INH 1 INH
2
2
PULH
CLI
1 INH 1 INH
2
2
PSHH
SEI
1 INH 1 INH
1
1
CLRH
RSP
1 INH 1 INH
1
NOP
1 INH
1
STOP
*
1 INH
1
1
WAIT
TXA
1 INH 1 INH
2
SUB
2 IMM
2
CMP
2 IMM
2
SBC
2 IMM
2
CPX
2 IMM
2
AND
2 IMM
2
BIT
2 IMM
2
LDA
2 IMM
2
AIS
2 IMM
2
EOR
2 IMM
2
ADC
2 IMM
2
ORA
2 IMM
2
ADD
2 IMM
3
SUB
2 DIR
3
CMP
2 DIR
3
SBC
2 DIR
3
CPX
2 DIR
3
AND
2 DIR
3
BIT
2 DIR
3
LDA
2 DIR
3
STA
2 DIR
3
EOR
2 DIR
3
ADC
2 DIR
3
ORA
2 DIR
3
ADD
2 DIR
2
JMP
2 DIR
4
4
BSR
JSR
2 REL 2 DIR
2
3
LDX
LDX
2 IMM 2 DIR
2
3
AIX
STX
2 IMM 2 DIR
MSB
0
3
SUB
2 IX1
3
CMP
2 IX1
3
SBC
2 IX1
3
CPX
2 IX1
3
AND
2 IX1
3
BIT
2 IX1
3
LDA
2 IX1
3
STA
2 IX1
3
EOR
2 IX1
3
ADC
2 IX1
3
ORA
2 IX1
3
ADD
2 IX1
3
JMP
2 IX1
5
JSR
2 IX1
5
3
LDX
LDX
4 SP2 2 IX1
5
3
STX
STX
4 SP2 2 IX1
4
SUB
3 SP1
4
CMP
3 SP1
4
SBC
3 SP1
4
CPX
3 SP1
4
AND
3 SP1
4
BIT
3 SP1
4
LDA
3 SP1
4
STA
3 SP1
4
EOR
3 SP1
4
ADC
3 SP1
4
ORA
3 SP1
4
ADD
3 SP1
2
SUB
1 IX
2
CMP
1 IX
2
SBC
1 IX
2
CPX
1 IX
2
AND
1 IX
2
BIT
1 IX
2
LDA
1 IX
2
STA
1 IX
2
EOR
1 IX
2
ADC
1 IX
2
ORA
1 IX
2
ADD
1 IX
2
JMP
1 IX
4
JSR
1 IX
4
2
LDX
LDX
3 SP1 1 IX
4
2
STX
STX
3 SP1 1 IX
High Byte of Opcode in Hexadecimal
LSB
Low Byte of Opcode in Hexadecimal
0
5
Cycles
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode
Central Processor Unit (CPU)
Advance Information
96
Table 7-2. Opcode Map
Bit Manipulation
DIR
DIR
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.4.1
Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.4.2
Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .101
8.4.2.1
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.4.2.2
Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . .103
8.4.2.3
Manual and Automatic PLL Bandwidth Modes . . . . . . .103
8.4.2.4
Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . .105
8.4.2.5
Special Programming Exceptions . . . . . . . . . . . . . . . . .107
8.4.3
Base Clock Selector Circuit. . . . . . . . . . . . . . . . . . . . . . . .107
8.4.4
CGM External Connections. . . . . . . . . . . . . . . . . . . . . . . .108
8.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
8.5.1
Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . .109
8.5.2
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . .109
8.5.3
External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . .109
8.5.4
Analog Power Pin (VDDA/VDDAREF). . . . . . . . . . . . . . . . . .110
8.5.5
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . .110
8.5.6
Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . .110
8.5.7
CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . .110
8.5.8
CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . .110
8.6
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8.6.1
PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.6.2
PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .114
8.6.3
PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . .116
8.7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
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R E Q U I R E D
8.1 Contents
A G R E E M E N T
Section 8. Clock Generator Module (CGM)
N O N - D I S C L O S U R E
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N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Clock Generator Module (CGM)
8.8
Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
8.9
CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .119
8.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .119
8.10.1
Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . .119
8.10.2
Parametric Influences on Reaction Time . . . . . . . . . . . . .121
8.10.3
Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . .122
8.10.4
Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . .123
8.2 Introduction
This section describes the clock generator module (CGM). The CGM
generates the crystal clock signal, CGMXCLK, which operates at the
frequency of the crystal. The CGM also generates the base clock signal,
CGMOUT, from which the system integration module (SIM) derives the
system clocks. CGMOUT is based on either the crystal clock divided by
two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.
The PLL is a frequency generator designed for use with 1-MHz to
16-MHz crystals or ceramic resonators. The PLL can generate an 8-MHz
bus frequency without using a 32-MHz crystal.
8.3 Features
Features of the CGM include:
•
Phase-locked loop with output frequency in integer multiples of the
crystal reference
•
Programmable hardware voltage-controlled oscillator (VCO) for
low-jitter operation
•
Automatic bandwidth control mode for low-jitter operation
•
Automatic frequency lock detector
•
CPU interrupt on entry or exit from locked condition
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•
Crystal oscillator circuit — The crystal oscillator circuit generates
the constant crystal frequency clock, CGMXCLK.
•
Phase-locked loop (PLL) — The PLL generates the
programmable VCO frequency clock CGMVCLK.
•
Base clock selector circuit — This software-controlled circuit
selects either CGMXCLK divided by two or the VCO clock,
CGMVCLK, divided by two as the base clock, CGMOUT. The SIM
derives the system clocks from CGMOUT.
Figure 8-1 shows the structure of the CGM.
8.4.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal from the system integration
module (SIM) enables the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. CGMXCLK is then buffered
to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing
for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%
and depends on external factors, including the crystal and related
external components.
An externally generated clock also can feed the OSC1 pin of the crystal
oscillator circuit. Connect the external clock to the OSC1 pin and let the
OSC2 pin float.
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A G R E E M E N T
The CGM consists of three major submodules:
N O N - D I S C L O S U R E
8.4 Functional Description
R E Q U I R E D
Clock Generator Module (CGM)
Functional Description
R E Q U I R E D
Clock Generator Module (CGM)
CRYSTAL OSCILLATOR
OSC2
CGMXCLK
CLOCK
SELECT
CIRCUIT
OSC1
÷2
CGMOUT
B S*
TO SIM
*When S = 1, CGMOUT = B
SIMOSCEN
CGMRDV
CGMRCLK
VDDA
A G R E E M E N T
A
TO SIM, SCI, ADC,
BDLC, COP
BCS
CGMXFC
USER MODE
VSS
VRS[7:4]
PTC3
MONITOR MODE
PHASE
DETECTOR
VOLTAGE
CONTROLLED
OSCILLATOR
LOOP
FILTER
PLL ANALOG
LOCK
DETECTOR
N O N - D I S C L O S U R E
LOCK
BANDWIDTH
CONTROL
AUTO
ACQ
INTERRUPT
CONTROL
PLLIE
CGMINT
PLLF
MUL[7:4]
CGMVDV
FREQUENCY
DIVIDER
CGMVCLK
Figure 8-1. CGM Block Diagram
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Read:
PLL Control Register
(PCTL) Write:
See page 112.
Reset:
$001C
Read:
PLL Bandwidth Control
Register (PBWC) Write:
See page 114.
Reset:
$001D
$001E
Bit 7
Read:
PLL Programming Register
(PPG) Write:
See page 116.
Reset:
6
5
4
PLLON
BCS
PLLF
PLLIE
R
0
0
1
0
ACQ
XLD
LOCK
AUTO
R
3
2
1
Bit 0
1
1
1
1
R
R
R
R
1
1
1
1
0
0
0
0
R
R
R
R
0
0
0
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
0
1
1
0
0
1
1
0
R
= Reserved
Figure 8-2. CGM I/O Register Summary
8.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually. Refer to 21.9 CGM Operating
Conditions for operating frequencies while reading this section.
8.4.2.1 Circuits
The PLL consists of these circuits:
•
Voltage-controlled oscillator (VCO)
•
Modulo VCO frequency divider
•
Phase detector
•
Loop filter
•
Lock detector
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A G R E E M E N T
Register Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Clock Generator Module (CGM)
Functional Description
R E Q U I R E D
Clock Generator Module (CGM)
A G R E E M E N T
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. (For maximum immunity guidelines, refer to
document numbers AN1050/D and AN1263/D on electromagnetic
compatibility available from your Motorola sales office.) The VCO
frequency is bound to a range from roughly one-half to twice the
center-of-range frequency, fVRS. Modulating the voltage on the CGMXFC
pin changes the frequency within this range. By design, fVRS is equal to
the nominal center-of-range frequency, fNOM, 4.9152 MHz times a linear
factor (L) or fNOM.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a crystal frequency, fRCLK, and is fed to the PLL
through a buffer. The buffer output is the final reference clock,
CGMRDV, running at a frequency equal to fRCLK.
N O N - D I S C L O S U R E
The VCO’s output clock, CGMVCLK, running at a frequency fVCLK is fed
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N (see 8.4.2.4 Programming the
PLL). The divider’s output is the VCO feedback clock, CGMVDV,
running at a frequency equal to fVCLK/N. See 21.9 CGM Operating
Conditions for more information.
The phase detector then compares the VCO feedback clock (CGMVDV)
with the final reference clock (CGMRDV). A correction pulse is
generated based on the phase difference between the two signals. The
loop filter then slightly alters the dc voltage on the external capacitor
connected to CGMXFC, based on the width and direction of the
correction pulse. The filter can make fast or slow corrections, depending
on its mode, described in 8.4.2.2 Acquisition and Tracking Modes.
The value of the external capacitor and the reference frequency
determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, fRD. The circuit determines the mode of the PLL and the lock
condition based on this comparison.
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•
Acquisition mode — In acquisition mode, the filter can make large
(see 21.11 CGM Acquisition/Lock Time Information) frequency
corrections to the VCO. This mode is used at PLL startup or when
the PLL has suffered a severe noise hit and the VCO frequency is
far off the desired frequency. When in acquisition mode, the ACQ
bit is clear in the PLL bandwidth control register (See 8.6.2 PLL
Bandwidth Control Register.)
•
Tracking mode — In tracking mode, the filter makes only small
(see 21.11 CGM Acquisition/Lock Time Information)
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. (See 8.4.3 Base Clock Selector Circuit.) The PLL is
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
8.4.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See 8.6.2 PLL Bandwidth Control Register.) If PLL
interrupts are enabled, the software can wait for a PLL interrupt request
and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (during PLL startup, usually) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe
to use as the source for the base clock. (See 8.4.3 Base Clock Selector
Circuit.) If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
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A G R E E M E N T
The PLL filter is manually or automatically configurable into one of two
operating modes:
N O N - D I S C L O S U R E
8.4.2.2 Acquisition and Tracking Modes
R E Q U I R E D
Clock Generator Module (CGM)
Functional Description
R E Q U I R E D
Clock Generator Module (CGM)
software must take appropriate action, depending on the application.
(See 8.7 Interrupts for information and precautions on using interrupts.)
N O N - D I S C L O S U R E
A G R E E M E N T
The following conditions apply when the PLL is in automatic bandwidth
control mode:
•
The ACQ bit (see 8.6.2 PLL Bandwidth Control Register) is a
read-only indicator of the mode of the filter. (See 8.4.2.2
Acquisition and Tracking Modes.)
•
The ACQ bit is set when the VCO frequency is within a certain
tolerance, ∆TRK, and is cleared when the VCO frequency is out of
a certain tolerance, ∆UNT. (See 8.10 Acquisition/Lock Time
Specifications for more information.)
•
The LOCK bit is a read-only indicator of the locked state of the
PLL.
•
The LOCK bit is set when the VCO frequency is within a certain
tolerance, ∆Lock, and is cleared when the VCO frequency is out of
a certain tolerance, ∆UNL. (See 8.10 Acquisition/Lock Time
Specifications for more information.)
•
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See 8.6.1 PLL
Control Register.)
The PLL also can operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below fBUSMAX and
require fast startup.
The following conditions apply when in manual mode:
•
ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
•
Before entering tracking mode (ACQ = 1), software must wait a
given time, tACQ (see 8.10 Acquisition/Lock Time
Specifications), after turning on the PLL by setting PLLON in the
PLL control register (PCTL).
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•
Software must wait a given time, tAL, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
•
The LOCK bit is disabled.
•
CPU interrupts from the CGM are disabled.
8.4.2.4 Programming the PLL
R E Q U I R E D
Clock Generator Module (CGM)
Functional Description
1. Choose the desired bus frequency, fBUSDES.
Example: fBUSDES = 8 MHz
2. Calculate the desired VCO frequency, fVCLKDES.
fVCLKDES = 4 × fBUSDES
Example: fVCLKDES = 4 × 8 MHz = 32 MHz
3. Using a reference frequency, fRCLK, equal to the crystal frequency,
calculate the VCO frequency multiplier, N.
The round function means that the result is rounded to the nearest
integer.
f VCLKDES
N = round  -------------------- fRCLK -
N O N - D I S C L O S U R E
NOTE:
32 MHz
Example: N = -------------------- = 8
4 MHz
4. Calculate the VCO frequency, fVCLK.
f VCLK = N × f RCLK
Example: fVCLK = 8 × 4 MHz = 32 MHz
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A G R E E M E N T
Use this procedure to program the PLL:
105
R E Q U I R E D
Clock Generator Module (CGM)
5. Calculate the bus frequency, fBUS, and compare fBUS with fBUSDES.
If the calculated fBUS is not within the tolerance limits of your
application, select another fBUSDES or another fRCLK.
f VCLK
f BUS = -----------4
A G R E E M E N T
32 MHz
Example: f BUS = -------------------- = 8 MHz
4
6. Using the value 4.9152 MHz for fNOM, calculate the VCO linear
range multiplier, L. The linear range multiplier controls the
frequency range of the PLL.
f VCLK
L = round  ----------- f NOM-
Example: L
=
32 MHz
-------------------------------- = 7
4.9152 MHz
N O N - D I S C L O S U R E
7. Calculate the VCO center-of-range frequency, fVRS. The
center-of-range frequency is the midpoint between the minimum
and maximum frequencies attainable by the PLL.
fVRS = L × fNOM
Example: fVRS = 7 × 4.9152 MHz = 34.4 MHz
NOTE:
Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
For proper operation,
f NOM
f VRS – f VCLK ≤ --------------2
8. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG),
program the binary equivalent of N.
b. In the lower four bits of the PLL programming register (PPG),
program the binary equivalent of L.
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•
A 0 value for N is interpreted exactly the same as a value of 1.
•
A 0 value for L disables the PLL and prevents its selection as the
source for the base clock. (See 8.4.3 Base Clock Selector
Circuit.)
8.4.3 Base Clock Selector Circuit
This circuit is used to select either the crystal clock (CGMXCLK) or the
VCO clock (CGMVCLK) as the source of the base clock (CGMOUT).
The two input clocks go through a transition control circuit that waits up
to three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock. The VCO clock also cannot
be selected as the base clock source if the factor L is programmed to a
0. This value would set up a condition inconsistent with the operation of
the PLL, so that the PLL would be disabled and the crystal clock would
be forced as the source of the base clock.
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A G R E E M E N T
The programming method described in 8.4.2.4 Programming the PLL
does not account for two possible exceptions. A value of 0 for N or L is
meaningless when used in the equations given. To account for these
exceptions:
N O N - D I S C L O S U R E
8.4.2.5 Special Programming Exceptions
R E Q U I R E D
Clock Generator Module (CGM)
Functional Description
8.4.4 CGM External Connections
In its typical configuration, the CGM requires seven external
components. Five of these are for the crystal oscillator and two are for
the PLL.
The crystal oscillator is normally connected in a Pierce oscillator
configuration, as shown in Figure 8-3. Figure 8-3 shows only the logical
representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
A G R E E M E N T
R E Q U I R E D
Clock Generator Module (CGM)
•
Crystal, X1
•
Fixed capacitor, C1
•
Tuning capacitor, C2, can also be a fixed capacitor
•
Feedback resistor, RB
•
Series resistor, RS, optional
N O N - D I S C L O S U R E
The series resistor (RS) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high-frequency crystals. Refer to the crystal
manufacturer’s data for more information.
Figure 8-3 also shows the external components for the PLL:
•
Bypass capacitor, CBYP
•
Filter capacitor, CF
Routing should be done with great care to minimize signal cross talk and
noise. (See 8.10 Acquisition/Lock Time Specifications for routing
information and more information on the filter capacitor’s value and its
effects on PLL performance.)
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CGMXCLK
OSC1
OSC2
VSS
RS*
CGMXFC
VDDA/VDDAREF
VDD
CF
CBYP
RB
C1
A G R E E M E N T
X1
C2
*RS can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data.
Figure 8-3. CGM External Connections
8.5 I/O Signals
The following paragraphs describe the CGM I/O signals.
8.5.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
8.5.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
8.5.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase
corrections. A small external capacitor is connected to this pin.
NOTE:
To prevent noise problems, CF should be placed as close to the
CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the CF connection.
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N O N - D I S C L O S U R E
SIMOSCEN
R E Q U I R E D
Clock Generator Module (CGM)
I/O Signals
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Clock Generator Module (CGM)
8.5.4 Analog Power Pin (VDDA/VDDAREF)
VDDA/VDDAREF is a power pin used by the analog portions of the PLL.
Connect the VDDA/VDDAREF pin to the same voltage potential as the VDD
pin.
NOTE:
Route VDDA/VDDAREF carefully for maximum noise immunity and place
bypass capacitors as close as possible to the package.
8.5.5 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator and PLL.
8.5.6 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal, fXCLK, and comes directly from the crystal oscillator circuit.
Figure 8-3 shows only the logical relation of CGMXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
8.5.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM,
which generates the MCU clocks. CGMOUT is a 50% duty cycle clock
running at twice the bus frequency. CGMOUT is software programmable
to be either the oscillator output, CGMXCLK, divided by two or the VCO
clock, CGMVCLK, divided by two.
8.5.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
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MOTOROLA
•
PLL control register (PCTL) (See 8.6.1 PLL Control Register.)
•
PLL bandwidth control register (PBWC) (See 8.6.2 PLL
Bandwidth Control Register.)
•
PLL programming register (PPG) (See 8.6.3 PLL Programming
Register.)
Figure 8-4 is a summary of the CGM registers.
Addr.
Register Name
Read:
PLL Control Register
(PCTL) Write:
See page 112.
Reset:
$001C
Read:
PLL Bandwidth Control
Register (PBWC) Write:
See page 114.
Reset:
$001D
$001E
Read:
PLL Programming Register
(PPG) Write:
See page 116.
Reset:
Bit 7
6
5
4
PLLON
BCS
PLLF
PLLIE
R
0
0
1
0
ACQ
XLD
LOCK
AUTO
R
3
2
1
Bit 0
1
1
1
1
R
R
R
R
1
1
1
1
0
0
0
0
R
R
R
R
0
0
0
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
0
1
1
0
0
1
1
0
R
= Reserved
NOTES:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 8-4. CGM I/O Register Summary
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A G R E E M E N T
These registers control and monitor operation of the CGM:
N O N - D I S C L O S U R E
8.6 CGM Registers
R E Q U I R E D
Clock Generator Module (CGM)
CGM Registers
R E Q U I R E D
Clock Generator Module (CGM)
8.6.1 PLL Control Register
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
Address:
$001C
Bit 7
Read:
6
Write:
A G R E E M E N T
4
PLLON
BCS
PLLF
PLLIE
Reset:
5
R
0
R
0
1
0
3
2
1
Bit 0
1
1
1
1
R
R
R
R
1
1
1
1
= Reserved
Figure 8-5. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
N O N - D I S C L O S U R E
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE:
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
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PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). (See 8.4.3 Base Clock Selector
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU
is powering up.
1 = PLL on
0 = PLL off
R E Q U I R E D
Clock Generator Module (CGM)
CGM Registers
NOTE:
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. (See 8.4.3 Base Clock Selector Circuit.)
PCTL[3:0] — Unimplemented bits
These bits provide no function and always read as logic 1s.
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N O N - D I S C L O S U R E
This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM
output, CGMOUT. CGMOUT frequency is one-half the frequency of
the selected clock. BCS cannot be set while the PLLON bit is clear.
After toggling BCS, it may take up to three CGMXCLK and three
CGMVCLK cycles to complete the transition from one source clock to
the other. During the transition, CGMOUT is held in stasis. (See 8.4.3
Base Clock Selector Circuit.) Reset and the STOP instruction clear
the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
A G R E E M E N T
BCS — Base Clock Select Bit
8.6.2 PLL Bandwidth Control Register
The PLL bandwidth control register:
A G R E E M E N T
R E Q U I R E D
Clock Generator Module (CGM)
•
Selects automatic or manual (software-controlled) bandwidth
control mode
•
Indicates when the PLL is locked
•
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking mode
Address:
$001D
Bit 7
Read:
6
4
ACQ
XLD
3
2
1
Bit 0
0
0
0
0
R
R
R
R
0
0
0
0
LOCK
AUTO
Write:
Reset:
5
R
0
R
0
0
0
= Reserved
N O N - D I S C L O S U R E
Figure 8-6. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
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In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
XLD — Crystal Loss Detect Bit
When the VCO output (CGMVCLK) is driving CGMOUT, this
read/write bit can indicate whether the crystal reference frequency is
active or not. To check the status of the crystal reference, follow these
steps:
1. Write a logic 1 to XLD.
2. Wait N × 4 cycles. (N is the VCO frequency multiplier.)
3. Read XLD.
1 = Crystal reference not active
0 = Crystal reference active
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD
always reads as logic 0.
PBWC[3:0] — Reserved for Test
These bits enable test functions not available in user mode. To
ensure software portability from development systems to user
applications, software should write 0s to PBWC[3:0] whenever writing
to PBWC.
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A G R E E M E N T
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
N O N - D I S C L O S U R E
ACQ — Acquisition Mode Bit
R E Q U I R E D
Clock Generator Module (CGM)
CGM Registers
R E Q U I R E D
Clock Generator Module (CGM)
8.6.3 PLL Programming Register
The PLL programming register contains the programming information
for the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
Address:
$001E
Bit 7
6
5
4
3
2
1
Bit 0
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
0
1
1
0
0
1
1
0
A G R E E M E N T
Read:
Write:
Reset:
R
= Reserved
Figure 8-7. PLL Programming Register (PPG)
MUL[7:4] — Multiplier Select Bits
N O N - D I S C L O S U R E
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See 8.4.2 Phase-Locked Loop
Circuit (PLL).) A value of $0 in the multiplier select bits configures the
modulo feedback divider the same as a value of $1. Reset initializes
these bits to $6 to give a default multiply value of 6.
Table 8-1. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
VCO Frequency Multiplier (N)
0000
1
0001
1
0010
2
0011
3
1101
13
1110
14
1111
15
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VRS[7:4] — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency,
fVRS, (see 8.4.2 Phase-Locked Loop Circuit (PLL).) VRS[7:4] cannot
be written when the PLLON bit in the PLL control register (PCTL) is
set. (See 8.4.2.5 Special Programming Exceptions.) A value of $0
in the VCO range selects bits, disables the PLL, and clears the BCS
bit in the PCTL. (See 8.4.3 Base Clock Selector Circuit and 8.4.2.5
Special Programming Exceptions for more information.) Reset
initializes the bits to $6 to give a default range multiply value of 6.
NOTE:
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
8.7 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,
becomes set whether interrupts are enabled or not. When the AUTO bit
is clear, CPU interrupts from the PLL are disabled and PLLF reads as
logic 0.
Software should read the LOCK bit after a PLL interrupt request to see
if the request was due to an entry into lock or an exit from lock. When the
PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not frequency sensitive,
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A G R E E M E N T
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
N O N - D I S C L O S U R E
NOTE:
R E Q U I R E D
Clock Generator Module (CGM)
Interrupts
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Clock Generator Module (CGM)
interrupts should be disabled to prevent PLL interrupt service routines
from impeding software performance or from exceeding stack
limitations.
NOTE:
Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
8.8 Special Modes
The WAIT and STOP instructions put the MCU in low-power standby
modes.
8.8.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
8.8.2 Stop Mode
When the STOP instruction executes, the SIM drives the SIMOSCEN
signal low, disabling the CGM and holding low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If the STOP instruction is executed with the VCO clock (CGMVCLK)
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock
(CGMXCLK) divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
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To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the
PLLF bit.
8.10 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
8.10.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percent of the
step input or when the output settles to the desired value plus or minus
a percent of the frequency change. Therefore, the reaction time is
constant in this definition, regardless of the size of the step input. For
example, consider a system with a 5% acquisition time tolerance. If a
command instructs the system to change from 0 Hz to 1 MHz, the
acquisition time is the time taken for the frequency to reach
1 MHz ±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is
operating at 1 MHz and suffers a –100 kHz noise hit, the acquisition time
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A G R E E M E N T
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 9.8.3 SIM Break Flag Control
Register.)
N O N - D I S C L O S U R E
8.9 CGM During Break Interrupts
R E Q U I R E D
Clock Generator Module (CGM)
CGM During Break Interrupts
R E Q U I R E D
Clock Generator Module (CGM)
is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5%
of the 100-kHz step input.
A G R E E M E N T
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
N O N - D I S C L O S U R E
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are as follows:
•
Acquisition time, tACQ, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance, ∆TRK.
Acquisition time is based on an initial frequency error, [(fDES –
fORIG)/fDES], of not more than ±100%. In automatic bandwidth
control mode (see 8.4.2.3 Manual and Automatic PLL
Bandwidth Modes), acquisition time expires when the ACQ bit
becomes set in the PLL bandwidth control register (PBWC).
•
Lock time, tLOCK, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance, ∆LOCK. Lock
time is based on an initial frequency error, [(fDES – fORIG)/fDES], of not
more than ±100%. In automatic bandwidth control mode, lock time
expires when the LOCK bit becomes set in the PLL bandwidth
control register (PBWC). (See 8.4.2.3 Manual and Automatic
PLL Bandwidth Modes.)
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
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MOTOROLA
The most critical parameter which affects the PLL reaction times is the
reference frequency, fRDV. This frequency is the input to the phase
detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so
several corrections are required to reduce the frequency error.
Therefore, the slower the reference the longer it takes to make these
corrections. This parameter is also under user control via the choice of
an external crystal frequency, fXCLK.
Another critical parameter is the external filter capacitor. The PLL
modifies the voltage on the VCO by adding or subtracting charge from
this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus change in charge) is proportional to the
capacitor size. The size of the capacitor also is related to the stability of
the PLL. If the capacitor is too small, the PLL cannot make small enough
adjustments to the voltage and the system cannot lock. If the capacitor
is too large, the PLL may not be able to adjust the voltage in a
reasonable time. (See 8.10.3 Choosing a Filter Capacitor.)
Also important is the operating voltage potential applied to the PLL
analog portion potential (VDDA/VDDAREF). Typically VDDA/VDDAREF is at
the same potential as VDD. The power supply potential alters the
characteristics of the PLL. A fixed value is best. Variable supplies, such
as batteries, are acceptable if they vary within a known range at very
slow speeds. Noise on the power supply is not acceptable, because it
causes small frequency errors which continually change the acquisition
time of the PLL.
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A G R E E M E N T
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
N O N - D I S C L O S U R E
8.10.2 Parametric Influences on Reaction Time
R E Q U I R E D
Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
Temperature and processing also can affect acquisition time because
the electrical characteristics of the PLL change. The part operates as
specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of
the PLL. These factors include noise injected into the PLL through the
filter capacitor, filter capacitor leakage, stray impedances on the circuit
board, and even humidity or circuit board contamination.
8.10.3 Choosing a Filter Capacitor
As described in 8.10.2 Parametric Influences on Reaction Time, the
external filter capacitor, CF, is critical to the stability and reaction time of
the PLL. The PLL is also dependent on reference frequency, fRDV, and
supply voltage, VDD. The value of the capacitor, therefore, must be
chosen with supply potential and reference frequency in mind. For
proper operation, the external filter capacitor must be chosen according
to the following equation. Refer to 8.4.2 Phase-Locked Loop Circuit
(PLL) for the value of fRDV and 21.10 CGM Component Information for
the value of CFACT.
V DDA
C F = C FACT  ----------- f RDV-
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Clock Generator Module (CGM)
For the value of VDDA, choose the voltage potential at which the MCU is
operating. If the power supply is variable, choose a value near the
middle of the range of possible supply values.
This equation does not always yield a commonly available capacitor
size, so round to the nearest available size. If the value is between two
different sizes, choose the higher value for better stability. Choosing the
lower size may seem attractive for acquisition time improvement, but the
PLL can become unstable. Also, always choose a capacitor with a tight
tolerance (±20% or better) and low dissipation.
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•
Correct selection of filter capacitor, CF (See 8.10.3 Choosing a
Filter Capacitor.)
•
Room temperature operation
•
Negligible external leakage on CGMXFC
•
Negligible noise
The K factor in the equations is derived from internal PLL parameters.
KACQ is the K factor when the PLL is configured in acquisition mode, and
KTRK is the K factor when the PLL is configured in tracking mode. (See
8.4.2.2 Acquisition and Tracking Modes.)
t
 V DDA
8
=  -----------------  -----------------

ACQ
f
K
 RDV  ACQ
t
 V DDA
4
=  -----------------  ----------------

AL
f
K
 RDV  TRK
t
NOTE:
LOCK
= t
ACQ
+t
AL
There is an inverse proportionality between the lock time and the
reference frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See 8.4.2.3
Manual and Automatic PLL Bandwidth Modes.) A certain number of
clock cycles, nACQ, is required to ascertain that the PLL is within the
tracking mode entry tolerance, ∆TRK, before exiting acquisition mode.
Additionally, a certain number of clock cycles, nTRK, is required to
ascertain that the PLL is within the lock mode entry tolerance, ∆LOCK.
Therefore, the acquisition time, tACQ, is an integer multiple of nACQ/fRDV,
and the acquisition to lock time, tAL, is an integer multiple of nTRK/fRDV.
Refer to 8.4.2 Phase-Locked Loop Circuit (PLL) for the value of fRDV.
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A G R E E M E N T
The actual acquisition and lock times can be calculated using the
equations in this subsection. These equations yield nominal values
under the following conditions:
N O N - D I S C L O S U R E
8.10.4 Reaction Time Calculation
R E Q U I R E D
Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
R E Q U I R E D
Clock Generator Module (CGM)
Also, since the average frequency over the entire measurement period
must be within the specified tolerance, the total time usually is longer
than tLock as calculated above.
N O N - D I S C L O S U R E
A G R E E M E N T
In manual mode, it is usually necessary to wait considerably longer than
tLock before selecting the PLL clock (see 8.4.3 Base Clock Selector
Circuit), because the factors described in 8.10.2 Parametric
Influences on Reaction Time can slow the lock time considerably.
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Section 9. System Integration Module (SIM)
9.1 Contents
9.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .129
9.3.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
9.3.2
Clock Startup from POR or LVI Reset. . . . . . . . . . . . . . . .129
9.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . .130
9.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .130
9.4.1
External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.4.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . .132
9.4.2.1
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.4.2.2
Computer Operating Properly (COP) Reset. . . . . . . . . .134
9.4.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .134
9.4.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .134
9.4.2.5
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .134
9.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.5.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . .135
9.5.2
SIM Counter During Stop Mode Recovery . . . . . . . . . . . .135
9.5.3
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . .135
9.6
Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . .136
9.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
9.6.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9.6.1.2
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
9.6.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.6.3
Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.6.4
Status Flag Protection in Break Mode. . . . . . . . . . . . . . . .140
9.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
9.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
9.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
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A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
N O N - D I S C L O S U R E
9.2
R E Q U I R E D
Advance Information — MC68HC708AS48
9.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
9.8.1
SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . .144
9.8.2
Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9.8.3
SIM Break Flag Control Register. . . . . . . . . . . . . . . . . . . .147
9.2 Introduction
This section describes the system integration module (SIM), which
supports up to 24 external and/or internal interrupts. The SIM is a system
state controller that coordinates CPU and exception timing. Together
with the central processor unit (CPU), the SIM controls all MCU
activities. A block diagram of the SIM is shown in Figure 9-1. Figure 9-2
is a summary of the SIM input/output (I/O) registers.
A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
N O N - D I S C L O S U R E
– Internal clock control
•
Master reset control, including power-on reset (POR) and
computer operating properly (COP) timeout
•
Interrupt control
– Acknowledge timing
– Arbitration control timing
– Vector address generation
•
CPU enable/disable timing
•
Modular architecture expandable to 128 interrupt sources
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R E Q U I R E D
System Integration Module (SIM)
Introduction
MODULE STOP
MODULE WAIT
CPU STOP FROM CPU
CPU WAIT FROM CPU
STOP/WAIT
CONTROL
SIMOSCEN TO CGM
SIM
COUNTER
COP CLOCK
CGMXCLK FROM CGM
A G R E E M E N T
CGMOUT FROM CGM
÷2
RESET
PIN LOGIC
CLOCK GENERATORS
INTERNAL CLOCKS
LVI FROM LVI MODULE
POR CONTROL
MASTER
RESET
CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
ILLEGAL OPCODE FROM CPU
ILLEGAL ADDRESS FROM ADDRESS
MAP DECODERS
COP FROM COP MODULE
N O N - D I S C L O S U R E
CLOCK
CONTROL
RESET
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 9-1. SIM Block Diagram
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127
A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
Addr.
Register Name
$FE00
Read:
SIM Break Status Register
(SBSR) Write:
See page 144.
Reset:
$FE01
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
R
R
R
R
R
R
SBSW
R
0
Read:
SIM Reset Status Register
(SRSR) Write:
See page 146.
Reset:
Read:
SIM Break Flag Control
Register (SBFCR) Write:
See page 147.
Reset:
POR
PIN
COP
ILOP
ILAD
0
LVI
0
R
R
R
R
R
R
R
R
1
X
0
0
0
0
X
0
BCFE
R
R
R
R
R
R
R
0
R
= Reserved
X = Indeterminate
Figure 9-2. SIM I/O Register Summary
Table 9-1 shows the internal signal names used in this section.
Table 9-1. Signal Name Conventions
N O N - D I S C L O S U R E
Signal Name
Description
CGMXCLK
Buffered version of OSC1 from clock generator module
(CGM)
CGMVCLK
PLL output
CGMOUT
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
IAB
Internal address bus
IDB
Internal data bus
PORRST
Signal from the power-on reset module to the SIM
IRST
Internal reset signal
R/W
Read/write signal
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MOTOROLA
9.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 9-3. This clock can come
from either an external oscillator or from the on-chip PLL.
(See Section 8. Clock Generator Module (CGM).)
R E Q U I R E D
System Integration Module (SIM)
SIM Bus Clock Control and Generation
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. (See Section 8. Clock Generator Module (CGM).)
9.3.2 Clock Startup from POR or LVI Reset
CGMXCLK
OSC1
CGMVCLK
PLL
CLOCK
SELECT
CIRCUIT
÷2
A
CGMOUT
B S*
*When S = 1,
CGMOUT = B
N O N - D I S C L O S U R E
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after 4096 CGMXCLK cycles.
The RST pin is driven low by the SIM during this entire period. The bus
clocks start upon completion of the timeout.
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
BCS
PTC3
MONITOR MODE
USER MODE
CGM
Figure 9-3. CGM Clock Signals
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
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A G R E E M E N T
9.3.1 Bus Timing
129
9.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. (See 9.7.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. However, some modules can
be programmed to be active in wait mode. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode.
9.4 Reset and System Initialization
The MCU has these reset sources:
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
•
Power-on reset module (POR)
•
External reset pin (RST)
•
Computer operating properly module (COP)
•
Low-voltage inhibit module (LVI)
•
Illegal opcode
•
Illegal address
Each of these resets produces the vector $FFFE–FFFF ($FEFE–FEFF
in monitor mode) and assert the internal reset signal (IRST). IRST
causes all registers to be returned to their default values and all modules
to be returned to their reset states.
An internal reset clears the SIM counter (see 9.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). (See 9.8 SIM Registers.)
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MOTOROLA
9.4.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit
of the SIM reset status register (SRSR) is set as long as RST is held low
for a minimum of 67 CGMXCLK cycles, assuming that neither the POR
nor the LVI was the source of the reset. See Table 9-2 for details.
Figure 9-4 shows the relative timing.
Reset Type
Number of Cycles Required to Set PIN
POR/LVI
4163 (4096 + 64 + 3)
All Others
67 (64 + 3)
A G R E E M E N T
Table 9-2. PIN Bit Set Timing
CGMOUT
RST
IAB
PC
VECT H
R E Q U I R E D
System Integration Module (SIM)
Reset and System Initialization
VECT L
N O N - D I S C L O S U R E
Figure 9-4. External Reset Timing
MC68HC708AS48 — Rev. 4.0
MOTOROLA
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System Integration Module (SIM)
131
9.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles.
See Figure 9-5. An internal reset can be caused by an illegal address,
illegal opcode, COP timeout, LVI, or POR. (See Figure 9-6.) Note that
for LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST shown in
Figure 9-5.
A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
IRST
N O N - D I S C L O S U R E
RST
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 9-5. Internal Reset Timing
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Figure 9-6. Sources of Internal Reset
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System Integration Module (SIM)
MOTOROLA
9.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Another 64 CGMXCLK cycles later, the CPU
and memories are released from reset to allow the reset vector
sequence to occur.
R E Q U I R E D
System Integration Module (SIM)
Reset and System Initialization
A POR pulse is generated.
•
The internal reset signal is asserted.
•
The SIM enables CGMOUT.
•
Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
•
The RST pin is driven low during the oscillator stabilization time.
•
The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
N O N - D I S C L O S U R E
•
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
CGMXCLK
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 9-7. POR Recovery
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
System Integration Module (SIM)
A G R E E M E N T
At power-on, these events occur:
133
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
9.4.2.2 Computer Operating Properly (COP) Reset
The overflow of the COP counter causes an internal reset and sets the
COP bit in the SIM reset status register (SRSR) if the COPD bit in the
CONFIG register is at logic 0. (See Section 13. Computer Operating
Properly (COP).)
9.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
NOTE:
A $9E opcode (pre-byte for SP instructions) followed by an $8E opcode
(stop instruction) generates a stop mode recovery reset.
If the stop enable bit, STOP, in the CONFIG register is logic 0, the SIM
treats the STOP instruction as an illegal opcode and causes an illegal
opcode reset.
9.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset.
9.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit (LVI) module asserts its output to the SIM when
the VDD voltage falls to the VLVII voltage. The LVI bit in the SIM reset
status register (SRSR) is set and a chip reset is asserted if the LVIPWRD
and LVIRSTD bits in the CONFIG register are at logic 0. The RST pin
will be held low until the SIM counts 4096 CGMXCLK cycles after VDD
rises above VLVIR. Another 64 CGMXCLK cycles later, the CPU is
released from reset to allow the reset vector sequence to occur. (See
Section 10. Low-Voltage Inhibit (LVI).)
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System Integration Module (SIM)
MOTOROLA
9.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation module (CGM) to drive the
bus clock state machine.
9.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the
CONFIG register. If the SSREC bit is a logic 1, then the stop recovery is
reduced from the normal delay of 4096 CGMXCLK cycles down to 32
CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long startup times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC
cleared.
9.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 9.7.2 Stop Mode
for details.) The SIM counter is free-running after all reset states. (See
9.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
System Integration Module (SIM)
135
A G R E E M E N T
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly (COP) module. The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 12 bits long and is clocked by the falling edge of CGMXCLK.
N O N - D I S C L O S U R E
9.5 SIM Counter
R E Q U I R E D
System Integration Module (SIM)
SIM Counter
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
9.6 Program Exception Control
Normal, sequential program execution can be changed in three different
ways:
•
Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
•
Reset
•
Break interrupts
9.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 9-8 shows interrupt entry timing.
Figure 9-10 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced or the I bit is cleared.
(See Figure 9-9.)
MODULE
INTERRUPT
IAB
LAST
ADDRESS
IDB
SP
SP – 1
SP – 2
PC – 1
END OF
PC – 1
LAST INSTR. LOW BYTE HIGH BYTE
SP – 3
X
VECTOR
VECTOR
ADDR. HIGH ADDR. LOW
SP – 4
A
CCR
VECTOR
HIGH
NEW PC
VECTOR
LOW
NEW PC
+1
OPCODE
R/W
Figure 9-8. Interrupt Entry Timing
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MC68HC708AS48 — Rev. 4.0
System Integration Module (SIM)
MOTOROLA
R E Q U I R E D
System Integration Module (SIM)
Program Exception Control
FROM RESET
BREAK
INTERRUPT?
I BIT
SET?
YES
NO
I BIT SET?
A G R E E M E N T
YES
NO
HARDWARE
INTERRUPT?
YES
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
NO
FETCH NEXT
INSTRUCTION.
YES
N O N - D I S C L O S U R E
SWI
INSTRUCTION?
NO
RTI
INSTRUCTION?
YES
UNSTACK CPU REGISTERS.
NO
EXECUTE INSTRUCTION.
Figure 9-9. Interrupt Processing
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
System Integration Module (SIM)
137
MODULE
INTERRUPT
IAB
RTI
ADDRESS
RTI
ADDR. + 1
RTI
OPCODE
IDB
SP – 4
IRRELEVANT
DATA
SP – 3
CCR
SP – 2
A
SP – 1
X
SP
PC
PC – 1
PC – 1
HIGH BYTE LOW BYTE
PC + 1
OPCODE
OPERAND
R/W
Figure 9-10. Interrupt Recovery Timing
9.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register) and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 9-11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE:
To maintain compatibility with the M68HC05, M6805, and M146805
Families, the H register is not pushed on the stack during interrupt entry.
If the interrupt service routine modifies the H register or uses the indexed
addressing mode, software should save the H register and then restore
it prior to exiting the routine.
Advance Information
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MC68HC708AS48 — Rev. 4.0
System Integration Module (SIM)
MOTOROLA
CLI
BACKGROUND
ROUTINE
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
INT2
A G R E E M E N T
PULH
RTI
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 9-11. Interrupt Recognition Example
9.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
System Integration Module (SIM)
139
N O N - D I S C L O S U R E
LDA #$FF
R E Q U I R E D
System Integration Module (SIM)
Program Exception Control
9.6.2 Reset
All reset sources always have higher priority than interrupts and cannot
be arbitrated.
9.6.3 Break Interrupts
The break module can stop normal program flow at a
software-programmable break point by asserting its break interrupt
output. (See Section 11. Break Module (Break).) The SIM puts the
CPU into the break state by forcing it to the SWI vector location. Refer
to the break interrupt subsection of each module to see how the break
state affects each module.
9.6.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select to protect flags from
being cleared by properly initializing the break clear flag enable bit
(BCFE) in the SIM break flag control register (SBFCR). (See 9.8.3 SIM
Break Flag Control Register.)
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a two-step clearing mechanism — for example, a read
of one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the
flag as usual.
Advance Information
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MC68HC708AS48 — Rev. 4.0
System Integration Module (SIM)
MOTOROLA
9.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-power
mode for standby situations. The SIM holds the CPU in a non-clocked
state. The operation of each of these modes is described below. Both
STOP and WAIT clear the interrupt mask (I) in the condition code
register, allowing interrupts to occur.
R E Q U I R E D
System Integration Module (SIM)
Low-Power Modes
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module
is active or inactive in wait mode. Some modules can be programmed to
be active in wait mode.
Wait mode also can be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM
break status register (SBSR). If the COP disable bit, COPD, in the
configuration (CONFIG, $001F) register is logic 0, then the computer
operating properly module (COP) is enabled and remains active in wait
mode.
IAB
IDB
WAIT ADDR
WAIT ADDR + 1
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 9-12. Wait Mode Entry Timing
MC68HC708AS48 — Rev. 4.0
MOTOROLA
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System Integration Module (SIM)
141
N O N - D I S C L O S U R E
In wait mode, the CPU clocks are inactive while one set of peripheral
clocks continues to run. Figure 9-12 shows the timing for wait mode
entry.
A G R E E M E N T
9.7.1 Wait Mode
R E Q U I R E D
System Integration Module (SIM)
Figure 9-13 and Figure 9-14 show the timing for wait recovery.
IAB
IDB
$A6
$A6
$6E0C
$A6
$01
$00FF
$00FE
$0B
$00FD
$00FC
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin or CPU interrupt or break interrupt
A G R E E M E N T
N O N - D I S C L O S U R E
$6E0B
Figure 9-13. Wait Recovery from Interrupt or Break
32
CYCLES
IAB
IDB
$6E0B
$A6
$A6
32
CYCLES
RSTVCTH
RSTVCTL
$A6
RST
CGMXCLK
Figure 9-14. Wait Recovery from Internal Reset
9.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the short stop recovery (SSREC) bit in
the CONFIG register ($001F). If SSREC is set, stop recovery is reduced
from the normal delay of 4096 CGMXCLK cycles down to 32. This is
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System Integration Module (SIM)
MOTOROLA
NOTE:
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 9-15 shows stop mode entry timing.
CPUSTOP
IAB
IDB
STOP ADDR
STOP ADDR + 1
PREVIOUS DATA
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
N O N - D I S C L O S U R E
Figure 9-15. Stop Mode Entry Timing
STOP RECOVERY PERIOD
CGMXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 9-16. Stop Mode Recovery from Interrupt or Break
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
System Integration Module (SIM)
A G R E E M E N T
ideal for applications using canned oscillators that do not require long
startup times from stop mode.
R E Q U I R E D
System Integration Module (SIM)
Low-Power Modes
143
9.8 SIM Registers
The SIM has three memory mapped registers.
9.8.1 SIM Break Status Register
The SIM break status register contains a flag to indicate that a break
caused an exit from stop mode or wait mode.
A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
Address:
$FE00
Bit 7
6
5
4
3
2
1
Bit 0
R
R
R
R
R
R
SBSW
R
Read:
Write:
Reset:
0
R
= Reserved
Figure 9-17. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
N O N - D I S C L O S U R E
This status bit is useful in applications requiring a return to wait mode
or stop mode after exiting from a break interrupt. Clear SBSW by
writing a logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode exited by break interrupt
0 = Stop mode or wait mode not exited by break interrupt
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MC68HC708AS48 — Rev. 4.0
System Integration Module (SIM)
MOTOROLA
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the break
; service routine software.
HIBYTE
EQU
5
LOBYTE
EQU
6
;
If not SBSW, do RTI
BRCLR
SBSW,SBSR, RETURN
; See if wait mode or stop mode was exited by
; break.
TST
LOBYTE,SP
;If RETURNLO is not zero,
BNE
DOLO
;then just decrement low byte.
DEC
HIBYTE,SP
;Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
;Point to WAIT/STOP opcode.
RETURN
PULH
RTI
N O N - D I S C L O S U R E
;Restore H register.
A G R E E M E N T
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing 0 to the SBSW bit
clears it.
R E Q U I R E D
System Integration Module (SIM)
SIM Registers
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
System Integration Module (SIM)
145
9.8.2 Reset Status Register
This read-only register contains flags to show reset sources. A power-on
reset sets the POR flag and clears all other flags. Reset sources other
than power-on reset do not clear all other flags.
Reading the reset status register clears all reset flags. Reset service can
read the reset status register to clear the register after power-on reset
and to determine the source of any subsequent reset.
NOTE:
A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
Only a read of the reset status register clears all reset flags. After
multiple resets from different sources without reading the register,
multiple flags remain set.
Address:
$FE01
Bit 7
6
5
4
3
2
1
Bit 0
Read:
POR
PIN
COP
ILOP
ILAD
0
LVI
0
Write:
R
R
R
R
R
R
R
R
Reset:
1
X
0
0
0
0
X
0
R
= Reserved
X = Indeterminate
N O N - D I S C L O S U R E
Figure 9-18. SIM Reset Status Register (SRSR)
POR — Power-On Reset Flag
1 = Power-on reset since last read of RSR
0 = Read of RSR since last power-on reset
PIN — External Reset Flag
1 = External reset since last read of RSR
0 = Power-on reset or read of RSR since last external reset
COP — COP Reset Flag
1 = COP reset since last read of RSR
0 = Power-on reset or read of RSR since last COP reset
ILOP — Illegal Opcode Reset Flag
1 = Illegal opcode reset since last read of RSR
0 = Power-on reset or read of RSR since last illegal opcode reset
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MOTOROLA
ILAD — Illegal Address Reset Flag
1 = Illegal address reset since last read of RSR
0 = Power-on reset or read of RSR since last illegal address reset
LVI — Low-Voltage Inhibit Reset Flag
1 = LVI reset since last read of RSR
0 = Power-on reset or read of RSR since last LVI reset
R E Q U I R E D
System Integration Module (SIM)
SIM Registers
The SIM break control register contains a bit that enables software to
clear status bits while the MCU is in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
BCFE
R
R
R
R
R
R
R
Read:
Write:
Reset:
0
R
= Reserved
A G R E E M E N T
9.8.3 SIM Break Flag Control Register
BCFE — Break Clear Flag Enable Bit
In some module registers, this read/write bit will enable software to
clear status bits by accessing status registers only while the MCU is
in a break state. To clear status bits during the break state, the BCFE
bit must be set.This operation is important for modules with status bits
which can be cleared only by being read. See the register
descriptions in each module for additional details.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
System Integration Module (SIM)
147
N O N - D I S C L O S U R E
Figure 9-19. SIM Break Flag Control Register (SBFCR)
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
System Integration Module (SIM)
Advance Information
148
MC68HC708AS48 — Rev. 4.0
System Integration Module (SIM)
MOTOROLA
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
10.4.1
Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
10.4.2
Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . .151
10.5
LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.6
LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
10.7.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
10.7.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
10.2 Introduction
This section describes the low-voltage inhibit module (LVI), which
monitors the voltage on the VDD pin and can force a reset when the VDD
voltage falls to the LVI trip voltage.
10.3 Features
Features of the LVI module include:
•
Programmable LVI reset
•
Programmable power consumption
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Low-Voltage Inhibit (LVI)
149
R E Q U I R E D
10.1 Contents
A G R E E M E N T
Section 10. Low-Voltage Inhibit (LVI)
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
10.4 Functional Description
Figure 10-1 shows the structure of the LVI module. The LVI module
contains a bandgap reference circuit and comparator. The LVI power
disable bit, LVIPWRD, disables the LVI from monitoring VDD voltage.
The LVI reset disable bit, LVIRSTD, disables the LVI module from
generating a reset when VDD falls below a voltage, VLVII. LVIPWRD and
LVIRSTD are in the CONFIG register ($001F) (see 5.4 Configuration
Register). Once an LVI reset occurs, the MCU remains in reset until VDD
rises above a voltage, VLVIR. The output of the comparator controls the
state of the LVIOUT flag in the LVI status register (LVISR).
A G R E E M E N T
R E Q U I R E D
Low-Voltage Inhibit (LVI)
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
LVISTOP
VDD
STOP INSTRUCTION
LVIPWRD
N O N - D I S C L O S U R E
FROM CONFIG
FROM CONFIG
LVIRSTD
LVI RESET
LOW VDD
DETECTOR
LVIOUT
Figure 10-1. LVI Module Block Diagram
Advance Information
150
MC68HC708AS48 — Rev. 4.0
Low-Voltage Inhibit (LVI)
MOTOROLA
Addr.
Register Name
Bit 7
$FE0F
Read: LVIOUT
LVI Status Register
Write:
R
(LVISR)
Reset:
0
R
6
5
4
0
0
0
R
R
R
0
0
0
3
2
LVISTOP LVILCK
0
0
1
Bit 0
0
0
R
R
0
0
= Reserved
Figure 10-2. LVI I/O Register Summary
R E Q U I R E D
Low-Voltage Inhibit (LVI)
Functional Description
In applications that can operate at VDD levels below the VLVII level,
software can monitor VDD by polling the LVIOUT bit. In the CONFIG
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
10.4.2 Forced Reset Operation
N O N - D I S C L O S U R E
In applications that require VDD to remain above the VLVII level, enabling
LVI resets allows the LVI module to reset the MCU when VDD falls to the
VLVII level. In the CONFIG register, the LVIPWRD and LVIRSTD bits
must be at logic 0 to enable the LVI module and to enable LVI resets.
A G R E E M E N T
10.4.1 Polled LVI Operation
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Low-Voltage Inhibit (LVI)
151
10.5 LVI Status Register
The LVI status register flags VDD voltages below the VLVII level.
Address:
Read:
A G R E E M E N T
R E Q U I R E D
Low-Voltage Inhibit (LVI)
$FE0F
Bit 7
6
5
4
LVIOUT
0
0
0
Write:
R
R
R
R
Reset:
0
0
0
0
R
3
2
LVISTOP
LVILCK
0
0
1
Bit 0
0
0
R
R
0
0
= Reserved
Figure 10-3. LVI Status Register (LVISR)
LVILCK — LVI Lock Bit
This read/write bit inhibits writing to the LVI status and control
register. When LVILCK is set, writing to the LVI status and control
register has no effect. The LVILCK bit can be cleared only by reset.
1 = LVISCR write-protected
0 = LVISCR not write-protected
LVISTOP — LVI Disable in Stop Mode Bit
N O N - D I S C L O S U R E
This read/write bit turns off the low-voltage inhibit module (LVI) in stop
mode when clear.
1 = LVI not disabled during stop mode
0 = LVI disabled during stop mode
NOTE:
To meet the stop mode IDD specification, LVISTOP must be at logic 0.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the
VLVII voltage. (See Table 10-1.) Reset clears the LVIOUT bit.
Table 10-1. LVIOUT Bit Indication
VDD
LVIOUT
VDD > VLVIR
0
VDD < VLVII
1
VLVII < VDD < VLVIR
Previous Value
Advance Information
152
MC68HC708AS48 — Rev. 4.0
Low-Voltage Inhibit (LVI)
MOTOROLA
10.7 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power standby
modes.
10.7.1 Wait Mode
With the LVIPWRD bit in the CONFIG register programmed to logic 0,
the LVI module is active after a WAIT instruction.
With the LVIRSTD bit in the CONFIG register programmed to logic 0, the
LVI module can generate a reset and bring the MCU out of wait mode.
10.7.2 Stop Mode
When the LVIPWRD bit in the CONFIG register is programmed to logic
0 and the LVISTOP bit in the LVISR register is at logic 1, the LVI module
remains active after a STOP instruction.
NOTE:
If the LVIPWRD bit is at logic 0, the LVISTOP bit must be at logic 0 to
meet the minimum stop mode IDD specification.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Low-Voltage Inhibit (LVI)
153
A G R E E M E N T
The LVI module does not generate interrupt requests.
N O N - D I S C L O S U R E
10.6 LVI Interrupts
R E Q U I R E D
Low-Voltage Inhibit (LVI)
LVI Interrupts
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Low-Voltage Inhibit (LVI)
Advance Information
154
MC68HC708AS48 — Rev. 4.0
Low-Voltage Inhibit (LVI)
MOTOROLA
11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.4.1
Flag Protection During Break Interrupts . . . . . . . . . . . . . .157
11.4.2
CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . .158
11.4.3
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .158
11.4.4
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .158
11.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
11.5.1
Break Status and Control Register . . . . . . . . . . . . . . . . . .159
11.5.2
Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . .160
Wait or Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
11.2 Introduction
This section describes the break module (break). The break module can
generate a break interrupt that stops normal program flow at a defined
address to enter a background program.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Break Module (Break)
155
N O N - D I S C L O S U R E
11.6
R E Q U I R E D
Section 11. Break Module (Break)
A G R E E M E N T
Advance Information — MC68HC708AS48
11.3 Features
Features of the break module include:
•
Accessible I/O registers during the break interrupt
•
CPU-generated break interrupts
•
Software-generated break interrupts
•
COP disabling during break interrupts
11.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal (BKPT)
to the SIM. The SIM then causes the CPU to load the instruction register
with a software interrupt instruction (SWI) after completion of the current
CPU instruction. The program counter vectors to $FFFC and $FFFD
($FEFC and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Break Module (Break)
•
A CPU-generated address (the address in the program counter)
matches the contents of the break address registers
•
Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 11-1 shows the structure of the break module.
Advance Information
156
MC68HC708AS48 — Rev. 4.0
Break Module (Break)
MOTOROLA
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB[15:0]
BKPT
TO SIM
CONTROL
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB[7:0]
Figure 11-1. Break Module Block Diagram
Addr.
$FE0C
$FE0D
Register Name
Read:
Break Address Register High
(BRKH) Write:
See page 160.
Reset:
Read:
Break Address Register Low
(BRKL) Write:
See page 160.
Reset:
$FE0E
Read:
Break Status and Control
Register (BRKSCR) Write:
See page 159.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
BRKE
BRKA
0
0
0
0
0
0
R
R
R
R
R
R
0
0
0
0
0
0
0
0
R
= Reserved
Figure 11-2. Break I/O Register Summary
11.4.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether module status
bits can be cleared during the break state. The BCFE bit in the SIM break
flag control register (SBFCR) enables software to clear status bits during
the break state. (See 9.8.3 SIM Break Flag Control Register and the
Break Interrupts subsection for each module.)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Break Module (Break)
157
N O N - D I S C L O S U R E
IAB[15:8]
A G R E E M E N T
R E Q U I R E D
Break Module (Break)
Functional Description
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Break Module (Break)
11.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•
Loading the instruction register with the SWI instruction
•
Loading the program counter with $FFFC–$FFFD
($FEFC–$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
11.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
11.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when VDD + VHI is present
on the RST pin. For VHI see 21.5 5.0 Volt DC Electrical
Characteristics.
11.5 Break Module Registers
Three registers control and monitor operation of the break module:
•
Break status and control register, BRKSCR
•
Break address register high, BRKH
•
Break address register low, BRKL
Advance Information
158
MC68HC708AS48 — Rev. 4.0
Break Module (Break)
MOTOROLA
The break status and control register contains break module enable and
status bits.
Address:
$FE0E
Bit 7
6
BRKE
BRKA
Read:
Write:
Reset:
0
R
0
5
4
3
2
1
Bit 0
0
0
0
0
0
0
R
R
R
R
R
R
0
0
0
0
0
0
= Reserved
Figure 11-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
A G R E E M E N T
11.5.1 Break Status and Control Register
R E Q U I R E D
Break Module (Break)
Break Module Registers
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Break Module (Break)
159
N O N - D I S C L O S U R E
BRKA — Break Active Bit
R E Q U I R E D
Break Module (Break)
11.5.2 Break Address Registers
The break address registers contain the high and low bytes of the
desired breakpoint address. Reset clears the break address registers.
Address:
$FE0C
Bit 7
6
5
4
3
2
1
Bit 0
BIT 15
BIT 13
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
0
0
0
0
0
0
0
0
Read:
N O N - D I S C L O S U R E
A G R E E M E N T
Write:
Reset:
Figure 11-4. Break Address Register (BRKH)
Address:
$FE0D
Bit 7
6
5
4
3
2
1
Bit 0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 11-5. Break Address Register (BRKL)
11.6 Wait or Stop Mode
The WAIT and STOP instructions put the MCU in low-power standby
modes.
A break interrupt causes exit from wait or stop mode and sets the SBSW
bit in the SIM break status register (see 9.8 SIM Registers).
Advance Information
160
MC68HC708AS48 — Rev. 4.0
Break Module (Break)
MOTOROLA
12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
12.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
12.4.1
Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .164
12.4.2
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
12.4.3
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
12.4.4
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
12.4.5
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12.4.6
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
R E Q U I R E D
Section 12. Monitor ROM (MON)
A G R E E M E N T
Advance Information — MC68HC708AS48
This section describes the monitor ROM (MON). The monitor ROM
allows complete testing of the MCU through a single-wire interface with
a host computer.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Monitor ROM (MON)
161
N O N - D I S C L O S U R E
12.2 Introduction
12.3 Features
Features of the monitor ROM include:
•
Normal user-mode pin functionality
•
One pin dedicated to serial communication between monitor ROM
and host computer
•
Standard mark/space non-return-to-zero (NRZ) communication
with host computer
•
4800 baud–28.8 kbaud communication with host computer
•
Execution of code in RAM or EPROM/OTPROM
•
(E)EPROM/OTPROM programming
12.4 Functional Description
Monitor ROM receives and executes commands from a host computer.
Figure 12-1 shows a sample circuit used to enter monitor mode and
communicate with a host computer via a standard RS-232 interface.
While simple monitor commands can access any memory address, the
MC68HC708AS48 has an EPROM/OTPROM security feature that
requires proper procedures to be followed before the EPROM/OTPROM
can be accessed. Therefore, access to the EPROM/OTPROM is denied
to unauthorized users of customer specified software.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Monitor ROM (MON)
In monitor mode, the MCU can execute host-computer code in RAM
while all MCU pins except PTA0 retain normal operating mode functions.
All communication between the host computer and the MCU is through
the PTA0 pin. A level-shifting and multiplexing interface is required
between PTA0 and the host computer. PTA0 is used in a wired-OR
configuration and requires a pullup resistor.
Advance Information
162
MC68HC708AS48 — Rev. 4.0
Monitor ROM (MON)
MOTOROLA
R E Q U I R E D
Monitor ROM (MON)
Functional Description
VDD
68HC08
10 kΩ
RST
0.1 µF
VDD + VHI
10 Ω
VDDA
A G R E E M E N T
IRQ1/VPP
VDDA/VDDAREF
CGMXFC
1
+
3
4
10 µF
0.1 µF
20
+
OSC1
20 pF
17
+
+
10 µF
18
2
19
DB-25
2
5
16
3
6
15
10 µF
X1
4.9152 MHz
10 MΩ
OSC2
VDD
20 pF
VSS
N O N - D I S C L O S U R E
10 µF
MC145407
VDD
VDD
0.1 µF
7
VDD
1
MC74HC125
2
3
6
5
4
7
NOTE: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4
Position B — Bus clock = CGMXCLK ÷ 2
VDD
14
10 kΩ
PTA0
PTC3
VDD
VDD
10 kΩ
A
(SEE
NOTE.)
10 kΩ
B
PTC0
PTC1
Figure 12-1. Monitor Mode Circuit
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Monitor ROM (MON)
163
12.4.1 Entering Monitor Mode
Table 12-1 shows the pin conditions for entering monitor mode.
PTC0 Pin
PTC1 Pin
PTA0 Pin
PTC3 Pin
IRQ/VPP Pin
Table 12-1. Mode Selection
A G R E E M E N T
R E Q U I R E D
Monitor ROM (MON)
VDD +
VHI(1)
1
0
1
1
Monitor
CGMXCLK
CGMVCLK
----------------------------- or ----------------------------2
2
CGMOUT
-------------------------2
VDD +
VHI(1)
1
0
1
0
Monitor
CGMXCLK
CGMOUT
-------------------------2
Mode
CGMOUT
Bus
Frequency
1. For VHI see 21.5 5.0 Volt DC Electrical Characteristics and 21.2 Maximum Ratings
Enter monitor mode by either
•
Executing a software interrupt instruction (SWI) or
•
Applying a logic 0 and then a logic 1 to the RST pin.
N O N - D I S C L O S U R E
The MCU sends a break signal (10 consecutive logic 0s) to the host
computer, indicating that it is ready to receive a command. The break
signal also provides a timing reference to allow the host to determine the
necessary baud rate.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as
VDD + VHI (see 21.5 5.0 Volt DC Electrical Characteristics) is applied
to either the IRQ/VPP pin or the VDD pin. (See Section 9. System
Integration Module (SIM) for more information on modes of operation.)
NOTE:
Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Advance Information
164
MC68HC708AS48 — Rev. 4.0
Monitor ROM (MON)
MOTOROLA
Table 12-2. Mode Differences
Functions
Modes
COP
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
User
Enabled
$FFFE
$FFFF
$FFFC
$FFFD
$FFFC
$FFFD
Monitor
Disabled(1)
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
1. If the high voltage (VDD + VHI) is removed from the IRQ/VPP pin while in monitor mode,
the SIM asserts its COP enable output. The COP is an option enabled or disabled by
the COPD bit in the configuration register. (See 21.5 5.0 Volt DC Electrical
Characteristics.)
12.4.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. (See Figure 12-2 and Figure 12-3.)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
N O N - D I S C L O S U R E
The data transmit and receive rate can be anywhere from 4800 baud to
28.8 kBaud. Transmit and receive baud rates must be identical.
NEXT
START
BIT
Figure 12-2. Monitor Data Format
$A5
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BREAK
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
STOP
BIT
NEXT
START
BIT
NEXT
START
BIT
Figure 12-3. Sample Monitor Waveforms
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Monitor ROM (MON)
A G R E E M E N T
Table 12-2 is a summary of the differences between user mode and
monitor mode.
R E Q U I R E D
Monitor ROM (MON)
Functional Description
165
12.4.3 Echoing
As shown in Figure 12-4, the monitor ROM immediately echoes each
received byte back to the PTA0 pin for error checking.
Any result of a command appears after the echo of the last byte of the
command.
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
ECHO
RESULT
Figure 12-4. Read Transaction
12.4.4 Break Signal
A start bit followed by nine low bits is a break signal. (See Figure 12-5.)
When the monitor receives a break signal, it drives the PTA0 pin high for
the duration of two bits before echoing the break signal.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Monitor ROM (MON)
MISSING STOP BIT
TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 12-5. Break Transaction
Advance Information
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MC68HC708AS48 — Rev. 4.0
Monitor ROM (MON)
MOTOROLA
R E Q U I R E D
Monitor ROM (MON)
Functional Description
12.4.5 Commands
•
READ, read memory
•
WRITE, write memory
•
IREAD, indexed read
•
IWRITE, indexed write
•
READSP, read stack pointer
•
RUN, run user program
A G R E E M E N T
The monitor ROM uses these commands:
A sequence of IREAD or IWRITE commands can access a block of
memory sequentially over the full 64-Kbyte memory map.
Description
Read byte from memory
Operand
Specifies 2-byte address in high byte:low byte order
Data Returned
Returns contents of specified address
Opcode
$4A
N O N - D I S C L O S U R E
Table 12-3. READ (Read Memory) Command
Command Sequence
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ECHO
ADDR. LOW
DATA
RESULT
MC68HC708AS48 — Rev. 4.0
MOTOROLA
ADDR. LOW
Advance Information
Monitor ROM (MON)
167
R E Q U I R E D
Monitor ROM (MON)
Table 12-4. WRITE (Write Memory) Command
Description
Write byte to memory
Operand
Specifies 2-byte address in high byte:low byte order; low byte followed by data byte
Data Returned
None
Opcode
$49
Command Sequence
A G R E E M E N T
SENT TO
MONITOR
WRITE
WRITE
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
DATA
ECHO
N O N - D I S C L O S U R E
Table 12-5. IREAD (Indexed Read) Command
Description
Read next 2 bytes in memory from last address accessed
Operand
Specifies 2-byte address in high byte:low byte order
Data Returned
Returns contents of next two addresses
Opcode
$1A
Command Sequence
SENT TO
MONITOR
IREAD
IREAD
DATA
RESULT
ECHO
Advance Information
168
DATA
MC68HC708AS48 — Rev. 4.0
Monitor ROM (MON)
MOTOROLA
R E Q U I R E D
Monitor ROM (MON)
Functional Description
Table 12-6. IWRITE (Indexed Write) Command
Description
Write to last address accessed + 1
Operand
Specifies single data byte
Data Returned
None
Opcode
$19
Command Sequence
IWRITE
IWRITE
DATA
A G R E E M E N T
SENT TO
MONITOR
DATA
ECHO
Description
Reads stack pointer
Operand
None
Data Returned
Returns stack pointer in high byte:low byte order
Opcode
$0C
N O N - D I S C L O S U R E
Table 12-7. READSP (Read Stack Pointer) Command
Command Sequence
SENT TO
MONITOR
READSP
READSP
SP HIGH
RESULT
ECHO
MC68HC708AS48 — Rev. 4.0
MOTOROLA
SP LOW
Advance Information
Monitor ROM (MON)
169
R E Q U I R E D
Monitor ROM (MON)
Table 12-8. RUN (Run User Program) Command
Description
Executes RTI instruction
Operand
None
Data Returned
None
Opcode
$28
Command Sequence
RUN
RUN
ECHO
12.4.6 Baud Rate
With a 4.9152-MHz crystal and the PTC3 pin at logic 1 during reset, data
is transferred between the monitor and host at 4800 baud. If the PTC3
pin is at logic 0 during reset, the monitor baud rate is 9600. When the
CGM output, CGMOUT, is driven by the PLL, the baud rate is
determined by the MUL[7:4] bits in the PLL programming register (PPG).
(See Section 8. Clock Generator Module (CGM).)
N O N - D I S C L O S U R E
A G R E E M E N T
SENT TO
MONITOR
Table 12-9. Monitor Baud Rate Selection
VCO Frequency Multiplier (N)
1
2
3
4
5
6
Monitor Baud Rate (4.9152 MHz)
4800
9600
14,400
19,200
24,000
28,800
Monitor Baud Rate (4.194 MHz)
4096
8192
12,288
16,384
20,480
24,576
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MC68HC708AS48 — Rev. 4.0
Monitor ROM (MON)
MOTOROLA
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.1
CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.2
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.3
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.4
Internal Reset Resources . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.5
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.6
COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.4.7
COPL (COP Long Timeout) . . . . . . . . . . . . . . . . . . . . . . .175
13.5
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.6
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.7
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
13.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
13.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
13.9
COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . .176
13.2 Introduction
This section describes the computer operating properly (COP) module,
a free-running counter that generates a reset if allowed to overflow. The
COP module helps software recover from runaway code. Prevent a COP
reset by periodically clearing the COP counter.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Computer Operating Properly (COP)
171
R E Q U I R E D
13.1 Contents
A G R E E M E N T
Section 13. Computer Operating Properly (COP)
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
13.3 Functional Description
Figure 13-1 shows the structure of the COP module.
SIM
CGMXCLK
N O N - D I S C L O S U R E
SIM RESET CIRCUIT
12-BIT SIM COUNTER
SIM RESET STATUS REGISTER
CLEAR BITS 12–4
CLEAR ALL BITS
A G R E E M E N T
R E Q U I R E D
Computer Operating Properly (COP)
STOP INSTRUCTION
INTERNAL RESET SOURCES(1)
RESET VECTOR FETCH
COPCTL WRITE
COP MODULE
COPEN (FROM SIM)
COPD (FROM CONFIG)
6-BIT COP COUNTER
RESET
CLEAR
COP COUNTER
COPCTL WRITE
COPL
NOTE:
1. See 9.4.2 Active Resets from Internal Sources.
Figure 13-1. COP Block Diagram
Addr.
$FFFF
Register Name
Bit 7
Read:
COP Control Register
Write:
(COPCTL)
Reset:
6
5
4
3
2
1
Bit 0
Low Byte of Reset Vector
Writing to $FFFF Clears COP Counter
Unaffected by Reset
Figure 13-2. COP I/O Register Summary
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Computer Operating Properly (COP)
MOTOROLA
COP timeout period = 8,176 or 262,128 / fosc
With a 4.9152-MHz crystal and the COPL bit in the CONFIG register
($001F) set to a logic 1, the COP timeout period is approximately
53.3 ms. Writing any value to location $FFFF before overflow occurs
clears the COP counter, clears bits 12 through 4 of the SIM counter, and
prevents reset. A CPU interrupt routine can be used to clear the COP.
NOTE:
The COP should be serviced as soon as possible out of reset and before
entering or after exiting stop mode to guarantee the maximum selected
amount of time before the first timeout.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR) (see 9.8.2 Reset Status
Register).
While the microcontroller is in monitor mode, the COP module is
disabled if the RST pin or the IRQ/VPP pin is held at VDD + VHI (see 21.5
5.0 Volt DC Electrical Characteristics). During a break state, VDD +
VHI on the RST pin disables the COP module.
NOTE:
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Computer Operating Properly (COP)
173
A G R E E M E N T
If not cleared by software, the COP counter overflows and generates an
asynchronous reset after 8,176 or 262,128 CGMXCLK cycles,
depending upon COPL bit in the CONFIG register ($001F) (See 5.4
Configuration Register.)
N O N - D I S C L O S U R E
The COP counter is a free-running 6-bit counter preceded by the 12-bit
system integration module (SIM) counter. COP timeouts are determined
strictly by the CGM crystal oscillator clock signal (CGMXCLK), not the
CGMOUT signal (see Figure 8-1. CGM Block Diagram).
R E Q U I R E D
Computer Operating Properly (COP)
Functional Description
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Computer Operating Properly (COP)
13.4 I/O Signals
The following paragraphs describe the signals shown in Figure 13-1.
13.4.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
13.4.2 STOP Instruction
The STOP instruction clears the SIM counter.
13.4.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 13.5 COP
Control Register) clears the COP counter and clears bits 12 through 4
of the SIM counter. Reading the COP control register returns the reset
vector.
13.4.4 Internal Reset Resources
An internal reset clears the SIM counter and the COP counter. (See
9.4.2 Active Resets from Internal Sources.)
13.4.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the SIM counter.
13.4.6 COPD (COP Disable)
The COPD bit reflects the state of the COP disable bit (COPD) in the
CONFIG register ($001F).This signal disables COP generated resets
when asserted. (See 5.4 Configuration Register.)
Advance Information
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MC68HC708AS48 — Rev. 4.0
Computer Operating Properly (COP)
MOTOROLA
13.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address:
$FFFF
Bit 7
6
5
4
3
Read:
Low Byte of Reset Vector
Write:
Clear COP Counter
Reset:
Unaffected by Reset
2
1
Bit 0
Figure 13-3. COP Control Register (COPCTL)
13.6 Interrupts
The COP does not generate CPU interrupt requests.
13.7 Monitor Mode
The COP is disabled in monitor mode when VDD + VHI (see 21.5 5.0 Volt
DC Electrical Characteristics) is present on the IRQ/VPP pin or on the
RST pin.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Computer Operating Properly (COP)
175
A G R E E M E N T
The COPL bit selects the state of the COP long timeout bit (COPL) in the
CONFIG register ($001F). Timeout periods can be 8,176 or 262,128
CGMXCLK cycles. (See 5.4 Configuration Register.)
N O N - D I S C L O S U R E
13.4.7 COPL (COP Long Timeout)
R E Q U I R E D
Computer Operating Properly (COP)
COP Control Register
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Computer Operating Properly (COP)
13.8 Low-Power Modes
The following subsections describe the low-power modes.
13.8.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP
reset during wait mode, periodically clear the COP counter in a CPU
interrupt routine.
NOTE:
If the COP is enabled in wait mode, it must be periodically refreshed.
13.8.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the SIM
counter. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
The STOP bit in the CONFIG register ($001F) (see 5.4 Configuration
Register) enables the STOP instruction. To prevent inadvertently
turning off the COP with a STOP instruction, disable the STOP
instruction by programming the STOP bit to logic 0.
13.9 COP Module During Break Interrupts
The COP is disabled during a break interrupt when VDD + VHI (see 21.5
5.0 Volt DC Electrical Characteristics) is present on the RST pin.
Advance Information
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MC68HC708AS48 — Rev. 4.0
Computer Operating Properly (COP)
MOTOROLA
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
14.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
14.5
IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
14.6
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .182
14.7
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .182
14.2 Introduction
This section describes the non-maskable external interrupt (IRQ/VPP)
input.
14.3 Features
Features include:
•
Dedicated external interrupt pin (IRQ/VPP)
•
Hysteresis buffer
•
Programmable edge-only or edge and level interrupt sensitivity
•
Automatic interrupt acknowledge
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
External Interrupt
177
R E Q U I R E D
14.1 Contents
A G R E E M E N T
Section 14. External Interrupt
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
14.4 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt
request. Figure 14-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ/VPP pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:
A G R E E M E N T
R E Q U I R E D
External Interrupt
•
Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector
fetch.
•
Software clear — Software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (ISCR). Writing a logic 1 to the ACK bit clears the
IRQ latch.
•
Reset — A reset automatically clears both interrupt latches.
N O N - D I S C L O S U R E
INTERNAL ADDRESS BUS
ACK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
IRQF
D
CLR
Q
SYNCHRONIZER
CK
IRQ/VPP
IRQ
INTERRUPT
REQUEST
IRQ
LATCH
IMASK
MODE
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 14-1. IRQ Block Diagram
Advance Information
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MC68HC708AS48 — Rev. 4.0
External Interrupt
MOTOROLA
Read:
IRQ Status and Control Register
(ISCR) Write:
See page 183.
Reset:
Bit 7
6
5
4
3
2
0
0
0
0
IRQF
0
R
R
R
R
R
ACK
0
0
0
0
0
0
R
1
Bit 0
IMASK
MODE
0
0
= Reserved
Figure 14-2. IRQ I/O Register Summary
The external interrupt pin is falling-edge triggered and is softwareconfigurable to be both falling-edge and low-level triggered. The MODE
bit in the ISCR controls the triggering sensitivity of the IRQ/VPP pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
•
Vector fetch or software clear
•
Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the ISCR masks all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK bit is clear.
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See Figure 14-3.)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
External Interrupt
179
A G R E E M E N T
$001A
Register Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
External Interrupt
Functional Description
R E Q U I R E D
External Interrupt
FROM RESET
YES
I BIT SET?
NO
A G R E E M E N T
INTERRUPT?
YES
NO
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
N O N - D I S C L O S U R E
NO
RTI
INSTRUCTION?
YES
UNSTACK CPU REGISTERS.
NO
EXECUTE INSTRUCTION.
Figure 14-3. IRQ Interrupt Flowchart
Advance Information
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External Interrupt
MOTOROLA
If the MODE bit is set, the IRQ/VPP pin is both falling-edge sensitive and
low-level sensitive. With MODE set, both of the following actions must
occur to clear the IRQ latch:
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK bit in the interrupt status and control register (ISCR). The
ACK bit is useful in applications that poll the IRQ/VPP pin and
require software to clear the IRQ latch. Writing to the ACK bit can
also prevent spurious interrupts due to noise. Setting ACK does
not affect subsequent transitions on the IRQ/VPP pin. A falling
edge on IRQ/VPP that occurs after writing to the ACK bit latches
another interrupt request. If the IRQ mask bit, IMASK, is clear, the
CPU loads the program counter with the vector address at
locations $FFFA and $FFFB.
•
Return of the IRQ/VPP pin to logic 1 — As long as the IRQ/VPP pin
is at logic 0, the IRQ latch remains set.
The vector fetch or software clear and the return of the IRQ/VPP pin to
logic 1 can occur in any order. The interrupt request remains pending as
long as the IRQ/VPP pin is at logic 0. A reset will clear the latch and the
MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ/VPP pin is falling-edge sensitive only.
With MODE clear, a vector fetch or software clear immediately clears the
IRQ latch.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
External Interrupt
181
A G R E E M E N T
A logic 0 on the IRQ/VPP pin can latch an interrupt request into the IRQ
latch. A vector fetch, software clear, or reset clears the IRQ latch.
N O N - D I S C L O S U R E
14.5 IRQ/VPP Pin
R E Q U I R E D
External Interrupt
IRQ/VPP Pin
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
External Interrupt
The IRQF bit in the ISCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ/VPP pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
14.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ interrupt
latch can be cleared during the break state. The BCFE bit in the SIM
break flag control register (SBFCR) enables software to clear the latches
during the break state. (See 9.8.3 SIM Break Flag Control Register.)
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
14.7 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR has these functions:
•
Shows the state of the IRQ interrupt flag
•
Clears the IRQ interrupt latch
•
Masks IRQ interrupt request
•
Controls triggering sensitivity of the IRQ/VPP interrupt pin
Advance Information
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MC68HC708AS48 — Rev. 4.0
External Interrupt
MOTOROLA
Bit 7
6
5
4
3
2
Read:
0
0
0
0
IRQF
0
Write:
R
R
R
R
R
ACK
Reset:
0
0
0
0
0
0
R
1
Bit 0
IMASK
MODE
0
0
= Reserved
Figure 14-4. IRQ Status and Control Register (ISCR)
IRQF — IRQ/VPP Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ/VPP interrupt pending
0 = IRQ/VPP interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always
reads as logic 0. Reset clears ACK.
IMASK —IRQ/VPP Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ/VPP interrupt
requests. Reset clears IMASK.
1 = IRQ/VPP interrupt requests disabled
0 = IRQ/VPP interrupt requests enabled
MODE — IRQ/VPP Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ/VPP
pin. Reset clears MODE.
1 = IRQ/VPP interrupt requests on falling edges and low levels
0 = IRQ/VPP interrupt requests on falling edges only
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
External Interrupt
183
A G R E E M E N T
$001A
N O N - D I S C L O S U R E
Address:
R E Q U I R E D
External Interrupt
IRQ Status and Control Register
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
External Interrupt
Advance Information
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MC68HC708AS48 — Rev. 4.0
External Interrupt
MOTOROLA
Section 15. Input/Output (I/O) Ports
15.1 Contents
15.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
15.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
15.3.2
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .189
15.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.4.2
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .192
15.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
15.5.1
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
15.5.2
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .195
15.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
15.6.1
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
15.6.2
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . .199
15.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
15.7.1
Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
15.7.2
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . .203
15.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
15.8.1
Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
15.8.2
Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . .206
15.9 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
15.9.1
Port G Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
15.9.2
Data Direction Register G . . . . . . . . . . . . . . . . . . . . . . . . .209
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
185
A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
N O N - D I S C L O S U R E
15.2
R E Q U I R E D
Advance Information — MC68HC708AS48
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Input/Output (I/O) Ports
15.2 Introduction
In the 52-PLCC package (MC68HC708AS48CFN), thirty-nine
bidirectional input/output (I/O) pins and one input-only pin form six
parallel ports. In the 64-QFP package (engineering samples), forty-five
bidirectional I/O pins and one input only pin form seven parallel ports. All
I/O pins are programmable as inputs or outputs.
NOTE:
Addr.
$0000
$0001
$0002
$0003
$0004
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Register Name
Read:
Port A Data Register
(PTA) Write:
See page 188.
Reset:
Read:
Port B Data Register
(PTB) Write:
See page 191.
Reset:
Read:
Port C Data Register
(PTC) Write:
See page 194.
Reset:
Read:
Port D Data Register
(PTD) Write:
See page 197.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTC2
PTC1
PTC0
PTD2
PTD1
PTD0
Unaffected by Reset
PTB7
PTB6
PTB5
PTB4
PTB3
Unaffected by Reset
0
0
R
R
PTC5
PTC4
PTC3
Unaffected by Reset
PTD7
PTD6
PTD5
PTD4
PTD3
Unaffected by Reset
Read:
Data Direction Register A
DDRA7
(DDRA) Write:
See page 189.
Reset:
0
R
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
= Reserved
Figure 15-1. I/O Port Register Summary
Advance Information
186
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
Read:
Data Direction Register B
DDRB7
(DDRB) Write:
See page 192.
Reset:
0
$0005
$0006
$0007
Read:
Data Direction Register C
MCLKEN
(DDRC) Write:
See page 195.
Reset:
0
Read:
Data Direction Register D
DDRD7
(DDRD) Write:
See page 199.
Reset:
0
Read:
Port E Data Register
(PTE) Write:
See page 201.
Reset:
$0008
Read:
Port F Data Register
(PTF) Write:
See page 205.
Reset:
$0009
Read:
Port G Data Register
(PTG) Write:
See page 208.
Reset:
$000A
PTE7
Read:
Data Direction Register F
(DDRF) Write:
See page 206.
Reset:
$000D
Read:
Data Direction Register G
(DDRG) Write:
See page 209.
Reset:
6
5
4
3
2
1
Bit 0
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD1
DDRD0
0
R
0
R
0
0
0
0
0
0
0
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
PTF2
PTF1
PTF0
PTG2
PTG1
PTG0
Unaffected by Reset
0
0
0
R
R
R
PTF4
PTF3
Unaffected by Reset
0
0
0
0
0
R
R
R
R
R
Unaffected by Reset
Read:
Data Direction Register E
DDRE7
(DDRE) Write:
See page 203.
Reset:
0
$000C
$000E
Bit 7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
0
0
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
DDRG2
DDRG1
DDRG0
R
R
R
R
R
0
0
0
0
0
0
0
0
R
= Reserved
Figure 15-1. I/O Port Register Summary (Continued)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
187
A G R E E M E N T
Register Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Input/Output (I/O) Ports
Introduction
15.3 Port A
Port A is an 8-bit, general-purpose, bidirectional I/O port.
15.3.1 Port A Data Register
The port A data register contains a data latch for each of the eight
port A pins.
A G R E E M E N T
R E Q U I R E D
Input/Output (I/O) Ports
Address:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Read:
Write:
Reset:
Unaffected by Reset
Figure 15-2. Port A Data Register (PTA)
PTA[7:0] — Port A Data Bits
N O N - D I S C L O S U R E
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
Advance Information
188
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
15.3.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
Address:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
R E Q U I R E D
Input/Output (I/O) Ports
Port A
Reset:
Figure 15-3. Data Direction Register A (DDRA)
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 15-4 shows the port A I/O logic.
READ DDRA ($0004)
INTERNAL DATA BUS
WRITE DDRA ($0004)
RESET
DDRAx
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
Figure 15-4. Port A I/O Circuit
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
189
N O N - D I S C L O S U R E
Write:
A G R E E M E N T
Read:
R E Q U I R E D
Input/Output (I/O) Ports
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-1 summarizes
the operation of the port A pins.
Table 15-1. Port A Pin Functions
A G R E E M E N T
DDRA
Bit
PTA
Bit
I/O Pin
Mode
Accesses
to DDRA
Accesses to PTA
Read/Write
Read
Write
0
X
Input, Hi-Z
DDRA[7:0]
Pin
PTA[7:0](1)
1
X
Output
DDRA[7:0]
PTA[7:0]
PTA[7:0]
N O N - D I S C L O S U R E
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Advance Information
190
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
15.4.1 Port B Data Register
The port B data register contains a data latch for each of the eight port
B pins.
Address:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
ATD2
ATD1
ATD0
Read:
Write:
Reset:
Alternate
Functions:
Unaffected by Reset
ATD7
ATD6
ATD5
ATD4
ATD3
Figure 15-5. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
ATD[7:0] — ADC Channels
PTB7/ATD7–PTB0/ATD0 are eight of the analog-to-digital converter
channels. The ADC channel select bits, CH[4:0], determine whether
the PTB7/ATD7–PTB0/ATD0 pins are ADC channels or
general-purpose I/O pins. If an ADC channel is selected and a read of
this corresponding bit in the port B data register occurs, the data will
be 0 if the data direction for this bit is programmed as an input.
Otherwise, the data will reflect the value in the data latch. (See
Section 19. Analog-to-Digital Converter (ADC).) Data direction
register B (DDRB) does not affect the data direction of port B pins that
are being used by the ADC. However, the DDRB bits always
determine whether reading port B returns to the states of the latches
or logic 0.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
191
A G R E E M E N T
Port B is an 8-bit special function port that shares all of its pins with the
analog-to-digital converter (ADC).
N O N - D I S C L O S U R E
15.4 Port B
R E Q U I R E D
Input/Output (I/O) Ports
Port B
R E Q U I R E D
Input/Output (I/O) Ports
15.4.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
Address:
$0005
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
A G R E E M E N T
Read:
Write:
Reset:
Figure 15-6. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
N O N - D I S C L O S U R E
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 15-7 shows the port B I/O logic.
READ DDRB ($0005)
INTERNAL DATA BUS
WRITE DDRB ($0005)
RESET
DDRBx
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 15-7. Port B I/O Circuit
Advance Information
192
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin, or a logic 0 if that particular bit is in use by
the ADC. The data latch can always be written, regardless of the state
of its data direction bit. Table 15-2 summarizes the operation of the port
B pins.
Table 15-2. Port B Pin Functions
PTB
Bit
Bit
selected
by ADC
I/O Pin
Mode
Accesses
to DDRB
Accesses to PTB
Read/Write
Read
Write
0
X
No
Input, Hi-Z
DDRB[7:0]
Pin
PTB[7:0](1)
1
X
No
Output
DDRB[7:0]
PTB[7:0]
PTB[7:0]
0
X
Yes
Input, Hi-Z
DDRB[7:0]
0
PTB[7:0](1)
1
X
Yes
Input, Hi-Z
DDRB[7:0]
PTB[7:0]
PTB[7:0]
N O N - D I S C L O S U R E
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
A G R E E M E N T
DDRB
Bit
R E Q U I R E D
Input/Output (I/O) Ports
Port B
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
193
15.5 Port C
Port C is a 6-bit, general-purpose, bidirectional I/O port that shares one
of its pins with the bus clock (MCLK).
15.5.1 Port C Data Register
The port C data register contains a data latch for each of the six port C
pins.
A G R E E M E N T
R E Q U I R E D
Input/Output (I/O) Ports
Address:
$0002
Bit 7
6
Read:
0
0
Write:
R
R
5
4
3
2
1
Bit 0
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
Reset:
Unaffected by Reset
R
= Reserved
Alternate
Functions:
MCLK
N O N - D I S C L O S U R E
Figure 15-8. Port C Data Register (PTC)
PTC[5:0] — Port C Data Bits
These read/write bits are software-programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.
NOTE:
PTC5 is available only in the 64-pin QFP package.
MCLK — T12 System Bus Clock Bit
The bus clock (MCLK) is driven out of PTC2 when enabled by the
MCLKEN bit in PTCDDR7.
Advance Information
194
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
15.5.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer
for the corresponding port C pin; a logic 0 disables the output buffer.
$0006
Bit 7
4
3
2
1
Bit 0
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
MCLKEN
Write:
Reset:
5
R
0
R
0
= Reserved
Figure 15-9. Data Direction Register C (DDRC)
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTC2. If
MCLK is enabled, PTC2 is under the control of MCLKEN. Reset
clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRC[5:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE:
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
NOTE:
DDRC is available only in the 64-pin QFP package.
Figure 15-10 shows the port C I/O logic.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
195
A G R E E M E N T
Read:
6
N O N - D I S C L O S U R E
Address:
R E Q U I R E D
Input/Output (I/O) Ports
Port C
R E Q U I R E D
Input/Output (I/O) Ports
READ DDRC ($0006)
INTERNAL DATA BUS
WRITE DDRC ($0006)
RESET
DDRCx
WRITE PTC ($0002)
PTCx
PTCx
A G R E E M E N T
READ PTC ($0002)
Figure 15-10. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx
data latch. When bit DDRCx is a logic 0, reading address $0002 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-3 summarizes
the operation of the port C pins.
Table 15-3. Port C Pin Functions
N O N - D I S C L O S U R E
DDRC
Bit
[7] = 0
PTC
Bit
I/O Pin
Mode
PTC2
Accesses
to DDRC
Accesses to PTC
Read/Write
Read
Write
Input, Hi-Z
DDRC[7]
0
PTC2
[7] = 1
PTC2
Output, MCLK
DDRC[7]
Data Latch
—
0
X
Input, Hi-Z
DDRC[5:0]
Pin
PTC[5:3, 1:0](1)
1
X
Output
DDRC[5:0]
PTC[5:0]
PTC[5:3, 1:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Advance Information
196
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
Port D is an 8-bit special function I/O port that shares all of its pins with
the analog-to-digital converter (ADC).
PTD2/ATD10 is an input-only port pin
15.6.1 Port D Data Register
The port D data register contains a data latch for seven of the eight port
D pins. Writes to PTD2 are not latched since it is an input-only port bit.
Address:
$0003
Bit 7
6
5
4
3
PTD7
PTD6
PTD5
PTD4
PTD3
Read:
1
Bit 0
PTD1
PTD0
ATD9
ATD8
PTD2
Write:
R
Reset:
Alternate
Functions:
2
Unaffected by Reset
ATD15
R
ATD14/
TCLK
ATD13
ATD12
ATD11
ATD10
= Reserved
Figure 15-11. Port D Data Register (PTD)
PTD[7:3, 1:0] — Port D Data Bits
PTD[7:3, 1:0] are read/write, software programmable bits. Data
direction of PTD[7:3, 1:0] pins are under the control of the
corresponding bit in data direction register D.
ATD[15:8] — ADC Channel Status Bits
PTD7/ATD15–PTD0/ATD8 are eight of the analog-to-digital converter
channels. The ADC channel select bits, CH[4:0], determine whether
the PTD7/ATD15–PTD0/ATD8 pins are ADC channels or
general-purpose I/O pins. If an ADC channel is selected and a read of
this corresponding bit in the port B data register occurs, the data will
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
197
N O N - D I S C L O S U R E
NOTE:
A G R E E M E N T
15.6 Port D
R E Q U I R E D
Input/Output (I/O) Ports
Port D
R E Q U I R E D
Input/Output (I/O) Ports
be 0 if the data direction for this bit is programmed as an input.
Otherwise, the data will reflect the value in the data latch. (See
Section 19. Analog-to-Digital Converter (ADC).)
NOTE:
PTD7/ATD15 is available only in the 64-pin QFP package
A G R E E M E N T
Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the ADC. However, the DDRD bits
always determine whether reading port D returns the states of the
latches or logic 0.
TCLK — Timer Clock Input Bit
The PTD6/ATD14/TCLK pin is the external clock input for the TIM.
The prescaler select bits, PS[2:0], select PTD6/ATD14/TCLK as the
TIM clock input. (See 16.9.1 TIM Status and Control Register.)
When not selected as the TIM clock, PTD6/ATD14/TCLK is available
for general-purpose I/O or as an ADC channel.
Do not use ADC channel ATD14 when using the PTD6/ATD14/TCLK pin
as the clock input for the TIM.
N O N - D I S C L O S U R E
NOTE:
Advance Information
198
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
15.6.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic 0 disables the output buffer.
$0007
Bit 7
6
5
4
3
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
Read:
1
Bit 0
DDRD1
DDRD0
0
0
0
R
0
0
R
= Reserved
0
0
0
0
A G R E E M E N T
Write:
Reset:
2
Figure 15-12. Data Direction Register D (DDRD)
DDRD[7:3, 1:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:3, 1:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
NOTE:
DDRD7 is available only in the 64-pin QFP package.
Figure 15-13 shows the port D I/O logic PTD[7:3, 1:0].
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
199
N O N - D I S C L O S U R E
Address:
R E Q U I R E D
Input/Output (I/O) Ports
Port D
R E Q U I R E D
Input/Output (I/O) Ports
READ DDRD ($0007)
INTERNAL DATA BUS
WRITE DDRD ($0007)
RESET
DDRDx
WRITE PTD ($0003)
PTDx
PTDx
N O N - D I S C L O S U R E
A G R E E M E N T
READ PTD ($0003)
Figure 15-13. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic 0, reading address $0003 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-4 summarizes
the operation of the port D pins.
Table 15-4. Port D Pin Functions
DDRD
Bit
PTD
Bit
Bit selected
by ADC
I/O Pin
Mode
0
X
No
1
X
0
1
Accesses to
DDRD
Accesses to PTD
Read/Write
Read
Write
Input, Hi-Z
DDRD[7:3, 1:0]
Pin
PTD[7:3, 1:0](1)
No
Output
DDRD[7:3, 1:0]
PTD[7:3, 1:0]
PTD[7:3, 1:0]
X
Yes
Input, Hi-Z
DDRD[7:3, 1:0]
0
PTD[7:3, 1:0](1)
X
Yes
Input, Hi-Z
DDRD[7:3, 1:0]
PTD[7:3, 1:0]
PTD[7:3, 1:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Advance Information
200
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
Port E is an 8-bit special function port that shares two of its pins with the
timer interface module (TIM), two of its pins with the serial
communications interface module (SCI), and four of its pins with the
serial peripheral interface module (SPI).
15.7.1 Port E Data Register
The port E data register contains a data latch for each of the eight port
E pins.
Address:
$0008
Bit 7
6
5
4
3
2
1
Bit 0
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
TCH0
RxD
TxD
Read:
Write:
Reset:
Alternate
Function:
Unaffected by Reset
SPSCK
MOSI
MISO
SS
TCH1
A G R E E M E N T
15.7 Port E
R E Q U I R E D
Input/Output (I/O) Ports
Port E
PTE[7:0] — Port E Data Bits
PTE[7:0] are read/write, software programmable bits. Data direction
of each port E pin is under the control of the corresponding bit in data
direction register E.
SPSCK — SPI Serial Clock Bit
The PTE7/SPSCK pin is the serial clock input of an SPI slave module
and serial clock output of an SPI master module. When the SPE bit is
clear, the PTE7/SPSCK pin is available for general-purpose I/O.
MOSI — Master Out/Slave In Bit
The PTE6/MOSI pin is the master out/slave in terminal of the SPI
module. When the SPE bit is clear, the PTE6/MOSI pin is available for
general-purpose I/O. (See 18.14.1 SPI Control Register.)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
201
N O N - D I S C L O S U R E
Figure 15-14. Port E Data Register (PTE)
R E Q U I R E D
Input/Output (I/O) Ports
MISO — Master In/Slave Out Bit
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. (See 18.14.1 SPI Control Register.)
SS — Slave Select Bit
A G R E E M E N T
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set and
MODFEN bit is low, the PTE4/SS pin is available for general-purpose
I/O. (See 18.13.4 SS (Slave Select).) When the SPI is enabled as a
slave, the DDRE4 bit in data direction register E (DDRE) has no effect
on the PTE4/SS pin.
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 15-5.)
TCH[1:0] — Timer Channel I/O Bits
N O N - D I S C L O S U R E
The PTE3/TCH1–PTE2/TCH0 pins are the TIM input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTE3/TCH1–PTE2/TCH0 pins are timer channel I/O pins
or general-purpose I/O pins. (See 16.9.4 TIM Channel Status and
Control Registers.)
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIM. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 15-5.)
RxD — SCI Receive Data Input Bit
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. (See 17.9.1
SCI Control Register 1.)
Advance Information
202
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. (See
17.9.1 SCI Control Register 1.)
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 15-5.)
15.7.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
Address:
$000C
Bit 7
6
5
4
3
2
1
Bit 0
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
0
0
0
0
0
0
0
0
Read:
A G R E E M E N T
TxD — SCI Transmit Data Output
R E Q U I R E D
Input/Output (I/O) Ports
Port E
Reset:
Figure 15-15. Data Direction Register E (DDRE)
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE[7:0], configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE:
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 15-16 shows the port E I/O logic.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
203
N O N - D I S C L O S U R E
Write:
R E Q U I R E D
Input/Output (I/O) Ports
READ DDRE ($000C)
INTERNAL DATA BUS
WRITE DDRE ($000C)
DDREx
RESET
WRITE PTE ($0008)
PTEx
PTEx
A G R E E M E N T
READ PTE ($0008)
Figure 15-16. Port E I/O Circuit
When bit DDREx is a logic 1, reading address $0008 reads the PTEx
data latch. When bit DDREx is a logic 0, reading address $0008 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-5 summarizes
the operation of the port E pins.
Table 15-5. Port E Pin Functions
N O N - D I S C L O S U R E
DDRE
Bit
PTE
Bit
I/O Pin
Mode
Accesses
to DDRE
Accesses to PTE
Read/Write
Read
Write
0
X
Input, Hi-Z
DDRE[7:0]
Pin
PTE[7:0](1)
1
X
Output
DDRE[7:0]
PTE[7:0]
PTE[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Advance Information
204
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
15.8.1 Port F Data Register
The port F data register contains a data latch for each of the five port F
pins.
Address:
$0009
Bit 7
6
5
Read:
0
0
0
Write:
R
R
R
Reset:
4
3
2
1
Bit 0
PTF4
PTF3
PTF2
PTF1
PTF0
TCH4
TCH3
TCH2
Unaffected by Reset
Alternate
Function:
TCH5
R
= Reserved
Figure 15-17. Port F Data Register (PTF)
PTF[4:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of
each port F pin is under the control of the corresponding bit in data
direction register F. Reset has no effect on PTF[4:0].
NOTE:
PTF4 is available only in the 64-pin QFP package.
TCH[5:2] — Timer Channel I/O Bits
The PTF3/TCH5–PTF0/TCH2 pins are the TIM input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTF3/TCH5–PTF0/TCH2 pins are timer channel I/O pins
or general-purpose I/O pins. (See 16.9.4 TIM Channel Status and
Control Registers.)
NOTE:
Data direction register F (DDRF) does not affect the data direction of port
F pins that are being used by the TIM. However, the DDRF bits always
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
205
A G R E E M E N T
Port F is a 5-bit special function port that shares four of its pins with the
timer interface module (TIM).
N O N - D I S C L O S U R E
15.8 Port F
R E Q U I R E D
Input/Output (I/O) Ports
Port F
determine whether reading port F returns the states of the latches or the
states of the pins. (See Table 15-6.)
15.8.2 Data Direction Register F
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic 1 to a DDRF bit enables the output buffer for
the corresponding port F pin; a logic 0 disables the output buffer.
A G R E E M E N T
R E Q U I R E D
Input/Output (I/O) Ports
Address:
$000D
Bit 7
6
5
Read:
0
0
0
Write:
R
R
R
Reset:
0
0
0
R
4
3
2
1
Bit 0
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
0
0
0
0
0
= Reserved
Figure 15-18. Data Direction Register F (DDRF)
DDRF[4:0] — Data Direction Register F Bits
N O N - D I S C L O S U R E
These read/write bits control port F data direction. Reset clears
DDRF[4:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE:
DDRF4 is available only in the 64-pin QFP package.
NOTE:
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 15-19 shows the port F I/O logic.
Advance Information
206
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
DDRFx
RESET
WRITE PTF ($0009)
PTFx
PTFx
READ PTF ($0009)
Figure 15-19. Port F I/O Circuit
When bit DDRFx is a logic 1, reading address $0009 reads the PTFx
data latch. When bit DDRFx is a logic 0, reading address $0009 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-6 summarizes
the operation of the port F pins.
Table 15-6. Port F Pin Functions
DDRF
Bit
PTF
Bit
I/O Pin
Mode
Accesses
to DDRF
Accesses to PTF
Read/Write
Read
Write
0
X
Input, Hi-Z
DDRF[4:0]
Pin
PTF[4:0](1)
1
X
Output
DDRF[4:0]
PTF[3:0]
PTF[4:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
207
A G R E E M E N T
INTERNAL DATA BUS
WRITE DDRF ($000D)
N O N - D I S C L O S U R E
READ DDRF ($000D)
R E Q U I R E D
Input/Output (I/O) Ports
Port F
15.9 Port G
Port G is a 3-bit general-purpose I/O port.
NOTE:
Port G is available only in the 64-pin QFP package
15.9.1 Port G Data Register
The port G data register contains a data latch for each of the three port
G pins.
A G R E E M E N T
R E Q U I R E D
Input/Output (I/O) Ports
Address:
$000A
Bit 7
6
5
4
3
Read:
0
0
0
0
0
Write:
R
R
R
R
R
Reset:
2
1
Bit 0
PTG2
PTG1
PTG0
Unaffected by Reset
R
= Reserved
Figure 15-20. Port G Data Register (PTG)
PTG[2:0] — Port G Data Bits
N O N - D I S C L O S U R E
These read/write bits are software programmable. Data direction of
each port G pin is under the control of the corresponding bit in data
direction register G. Reset has no effect on PTG [2:0].
Advance Information
208
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
15.9.2 Data Direction Register G
Data direction register G determines whether each port G pin is an input
or an output. Writing a logic 1 to a DDRG bit enables the output buffer
for the corresponding port G pin; a logic 0 disables the output buffer.
$000E
6
5
4
3
Read:
0
0
0
0
0
Write:
R
R
R
R
R
Reset:
0
0
0
0
0
R
2
1
Bit 0
DDRG2
DDRG1
DDRG0
0
0
0
A G R E E M E N T
Bit 7
= Reserved
Figure 15-21. Data Direction Register G (DDRG)
DDRG[2:0] — Data Direction Register G Bits
These read/write bits control port G data direction. Reset clears
DDRG[2:0], configuring all port G pins as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
NOTE:
Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Figure 15-19 shows the port G I/O logic.
READ DDRG ($000E)
INTERNAL DATA BUS
WRITE DDRG ($000E)
RESET
DDRGx
WRITE PTG ($000A)
PTGx
PTGx
READ PTG ($000A)
Figure 15-22. Port G I/O Circuit
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Input/Output (I/O) Ports
209
N O N - D I S C L O S U R E
Address:
R E Q U I R E D
Input/Output (I/O) Ports
Port G
R E Q U I R E D
Input/Output (I/O) Ports
When bit DDRGx is a logic 1, reading address $000A reads the PTGx
data latch. When bit DDRGx is a logic 0, reading address $000A reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-7 summarizes
the operation of the port G pins.
Table 15-7. Port G Pin Functions
A G R E E M E N T
DDRG
Bit
PTG
Bit
I/O Pin
Mode
Accesses
to DDRG
Accesses to PTG
Read/Write
Read
Write
0
X
Input, Hi-Z
DDRG[2:0]
Pin
PTG[2:0](1)
1
X
Output
DDRG[2:0]
PTG[2:0]
PTG[2:0]
N O N - D I S C L O S U R E
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Advance Information
210
MC68HC708AS48 — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
16.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
16.4.1
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . .216
16.4.2
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
16.4.3
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
16.4.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .218
16.4.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .219
16.4.4
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . .220
16.4.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .221
16.4.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .222
16.4.4.3
PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
16.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
16.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
16.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
16.7
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .226
16.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
16.8.1
TIM Clock Pin (PTD6/ATD14/TCLK) . . . . . . . . . . . . . . . . .227
16.8.2
TIM Channel I/O Pins (PTF3/TCH5–PTF0/TCH2,
PTE3/TCH1–PTE2/TCH0) . . . . . . . . . . . . . . . . . . . . . .227
16.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
16.9.1
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .228
16.9.2
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .231
16.9.3
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .232
16.9.4
TIM Channel Status and Control Registers. . . . . . . . . . . .233
16.9.5
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .238
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Timer Interface (TIM)
211
R E Q U I R E D
16.1 Contents
A G R E E M E N T
Section 16. Timer Interface (TIM)
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
R E Q U I R E D
Timer Interface (TIM)
16.2 Introduction
This section describes the timer interface module (TIM6). The TIM is a
6-channel timer that provides a timing reference with input capture,
output compare, and pulse-width-modulation functions. Figure 16-1 is a
block diagram of the TIM.
A G R E E M E N T
16.3 Features
Features of the TIM include:
•
Six input capture/output compare channels
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
•
Buffered and unbuffered pulse width modulation (PWM) signal
generation
•
Programmable TIM clock input
– 7-frequency internal bus clock prescaler selection
N O N - D I S C L O S U R E
– External TIM clock input (4-MHz maximum frequency)
•
Free-running or modulo up-count operation
•
Toggle any channel pin on overflow
•
TIM counter stop and reset bits
Advance Information
212
MC68HC708AS48 — Rev. 4.0
Timer Interface (TIM)
MOTOROLA
R E Q U I R E D
Timer Interface (TIM)
Features
TCLK
PTD6/ATD14/TCLK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
PS2
TRST
PS1
PS0
16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
ELS0B
ELS0A
TOV0
CH0MAX
16-BIT COMPARATOR
TCH0H:TCH0L
CH0F
16-BIT LATCH
MS0A
CHANNEL 1
ELS1B
MS0B
ELS1A
TOV1
CH1MAX
16-BIT COMPARATOR
TCH1H:TCH1L
CH0IE
CH1F
16-BIT LATCH
CH1IE
MS1A
CHANNEL 2
ELS2B
ELS2A
TOV2
CH2MAX
16-BIT COMPARATOR
TCH2H:TCH2L
CH2F
16-BIT LATCH
MS2A
CHANNEL 3
ELS3B
MS2B
ELS3A
TOV3
CH3MAX
16-BIT COMPARATOR
TCH3H:TCH3L
CH2IE
CH3F
16-BIT LATCH
CH3IE
MS3A
CHANNEL 4
ELS4B
ELS4A
TOV4
CH5MAX
16-BIT COMPARATOR
TCH4H:TCH4L
CH4F
16-BIT LATCH
MS4A
CHANNEL 5
ELS5B
MS4B
ELS5A
TOV5
CH5MAX
16-BIT COMPARATOR
TCH5H:TCH5L
CH4IE
CH5F
16-BIT LATCH
MS5A
CH5IE
PTE2
LOGIC
PTE2/TCH0
INTERRUPT
LOGIC
PTE3
LOGIC
PTE3/TCH1
INTERRUPT
LOGIC
PTF0
LOGIC
PTF0/TCH2
INTERRUPT
LOGIC
PTF1
LOGIC
N O N - D I S C L O S U R E
CHANNEL 0
A G R E E M E N T
TMODH:TMODL
PTF1/TCH3
INTERRUPT
LOGIC
PTF2
LOGIC
PTF2/TCH4
INTERRUPT
LOGIC
PTF3
LOGIC
PTF3/TCH5
INTERRUPT
LOGIC
Figure 16-1. TIM Block Diagram
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Timer Interface (TIM)
213
R E Q U I R E D
Timer Interface (TIM)
Addr.
$0020
$0022
N O N - D I S C L O S U R E
A G R E E M E N T
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
Register Name
TIM Status and Control Read:
Register (TSC) Write:
See page 229. Reset:
TIM Counter Register High Read:
(TCNTH) Write:
See page 231. Reset:
TIM Counter Register Low Read:
(TCNTL) Write:
See page 231. Reset:
TIM Modulo Register High Read:
(TMODH) Write:
See page 232. Reset:
TIM Modulo Register Low Read:
(TMODL) Write:
See page 232. Reset:
TIM Channel 0 Status and Read:
Control Register (TSC0) Write:
See page 233. Reset:
TIM Channel 0 Register High Read:
(TCH0H) Write:
See page 239. Reset:
TIM Channel 0 Register Low Read:
(TCH0L) Write:
See page 239. Reset:
TIM Channel 1 Status and Read:
Control Register (TSC1) Write:
See page 233. Reset:
TIM Channel 1 Register High Read:
(TCH1H) Write:
See page 239. Reset:
TIM Channel 1 Register Low Read:
(TCH1L) Write:
See page 239. Reset:
TIM Channel 2 Status and Read:
Control Register (TSC2) Write:
See page 233. Reset:
Bit 7
TOF
0
0
Bit 15
R
0
Bit 7
R
0
6
5
1
13
R
0
5
R
0
4
0
TRST
0
12
R
0
4
R
0
3
0
R
0
11
R
0
3
R
0
2
1
Bit 0
TOIE
TSTOP
PS2
PS1
PS0
0
14
R
0
6
R
0
0
10
R
0
2
R
0
0
9
R
0
1
R
0
0
Bit 8
R
0
Bit 0
R
0
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
1
CH0F
0
0
1
1
1
1
1
1
1
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH1F
0
0
Bit 15
0
0
R
0
14
13
CH1IE
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH2F
0
0
R
CH2IE
MS2B
0
0
= Reserved
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
0
0
0
0
0
Figure 16-2. TIM I/O Register Summary
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MOTOROLA
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
TIM Channel 2 Register High Read:
(TCH2H) Write:
See page 239. Reset:
TIM Channel 2 Register Low Read:
(TCH2L) Write:
See page 239. Reset:
TIM Channel 3 Status and Read:
Control Register (TSC3) Write:
See page 233. Reset:
TIM Channel 3 Register High Read:
(TCH3H) Write:
See page 239.
Reset:
TIM Channel 3 Register Low Read:
(TCH3L) Write:
See page 239. Reset:
TIM Channel 4 Status and Read:
Control Register (TSC4) Write:
See page 233. Reset:
TIM Channel 4 Register High Read:
(TCH4H) Write:
See page 239. Reset:
TIM Channel 4 Register Low Read:
(TCH4L) Write:
See page 239. Reset:
TIM Channel 5 Status and Read:
Control Register (TSC5) Write:
See page 233. Reset:
TIM Channel 5 Register High Read:
(TCH5H) Write:
See page 239. Reset:
TIM Channel 5 Register Low Read:
(TCH5L) Write:
See page 239. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH3F
0
0
Bit 15
0
0
R
0
14
13
CH3IE
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
0
0
0
0
0
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH4F
0
0
Bit 15
CH4IE
MS4B
MS4A
ELS4B
ELS4A
TOV4
CH4MAX
0
0
0
0
0
0
0
14
13
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
CH5F
0
0
Bit 15
0
0
R
0
14
13
CH5IE
MS5A
ELS5B
ELS5A
TOV5
CH5MAX
0
0
0
0
0
12
11
10
9
Bit 8
2
1
Bit 0
Indeterminate after Reset
Bit 7
6
5
4
3
Indeterminate after Reset
R
= Reserved
Figure 16-2. TIM I/O Register Summary (Continued)
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215
A G R E E M E N T
$002D
Register Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Timer Interface (TIM)
Features
A G R E E M E N T
R E Q U I R E D
Timer Interface (TIM)
16.4 Functional Description
Figure 16-1 shows the TIM structure. The central component of the TIM
is the 16-bit TIM counter that can operate as a free-running counter or a
modulo up-counter. The TIM counter provides the timing reference for
the input capture and output compare functions. The TIM counter
modulo registers, TMODH–TMODL, control the modulo value of the TIM
counter. Software can read the TIM counter value at any time without
affecting the counting sequence.
The six TIM channels are programmable independently as input capture
or output compare channels.
16.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, PTD6/ATD14/TCLK. The prescaler generates seven
clock rates from the internal bus clock. The prescaler select bits, PS[2:0],
in the TIM status and control register select the TIM clock source.
N O N - D I S C L O S U R E
16.4.2 Input Capture
An input capture function has three basic parts: edge select logic, an
input capture latch, and a 16-bit counter. Two 8-bit registers, which make
up the 16-bit input capture register, are used to latch the value of the
free-running counter after the corresponding input capture edge detector
senses a defined transition. The polarity of the active edge is
programmable. The level transition which triggers the counter transfer is
defined by the corresponding input edge bits (ELSxB and ELSxA in
TSC0 through TSC5 control registers with x referring to the active
channel number). When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. Input captures can generate
TIM CPU interrupt requests. Software can determine that an input
capture event has occurred by enabling input capture interrupts or by
polling the status flag bit.
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MOTOROLA
By recording the times for successive edges on an incoming signal,
software can determine the period and/or pulse width of the signal. To
measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are
captured. Software should track the overflows at the 16-bit module
counter to extend its range.
Another use for the input capture function is to establish a time
reference. In this case, an input capture function is used in conjunction
with an output compare function. For example, to activate an output
signal a specified number of clock cycles after detecting an input event
(edge), use the input capture function to record the time at which the
edge occurred. A number corresponding to the desired delay is added
to this captured value and stored to an output compare register (see
16.9.5 TIM Channel Registers). Because both input captures and
output compares are referenced to the same 16-bit modulo counter, the
delay can be controlled to the resolution of the counter independent of
software latencies.
Reset does not affect the contents of the input capture register.
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217
A G R E E M E N T
The free-running counter contents are transferred to the TIM channel
status and control register (TSC0–TSC5, see 16.9.4 TIM Channel
Status and Control Registers) on each proper signal transition
regardless of whether the TIM channel flag (CH0F–CH5F in
TSC0–TSC5 registers) is set or clear. When the status flag is set, a CPU
interrupt is generated if enabled. The value of the count latched or
“captured” is the time of the event. Because this value is stored in the
input capture register when the actual event occurs, user software can
respond to this event at a later time and determine the actual time of the
event. However, this must be done prior to another input capture on the
same pin; otherwise, the previous time value will be lost.
N O N - D I S C L O S U R E
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization.
R E Q U I R E D
Timer Interface (TIM)
Functional Description
R E Q U I R E D
Timer Interface (TIM)
16.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests.
A G R E E M E N T
16.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare
pulses as described in 16.4.3 Output Compare. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
N O N - D I S C L O S U R E
An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.
Use these methods to synchronize unbuffered changes in the output
compare value on channel x:
•
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
•
When changing to a larger output compare value, enable channel
x TIM overflow interrupts and write the new value in the TIM
overflow interrupt routine. The TIM overflow interrupt occurs at the
end of the current counter overflow period. Writing a larger value
in an output compare interrupt routine (at the end of the current
pulse) could cause two output compares to occur in the same
counter overflow period.
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MOTOROLA
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
channel 0 registers initially controls the output on the PTE2/TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1
registers to synchronously control the output after the TIM overflows. At
each subsequent overflow, the TIM channel registers (0 or 1) that control
the output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
PTE2/TCH0, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare
channel whose output appears on the PTF0/TCH2 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS2B bit in TIM channel 2 status and control register (TSC2)
links channel 2 and channel 3. The output compare value in the TIM
channel 2 registers initially controls the output on the PTF0/TCH2 pin.
Writing to the TIM channel 3 registers enables the TIM channel 3
registers to synchronously control the output after the TIM overflows. At
each subsequent overflow, the TIM channel registers (2 or 3) that control
the output are the ones written to last. TSC2 controls and monitors the
buffered output compare function, and TIM channel 3 status and control
register (TSC3) is unused. While the MS2B bit is set, the channel 3 pin,
PTF1/TCH3, is available as a general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered output compare
channel whose output appears on the PTF2/TCH4 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS4B bit in TIM channel 4 status and control register (TSC4)
links channel 4 and channel 5. The output compare value in the TIM
channel 4 registers initially controls the output on the PTF2/TCH4 pin.
Writing to the TIM channel 5 registers enables the TIM channel 5
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219
A G R E E M E N T
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTE2/TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
N O N - D I S C L O S U R E
16.4.3.2 Buffered Output Compare
R E Q U I R E D
Timer Interface (TIM)
Functional Description
registers to synchronously control the output after the TIM overflows. At
each subsequent overflow, the TIM channel registers (4 or 5) that control
the output are the ones written to last. TSC4 controls and monitors the
buffered output compare function, and TIM channel 5 status and control
register (TSC5) is unused. While the MS4B bit is set, the channel 5 pin,
PTF3/TCH5, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
16.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare
channel, the TIM can generate a PWM signal. The value in the TIM
counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM
counter modulo registers. The time between overflows is the period of
the PWM signal.
As Figure 16-3 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIM to set the pin if the state of the PWM
pulse is logic 0.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Timer Interface (TIM)
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 16-3. PWM Period and Pulse Width
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MOTOROLA
16.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as
described in 16.4.4 Pulse Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
Use these methods to synchronize unbuffered changes in the PWM
pulse width on channel x:
•
When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
•
When changing to a longer pulse width, enable channel x TIM
overflow interrupts and write the new value in the TIM overflow
interrupt routine. The TIM overflow interrupt occurs at the end of
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A G R E E M E N T
The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256
increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.
N O N - D I S C L O S U R E
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000 (see 16.9.1 TIM Status and Control Register).
R E Q U I R E D
Timer Interface (TIM)
Functional Description
the current PWM period. Writing a larger value in an output
compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
NOTE:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
16.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the PTE2/TCH0 pin. The TIM channel registers of the
linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the PTE2/TCH0 pin. Writing to the TIM
channel 1 registers enables the TIM channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIM channel registers (0 or 1)
that control the pulse width are the ones written to last. TSC0 controls
and monitors the buffered PWM function, and TIM channel 1 status and
control register (TSC1) is unused. While the MS0B bit is set, the channel
1 pin, PTE3/TCH1, is available as a general-purpose I/O pin.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Timer Interface (TIM)
Channels 2 and 3 can be linked to form a buffered PWM channel whose
output appears on the PTF0/TCH2 pin. The TIM channel registers of the
linked pair alternately control the pulse width of the output.
Setting the MS2B bit in TIM channel 2 status and control register (TSC2)
links channel 2 and channel 3. The TIM channel 2 registers initially
control the pulse width on the PTF0/TCH2 pin. Writing to the TIM
channel 3 registers enables the TIM channel 3 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIM channel registers (2 or 3)
that control the pulse width are the ones written to last. TSC2 controls
and monitors the buffered PWM function, and TIM channel 3 status and
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MOTOROLA
Channels 4 and 5 can be linked to form a buffered PWM channel whose
output appears on the PTF2/TCH4 pin. The TIM channel registers of the
linked pair alternately control the pulse width of the output.
Setting the MS4B bit in TIM channel 4 status and control register (TSC4)
links channel 4 and channel 5. The TIM channel 4 registers initially
control the pulse width on the PTF2/TCH4 pin. Writing to the TIM
channel 5 registers enables the TIM channel 5 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIM channel registers (4 or 5)
that control the pulse width are the ones written to last. TSC4 controls
and monitors the buffered PWM function, and TIM channel 5 status and
control register (TSC5) is unused. While the MS4B bit is set, the channel
5 pin, PTF3/TCH5, is available as a general-purpose I/O pin.
NOTE:
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
A G R E E M E N T
control register (TSC3) is unused. While the MS2B bit is set, the channel
3 pin, PTF1/TCH3, is available as a general-purpose I/O pin.
R E Q U I R E D
Timer Interface (TIM)
Functional Description
To ensure correct operation when generating unbuffered or buffered
PWM signals, use this initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the
value for the required PWM period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for
the required pulse width.
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N O N - D I S C L O S U R E
16.4.4.3 PWM Initialization
R E Q U I R E D
Timer Interface (TIM)
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB–MSxA. (See Table 16-2.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
A G R E E M E N T
c.
NOTE:
Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See Table 16-2.)
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
N O N - D I S C L O S U R E
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H–TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels. MS0B
takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered
PWM operation. The TIM channel 2 registers (TCH2H–TCH2L) initially
control the PWM output. TIM status control register 2 (TSCR2) controls
and monitors the PWM signal from the linked channels. MS2B takes
priority over MS2A.
Setting MS4B links channels 4 and 5 and configures them for buffered
PWM operation. The TIM channel 4 registers (TCH4H–TCH4L) initially
control the PWM output. TIM status control register 4 (TSCR4) controls
and monitors the PWM signal from the linked channels. MS4B takes
priority over MS4A.
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MOTOROLA
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. (See 16.9.4 TIM
Channel Status and Control Registers.)
R E Q U I R E D
Timer Interface (TIM)
Interrupts
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value rolls over to $0000 after matching the value in the
TIM counter modulo registers. The TIM overflow interrupt enable
bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
•
TIM channel flags (CH5F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
16.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby
modes.
16.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait
mode, the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
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225
N O N - D I S C L O S U R E
These TIM sources can generate interrupt requests:
A G R E E M E N T
16.5 Interrupts
R E Q U I R E D
Timer Interface (TIM)
16.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIM
counter. TIM operation resumes when the MCU exits stop mode.
16.7 TIM During Break Interrupts
A G R E E M E N T
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 9.8.3 SIM Break Flag Control
Register.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
N O N - D I S C L O S U R E
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
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MOTOROLA
16.8 I/O Signals
Port D shares one of its pins with the TIM. Port E shares two of its pins
with the TIM and port F shares four of its pins with the TIM.
PTD6/ATD14/TCLK is an external clock input to the TIM prescaler. The
six TIM channel I/O pins are PTE2/TCH0, PTE3/TCH1, PTF0/TCH2,
PTF1/TCH3, PTF2/TCH4, and PTF3/TCH5.
R E Q U I R E D
Timer Interface (TIM)
I/O Signals
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD6/ATD14/TCLK is available as a general-purpose I/O pin or ADC
channel when not used as the TIM clock input. When the
PTD6/ATD14/TCLK pin is the TIM clock input, it is an input regardless of
the state of the DDRD6 bit in data direction register D.
16.8.2 TIM Channel I/O Pins (PTF3/TCH5–PTF0/TCH2, PTE3/TCH1–PTE2/TCH0)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE2/TCH0, PTE6/TCH2, and
PTF2/TCH4 can be configured as buffered output compare or buffered
PWM pins.
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N O N - D I S C L O S U R E
PTD6/ATD14/TCLK is an external clock input that can be the clock
source for the TIM counter instead of the prescaled internal bus clock.
Select the PTD6/ATD14/TCLK input by writing logic 1s to the three
prescaler select bits, PS[2:0]. (See 16.9.1 TIM Status and Control
Register.) The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is:
1
------------------------------------- + tSU
bus frequency
A G R E E M E N T
16.8.1 TIM Clock Pin (PTD6/ATD14/TCLK)
16.9 I/O Registers
These I/O registers control and monitor TIM operation:
•
TIM status and control register, TSC
•
TIM control registers, TCNTH–TCNTL
•
TIM counter modulo registers, TMODH–TMODL
•
TIM channel status and control registers, TSC0, TSC1, TSC2,
TSC3, TSC4, and TSC5
•
TIM channel registers, TCH0H–TCH0L, TCH1H–TCH1L,
TCH2H–TCH2L, TCH3H–TCH3L, TCH4H–TCH4L, and
TCH5H–TCH5L
16.9.1 TIM Status and Control Register
The TIM status and control register:
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Timer Interface (TIM)
•
Enables TIM overflow interrupts
•
Flags TIM overflows
•
Stops the TIM counter
•
Resets the TIM counter
•
Prescales the TIM counter clock
Advance Information
228
MC68HC708AS48 — Rev. 4.0
Timer Interface (TIM)
MOTOROLA
Bit 7
Read:
6
5
TOIE
TSTOP
4
3
0
0
TRST
R
0
0
TOF
Write:
0
Reset:
0
R
0
1
2
1
Bit 0
PS2
PS1
PS0
0
0
0
= Reserved
Figure 16-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter resets to $0000 after
reaching the modulo value programmed in the TIM counter modulo
registers. Clear TOF by reading the TIM status and control register
when TOF is set and then writing a logic 0 to TOF. If another TIM
overflow occurs before the clearing sequence is complete, then
writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value.
0 = TIM counter has not reached modulo value.
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Timer Interface (TIM)
229
A G R E E M E N T
$0020
N O N - D I S C L O S U R E
Address:
R E Q U I R E D
Timer Interface (TIM)
I/O Registers
R E Q U I R E D
Timer Interface (TIM)
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic 0. Reset clears the
TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
A G R E E M E N T
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD6/ATD14/TCLK pin or one
of the seven prescaler outputs as the input to the TIM counter as
Table 16-1 shows. Reset clears the PS[2:0] bits.
N O N - D I S C L O S U R E
Table 16-1. Prescaler Selection
PS[2:0]
TIM Clock Source
000
Internal Bus Clock ÷1
001
Internal Bus Clock ÷ 2
010
Internal Bus Clock ÷ 4
011
Internal Bus Clock ÷ 8
100
Internal Bus Clock ÷ 16
101
Internal Bus Clock ÷ 32
110
Internal Bus Clock ÷ 64
111
PTD6/ATD14/TCLK
Advance Information
230
MC68HC708AS48 — Rev. 4.0
Timer Interface (TIM)
MOTOROLA
NOTE:
If TCNTH is read during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Register Name and Address: TCNTH — $0022
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
Register Name and Address: TCNTL — $0023
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 16-5. TIM Counter Registers (TCNTH and TCNTL)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Timer Interface (TIM)
231
A G R E E M E N T
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
N O N - D I S C L O S U R E
16.9.2 TIM Counter Registers
R E Q U I R E D
Timer Interface (TIM)
I/O Registers
R E Q U I R E D
Timer Interface (TIM)
16.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next clock. Writing to the high byte (TMODH) inhibits
the TOF bit and overflow interrupts until the low byte (TMODL) is written.
Reset sets the TIM counter modulo registers.
A G R E E M E N T
Register Name and Address: TMODH — $0024
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Register Name and Address: TMODL — $0025
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Read:
Write:
N O N - D I S C L O S U R E
Reset:
R
R = Reserved
Figure 16-6. TIM Counter Modulo Registers (TMODH and TMODL)
NOTE:
Reset the TIM counter before writing to the TIM counter modulo registers.
Advance Information
232
MC68HC708AS48 — Rev. 4.0
Timer Interface (TIM)
MOTOROLA
Each of the TIM channel status and control registers:
•
Flags input captures and output compares
•
Enables input capture and output compare interrupts
•
Selects input capture, output compare, or PWM operation
•
Selects high, low, or toggling output on output compare
•
Selects rising edge, falling edge, or any edge as the active input
capture trigger
•
Selects output toggling on TIM overflow
•
Selects 100% PWM duty cycle
•
Selects buffered or unbuffered output compare/PWM operation
Register Name and Address: TSC0 — $0026
Bit 7
Read:
CH0F
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
0
0
0
0
0
0
0
4
3
2
1
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
0
0
0
0
0
Register Name and Address: TSC1 — $0029
Bit 7
Read:
6
CH1F
5
0
CH1IE
Write:
0
Reset:
0
R
0
0
Figure 16-7. TIM Channel Status
and Control Registers (TSC0–TSC5)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Timer Interface (TIM)
233
N O N - D I S C L O S U R E
16.9.4 TIM Channel Status and Control Registers
A G R E E M E N T
R E Q U I R E D
Timer Interface (TIM)
I/O Registers
R E Q U I R E D
Timer Interface (TIM)
Register Name and Address: TSC2 — $002C
Bit 7
Read:
CH2F
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
CH2IE
MS2B
MS2A
ELS2B
ELS2A
TOV2
CH2MAX
0
0
0
0
0
0
0
4
3
2
1
Bit 0
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
0
0
0
0
0
Register Name and Address: TSC3 — $002F
A G R E E M E N T
Bit 7
Read:
6
CH3F
5
0
CH3IE
Write:
0
Reset:
0
R
0
0
Register Name and Address: TSC4 — $0032
Bit 7
Read:
CH4F
Write:
0
Reset:
0
6
5
4
3
2
1
Bit 0
CH4IE
MS4B
MS4A
ELS4B
ELS4A
TOV4
CH4MAX
0
0
0
0
0
0
0
4
3
2
1
Bit 0
MS5A
ELS5B
ELS5A
TOV5
CH5MAX
0
0
0
0
0
N O N - D I S C L O S U R E
Register Name and Address: TSC5 — $0035
Bit 7
Read:
6
CH5F
5
0
CH5IE
Write:
0
R
Reset:
0
0
R
= Reserved
0
Figure 16-7. TIM Channel Status
and Control Registers (TSC0–TSC5) (Continued)
Advance Information
234
MC68HC708AS48 — Rev. 4.0
Timer Interface (TIM)
MOTOROLA
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When CHxIE = 0, clear CHxF by reading TIM channel x status and
control register with CHxF set, and then writing a logic 0 to CHxF. If
another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
A G R E E M E N T
CHxF — Channel x Flag Bit
R E Q U I R E D
Timer Interface (TIM)
I/O Registers
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0, TIM channel 2, and TIM
channel 4 status and control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and
reverts TCH3 to general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and
reverts TCH5 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Timer Interface (TIM)
235
N O N - D I S C L O S U R E
MSxB — Mode Select Bit B
R E Q U I R E D
Timer Interface (TIM)
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. (See Table
16-2.)
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
A G R E E M E N T
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin. (See Table 16-2.) Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
N O N - D I S C L O S U R E
When ELSxB and ELSxA are both clear, channel x is not connected
to port E or port F, and pin PTEx/TCHx or pin PTFx/TCHx is available
as a general-purpose I/O pin. Table 16-2 shows how ELSxB and
ELSxA work. Reset clears the ELSxB and ELSxA bits.
Advance Information
236
MC68HC708AS48 — Rev. 4.0
Timer Interface (TIM)
MOTOROLA
MSxB:MSxA
ELSxB:ELSxA
X0
00
Mode
Output
Preset
NOTE:
X1
00
00
01
00
10
00
11
01
01
01
10
01
11
1X
01
1X
10
1X
11
Configuration
Pin under Port Control; Initial
Output Level High
Pin under Port Control; Initial
Output Level Low
Capture on Rising Edge Only
Input
Capture
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Output
Compare
or PWM
Buffered
Output
Compare
orBuffered
PWM
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Before enabling a TIM channel register for input capture operation, make
sure that the PTEx/TCHx pin or PTFx/TCHx pin is stable for at least two
bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Timer Interface (TIM)
237
N O N - D I S C L O S U R E
Table 16-2. Mode, Edge, and Level Selection
A G R E E M E N T
R E Q U I R E D
Timer Interface (TIM)
I/O Registers
R E Q U I R E D
Timer Interface (TIM)
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 16-8 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 16-8. CHxMAX Latency
16.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
N O N - D I S C L O S U R E
A G R E E M E N T
OVERFLOW
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
Advance Information
238
MC68HC708AS48 — Rev. 4.0
Timer Interface (TIM)
MOTOROLA
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read
Write
Reset:
Indeterminate after Reset
Register Name and Address: TCH0L — $0028
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
Write
Reset:
Indeterminate after Reset
Register Name and Address: TCH1H — $002A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read
Write
Reset:
Indeterminate after Reset
Register Name and Address: TCH1L — $002B
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
Write
Reset:
Indeterminate after Reset
Register Name and Address: TCH2H — $002D
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read
Write
Reset:
Indeterminate after Reset
Figure 16-9. TIM Channel Registers
(TCH0H/L–TCH3H/L) (Sheet 1 of 3)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Timer Interface (TIM)
239
A G R E E M E N T
Bit 7
N O N - D I S C L O S U R E
Register Name and Address: TCH0H — $0027
R E Q U I R E D
Timer Interface (TIM)
I/O Registers
R E Q U I R E D
Timer Interface (TIM)
Register Name and Address: TCH2L — $002E
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
Write
Reset:
Indeterminate after Reset
A G R E E M E N T
Register Name and Address: TCH3H — $0030
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read
Write
Reset:
Indeterminate after Reset
Register Name and Address: TCH3L — $0031
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
Write
Reset:
Indeterminate after Reset
N O N - D I S C L O S U R E
Register Name and Address: TCH4H — $0033
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read
Write
Reset:
Indeterminate after Reset
Register Name and Address: TCH4L — $0034
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
Write
Reset:
Indeterminate after Reset
Figure 16-9. TIM Channel Registers
(TCH0H/L–TCH3H/L) (Sheet 2 of 3)
Advance Information
240
MC68HC708AS48 — Rev. 4.0
Timer Interface (TIM)
MOTOROLA
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read
Write
Reset:
Indeterminate after Reset
Register Name and Address: TCH5L — $0037
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
Write
Reset:
Indeterminate after Reset
N O N - D I S C L O S U R E
Figure 16-9. TIM Channel Registers
(TCH0H/L–TCH3H/L) (Sheet 3 of 3)
A G R E E M E N T
Register Name and Address: TCH5H — $0036
R E Q U I R E D
Timer Interface (TIM)
I/O Registers
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Timer Interface (TIM)
241
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Timer Interface (TIM)
Advance Information
242
MC68HC708AS48 — Rev. 4.0
Timer Interface (TIM)
MOTOROLA
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
17.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
17.4.1
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.4.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.4.3
Character Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.4.4
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . .249
17.4.5
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
17.4.6
Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
17.4.7
Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . .253
17.4.8
Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
17.4.9
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
17.4.10 Character Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
17.4.11 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
17.4.12 Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
17.4.13 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
17.4.14 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
17.5 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
17.5.1
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
17.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
17.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
17.7
SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .263
17.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
17.8.1
PTE0/TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . .264
17.8.2
PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . .264
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Serial Communications Interface (SCI)
243
R E Q U I R E D
17.1 Contents
A G R E E M E N T
Section 17. Serial Communications Interface (SCI)
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
17.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
17.9.1
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .265
17.9.2
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .269
17.9.3
SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .271
17.9.4
SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
17.9.5
SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
17.9.6
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
17.9.7
SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .280
17.2 Introduction
This section describes the serial communications interface module (SCI,
Version D), which allows high-speed asynchronous communications
with peripheral devices and other MCUs.
17.3 Features
Features of the SCI module include:
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
•
Full duplex operation
•
Standard mark/space non-return-to-zero (NRZ) format
•
32 programmable baud rates
•
Programmable 8-bit or 9-bit character length
•
Separately enabled transmitter and receiver
•
Separate receiver and transmitter CPU interrupt requests
•
Programmable transmitter output polarity
•
Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
Advance Information
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MC68HC708AS48 — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
•
R E Q U I R E D
Serial Communications Interface (SCI)
Functional Description
Interrupt-driven operation with eight interrupt flags:
– Transmitter empty
– Transmission complete
– Receiver full
– Idle receiver input
– Receiver overrun
– Noise error
•
Receiver framing error detection
•
Hardware parity checking
•
1/16 bit-time noise detection
17.4 Functional Description
Figure 17-1 shows the structure of the SCI module. The SCI allows
full-duplex, asynchronous, NRZ serial communication between the MCU
and remote devices, including other MCUs. The transmitter and receiver
of the SCI operate independently, although they use the same baud rate
generator. During normal operation, the CPU monitors the status of the
SCI, writes the data to be transmitted, and processes received data.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Serial Communications Interface (SCI)
245
N O N - D I S C L O S U R E
– Parity error
A G R E E M E N T
– Framing error
INTERNAL BUS
SCI DATA
REGISTER
ERROR
INTERRUPT
CONTROL
RECEIVE
SHIFT REGISTER
PTE1/RxD
RECEIVER
INTERRUPT
CONTROL
SCI DATA
REGISTER
TRANSMITTER
INTERRUPT
CONTROL
R E Q U I R E D
Serial Communications Interface (SCI)
TRANSMIT
SHIFT REGISTER
PTE0/TxD
TXINV
SCTIE
R8
A G R E E M E N T
TCIE
T8
SCRIE
ILIE
TE
SCTE
RE
TC
RWU
SBK
SCRF
OR
ORIE
IDLE
NF
NEIE
FE
FEIE
PE
PEIE
LOOPS
LOOPS
N O N - D I S C L O S U R E
FLAG
CONTROL
RECEIVE
CONTROL
WAKEUP
CONTROL
ENSCI
ENSCI
TRANSMIT
CONTROL
BKF
M
RPF
WAKE
ILTY
CGMXCLK
÷4
PRESCALER
PEN
BAUD RATE
GENERATOR
÷ 16
PTY
DATA SELECTION
CONTROL
Figure 17-1. SCI Module Block Diagram
Advance Information
246
MC68HC708AS48 — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
$0014
$0015
$0016
$0017
$0018
$0019
Bit 7
6
5
4
3
2
1
Bit 0
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
T8
R
R
ORIE
NEIE
FEIE
PEIE
Read:
SCI Control Register 1
LOOPS
(SCC1) Write:
See page 266.
Reset:
0
Read:
SCI Control Register 2
(SCC2) Write:
See page 269.
Reset:
Read:
SCI Control Register 3
(SCC3) Write:
See page 272.
Reset:
R8
U
U
0
0
0
0
0
0
Read:
SCI Status Register 1
(SCS1) Write:
See page 274.
Reset:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
R
R
R
R
R
R
R
R
1
1
0
0
0
0
0
0
Read:
SCI Status Register 2
(SCS2) Write:
See page 278.
Reset:
0
0
0
0
0
0
BKF
RPF
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
SCI Data Register
(SCDR) Write:
See page 279.
Reset:
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Read:
SCI Baud Rate Register
(SCBR) Write:
See page 280.
Reset:
0
0
R
R
0
0
R
Unaffected by Reset
R
= Reserved
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
U = Unaffected
Figure 17-2. SCI I/O Register Summary
MC68HC708AS48 — Rev. 4.0
MOTOROLA
A G R E E M E N T
$0013
Register Name
Advance Information
Serial Communications Interface (SCI)
247
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Serial Communications Interface (SCI)
Functional Description
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
17.4.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 17-3.
8-BIT DATA FORMAT
(BIT M IN SCC1 CLEAR)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
POSSIBLE
PARITY
BIT
BIT 6
BIT 7
9-BIT DATA FORMAT
(BIT M IN SCC1 SET)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
STOP
BIT
NEXT
START
BIT
POSSIBLE
PARITY
BIT
BIT 6
BIT 7
BIT 8
STOP
BIT
NEXT
START
BIT
Figure 17-3. SCI Data Formats
17.4.2 Transmitter
Figure 17-4 shows the structure of the SCI transmitter.
17.4.3 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCC1) determines character length.
When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is
the ninth bit (bit 8).
Advance Information
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MC68HC708AS48 — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
1. Initialize the Tx and Rx rate in the SCI baud register (SCBR)
($0019) 17.9.7 SCI Baud Rate Register.
2. Enable the SCI by writing a logic 1 to ENSCI in SCI control register
1 (SCC1) ($0013).
3. Enable the transmitter by writing a logic 1 to the transmitter enable
bit (TE) in SCI control register 2 (SCC2) ($0014).
4. Clear the SCI transmitter empty bit (SCTE) by first reading SCI
status register (SCS1) ($0016) and then writing to the SCDR
($0018).
5. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of 10 or 11 logic 1s. After
the preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes
into the most significant bit position.
The SCI transmitter empty bit, SCTE in the SCI status control register
(SCS1), becomes set when the SCDR transfers a byte to the transmit
shift register. The SCTE bit indicates that the SCDR can accept new
data from the internal data bus. If the SCI transmit interrupt enable bit,
SCTI E (SCC2), is also set, the SCTE bit generates a transmitter CPU
interrupt request.
When the transmit shift register is not transmitting a character, the
PTE0/TxD pin goes to the idle condition, logic 1. If at any time software
clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port E pins.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Serial Communications Interface (SCI)
249
A G R E E M E N T
During an SCI transmission, the transmit shift register shifts a character
out to the PTE0/TxD pin. The SCI data register (SCDR) is the write-only
buffer between the internal data bus and the transmit shift register. To
initiate an SCI transmission:
N O N - D I S C L O S U R E
17.4.4 Character Transmission
R E Q U I R E D
Serial Communications Interface (SCI)
Functional Description
R E Q U I R E D
Serial Communications Interface (SCI)
INTERNAL BUS
÷ 16
SCI DATA REGISTER
SCP1
11-BIT
TRANSMIT
SHIFT REGISTER
STOP
CGMXCLK
BAUD
DIVIDER
SCP0
SCR1
H
SCR2
8
7
6
5
4
3
2
START
PRESCALER
÷4
1
0
L
PTE0/TxD
MSB
TXINV
PARITY
GENERATION
T8
BREAK
ALL ZEROS
PTY
PREAMBLE
ALL ONES
PEN
SHIFT ENABLE
M
LOAD FROM SCDR
A G R E E M E N T
TRANSMITTER CPU INTERRUPT REQUEST
SCR0
TRANSMITTER
CONTROL LOGIC
SCTE
SBK
SCTE
N O N - D I S C L O S U R E
SCTIE
TC
TCIE
LOOPS
SCTIE
ENSCI
TC
TE
TCIE
Figure 17-4. SCI Transmitter
Advance Information
250
MC68HC708AS48 — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
$0014
$0015
$0016
$0017
$0018
$0019
Bit 7
6
5
4
3
2
1
Bit 0
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
T8
R
R
ORIE
NEIE
FEIE
PEIE
Read:
SCI Control Register 1
LOOPS
(SCC1) Write:
See page 266.
Reset:
0
Read:
SCI Control Register 2
(SCC2) Write:
See page 269.
Reset:
Read:
SCI Control Register 3
(SCC3) Write:
See page 272.
Reset:
R8
U
U
0
0
0
0
0
0
Read:
SCI Status Register 1
(SCS1) Write:
See page 274.
Reset:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
R
R
R
R
R
R
R
R
1
1
0
0
0
0
0
0
Read:
SCI Status Register 2
(SCS2) Write:
See page 278.
Reset:
0
0
0
0
0
0
BKF
RPF
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
SCI Data Register
(SCDR) Write:
See page 279.
Reset:
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Read:
SCI Baud Rate Register
(SCBR) Write:
See page 280.
Reset:
0
0
R
R
0
0
R
Unaffected by Reset
R
= Reserved
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
U = Unaffected
Figure 17-5. Transmitter I/O Register Summary
MC68HC708AS48 — Rev. 4.0
MOTOROLA
A G R E E M E N T
$0013
Register Name
Advance Information
Serial Communications Interface (SCI)
251
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Serial Communications Interface (SCI)
Functional Description
17.4.5 Break Characters
Writing a logic 1 to the send break bit, SBK (SCC2), loads the transmit
shift register with a break character. A break character contains all logic
0s and has no start, stop, or parity bit. Break character length depends
on the M bit (SCC1). As long as SBK is at logic 1, transmitter logic
continuously loads break characters into the transmit shift register. After
software clears the SBK bit, the shift register finishes transmitting the
last break character and then transmits at least one logic 1. The
automatic logic 1 at the end of a break character guarantees the
recognition of the start bit of the next character.
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
N O N - D I S C L O S U R E
The SCI recognizes a break character when a start bit is followed by
eight or nine logic 0 data bits and a logic 0 where the stop bit should be.
Receiving a break character has these effects on SCI registers:
•
Sets the framing error bit (FE) in SCS1
•
Sets the SCI receiver full bit (SCRF) in SCS1
•
Clears the SCI data register (SCDR)
•
Clears the R8 bit in SCC3
•
Sets the break flag bit (BKF) in SCS2
•
May set the overrun (OR), noise flag (NF), parity error (PE), or
reception in progress flag (RPF) bits
Advance Information
252
MC68HC708AS48 — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
If the TE bit (transmitter enable) is cleared during a transmission, the
PTE0/TxD pin becomes idle after completion of the transmission in
progress. Clearing and then setting the TE bit during a transmission
queues an idle character to be sent after the character currently being
transmitted.
NOTE:
When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the PTE0/TxD pin. Setting
TE after the stop bit appears on PTE0/TxD causes data previously
written to the SCDR to be lost.
A good time to toggle the TE bit is when the SCTE bit becomes set and
just before writing the next byte to the SCDR.
17.4.7 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
(See 17.9.1 SCI Control Register 1.)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Serial Communications Interface (SCI)
253
A G R E E M E N T
An idle character contains all logic 1s and has no start, stop, or parity bit.
Idle character length depends on the M bit (mode character length) in
SCC1. The preamble is a synchronizing idle character that begins every
transmission.
N O N - D I S C L O S U R E
17.4.6 Idle Characters
R E Q U I R E D
Serial Communications Interface (SCI)
Functional Description
17.4.8 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI
transmitter:
•
SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE (SCC2),
enables the SCTE bit to generate transmitter CPU interrupt
requests.
•
Transmission complete (TC) — The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE (SCC2), enables the TC bit to
generate transmitter CPU interrupt requests.
17.4.9 Receiver
Figure 17-6 shows the structure of the SCI receiver.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
Advance Information
254
MC68HC708AS48 — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
R E Q U I R E D
Serial Communications Interface (SCI)
Functional Description
INTERNAL BUS
SCR1
÷ 16
CGMXCLK
DATA
RECOVERY
PTE1/RxD
BKF
ALL ZEROS
CPU INTERRUPT REQUEST
ERROR CPU INTERRUPT REQUEST
RPF
H
11-BIT
RECEIVE SHIFT REGISTER
8
7
6
M
WAKE
ILTY
PEN
PTY
5
4
3
2
1
0
L
SCRF
WAKEUP
LOGIC
PARITY
CHECKING
IDLE
ILIE
SCRF
SCRIE
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
A G R E E M E N T
BAUD
DIVIDER
STOP
PRESCALER
ALL ONES
÷4
SCI DATA REGISTER
RWU
IDLE
R8
ILIE
SCRIE
N O N - D I S C L O S U R E
SCR0
START
SCR2
SCP0
MSB
SCP1
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
Figure 17-6. SCI Receiver Block Diagram
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Serial Communications Interface (SCI)
255
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
Addr.
$0013
$0014
$0015
$0016
$0017
$0018
$0019
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
T8
R
R
ORIE
NEIE
FEIE
PEIE
Read:
SCI Control Register 1
LOOPS
(SCC1) Write:
See page 266.
Reset:
0
Read:
SCI Control Register 2
(SCC2) Write:
See page 269.
Reset:
Read:
SCI Control Register 3
(SCC3) Write:
See page 272.
Reset:
R8
U
U
0
0
0
0
0
0
Read:
SCI Status Register 1
(SCS1) Write:
See page 274.
Reset:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
R
R
R
R
R
R
R
R
1
1
0
0
0
0
0
0
Read:
SCI Status Register 2
(SCS2) Write:
See page 278.
Reset:
0
0
0
0
0
0
BKF
RPF
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Read:
SCI Data Register
(SCDR) Write:
See page 279.
Reset:
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Read:
SCI Baud Rate Register
(SCBR) Write:
See page 280.
Reset:
0
0
R
R
0
0
R
Unaffected by Reset
R
= Reserved
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
U = Unaffected
Figure 17-7. SCI Receiver I/O Register Summary
Advance Information
256
MC68HC708AS48 — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
17.4.10 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).
R E Q U I R E D
Serial Communications Interface (SCI)
Functional Description
During an SCI reception, the receive shift register shifts characters in
from the PTE1/RxD pin. The SCI data register (SCDR) is the read-only
buffer between the internal data bus and the receive shift register.
N O N - D I S C L O S U R E
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE
(SCC2), is also set, the SCRF bit generates a receiver CPU interrupt
request.
A G R E E M E N T
17.4.11 Character Reception
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Serial Communications Interface (SCI)
257
17.4.12 Data Sampling
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT
clock is an internal signal with a frequency 16 times the baud rate. To
adjust for baud rate mismatch, the RT clock is resynchronized at these
times (see Figure 17-8):
A G R E E M E N T
•
After every start bit
•
After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
START BIT
LSB
N O N - D I S C L O S U R E
PTE1/RxD
START BIT
QUALIFICATION
SAMPLES
START BIT
VERIFICATION
DATA
SAMPLING
RT4
RT3
RT2
RT16
RT1
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
RT6
RT5
RT4
RT3
RT2
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT CLOCK
STATE
RT1
RT
CLOCK
RT1
R E Q U I R E D
Serial Communications Interface (SCI)
RT CLOCK
RESET
Figure 17-8. Receiver Data Sampling
Advance Information
258
MC68HC708AS48 — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
RT3, RT5, and RT7
Samples
Start Bit
Verification
Noise Flag
000
Yes
0
001
Yes
1
010
Yes
1
011
No
0
100
Yes
1
101
No
0
110
No
0
111
No
0
If start bit verification is not successful, the RT clock is reset and a new
search for a start bit begins.
To determine the value of a data bit and to detect noise, recovery logic
takes samples at RT8, RT9, and RT10. Table 17-2 summarizes the
results of the data bit samples.
Table 17-2. Data Bit Recovery
RT8, RT9, and RT10
Samples
Data Bit
Determination
Noise Flag
000
0
0
001
0
1
010
0
1
011
1
1
100
0
1
101
1
1
110
1
1
111
1
0
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Serial Communications Interface (SCI)
259
A G R E E M E N T
Table 17-1. Start Bit Verification
N O N - D I S C L O S U R E
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7. Table 17-1 summarizes the results of
the start bit verification samples.
R E Q U I R E D
Serial Communications Interface (SCI)
Functional Description
R E Q U I R E D
Serial Communications Interface (SCI)
NOTE:
The RT8, RT9, and RT10 samples do not affect start bit verification. If
any or all of the RT8, RT9, and RT10 start bit samples are logic 1s
following a successful start bit verification, the noise flag (NF) is set and
the receiver assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at
RT8, RT9, and RT10. Table 17-3 summarizes the results of the stop bit
samples.
N O N - D I S C L O S U R E
A G R E E M E N T
Table 17-3. Stop Bit Recovery
RT8, RT9, and RT10
Samples
Framing
Error Flag
Noise Flag
000
1
0
001
1
1
010
1
1
011
0
1
100
1
1
101
0
1
110
0
1
111
0
0
17.4.13 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error bit, FE, in
SCS1. The FE flag is set at the same time that the SCRF bit (SCS1) is
set. A break character that has no stop bit also sets the FE bit.
17.4.14 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup bit, RWU (SCC2), puts the
receiver into a standby state during which receiver interrupts are
disabled.
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MOTOROLA
NOTE:
Address mark — An address mark is a logic 1 in the most
significant bit position of a received character. When the WAKE bit
is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI
receiver full bit, SCRF. Software can then compare the character
containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and
processes the characters that follow. If they are not the same,
software can set the RWU bit and put the receiver back into the
standby state.
•
Idle input line condition — When the WAKE bit is clear, an idle
character on the PTE1/RxD pin wakes the receiver from the
standby state by clearing the RWU bit. The idle character that
wakes the receiver does not set the receiver idle bit, IDLE, or the
SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines
whether the receiver begins counting logic 1s as idle character bits
after the start bit or after the stop bit.
Clearing the WAKE bit after the PTE1/RxD pin has been idle may cause
the receiver to wake up immediately.
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A G R E E M E N T
•
N O N - D I S C L O S U R E
Depending on the state of the WAKE bit in SCC1, either of two
conditions on the PTE1/RxD pin can bring the receiver out of the standby
state:
R E Q U I R E D
Serial Communications Interface (SCI)
Functional Description
17.5 Receiver Interrupts
These sources can generate CPU interrupt requests from the SCI
receiver:
•
SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that
the receive shift register has transferred a character to the SCDR.
SCRF can generate a receiver CPU interrupt request. Setting the
SCI receive interrupt enable bit, SCRIE (SCC2), enables the
SCRF bit to generate receiver CPU interrupts.
•
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the PTE1/RxD pin. The idle
line interrupt enable bit, ILIE (SCC2), enables the IDLE bit to
generate CPU interrupt requests.
17.5.1 Error Interrupts
These receiver error flags in SCS1 can generate CPU interrupt requests:
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
•
Receiver overrun (OR) — The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the SCDR. The previous character
remains in the SCDR, and the new character is lost. The overrun
interrupt enable bit, ORIE (SCC3), enables OR to generate SCI
error CPU interrupt requests.
•
Noise flag (NF) — The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE (SCC3), enables
NF to generate SCI error CPU interrupt requests.
•
Framing error (FE) — The FE bit in SCS1 is set when a logic zero
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE (SCC3), enables FE to generate SCI
error CPU interrupt requests.
•
Parity error (PE) — The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE (SCC3), enables PE to generate SCI error CPU
interrupt requests.
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17.6.1 Wait Mode
The SCI module remains active after the execution of a WAIT
instruction. In wait mode, the SCI module registers are not accessible by
the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
17.6.2 Stop Mode
The SCI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect SCI register states. SCI module
operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
17.7 SCI During Break Module Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during interrupts generated by the break
module. The BCFE bit in the SIM break flag control register (SBFCR)
enables software to clear status bits during the break state.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic z0ero to the
BCFE bit. With BCFE at logic 0 (its default state), software can read and
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A G R E E M E N T
The WAIT and STOP instructions put the MCU in low-power standby
modes.
N O N - D I S C L O S U R E
17.6 Low-Power Modes
R E Q U I R E D
Serial Communications Interface (SCI)
Low-Power Modes
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
write I/O registers during the break state without affecting status bits.
Some status bits have a two-step read/write clearing procedure. If
software does the first step on such a bit before the break, the bit cannot
change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
17.8 I/O Signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins
are:
•
PTE0/TxD — Transmit data
•
PTE1/RxD — Receive data
17.8.1 PTE0/TxD (Transmit Data)
The PTE0/TxD pin is the serial data output from the SCI transmitter. The
SCI shares the PTE0/TxD pin with port E. When the SCI is enabled, the
PTE0/TxD pin is an output regardless of the state of the DDRE0 bit in
data direction register E (DDRE).
17.8.2 PTE1/RxD (Receive Data)
The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI
shares the PTE1/RxD pin with port E. When the SCI is enabled, the
PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data
direction register E (DDRE).
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MOTOROLA
R E Q U I R E D
Serial Communications Interface (SCI)
I/O Registers
17.9 I/O Registers
•
SCI control register 1, SCC1
•
SCI control register 2, SCC2
•
SCI control register 3, SCC3
•
SCI status register 1, SCS1
•
SCI status register 2, SCS2
•
SCI data register, SCDR
•
SCI baud rate register, SCBR
A G R E E M E N T
These I/O registers control and monitor SCI operation:
17.9.1 SCI Control Register 1
•
Enables loop mode operation
•
Enables the SCI
•
Controls output polarity
•
Controls character length
•
Controls SCI wakeup method
•
Controls idle character detection
•
Enables parity function
•
Controls parity type
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N O N - D I S C L O S U R E
SCI control register 1:
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R E Q U I R E D
Serial Communications Interface (SCI)
Address:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
ENSCI
TXINV
M
WAKE
ILTY
PEN
PTY
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 17-9. SCI Control Register 1 (SCC1)
A G R E E M E N T
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the
PTE1/RxD pin is disconnected from the SCI, and the transmitter
output goes into the receiver input. Both the transmitter and the
receiver must be enabled to use loop mode. Reset clears the LOOPS
bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
N O N - D I S C L O S U R E
This read/write bit enables the SCI and the SCI baud rate generator.
Clearing ENSCI sets the SCTE and TC bits in SCI status register 1
and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE:
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
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WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition on the PTE1/RxD pin. Reset clears the
WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s
as idle character bits. The counting begins either after the start bit or
after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit can cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 17-4.)
When enabled, the parity function inserts a parity bit in the most
significant bit position. (See Figure 17-3.) Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
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A G R E E M E N T
This read/write bit determines whether SCI characters are eight or
nine bits long. (See Table 17-4.) The ninth bit can serve as an extra
stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
N O N - D I S C L O S U R E
M — Mode (Character Length) Bit
R E Q U I R E D
Serial Communications Interface (SCI)
I/O Registers
R E Q U I R E D
Serial Communications Interface (SCI)
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity. (See Table 17-4.) Reset clears the PTY
bit.
1 = Odd parity
0 = Even parity
A G R E E M E N T
NOTE:
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 17-4. Character Format Selection
Control Bits
Character Format
PEN:PTY
Start Bits
Data Bits
Parity
Stop Bits
Character
Length
0
0X
1
8
None
1
10 Bits
1
0X
1
9
None
1
11 Bits
0
10
1
7
Even
1
10 Bits
0
11
1
7
Odd
1
10 Bits
1
10
1
8
Even
1
11 Bits
1
11
1
8
Odd
1
11 Bits
N O N - D I S C L O S U R E
M
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17.9.2 SCI Control Register 2
SCI control register 2:
Enables these CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt
requests
– Enables the TC bit to generate transmitter CPU interrupt
requests
A G R E E M E N T
– Enables the SCRF bit to generate receiver CPU interrupt
requests
– Enables the IDLE bit to generate receiver CPU interrupt
requests
•
Enables the transmitter
•
Enables the receiver
•
Enables SCI wakeup
•
Transmits SCI break characters
Address:
$0014
Bit 7
6
5
4
3
2
1
Bit 0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 17-10. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter
CPU interrupt requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt requests
0 = SCTE not enabled to generate CPU interrupt requests
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
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N O N - D I S C L O S U R E
•
R E Q U I R E D
Serial Communications Interface (SCI)
I/O Registers
R E Q U I R E D
Serial Communications Interface (SCI)
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver
CPU interrupt requests. Reset clears the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt requests
0 = SCRF not enabled to generate CPU interrupt requests
ILIE — Idle Line Interrupt Enable Bit
A G R E E M E N T
This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
N O N - D I S C L O S U R E
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PTE0/TxD pin. If software clears the TE bit, the transmitter completes
any transmission in progress before the PTE0/TxD returns to the idle
condition (logic 1). Clearing and then setting TE during a transmission
queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE:
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE:
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
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MOTOROLA
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break
character followed by a logic 1. The logic 1 after the break character
guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s
between them. Reset clears the SBK bit.
1 = Transmit break characters
0 = No break characters transmitted
NOTE:
Do not toggle the SBK bit immediately after setting the SCTE bit
because toggling SBK too early causes the SCI to send a break
character instead of a preamble.
17.9.3 SCI Control Register 3
SCI control register 3:
•
Stores the ninth SCI data bit received and the ninth SCI data bit to
be transmitted
•
Enables these interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
– Parity error interrupts
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A G R E E M E N T
This read/write bit puts the receiver in a standby state during which
receiver interrupts are disabled. The WAKE bit in SCC1 determines
whether an idle input or an address mark brings the receiver out of the
standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
N O N - D I S C L O S U R E
RWU — Receiver Wakeup Bit
R E Q U I R E D
Serial Communications Interface (SCI)
I/O Registers
R E Q U I R E D
Serial Communications Interface (SCI)
Address:
$0015
Bit 7
6
5
4
3
2
1
Bit 0
T8
R
R
ORIE
NEIE
FEIE
PEIE
0
0
0
0
0
0
Read:
R8
Write:
R
Reset:
U
U
R
= Reserved
U = Unaffected
A G R E E M E N T
Figure 17-11. SCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other eight bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
T8 — Transmitted Bit 8
N O N - D I S C L O S U R E
When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the noise error bit, NE. Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
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R E Q U I R E D
Serial Communications Interface (SCI)
I/O Registers
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
A G R E E M E N T
This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. (See Figure 17-12.) Reset
clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
17.9.4 SCI Status Register 1
SCI status register 1 contains flags to signal these conditions:
Transfer of SCDR data to transmit shift register complete
•
Transmission complete
•
Transfer of receive shift register data to SCDR complete
•
Receiver input idle
•
Receiver overrun
•
Noisy data
•
Framing error
•
Parity error
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N O N - D I S C L O S U R E
•
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R E Q U I R E D
Serial Communications Interface (SCI)
Address:
$0016
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
Write:
R
R
R
R
R
R
R
R
Reset:
1
1
0
0
0
0
0
0
R
= Reserved
A G R E E M E N T
Figure 17-12. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
operation, clear the SCTE bit by reading SCS1 with SCTE set and
then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
N O N - D I S C L O S U R E
NOTE:
Setting the TE bit for the first time also sets the SCTE bit. Setting the TE
and SCTIE bits generates an SCI transmitter CPU request.
TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set and no data,
preamble, or break character is being transmitted. TC generates an
SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also
set. TC is cleared automatically when data, preamble, or break
character is queued and ready to be sent. There may be up to 1.5
transmitter clocks of latency between queueing data, preamble, and
break character and the transmission actually starting. Reset sets the
TC bit.
1 = No transmission in progress
0 = Transmission in progress
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SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. SCRF can generate an SCI
receiver CPU interrupt request. In normal operation, clear the SCRF
bit by reading SCS1 with SCRF set and then reading the SCDR.
Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
R E Q U I R E D
Serial Communications Interface (SCI)
I/O Registers
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the
SCDR before the receive shift register receives the next character.
The OR bit generates an SCI error CPU interrupt request if the ORIE
bit in SCC3 is also set. The data in the shift register is lost, but the data
already in the SCDR is not affected. Clear the OR bit by reading SCS1
with OR set and then reading the SCDR. Reset clears the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of
SCS1 and SCDR in the flag-clearing sequence. Figure 17-13 shows
the normal flag-clearing sequence and an example of an overrun
caused by a delayed flag-clearing sequence. The delayed read of
SCDR does not clear the OR bit because OR was not set when SCS1
was read. Byte 2 caused the overrun and is lost. The next
flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.
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N O N - D I S C L O S U R E
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an SCI error CPU
interrupt request if the ILIE bit in SCC2 is also set and the DMARE bit
in SCC3 is clear. Clear the IDLE bit by reading SCS1 with IDLE set
and then reading the SCDR. After the receiver is enabled, it must
receive a valid character that sets the SCRF bit before an idle
condition can set the IDLE bit. Also, after the IDLE bit has been
cleared, a valid character must again set the SCRF bit before an idle
condition can set the IDLE bit. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
A G R E E M E N T
IDLE — Receiver Idle Bit
R E Q U I R E D
Serial Communications Interface (SCI)
In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the
flag-clearing routine can check the OR bit in a second read of SCS1
after reading the data register.
NF — Receiver Noise Flag Bit
A G R E E M E N T
This clearable, read-only bit is set when the SCI detects noise on the
PTE1/RxD pin. NF generates an NF CPU interrupt request if the NEIE
bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then
reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
N O N - D I S C L O S U R E
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
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MOTOROLA
R E Q U I R E D
Serial Communications Interface (SCI)
I/O Registers
BYTE 3
SCRF = 0
SCRF = 1
SCRF = 0
BYTE 2
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCDR
BYTE 2
READ SCDR
BYTE 3
A G R E E M E N T
BYTE 1
SCRF = 1
SCRF = 0
SCRF = 1
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
SCRF = 0
OR = 0
SCRF = 1
OR = 1
SCRF = 0
OR = 1
SCRF = 1
OR = 1
SCRF = 1
DELAYED FLAG CLEARING SEQUENCE
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
N O N - D I S C L O S U R E
Figure 17-13. Flag Clearing Sequence
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17.9.5 SCI Status Register 2
SCI status register 2 contains flags to signal two conditions:
1. Break character detected
2. Incoming data
Address:
$0017
Bit 7
6
5
4
3
2
R
R
R
R
R
R
Read:
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
Write:
Reset:
0
R
0
0
0
0
0
1
Bit 0
BKF
RPF
R
R
0
0
= Reserved
Figure 17-14. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
N O N - D I S C L O S U R E
This clearable, read-only bit is set when the SCI detects a break
character on the PTE1/RxD pin. In SCS1, the FE and SCRF bits are
also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF
by reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after logic 1s again appear
on the PTE1/RxD pin followed by another break character. Reset
clears the BKF bit.
1 = Break character detected
0 = No break character detected
RPF —Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start
bits, usually from noise or a baud rate mismatch or when the receiver
detects an idle character. Polling RPF before disabling the SCI
module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
Advance Information
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MC68HC708AS48 — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
The SCI data register is the buffer between the internal data bus and the
receive and transmit shift registers. Reset has no effect on data in the
SCI data register.
Address:
$0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by Reset
Figure 17-15. SCI Data Register (SCDR)
R7/T7:R0/T0 — Receive/Transmit Data Bits
N O N - D I S C L O S U R E
Reading address $0018 accesses the read-only received data bits,
R7:R0. Writing to address $0018 writes the data to be transmitted,
T7:T0. Reset has no effect on the SCI data register.
A G R E E M E N T
17.9.6 SCI Data Register
R E Q U I R E D
Serial Communications Interface (SCI)
I/O Registers
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Serial Communications Interface (SCI)
279
17.9.7 SCI Baud Rate Register
The baud rate register selects the baud rate for both the receiver and the
transmitter.
Address:
$0019
Bit 7
6
5
4
3
2
1
Bit 0
R
R
SCP1
SCP0
R
SCR2
SCR1
SCR0
0
0
0
0
0
0
0
0
Read:
Write:
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
Reset:
R
= Reserved
Figure 17-16. SCI BAUD Rate Register 1 (SCBR)
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown
in Table 17-5. Reset clears SCP1 and SCP0.
N O N - D I S C L O S U R E
Table 17-5. SCI Baud Rate Prescaling
SCP1:SCP0
Prescaler Divisor (PD)
00
1
01
3
10
4
11
13
SCR2:SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in
Table 17-6. Reset clears SCR2:SCR0.
Advance Information
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MC68HC708AS48 — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
R E Q U I R E D
Serial Communications Interface (SCI)
I/O Registers
Table 17-6. SCI Baud Rate Selection
Baud Rate Divisor (BD)
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
A G R E E M E N T
SCR2:SCR1:SCR0
Use this formula to calculate the SCI baud rate:
CGMXCLK
Baud rate = -----------------------------------64 × PD × BD
PD = Prescale divisor (see Table 17-5)
N O N - D I S C L O S U R E
BD = Baud rate divisor (see Table 17-6)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Serial Communications Interface (SCI)
281
Table 17-7 shows the SCI baud rates that can be generated with a
4.194-MHz crystal.
Table 17-7. SCI Baud Rate Selection Examples
SCP1:SCP0
Prescaler Divisor
(PD)
SCR2:SCR1:SCR0
Baud Rate Divisor
(BD)
Baud Rate
(fXCLK = 4.194 MHz)
00
1
000
1
65,531
00
1
001
2
32,766
00
1
010
4
16,383
00
1
011
8
8191
00
1
100
16
4095
00
1
101
32
2048
00
1
110
64
1024
00
1
111
128
512
01
3
000
1
21,844
01
3
001
2
10,922
01
3
010
4
5461
01
3
011
8
2730
01
3
100
16
1365
01
3
101
32
683
01
3
110
64
341
01
3
111
128
171
10
4
000
1
16,383
10
4
001
2
8191
10
4
010
4
4096
10
4
011
8
2048
10
4
100
16
1024
10
4
101
32
512
10
4
110
64
256
10
4
111
128
128
11
13
000
1
5041
11
13
001
2
1664
11
13
010
4
1260
11
13
011
8
630
11
13
100
16
315
11
13
101
32
158
11
13
110
64
78.8
11
13
111
128
39.4
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Communications Interface (SCI)
Advance Information
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MC68HC708AS48 — Rev. 4.0
Serial Communications Interface (SCI)
MOTOROLA
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
18.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
18.4
Pin Name and Register Name Conventions . . . . . . . . . . . . . .285
18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
18.5.1
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
18.5.2
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
18.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
18.6.1
Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . .290
18.6.2
Transmission Format When CPHA = 0 . . . . . . . . . . . . . . .291
18.6.3
Transmission Format When CPHA = 1 . . . . . . . . . . . . . . .292
18.6.4
Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . .294
18.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
18.7.1
Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
18.7.2
Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
18.8
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
18.9
Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .301
18.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
18.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
18.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
18.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
18.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .305
18.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
18.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . .306
18.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . .307
MC68HC708AS48 — Rev. 4.0
MOTOROLA
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R E Q U I R E D
18.1 Contents
A G R E E M E N T
Section 18. Serial Peripheral Interface (SPI)
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
18.13.3
18.13.4
18.13.5
SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
VSS (Clock Ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
18.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
18.14.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
18.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .312
18.14.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
18.2 Introduction
This section describes the serial peripheral interface (SPI) module,
which allows full-duplex, synchronous, serial communications with
peripheral devices.
18.3 Features
Features of the SPI module include:
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
•
Full-duplex operation
•
Master and slave modes
•
Double-buffered operation with separate transmit and receive
registers
•
Four master mode frequencies (maximum = bus frequency ÷ 2)
•
Maximum slave mode frequency = bus frequency
•
Serial clock with programmable polarity and phase
•
Two separately enabled interrupts with CPU service:
– SPRF, SPI receiver full
– SPTE, SPI transmitter empty
•
Mode fault error flag with CPU interrupt capability
•
Overflow error flag with CPU interrupt capability
•
Programmable wired-OR mode
•
I2C (inter-integrated circuit) compatibility
Advance Information
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Serial Peripheral Interface (SPI)
MOTOROLA
The generic names of the SPI input/output (I/O) pins are:
•
SS (slave select)
•
SPSCK (SPI serial clock)
•
MOSI (master out slave in)
•
MISO (master in slave out)
The SPI shares four I/O pins with a parallel I/O port. The full name of an
SPI pin reflects the name of the shared port pin. Table 18-1 shows the
full names of the SPI I/O pins. The generic pin names appear in the text
that follows.
Table 18-1. Pin Name Conventions
SPI Generic Pin Name:
Full SPI Pin Name:
MISO
MOSI
SS
SPSCK
PTE5/MISO
PTE6/MOSI
PTE4/SS
PTE7/SPSCK
The generic names of the SPI I/O registers are:
•
SPI control register (SPCR)
•
SPI status and control register (SPSCR)
•
SPI data register (SPDR)
Table 18-2 shows the names and the addresses of the SPI I/O registers.
Table 18-2. I/O Register Addresses
Register Name
SPI control register (SPCR)
$0010
SPI status and control
register (SPSCR)
$0011
SPI data register (SPDR)
$0012
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Address
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N O N - D I S C L O S U R E
18.4 Pin Name and Register Name Conventions
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
Pin Name and Register Name Conventions
R E Q U I R E D
Serial Peripheral Interface (SPI)
18.5 Functional Description
Figure 18-1 summarizes the SPI I/O registers and Figure 18-2 shows
the structure of the SPI module.
Addr.
$0011
$0012
SPI Control Register Read:
(SPCR)
Write:
See page 310.
Reset:
Read:
SPI Status and Control
Register (SPSCR) Write:
See page 313.
Reset:
Read:
SPI Data Register
(SPDR) Write:
See page 316.
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
SPRIE
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
0
0
1
0
1
0
0
0
OVRF
MODF
SPTE
R
R
R
MODFEN
SPR1
SPR0
SPRF
R
ERRIE
0
0
0
0
1
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
T7
T6
T5
T4
T3
T2
T1
T0
Indeterminate after Reset
R
= Reserved
Figure 18-1. SPI I/O Register Summary
N O N - D I S C L O S U R E
A G R E E M E N T
$0010
Register Name
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MC68HC708AS48 — Rev. 4.0
Serial Peripheral Interface (SPI)
MOTOROLA
R E Q U I R E D
Serial Peripheral Interface (SPI)
Functional Description
INTERNAL BUS
TRANSMIT DATA REGISTER
SHIFT REGISTER
BUS CLOCK
7
6
5
4
3
2
1
MISO
0
÷2
MOSI
÷8
RECEIVE DATA REGISTER
÷ 32
PIN
CONTROL
LOGIC
÷ 128
SPMSTR
SPE
CLOCK
SELECT
SPR1
A G R E E M E N T
CLOCK
DIVIDER
SPSCK
M
CLOCK
LOGIC
S
SS
SPR0
SPMSTR
TRANSMITTER CPU INTERRUPT REQUEST
CPHA
MODFEN
CPOL
SPWOM
ERRIE
SPI
CONTROL
SPTIE
RECEIVER/ERROR CPU INTERRUPT REQUEST
SPE
SPRF
SPTE
OVRF
MODF
Figure 18-2. SPI Module Block Diagram
The SPI module allows full-duplex, synchronous, serial communication
between the MCU and peripheral devices, including other MCUs.
Software can poll the SPI status flags or SPI operation can be
interrupt-driven. All SPI interrupts can be serviced by the CPU.
The operation of the SPI module is described here.
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287
N O N - D I S C L O S U R E
SPRIE
18.5.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR
(SPCR $0010), is set.
NOTE:
Configure the SPI modules as master and slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave
SPI before disabling the master SPI. (See 18.14.1 SPI Control
Register.)
Only a master SPI module can initiate transmissions. Software begins
the transmission from a master SPI module by writing to the SPI data
register. If the shift register is empty, the byte immediately transfers to
the shift register, setting the SPI transmitter empty bit, SPTE (SPSCR
$0011). The byte begins shifting out on the MOSI pin under the control
of the serial clock. (See Figure 18-3.)
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
N O N - D I S C L O S U R E
The SPR1 and SPR0 bits control the baud rate generator and determine
the speed of the shift register. (See 18.14.2 SPI Status and Control
Register.) Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
MASTER MCU
SHIFT REGISTER
SLAVE MCU
MISO
MISO
MOSI
MOSI
SHIFT REGISTER
SPSCK
BAUD RATE
GENERATOR
SS
SPSCK
VDD
SS
Figure 18-3. Full-Duplex Master-Slave Connections
Advance Information
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MC68HC708AS48 — Rev. 4.0
Serial Peripheral Interface (SPI)
MOTOROLA
The SPI operates in slave mode when the SPMSTR bit (SPCR $0010)
is clear. In slave mode the SPSCK pin is the input for the serial clock
from the master MCU. Before a data transmission occurs, the SS pin of
the slave MCU must be at logic 0. SS must remain low until the
transmission is complete. (See 18.7.2 Mode Fault Error.)
In a slave SPI module, data enters the shift register under the control of
the serial clock from the master SPI module. After a byte enters the shift
register of a slave SPI, it is transferred to the receive data register, and
the SPRF bit (SPSCR) is set. To prevent an overflow condition, slave
software then must read the SPI data register before another byte enters
the shift register.
The maximum frequency of the SPSCK for an SPI configured as a slave
is the bus clock speed, which is twice as fast as the fastest master
SPSCK clock that can be generated. The frequency of the SPSCK for an
SPI configured as a slave does not have to correspond to any SPI baud
rate. The baud rate only controls the speed of the SPSCK generated by
an SPI configured as a master. Therefore, the frequency of the SPSCK
for an SPI configured as a slave can be any frequency less than or equal
to the bus speed.
When the master SPI starts a transmission, the data in the slave shift
register begins shifting out on the MISO pin. The slave can load its shift
register with a new byte for the next transmission by writing to its transmit
data register. The slave must write to its transmit data register at least
one bus cycle before the master starts the next transmission. Otherwise
the byte already in the slave shift register shifts out on the MISO pin.
MC68HC708AS48 — Rev. 4.0
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A G R E E M E N T
18.5.2 Slave Mode
N O N - D I S C L O S U R E
As the byte shifts out on the MOSI pin of the master, another byte shifts
in from the slave on the master’s MISO pin. The transmission ends when
the receiver full bit, SPRF (SPSCR), becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data
register. In normal operation, SPRF signals the end of a transmission.
Software clears SPRF by reading the SPI status and control register and
then reading the SPI data register. Writing to the SPI data register clears
the SPTIE bit.
R E Q U I R E D
Serial Peripheral Interface (SPI)
Functional Description
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
Data written to the slave shift register during a a transmission remains in
a buffer until the end of the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts
a transmission. When CPHA is clear, the falling edge of SS starts a
transmission. (See 18.6 Transmission Formats.)
If the write to the data register is late, the SPI transmits the data already
in the shift register from the previous transmission.
NOTE:
To prevent SPSCK from appearing as a clock edge, SPSCK must be in
the proper idle state before the slave is enabled.
18.6 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted
out serially) and received (shifted in serially). A serial clock line
synchronizes shifting and sampling on the two serial data lines. A slave
select line allows individual selection of a slave SPI device; slave
devices that are not selected do not interfere with SPI bus activities. On
a master SPI device, the slave select line can be used optionally to
indicate a multiple-master bus contention.
18.6.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SCK) phase
and polarity using two bits in the SPI control register (SPCR). The clock
polarity is specified by the CPOL control bit, which selects an active high
or low clock and has no significant effect on the transmission format.
The clock phase (CPHA) control bit (SPCR) selects one of two
fundamentally different transmission formats. The clock phase and
polarity should be identical for the master SPI device and the
communicating slave device. In some cases, the phase and polarity are
changed between transmissions to allow a master device to
communicate with peripheral slaves having different requirements.
NOTE:
Before writing to the CPOL bit or the CPHA bit (SPCR), disable the SPI
by clearing the SPI enable bit (SPE).
Advance Information
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Serial Peripheral Interface (SPI)
MOTOROLA
SCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
N O N - D I S C L O S U R E
Figure 18-4 shows an SPI transmission in which CPHA (SPCR) is
logic 0. The figure should not be used as a replacement for data sheet
parametric information.Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted
as a master or slave timing diagram since the serial clock (SCK), master
in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the
output from the slave, and the MOSI signal is the output from the master.
The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that
only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must
be high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See 18.7.2 Mode Fault Error.) When CPHA = 0, the first SPSCK
edge is the MSB capture strobe. Therefore, the slave must begin driving
its data before the first SPSCK edge, and a falling edge on the SS pin is
used to start the transmission. The SS pin must be toggled high and then
low again between each byte transmitted as shown in Figure 18-5.
SCK CPOL = 0
SCK CPOL = 1
MOSI
FROM MASTER
MISO
FROM SLAVE
MSB
SS TO SLAVE
CAPTURE STROBE
Figure 18-4. Transmission Format (CPHA = 0)
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Serial Peripheral Interface (SPI)
A G R E E M E N T
18.6.2 Transmission Format When CPHA = 0
R E Q U I R E D
Serial Peripheral Interface (SPI)
Transmission Formats
291
MISO/MOSI
BYTE 1
BYTE 2
BYTE 3
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 18-5. CPHA/SS Timing
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the falling edge of SS. Any data
written after the falling edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
18.6.3 Transmission Format When CPHA = 1
Figure 18-6 shows an SPI transmission in which CPHA (SPCR) is
logic 1. The figure should not be used as a replacement for data sheet
parametric information. Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted
as a master or slave timing diagram since the serial clock (SCK), master
in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the
output from the slave, and the MOSI signal is the output from the master.
The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that
only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must
be high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See 18.7.2 Mode Fault Error.) When CPHA = 1, the master
begins driving its MOSI pin on the first SPSCK edge. Therefore, the
slave uses the first SPSCK edge as a start transmission signal. The SS
pin can remain low between transmissions. This format may be
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
Advance Information
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MC68HC708AS48 — Rev. 4.0
Serial Peripheral Interface (SPI)
MOTOROLA
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the first edge of SPSCK. Any
data written after the first edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
SCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
MOSI
FROM MASTER
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MISO
FROM SLAVE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
SCK CPOL = 0
N O N - D I S C L O S U R E
SCK CPOL =1
LSB
SS TO SLAVE
CAPTURE STROBE
Figure 18-6. Transmission Format (CPHA = 1)
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preferable in systems having only one master and only one slave driving
the MISO data line.
R E Q U I R E D
Serial Peripheral Interface (SPI)
Transmission Formats
293
18.6.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), transmissions
are started by a software write to the SPDR ($0012). CPHA has no effect
on the delay to the start of the transmission, but it does affect the initial
state of the SCK signal. When CPHA = 0, the SCK signal remains
inactive for the first half of the first SCK cycle. When CPHA = 1, the first
SCK cycle begins with an edge on the SCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1:SPR0) affects the
delay from the write to SPDR and the start of the SPI transmission. (See
Figure 18-7.) The internal SPI clock in the master is a free-running
derivative of the internal MCU clock. It is only enabled when both the
SPE and SPMSTR bits (SPCR) are set to conserve power. SCK edges
occur halfway through the low time of the internal MCU clock. Since the
SPI clock is free-running, it is uncertain where the write to the SPDR will
occur relative to the slower SCK. This uncertainty causes the variation
in the initiation delay shown in Figure 18-7. This delay will be no longer
than a single SPI bit time. That is, the maximum delay between the write
to SPDR and the start of the SPI transmission is two MCU bus cycles for
DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and
128 MCU bus cycles for DIV128.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
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WRITE
TO SPDR
R E Q U I R E D
Serial Peripheral Interface (SPI)
Transmission Formats
INITIATION DELAY
BUS
CLOCK
MOSI
MSB
BIT 6
BIT 5
SCK
CPHA = 1
SCK
CPHA = 0
1
2
3
A G R E E M E N T
SCK CYCLE
NUMBER
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN








WRITE
TO SPDR
BUS
CLOCK
EARLIEST LATEST
SCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
WRITE
TO SPDR
EARLIEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
SCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
LATEST
SCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
LATEST
N O N - D I S C L O S U R E
BUS
CLOCK
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
Figure 18-7. Transmission Start Delay (Master)
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18.7 Error Conditions
Two flags signal SPI error conditions:
1. Overflow (OVRFin SPSCR) — Failing to read the SPI data register
before the next byte enters the shift register sets the OVRF bit.
The new byte does not transfer to the receive data register, and
the unread byte still can be read by accessing the SPI data
register. OVRF is in the SPI status and control register.
2. Mode fault error (MODF in SPSCR) — The MODF bit indicates
that the voltage on the slave select pin (SS) is inconsistent with the
mode of the SPI. MODF is in the SPI status and control register.
18.7.1 Overflow Error
The overflow flag (OVRF in SPSCR) becomes set if the SPI receive data
register still has unread data from a previous transmission when the
capture strobe of bit 1 of the next transmission occurs. (See Figure 18-4
and Figure 18-6.) If an overflow occurs, the data being received is not
transferred to the receive data register so that the unread data can still
be read. Therefore, an overflow error always indicates the loss of data.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
OVRF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE in SPSCR) is also set. MODF and OVRF can
generate a receiver/error CPU interrupt request. (See Figure 18-10.) It
is not possible to enable only MODF or OVRF to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
If an end-of-block transmission interrupt was meant to pull the MCU out
of wait, having an overflow condition without overflow interrupts enabled
causes the MCU to hang in wait mode. If the OVRF is enabled to
generate an interrupt, it can pull the MCU out of wait mode instead.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition. Figure 18-8 shows how it is possible to
miss an overflow.
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BYTE 3
6
BYTE 4
8
SPRF
OVRF
READ SPSCR
READ SPDR
2
5
3
1
BYTE 1 SETS SPRF BIT.
2
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
BYTE 2 SETS SPRF BIT.
3
4
7
5
6
7
8
CPU READS SPSCRW WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS SET. BYTE 4 IS LOST.
Figure 18-8. Missed Read of Overflow Condition
The first part of Figure 18-8 shows how to read the SPSCR and SPDR
to clear the SPRF without problems. However, as illustrated by the
second transmission example, the OVRF flag can be set in between the
time that SPSCR and SPDR are read.
In this case, an overflow can be easily missed. Since no more SPRF
interrupts can be generated until this OVRF is serviced, it will not be
obvious that bytes are being lost as more transmissions are completed.
To prevent this, either enable the OVRF interrupt or do another read of
the SPSCR after the read of the SPDR. This ensures that the OVRF was
not set before the SPRF was cleared and that future transmissions will
complete with an SPRF interrupt. Figure 18-9 illustrates this process.
Generally, to avoid this second SPSCR read, enable the OVRF to the
CPU by setting the ERRIE bit (SPSCR).
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A G R E E M E N T
BYTE 2
4
N O N - D I S C L O S U R E
BYTE 1
1
R E Q U I R E D
Serial Peripheral Interface (SPI)
Error Conditions
R E Q U I R E D
Serial Peripheral Interface (SPI)
BYTE 1
BYTE 2
BYTE 3
BYTE 4
1
5
7
11
SPI RECEIVE
COMPLETE
SPRF
OVRF
2
READ SPSCR
A G R E E M E N T
6
9
3
READ SPDR
N O N - D I S C L O S U R E
4
8
1
BYTE 1 SETS SPRF BIT.
2
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
3
12
10
14
13
8
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
9
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
10 CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
4
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
5
BYTE 2 SETS SPRF BIT.
12 CPU READS SPSCR.
6
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
13 CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
14 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
11 BYTE 4 SETS SPRF BIT.
Figure 18-9. Clearing SPRF When OVRF Interrupt Is Not Enabled
18.7.2 Mode Fault Error
For the MODF flag (in SPSCR) to be set, the mode fault error enable bit
(MODFEN in SPSCR) must be set. Clearing the MODFEN bit does not
clear the MODF flag but does prevent MODF from being set again after
MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE in SPSCR) is also set. The SPRF, MODF,
and OVRF interrupts share the same CPU interrupt vector. MODF and
OVRF can generate a receiver/error CPU interrupt request. (See Figure
18-10.) It is not possible to enable only MODF or OVRF to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
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If ERRIE = 1, the SPI generates an SPI receiver/error CPU
interrupt request.
•
The SPE bit is cleared.
•
The SPTE bit is set.
•
The SPI state counter is cleared.
•
The data direction register of the shared I/O port regains control of
port drivers.
NOTE:
To prevent bus contention with another master SPI after a mode fault
error, clear all data direction register (DDR) bits associated with the SPI
shared port pins.
NOTE:
Setting the MODF flag (SPSCR) does not clear the SPMSTR bit.
Reading SPMSTR when MODF = 1 will indicate a MODE fault error
occurred in either master mode or slave mode.
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS
goes high during a transmission. When CPHA = 0, a transmission begins
when SS goes low and ends once the incoming SPSCK returns to its idle
level after the shift of the eighth data bit. When CPHA = 1, the
transmission begins when the SPSCK leaves its idle level and SS is
already low. The transmission continues until the SPSCK returns to its
IDLE level after the shift of the last data bit. (See 18.6 Transmission
Formats.)
NOTE:
When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0)
and later unselected (SS is at logic 1) even if no SPSCK is sent to that
slave. This happens because SS at logic 0 indicates the start of the
transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, a slave can be selected and then later unselected with
no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
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A G R E E M E N T
•
N O N - D I S C L O S U R E
In a master SPI with the mode fault enable bit (MODFEN) set, the mode
fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master
SPI causes these events to occur:
R E Q U I R E D
Serial Peripheral Interface (SPI)
Error Conditions
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by toggling the SPE bit of the slave.
NOTE:
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if a transmission has begun.
To clear the MODF flag, read the SPSCR and then write to the SPCR
register. This entire clearing procedure must occur with no MODF
condition existing or else the flag will not be cleared.
18.8 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt
requests:
Table 18-3. SPI Interrupts
Flag
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
Request
SPTE (Transmitter Empty)
SPI Transmitter CPU Interrupt Request (SPTIE = 1)
SPRF (Receiver Full)
SPI Receiver CPU Interrupt Request (SPRIE = 1)
OVRF (Overflow)
SPI Receiver/Error Interrupt Request (SPRIE = 1,
ERRIE = 1)
MODF (Mode Fault)
SPI Receiver/Error Interrupt Request (SPRIE = 1,
ERRIE = 1, MODFEN = 1)
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt, provided that the SPI is enabled
(SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF flags to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF flag is enabled to generate
receiver/error CPU interrupt requests.
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SPTE
SPTIE
R E Q U I R E D
Serial Peripheral Interface (SPI)
Queuing Transmission Data
SPE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPRIE
SPRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
ERRIE
MODF
Two sources in the SPI status and control register can generate CPU
interrupt requests:
1. SPI receiver full bit (SPRF) — The SPRF bit becomes set every
time a byte transfers from the shift register to the receive data
register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate an SPI receiver/error CPU interrupt request.
2. SPI transmitter empty (SPTE) — The SPTE bit becomes set every
time a byte transfers from the transmit data register to the shift
register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate an SPTE CPU interrupt request.
18.9 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates
when the transmit data buffer is ready to accept new data. Write to the
SPI data register only when the SPTE bit is high. Figure 18-11 shows
the timing associated with doing back-to-back transmissions with the
SPI (SPSCK has CPHA: CPOL = 1:0).
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N O N - D I S C L O S U R E
Figure 18-10. SPI Interrupt Request Generation
A G R E E M E N T
OVRF
R E Q U I R E D
Serial Peripheral Interface (SPI)
WRITE TO SPDR
SPTE
1
3
8
5
2
10
SPSCK (CPHA:CPOL = 1:0)
MOSI
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
6 5 4 3 2 1
6 5 4 3 2 1
6 5 4
BYTE 1
BYTE 2
BYTE 3
A G R E E M E N T
9
4
SPRF
6
READ SPSCR
7
READ SPDR
N O N - D I S C L O S U R E
11
1
CPU WRITES BYTE 1 TO SPDR, CLEARING
SPTE BIT.
2
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
3
CPU WRITES BYTE 2 TO SPDR, QUEUEING
BYTE 2 AND CLEARING SPTE BIT.
4
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
5
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
6
CPU READS SPSCR WITH SPRF BIT SET.
12
7
CPU READS SPDR, CLEARING SPRF BIT.
8
CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
9
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
10 BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
Figure 18-11. SPRF/SPTE CPU Interrupt Timing
The transmit data buffer allows back-to-back transmissions without the
slave precisely timing its writes between transmissions as in a system
with a single data buffer. Also, if no new data is written to the data buffer,
the last value contained in the shift register is the next data word to be
transmitted.
For an idle master or idle slave that has no data loaded into its transmit
buffer, the SPTE is set again no more than two bus cycles after the
transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of
the shift register cannot occur until the transmission is completed. This
implies that a back-to-back write to the transmit data register is not
possible. The SPTE indicates when the next write can occur.
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•
The SPTE flag is set.
•
Any transmission currently in progress is aborted.
•
The shift register is cleared.
•
The SPI state counter is cleared, making it ready for a new
complete transmission.
•
All the SPI port logic is defaulted back to being general-purpose
I/O.
These additional items are reset only by a system reset:
•
All control bits in the SPCR register
•
All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,
and SPR0)
•
The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE
between transmissions without having to reset all control bits when SPE
is set back to high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still
service these interrupts after the SPI has been disabled. The user can
disable the SPI by writing 0 to the SPE bit. The SPI also can be disabled
by a mode fault occurring in an SPI that was configured as a master with
the MODFEN bit set.
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A G R E E M E N T
Any system reset completely resets the SPI. Partial resets occur
whenever the SPI enable bit (SPE) is low. Whenever SPE is low, these
occurs:
N O N - D I S C L O S U R E
18.10 Resetting the SPI
R E Q U I R E D
Serial Peripheral Interface (SPI)
Resetting the SPI
18.11 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby
modes.
18.11.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction.
In wait mode, the SPI module registers are not accessible by the CPU.
Any enabled CPU interrupt request from the SPI module can bring the
MCU out of wait mode.
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF
bit to generate CPU interrupt requests by setting the error interrupt
enable bit (ERRIE). (See 18.8 Interrupts.)
N O N - D I S C L O S U R E
18.11.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect register conditions. SPI operation
resumes after the MCU exits stop mode. If stop mode is exited by reset,
any transfer in progress is aborted and the SPI is reset.
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To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the data register in break mode will not initiate a
transmission nor will this data be transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.
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A G R E E M E N T
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR $FE03) enables software to
clear status bits during the break state. (See 9.8.3 SIM Break Flag
Control Register.)
N O N - D I S C L O S U R E
18.12 SPI During Break Interrupts
R E Q U I R E D
Serial Peripheral Interface (SPI)
SPI During Break Interrupts
18.13 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel
I/O port.
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
•
MISO — Data received
•
MOSI — Data transmitted
•
SPSCK — Serial clock
•
SS — Slave select
•
VSS — Clock ground
The SPI has limited inter-integrated circuit (I2C) capability (requiring
software support) as a master in a single-master environment. To
communicate with I2C peripherals, MOSI becomes an open-drain output
when the SPWOM bit in the SPI control register is set. In I2C
communication, the MOSI and MISO pins are connected to a
bidirectional pin from the I2C peripheral and through a pullup resistor
to VDD.
N O N - D I S C L O S U R E
18.13.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmit serial data. In full
duplex operation, the MISO pin of the master SPI module is connected
to the MISO pin of the slave SPI module. The master SPI simultaneously
receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is
configured as a slave. The SPI is configured as a slave when its
SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a
multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a
high-impedance state.
When enabled, the SPI controls data direction of the MISO pin
regardless of the state of the data direction register of the shared I/O
port.
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MOSI is one of the two SPI module pins that transmit serial data. In full
duplex operation, the MOSI pin of the master SPI module is connected
to the MOSI pin of the slave SPI module. The master SPI simultaneously
transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin
regardless of the state of the data direction register of the shared I/O
port.
18.13.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and
slave devices. In a master MCU, the SPSCK pin is the clock output. In a
slave MCU, the SPSCK pin is the clock input. In full duplex operation,
the master and slave MCUs exchange a byte of data in eight serial clock
cycles.
N O N - D I S C L O S U R E
When enabled, the SPI controls data direction of the SPSCK pin
regardless of the state of the data direction register of the shared I/O
port.
A G R E E M E N T
18.13.2 MOSI (Master Out/Slave In)
R E Q U I R E D
Serial Peripheral Interface (SPI)
I/O Signals
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18.13.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the
SPI. For an SPI configured as a slave, the SS is used to select a slave.
For CPHA = 0, the SS is used to define the start of a transmission. (See
18.6 Transmission Formats.) Since it is used to indicate the start of a
transmission, the SS must be toggled high and low between each byte
transmitted for the CPHA = 0 format. However, it can remain low
throughout the transmission for the CPHA = 1 format. See Figure 18-12.
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
MISO/MOSI
BYTE 1
BYTE 2
BYTE 3
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 18-12. CPHA/SS Timing
N O N - D I S C L O S U R E
When an SPI is configured as a slave, the SS pin is always configured
as an input. It cannot be used as a general-purpose I/O regardless of the
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. (See 18.14.2
SPI Status and Control Register.)
NOTE:
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK
clocks, even if a transmission already has begun.
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. (See 18.7.2 Mode Fault Error.) For the state of the
SS pin to set the MODF flag, the MODFEN bit in the SPSCK register
must be set. If the MODFEN bit is low for an SPI master, the SS pin can
be used as a general-purpose I/O under the control of the data direction
register of the shared I/O port. With MODFEN high, it is an input-only pin
to the SPI regardless of the state of the data direction register of the
shared I/O port.
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The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the data register.
(See Table 18-4.)
Table 18-4. SPI Configuration
SPE SPMSTR MODFEN
SPI Configuration
State of SS Logic
0
X
X
Not Enabled
General-Purpose I/O;
SS Ignored by SPI
1
0
X
Slave
Input-Only to SPI
1
1
0
Master without MODF
General-Purpose I/O;
SS Ignored by SPI
1
1
1
Master with MODF
Input-Only to SPI
X = don’t care
18.13.5 VSS (Clock Ground)
N O N - D I S C L O S U R E
VSS is the ground return for the serial clock pin, SPSCK, and the ground
for the port output buffers. To reduce the ground return path loop and
minimize radio frequency (RF) emissions, connect the ground pin of the
slave to the VSS pin.
18.14 I/O Registers
Three registers control and monitor SPI operation:
•
SPI control register (SPCR, $0010)
•
SPI status and control register (SPSCR, $0011)
•
SPI data register (SPDR, $0012)
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Serial Peripheral Interface (SPI)
I/O Registers
309
18.14.1 SPI Control Register
The SPI control register:
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
•
Enables SPI module interrupt requests
•
Selects CPU interrupt requests
•
Configures the SPI module as master or slave
•
Selects serial clock polarity and phase
•
Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
•
Enables the SPI module
Address:
$0010
Bit 7
6
5
4
3
2
1
Bit 0
SPRIE
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
0
0
1
0
1
0
0
0
Read:
Write:
Reset:
R
= Reserved
N O N - D I S C L O S U R E
Figure 18-13. SPI Control Register (SPCR)
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
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CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial
clock and SPI data. (See Figure 18-4 and Figure 18-6.) To transmit
data between SPI modules, the SPI modules must have identical
CPHA bits. When CPHA = 0, the SS pin of the slave SPI module must
be set to logic 1 between bytes. (See Figure 18-12.) Reset sets the
CPHA bit.
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle
state and begin driving the MISO pin with the MSB of its data. Once
the transmission begins, no new data is allowed into the shift register
from the data register. Therefore, the slave data register must be
loaded with the desired transmit data before the falling edge of SS.
Any data written after the falling edge is stored in the data register and
transferred to the shift register at the current transmission.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. The same applies when SS is high for
a slave. The MISO pin is held in a high-impedance state, and the
incoming SPSCK is ignored. In certain cases, it may also cause the
MODF flag to be set. (See 18.7.2 Mode Fault Error.) A logic 1 on the
SS pin does not in any way affect the state of the SPI state machine.
SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
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A G R E E M E N T
This read/write bit determines the logic state of the SPSCK pin
between transmissions. (See Figure 18-4 and Figure 18-6.) To
transmit data between SPI modules, the SPI modules must have
identical CPOL bits. Reset clears the CPOL bit.
N O N - D I S C L O S U R E
CPOL — Clock Polarity Bit
R E Q U I R E D
Serial Peripheral Interface (SPI)
I/O Registers
SPE — SPI Enable Bit
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI. (See 18.10 Resetting the SPI.) Reset clears
the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE— SPI Transmit Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
18.14.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these
conditions:
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
•
Receive data register full
•
Failure to clear SPRF bit before next byte is received (overflow
error)
•
Inconsistent logic level on SS pin (mode fault error)
•
Transmit data register empty
The SPI status and control register also contains bits that perform these
functions:
•
Enable error interrupts
•
Enable mode fault error detection
•
Select master SPI baud rate
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Bit 7
Read:
6
SPRF
5
4
3
OVRF
MODF
SPTE
R
R
R
0
0
1
ERRIE
Write:
R
Reset:
0
R
0
2
1
Bit 0
MODFEN
SPR1
SPR0
0
0
0
= Reserved
Figure 18-14. SPI Status and Control Register (SPSCR)
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register. Any read of the SPI data register clears the SPRF
bit.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read-only bit enables the MODF and OVRF flags to generate
CPU interrupt requests. Reset clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the SPI data register. Reset clears the OVRF flag.
1 = Overflow
0 = No overflow
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A G R E E M E N T
$0011
N O N - D I S C L O S U R E
Address:
R E Q U I R E D
Serial Peripheral Interface (SPI)
I/O Registers
R E Q U I R E D
Serial Peripheral Interface (SPI)
MODF — Mode Fault Bit
This clearable, ready-only flag is set in a slave SPI if the SS pin goes
high during a transmission. In a master SPI, the MODF flag is set if
the SS pin goes low at any time. Clear the MODF bit by reading the
SPI status and control register with MODF set and then writing to the
SPI data register. Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
A G R E E M E N T
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data
register transfers a byte into the shift register. SPTE generates an
SPTE CPU interrupt request if the SPTIE bit in the SPI control register
is set also.
NOTE:
Do not write to the SPI data register unless the SPTE bit is high.
N O N - D I S C L O S U R E
For an idle master or idle slave that has no data loaded into its
transmit buffer, the SPTE will be set again within two bus cycles since
the transmit buffer empties into the shift register. This allows the user
to queue up a 16-bit value to send. For an already active slave, the
load of the shift register cannot occur until the transmission is
completed. This implies that a back-to-back write to the transmit data
register is not possible. The SPTE indicates when the next write can
occur.
Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set to 1, allows the MODF flag to be set. If
the MODF flag is set, clearing the MODFEN does not clear the MODF
flag. If the SPI is enabled as a master and the MODFEN bit is low,
then the SS pin is available as a general-purpose I/O.
If the MODFEN bit is set, then this pin is not available as a general
purpose I/O. When the SPI is enabled as a slave, the SS pin is not
available as a general-purpose I/O regardless of the value of
MODFEN. (See 18.13.4 SS (Slave Select).)
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If the MODFEN bit is low, the level of the SS pin does not affect the
operation of an enabled SPI configured as a master. For an enabled
SPI configured as a slave, having MODFEN low only prevents the
MODF flag from being set. It does not affect any other part of SPI
operation. (See 18.7.2 Mode Fault Error.)
SPR1 and SPR0 — SPI Baud Rate Select Bits
Table 18-5. SPI Master Baud Rate Selection
SPR1:SPR0
Baud Rate Divisor (BD)
00
2
01
8
10
32
11
128
Use this formula to calculate the SPI baud rate:
CGMOUT
Bus clock
Baud rate = -------------------------- = ------------------------2 × BD
BD
where:
CGMOUT = base clock output of the clock generator module (CGM),
see Section 8. Clock Generator Module (CGM).
BD = baud rate divisor
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N O N - D I S C L O S U R E
A G R E E M E N T
In master mode, these read/write bits select one of four baud rates as
shown in Table 18-5. SPR1 and SPR0 have no effect in slave mode.
Reset clears SPR1 and SPR0.
R E Q U I R E D
Serial Peripheral Interface (SPI)
I/O Registers
18.14.3 SPI Data Register
The SPI data register is the read/write buffer for the receive data register
and the transmit data register. Writing to the SPI data register writes data
into the transmit data register. Reading the SPI data register reads data
from the receive data register. The transmit data and receive data
registers are separate buffers that can contain different values. See
Figure 18-2.
Address:
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
$0012
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Indeterminate after Reset
Figure 18-15. SPI Data Register (SPDR)
R7:R0/T7:T0 — Receive/Transmit Data Bits
Do not use read-modify-write instructions on the SPI data register since
the buffer read is not the same as the buffer written.
N O N - D I S C L O S U R E
NOTE:
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19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
19.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
19.4.1
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
19.4.2
Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
19.4.3
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
19.4.4
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .321
19.4.5
Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . .321
19.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
19.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
19.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
19.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
19.7.1
ADC Analog Power Pin (VDDAREF)/ADC
Voltage Reference Pin (VREFH) . . . . . . . . . . . . . . . . . .322
19.7.2
ADC Analog Ground Pin (VSSA)/ADC
Voltage Reference Low Pin (VREFL). . . . . . . . . . . . . . .323
19.7.3
ADC Voltage In (ADCVIN). . . . . . . . . . . . . . . . . . . . . . . . .323
19.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
19.8.1
ADC Status and Control Register . . . . . . . . . . . . . . . . . . .324
19.8.2
ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
19.8.3
ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . .327
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R E Q U I R E D
19.1 Contents
A G R E E M E N T
Section 19. Analog-to-Digital Converter (ADC)
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
19.2 Introduction
This section describes the 8-bit analog-to-digital converter (ADC).
19.3 Features
Features of the ADC module include:
•
15 channels (52-pin PLCC), 16 channels (64-pin QFP) with
multiplexed input
•
Linear successive approximation
•
8-bit resolution
•
Single or continuous conversion
•
Conversion complete flag or conversion complete interrupt
•
Selectable ADC clock
19.4 Functional Description
Fifteen ADC channels are available in the 52-PLCC
(MC68HC708AS48CFN) for sampling external sources at pins
PTD6/ATD14/TCLK–PTD0/ATD8 and PTB7/ATD7–PTB0/ATD0.
Sixteen ADC channels are available in the 64-QFP (engineering sample)
for sampling external sources at pins PTD7/ATD15–PTD0/ATD8 and
PTB7/ATD7–PTB0/ATD0. An analog multiplexer allows the single ADC
converter to select one of the ADC channels as ADC voltage input
(ADCVIN). ADCVIN is converted by the successive approximation
register-based counters. When the conversion is completed, ADC
places the result in the ADC data register and sets a flag or generates
an interrupt. (See Figure 19-1.)
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Analog-to-Digital Converter (ADC)
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Analog-to-Digital Converter (ADC)
Functional Description
INTERNAL
DATA BUS
READ DDRB/DDRB
RESET
WRITE PTB/PTD
DISABLE
DDRBx/DDRDx
PTBx/PTDx
PTBx/PTDx
ADC CHANNEL x
A G R E E M E N T
READ PTB/PTD
DISABLE
ADC DATA REGISTER
INTERRUPT
LOGIC
AIEN
CONVERSION
COMPLETE
ADC VOLTAGE IN
ADCVIN
ADC
CHANNEL
SELECT
ADCH[4:0]
COCO
ADC CLOCK
CGMXCLK
BUS CLOCK
CLOCK
GENERATOR
ADIV[2:0]
ADICLK
Figure 19-1. ADC Block Diagram
19.4.1 ADC Port I/O Pins
PTD7/ATD15-PTD0/ATD8 and PTB7/ATD7-PTB0/ATD0 are
general-purpose I/O pins that are shared with the ADC channels.
PTD2/ATD10 is an input-only pin that is also shared with an ADC
channel.
NOTE:
PTD7/ATD15 is available only on the 64-pin QFP package.
The channel select bits (ADC status control register, $0038), define
which ADC channel/port pin will be used as the input signal. The ADC
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N O N - D I S C L O S U R E
WRITE DDRB/DDRD
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Analog-to-Digital Converter (ADC)
overrides the port I/O logic by forcing that pin as input to the ADC. The
remaining ADC channels/port pins are controlled by the port I/O logic
and can be used as general-purpose I/O. Writes to the port register or
DDR will not have any affect on the port pin that is selected by the ADC.
Read of a port pin which is in use by the ADC will return a logic 0 if the
corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value
in the port data latch is read.
NOTE:
Do not use ADC channel ATD14 when using the PTD6/ATD14/TCLK pin
as the clock input for the TIM.
19.4.2 Voltage Conversion
When the input voltage to the ADC equals VREFH (see 21.7 ADC
Characteristics), the ADC converts the signal to $FF (full scale). If the
input voltage equals VSSA/VREFL, the ADC converts it to $00. Input
voltages between VREFH and VSSA/VREFL are a straight-line linear
conversion. All other input voltages will result in $FF if greater than
VREFH and $00 if less than VSSA/VREFL.
NOTE:
Input voltage should not exceed the analog supply voltages.
19.4.3 Conversion Time
Sixteen ADC internal clocks are required to perform one conversion. The
ADC starts a conversion on the first rising edge of the ADC internal clock
immediately following a write to the ADSCR. If the ADC internal clock is
selected to run at 1 MHz, then one conversion will take 16 µs to
complete. But since the ADC can run almost completely asynchronously
to the bus clock, (for example, the ADC is configured to derive its internal
clock from CGMXCLK and the bus clock is being derived from the PLL
within the CGM [CGMOUT]), this 16 µs conversion can take up to 17 µs
to complete. This worst-case could occur if the write to the ADSCR
happened directly after the rising edge of the ADC internal clock causing
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Number of Bus Cycles = Conversion Time x Bus Frequency
19.4.4 Continuous Conversion
In the continuous conversion mode the ADC continuously converts the
selected channel, filling the ADC data register with new data after each
conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until
the ADCO bit is cleared. The COCO bit (ADC status control register,
$0038) is set after each conversion and can be cleared by writing the
ADC status and control register or reading of the ADC data register.
19.4.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes. See
21.7 ADC Characteristics for accuracy information.
19.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit is at logic 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
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A G R E E M E N T
16 to 17 ADC Clock Cycles
Conversion Time = 
ADC Clock Frequency
N O N - D I S C L O S U R E
the conversion to wait until the next rising edge of the ADC internal clock.
With a 1 MHz ADC internal clock the maximum sample rate is 59 kHz to
62 kHz. Refer to 21.7 ADC Characteristics.
R E Q U I R E D
Analog-to-Digital Converter (ADC)
Interrupts
A G R E E M E N T
R E Q U I R E D
Analog-to-Digital Converter (ADC)
19.6 Low-Power Modes
The low-power modes are described here.
19.6.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting the ADCH[4:0] bits in the ADC status
and control register to logic 1s before executing the WAIT instruction.
19.6.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode. Allow one conversion cycle to stabilize the analog
circuitry before attempting a new ADC conversion after exiting stop
mode.
N O N - D I S C L O S U R E
19.7 I/O Signals
In the 52-pin PLCC package, the ADC module has 15 channels that are
shared with I/O ports B and D and one channel with an input-only port
bit on port D. In the 64-pin QFP package, the ADC module has 16
channels that are shared with I/O ports B and D and one channel with an
input-only port bit on port D. Refer to 21.7 ADC Characteristics for
voltages referenced below.
19.7.1 ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH)
The ADC analog portion uses VDDA/VDDAREF as its power pin. Connect
the VDDA/VDDAREF pin to the same voltage potential as VDD. External
filtering may be necessary to ensure clean VDDA/VDDAREF for good
results.
VDDA/VDDAREF is the high reference voltage for all analog-to-digital
conversions. Connect the VREFH pin to a voltage potential between
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NOTE:
Route VDDA/VDDAREF carefully for maximum noise immunity and place
bypass capacitors as close as possible to the package.
19.7.2 ADC Analog Ground Pin (VSSA)/ADC Voltage Reference Low Pin (VREFL)
The ADC analog portion uses VSSA as its ground pin. Connect the VSSA
pin to the same voltage potential as VSS.
VREFL is the lower reference supply for the ADC. Connect the VREFL pin
to a voltage potential between VSSA and 0.5 volts depending on the
desired lower conversion boundary.
19.7.3 ADC Voltage In (ADCVIN)
ADCVIN is the input voltage signal from one of the ADC channels to the
ADC module.
A G R E E M E N T
1.5 volts and VDDAREF/VDDA depending on the desired upper conversion
boundary.
R E Q U I R E D
Analog-to-Digital Converter (ADC)
I/O Registers
N O N - D I S C L O S U R E
19.8 I/O Registers
These I/O registers control and monitor ADC operation:
•
ADC status and control register (ADSCR)
•
ADC data register (ADR)
•
ADC clock register (ADICLK)
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19.8.1 ADC Status and Control Register
These paragraphs describe the function of the ADC status and control
register.
Address:
$0038
Bit 7
A G R E E M E N T
R E Q U I R E D
Analog-to-Digital Converter (ADC)
Read:
COCO
Write:
R
Reset:
0
R
6
5
4
3
2
1
Bit 0
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
0
1
1
1
1
1
= Reserved
Figure 19-2. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
N O N - D I S C L O S U R E
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADC status and control register is written or whenever the ADC
data register is read. Reset clears this bit.
1 = conversion completed (AIEN = 0)
0 = conversion not completed (AIEN = 0)
or
0 = CPU interrupt enabled (AIEN = 1)
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
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When set, the ADC will convert samples continuously and update the
ADR register at the end of each conversion. Only one conversion is
allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field
which is used to select one of the ADC channels. The five channel
select bits are detailed in Table 19-1.
NOTE:
Care should be taken when using a port pin as both an analog and a
digital input simultaneously to prevent switching noise from corrupting
the analog signal.
The ADC subsystem is turned off when the channel select bits are all
set to one. This feature allows for reduced power consumption for the
MCU when the ADC is not used. Reset sets all of these bits to a
logic 1.
Recovery from the disabled state requires one conversion cycle to
stabilize.
N O N - D I S C L O S U R E
NOTE:
A G R E E M E N T
ADCO — ADC Continuous Conversion Bit
R E Q U I R E D
Analog-to-Digital Converter (ADC)
I/O Registers
MC68HC708AS48 — Rev. 4.0
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R E Q U I R E D
Analog-to-Digital Converter (ADC)
A G R E E M E N T
Table 19-1. Mux Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
0
0
0
0
PTB0/ATD0
0
0
0
0
1
PTB1/ATD1
0
0
0
1
0
PTB2/ATD2
0
0
0
1
1
PTB3/ATD3
0
0
1
0
0
PTB4/ATD4
0
0
1
0
1
PTB5/ATD5
0
0
1
1
0
PTB6/ATD6
0
0
1
1
1
PTB7/ATD7
0
1
0
0
0
PTD0/ATD8
0
1
0
0
1
PTD1/ATD9
0
1
0
1
0
PTD2/ATD10
0
1
0
1
1
PTD3/ATD11
0
1
1
0
0
PTD4/ATD12
0
1
1
0
1
PTD5/ATD13
0
1
1
1
0
PTD6/ATD14/TCLK
0
1
1
1
1
PTD7/ATD15
(see Note 3)
N O N - D I S C L O S U R E
Range 10000 ($10) to 11010 ($1A)
Unused (see Note 1)
1
1
0
1
1
Reserved
1
1
1
0
0
VDDAREF/VDDA
(see Note 2)
1
1
1
0
1
VREFH
(see Note 2)
1
1
1
1
0
VSSA/VREFL
(see Note 2)
1
1
1
1
1
[ADC power off]
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are
used to verify the operation of the ADC converter both in production test and for user
applications.
3. This channel is only available in the 64-pin QFP package.
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MOTOROLA
19.8.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
$0039
6
5
4
3
2
1
Bit 0
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
R
R
R
R
R
R
R
R
Reset:
A G R E E M E N T
Bit 7
Indeterminate after Reset
R
= Reserved
Figure 19-3. ADC Data Register (ADR)
19.8.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address:
$003A
Bit 7
6
5
4
ADIV2
ADIV1
ADIV0
ADICLK
Read:
Write:
Reset:
0
R
0
0
0
3
2
1
Bit 0
0
0
0
0
R
R
R
R
0
0
0
0
= Reserved
Figure 19-4. ADC Input Clock Register (ADICLK)
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 19-2
shows the available clock configurations. The ADC clock should be
set to approximately 1 MHz.
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N O N - D I S C L O S U R E
Address:
R E Q U I R E D
Analog-to-Digital Converter (ADC)
I/O Registers
R E Q U I R E D
Analog-to-Digital Converter (ADC)
Table 19-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
0
0
0
ADC Input Clock /1
0
0
1
ADC Input Clock / 2
0
1
0
ADC Input Clock / 4
0
1
1
ADC Input Clock / 8
1
X
X
ADC Input Clock / 16
A G R E E M E N T
X = don’t care
ADICLK — ADC Input Clock Register Bit
ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
N O N - D I S C L O S U R E
If the external clock (CGMXCLK) is equal to or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at
approximately 1 MHz, correct operation can be guaranteed. (See
21.7 ADC Characteristics.)
1 = Internal bus clock
0 = External clock (CGMXCLK)
fXCLK or Bus Frequency
1 MHz = 
ADIV[2:0]
NOTE:
During the conversion process, changing the ADC clock will result in an
incorrect conversion.
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MOTOROLA
20.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
20.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
20.4.1
BDLC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . .334
20.4.1.1
Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
20.4.1.2
Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
20.4.1.3
Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
20.4.1.4
BDLC Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
20.4.1.5
BDLC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336
20.4.1.6
Digital Loopback Mode. . . . . . . . . . . . . . . . . . . . . . . . . .336
20.4.1.7
Analog Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . .336
20.5 BDLC MUX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
20.5.1
Rx Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
20.5.1.1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
20.5.1.2
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
20.5.2
J1850 Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
20.5.3
J1850 VPW Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
20.5.4
J1850 VPW Valid/Invalid Bits and Symbols . . . . . . . . . . .346
20.5.5
Message Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
20.6 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
20.6.1
Protocol Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
20.6.2
Rx and Tx Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . .353
20.6.3
Rx and Tx Shadow Registers . . . . . . . . . . . . . . . . . . . . . .354
20.6.4
Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . .354
20.6.5
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
20.6.5.1
4X Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
20.6.5.2
Receiving a Message in Block Mode . . . . . . . . . . . . . . .355
20.6.5.3
Transmitting a Message in Block Mode . . . . . . . . . . . . .355
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R E Q U I R E D
20.1 Contents
A G R E E M E N T
Section 20. Byte Data Link Controller–Digital (BDLC–D)
N O N - D I S C L O S U R E
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R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
20.6.5.4
20.6.5.5
J1850 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
20.7 BDLC CPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
20.7.1
BDLC Analog and Roundtrip Delay. . . . . . . . . . . . . . . . . .358
20.7.2
BDLC Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . .360
20.7.3
BDLC Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . .363
20.7.4
BDLC State Vector Register . . . . . . . . . . . . . . . . . . . . . . .371
20.7.5
BDLC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
N O N - D I S C L O S U R E
A G R E E M E N T
20.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
20.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
20.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
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R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
Introduction
20.2 Introduction
The byte data link controller (BDLC) provides access to an external
serial communication multiplex bus, operating according to the SAE
J1850 protocol.
20.3 Features
SAE J1850 Class B Data Communications Network Interface
compatible and ISO compatible for low-speed (<125 kbps) serial
data communications in automotive applications
•
10.4-kbps variable pulse width (VPW) bit format
•
Digital noise filter
•
Collision detection
•
Hardware cyclical redundancy check (CRC) generation and
checking
•
Two power-saving modes with automatic wakeup on network
activity
•
Polling or CPU interrupts
•
Block mode receive and transmit supported
•
4X receive mode, 41.6 kbps, supported
•
Digital loopback mode
•
Analog loopback mode
•
In-frame response (IFR) types 0, 1, 2, and 3 supported
MC68HC708AS48 — Rev. 4.0
MOTOROLA
N O N - D I S C L O S U R E
•
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Byte Data Link Controller–Digital (BDLC–D)
A G R E E M E N T
Features of the BDLC module include:
331
20.4 Functional Description
Figure 20-1 shows the organization of the BDLC module. The CPU
interface contains the software addressable registers and provides the
link between the CPU and the buffers. The buffers provide storage for
data received and data to be transmitted onto the J1850 bus. The
protocol handler is responsible for the encoding and decoding of data
bits and special message symbols during transmission and reception.
The MUX interface provides the link between the BDLC digital section
and the analog physical interface. The wave shaping, driving, and
digitizing of data is performed by the physical interface.
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
Use of the BDLC module in message networking fully implements the
SAE Standard J1850 Class B Data Communication Network Interface
specification.
NOTE:
It is recommended that the reader be familiar with the SAE J1850
document and ISO Serial Communication document prior to proceeding
with this section of the MC68HC08AS20 specification.
N O N - D I S C L O S U R E
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 20-1. BDLC Block Diagram
.
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Read:
BDLC Analog and Roundtrip
Delay Register (BARD) Write:
See page 358.
Reset:
Read:
BDLC Control Register 1
(BCR1) Write:
See page 360.
Reset:
$003C
6
ATE
RXPOL
Read:
BDLC State Vector Register
(BSVR) Write:
See page 371.
Reset:
$003F
BDLC Data Register Read:
(BDR)
See page 373. Write:
5
4
0
0
R
R
1
1
0
0
IMSG
CLKS
R1
R0
1
3
2
1
Bit 0
BO3
BO2
BO1
BO0
0
1
1
1
0
0
IE
WCM
R
R
1
1
0
0
0
0
0
DLOOP
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
1
0
0
0
0
0
0
0
0
I3
I2
I1
I0
0
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
Read:
BDLC Control Register 2
ALOOP
(BCR2) Write:
See page 363.
Reset:
1
$003D
$003E
Bit 7
Reset:
Undetermined after Reset
R
= Reserved
Figure 20-2. BDLC Input/Output (I/O) Register Summary
MC68HC708AS48 — Rev. 4.0
MOTOROLA
A G R E E M E N T
$003B
Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
Functional Description
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333
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
20.4.1 BDLC Operating Modes
The BDLC has five main modes of operation which interact with the
power supplies, pins, and rest of the MCU as shown in Figure 20-3.
POWER OFF
VDD > VDD (MINIMUM) AND
ANY MCU RESET SOURCE ASSERTED
N O N - D I S C L O S U R E
A G R E E M E N T
VDD ≤ VDD (MINIMUM)
RESET
ANY MCU RESET SOURCE ASSERTED
FROM ANY MODE
(COP, ILLADDR, PU, RESET, LVR, POR)
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
NO MCU RESET SOURCE ASSERTED
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
RUN
BDLC STOP
BDLC WAIT
STOP INSTRUCTION OR
WAIT INSTRUCTION AND WCM = 1
WAIT INSTRUCTION AND WCM = 0
Figure 20-3. BDLC Operating Modes State Diagram
20.4.1.1 Power Off Mode
For the BDLC to guarantee operation, this mode is entered from reset
mode whenever the BDLC supply voltage, VDD, drops below its
minimum specified value. The BDLC will be placed in reset mode by
low-voltage reset (LVR) before being powered down. In power off mode,
the pin input and output specifications are not guaranteed.
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MOTOROLA
In reset mode, the internal BDLC voltage references are operative, VDD
is supplied to the internal circuits which are held in their reset state, and
the internal BDLC system clock is running. Registers will assume their
reset condition. Because outputs are held in their programmed reset
state, inputs and network activity are ignored.
20.4.1.3 Run Mode
This mode is entered from reset mode after all MCU reset sources are
no longer asserted. Run mode is entered from the BDLC wait mode
whenever activity is sensed on the J1850 bus.
Run mode is entered from the BDLC stop mode whenever network
activity is sensed, although messages will not be received properly until
the clocks have stabilized and the CPU is also in run mode.
In this mode, normal network operation takes place. The user should
ensure that all BDLC transmissions have ceased before exiting this
mode.
20.4.1.4 BDLC Wait Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and if the WCM bit in
the BCR1 register is cleared previously.
In this mode, the BDLC internal clocks continue to run. The first
passive-to-active transition of the bus generates a CPU interrupt request
from the BDLC, which wakes up the BDLC and the CPU. In addition, if
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A G R E E M E N T
This mode is entered from power off mode whenever the BDLC supply
voltage, VDD, rises above its minimum specified value
(VDD –10%) and some MCU reset source is asserted. The internal MCU
reset must be asserted while powering up the BDLC or an unknown
state will be entered and correct operation cannot be guaranteed. Reset
mode is also entered from any other mode as soon as one of the MCU’s
possible reset sources (such as LVR, POR, COP watchdog, reset pin,
etc.) is asserted.
N O N - D I S C L O S U R E
20.4.1.2 Reset Mode
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
Functional Description
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
the BDLC receives a valid end-of-frame (EOF) symbol while operating in
wait mode, then the BDLC also will generate a CPU interrupt request,
which wakes up the BDLC and the CPU. See 20.8.1 Wait Mode.
20.4.1.5 BDLC Stop Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BCR1 ($003E) is set
previously.
In this mode, the BDLC internal clocks are stopped but the physical
interface circuitry is placed in a low-power mode and awaits network
activity. If network activity is sensed, then a CPU interrupt request will be
generated, restarting the BDLC internal clocks. See 20.8.2 Stop Mode.
20.4.1.6 Digital Loopback Mode
When a bus fault has been detected, the digital loopback mode is used
to determine if the fault condition is caused by failure in the node’s
internal circuits or elsewhere in the network, including the node’s analog
physical interface. In this mode, the transmit digital output pin (BDTxD)
and the receive digital input pin (BDRxD) of the digital interface are
disconnected from the analog physical interface and tied together to
allow the digital portion of the BDLC to transmit and receive its own
messages without driving the J1850 bus.
20.4.1.7 Analog Loopback Mode
Analog loopback mode is used to determine if a bus fault has been
caused by a failure in the node’s off-chip analog transceiver or
elsewhere in the network. The BCLD analog loopback mode does not
modify the digital transmit or receive functions of the BDLC. It does,
however, ensure that once analog loopback mode is exited, the BDLC
will wait for an idle bus condition before participation in network
communication resumes. If the off-chip analog transceiver has a
loopback mode, it usually causes the input to the output drive stage to
be looped back into the receiver, allowing the node to receive messages
it has transmitted without driving the J1850 bus. In this mode, the output
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MOTOROLA
20.5 BDLC MUX Interface
The MUX interface is responsible for bit encoding/decoding and digital
noise filtering between the protocol handler and the physical interface.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
A G R E E M E N T
to the J1850 bus typically is high impedance. This allows the
communication path through the analog transceiver to be tested without
interfering with network activity. Using the BDLC analog loopback mode
in conjunction with the analog transceiver’s loopback mode ensures
that, once the off-chip analog transceiver has exited loopback mode, the
BCLD will not begin communicating before a known condition exists on
the J1850 bus.
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC MUX Interface
N O N - D I S C L O S U R E
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 20-4. BDLC Block Diagram
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20.5.1 Rx Digital Filter
The receiver section of the BDLC includes a digital low pass filter to
remove narrow noise pulses from the incoming message. An outline of
the digital filter is shown in Figure 20-5.
RX DATA
FROM
PHYSICAL
INTERFACE
(BDRxD)
INPUT
SYNC
D
Q
DATA
LATCH
4-BIT UP/DOWN COUNTER
UP/DOWN
OUT
FILTERED
RX DATA OUT
D
Q
MUX
INTERFACE
CLOCK
Figure 20-5. BDLC Rx Digital Filter Block Diagram
20.5.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see
fBDLC parameter in Table 20-3). At each positive edge of the clock
signal, the current state of the receiver physical interface (BDRxD) signal
is sampled. The BDRxD signal state is used to determine whether the
counter should increment or decrement at the next negative edge of the
clock signal.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
The counter will increment if the input data sample is high but decrement
if the input sample is low. Therefore, the counter will thus progress either
up toward 15 if, on average, the BDRxD signal remains high or progress
down toward 0 if, on average, the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter
decides that the condition of the BDRxD signal is at a stable logic level
1 and the data latch is set, causing the filtered Rx data signal to become
a logic level 1. Furthermore, the counter is prevented from overflowing
and can be decremented only from this state.
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MOTOROLA
Alternatively, should the counter eventually reach the value 0, the digital
filter decides that the condition of the BDRxD signal is at a stable logic
level 0 and the data latch is reset, causing the filtered Rx data signal to
become a logic level 0. Furthermore, the counter is prevented from
underflowing and can only be incremented from this state.
The data latch will retain its value until the counter next reaches the
opposite end point, signifying a definite transition of the signal.
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC MUX Interface
If the signal on the BDRxD signal transitions, then there will be a delay
before that transition appears at the filtered Rx data output signal. This
delay will be between 15 and 16 clock periods, depending on where the
transition occurs with respect to the sampling points. This filter delay
must be taken into account when performing message arbitration.
For example, if the frequency of the MUX interface clock (fBDLC) is
1.0486 MHz, then the period (tBDLC) is 954 ns and the maximum filter
delay in the absence of noise will be 15.259 µs.
The effect of random noise on the BDRxD signal depends on the
characteristics of the noise itself. Narrow noise pulses on the BDRxD
signal will be ignored completely if they are shorter than the filter delay.
This provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition
can be delayed by an amount equal to the length of the noise burst. This
is just a reflection of the uncertainty of where the transition is truly
occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the
shortest allowable symbol length, will be detected by the next stage of
the BDLC’s receiver as an invalid symbol.
Noise pulses that are longer than the shortest allowable symbol length
will be detected normally as an invalid symbol or as invalid data when
the frame’s CRC is checked.
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N O N - D I S C L O S U R E
The performance of the digital filter is best described in the time domain
rather than the frequency domain.
A G R E E M E N T
20.5.1.2 Performance
20.5.2 J1850 Frame Format
All messages transmitted on the J1850 bus are structured using the
format shown in Figure 20-6.
J1850 states that each message has a maximum length of 101 PWM bit
times or 12 VPW bytes, excluding SOF, EOD, NB, and EOF, with each
byte transmitted most significant bit (MSB) first.
All VPW symbol lengths described here are typical values at a 10.4-kbps
bit rate.
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
SOF — Start-of-Frame Symbol
All messages transmitted onto the J1850 bus must begin with a
long-active 200 µs period SOF symbol. This indicates the start of a
new message transmission. The SOF symbol is not used in the CRC
calculation.
Data — In-Message Data Bytes
The data bytes contained in the message include the message
priority/type, message ID byte (typically the physical address of the
responder), and any actual data being transmitted to the receiving
node. The message format used by the BDLC is similar to the 3-byte
consolidated header message format outlined by the SAE J1850
document. See SAE J1850 Class B Data Communications Network
Interface for more information about 1- and 3-byte headers.
Messages transmitted by the BDLC onto the J1850 bus must contain
at least one data byte, and, therefore, can be as short as one data
byte and one CRC byte. Each data byte in the message is eight bits
in length and is transmitted MSB to LSB (least significant bit).
DATA
IDLE
SOF
PRIORITY
(DATA0)
MESSAGE ID
(DATA1)
DATAN
CRC
E
O
D
OPTIONAL
N
B
IFR
EOF
I
F
S
IDLE
Figure 20-6. J1850 Bus Message Format (VPW)
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This byte is used by the receiver(s) of each message to determine if
any errors have occurred during the transmission of the message.
The BDLC calculates the CRC byte and appends it onto any
messages transmitted onto the J1850 bus. It also performs CRC
detection on any messages it receives from the J1850 bus.
CRC generation uses the divisor polynomial X8 + X4 + X3 + X2 + 1.
The remainder polynomial initially is set to all ones. Each byte in the
message after the start-of-frame (SOF) symbol is processed serially
through the CRC generation circuitry. The one’s complement of the
remainder then becomes the 8-bit CRC byte, which is appended to
the message after the data bytes, in MSB-to-LSB order.
When receiving a message, the BDLC uses the same divisor
polynomial. All data bytes, excluding the SOF and end of data
symbols (EOD) but including the CRC byte, are used to check the
CRC. If the message is error free, the remainder polynomial will equal
X7 + X6 + X2 = $C4, regardless of the data contained in the message.
If the calculated CRC does not equal $C4, the BDLC will recognize
this as a CRC error and set the CRC error flag in the BSVR ($003E).
A G R E E M E N T
CRC — Cyclical Redundancy Check Byte
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC MUX Interface
The EOD symbol is a long 200-µs passive period on the J1850 bus
used to signify to any recipients of a message that the transmission
by the originator has completed. No flag is set upon reception of the
EOD symbol.
IFR — In-Frame Response Bytes
The IFR section of the J1850 message format is optional. Users
desiring further definition of in-frame response should review the SAE
J1850 Class B Data Communications Network Interface specification.
EOF — End-of-Frame Symbol
This symbol is a long 280-µs passive period on the J1850 bus and is
longer than an end-of-data (EOD) symbol, which signifies the end of
a message. Since an EOF symbol is longer than a 200-µs EOD
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N O N - D I S C L O S U R E
EOD — End-of-Data Symbol
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
symbol, if no response is transmitted after an EOD symbol, it
becomes an EOF, and the message is assumed to be completed. The
EOF flag is set upon receiving the EOF symbol.
IFS — Inter-Frame Separation Symbol
A G R E E M E N T
The IFS symbol is a 20-µs passive period on the J1850 bus which
allows proper synchronization between nodes during continuous
message transmission. The IFS symbol is transmitted by a node after
the completion of the end-of-frame (EOF) period and, therefore is
seen as a 300-µs passive period.
When the last byte of a message has been transmitted onto the J1850
bus and the EOF symbol time has expired, all nodes then must wait
for the IFS symbol time to expire before transmitting a start-of-frame
(SOF) symbol, marking the beginning of another message.
However, if the BDLC is waiting for the IFS period to expire before
beginning a transmission and a rising edge is detected before the IFS
time has expired, it will synchronize internally to that edge.
N O N - D I S C L O S U R E
A rising edge may occur during the IFS period because of varying
clock tolerances and loading of the J1850 bus, causing different
nodes to observe the completion of the IFS period at different times.
To allow for individual clock tolerances, receivers must synchronize to
any SOF occurring during an IFS period.
BREAK — Break
The BDLC cannot transmit a BREAK symbol.
If the BDLC is transmitting at the time a BREAK is detected, it treats
the BREAK as if a transmission error had occurred and halts
transmission.
If the BDLC detects a BREAK symbol while receiving a message, it
treats the BREAK as a reception error and sets the invalid symbol flag
in the BSVR, also ignoring the frame it was receiving. If while
receiving a message in 4X mode, the BDLC detects a BREAK
symbol, it treats the BREAK as a reception error, sets the invalid
symbol flag, and exits 4X mode (the RX4XE bit in BCR2 is cleared
automatically). If bus control is required after the BREAK symbol is
received and the IFS time has elapsed, the programmer must resend
the transmission byte using highest priority.
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NOTE:
The J1850 protocol BREAK symbol is not related to the HC08 Break
Module (See Section 11. Break Module (Break).)
IDLE — Idle Bus
An idle condition exists on the bus during any passive period after
expiration of the IFS period (for example, > 300 µs). Any node sensing
an idle bus condition can begin transmission immediately.
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC MUX Interface
Each logic 1 or logic 0 contains a single transition and can be at either
the active or passive level and one of two lengths, either 64 µs or 128 µs
(tNOM at 10.4 kbps baud rate), depending upon the encoding of the
previous bit. The start-of-frame (SOF), end-of-data (EOD), end-of-frame
(EOF), and inter-frame separation (IFS) symbols always will be encoded
at an assigned level and length. See Figure 20-7.
Each message will begin with an SOF symbol, an active symbol, and,
therefore, each data byte (including the CRC byte) will begin with a
passive bit, regardless of whether it is a logic 1 or a logic 0.
All VPW bit lengths stated here are typical values at a 10.4-kbps bit rate.
EOF, EOD, IFS, and IDLE, however, are not driven J1850 bus states.
They are passive bus periods observed by each node’s CPU.
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N O N - D I S C L O S U R E
Huntsinger’s variable pulse width modulation (VPW) is an encoding
technique in which each bit is defined by the time between successive
transitions and by the level of the bus between transitions, (for instance,
active or passive). Active and passive bits are used alternately. This
encoding technique is used to reduce the number of bus transitions for
a given bit rate.
A G R E E M E N T
20.5.3 J1850 VPW Symbols
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
Logic 0
A logic 0 is defined as either:
– An active-to-passive transition followed by a passive period
64 µs in length, or
– A passive-to-active transition followed by an active period
128 µs in length
A G R E E M E N T
See Figure 20-7(a).
ACTIVE
128 µs
OR
64 µs
OR
64 µs
PASSIVE
(A) LOGIC 0
ACTIVE
128 µs
PASSIVE
N O N - D I S C L O S U R E
(B) LOGIC 1
ACTIVE
200 µs
≥ 240 µs
200 µs
PASSIVE
(C) BREAK
(D) START OF FRAME
(E) END OF DATA
300 µs
ACTIVE
280 µs
20 µs
IDLE > 300 µs
PASSIVE
(F) END OF FRAME
(G) INTER-FRAME
SEPARATION
(H) IDLE
Figure 20-7. J1850 VPW Symbols with Nominal Symbol Times
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Logic 1
A logic 1 is defined as either:
– An active-to-passive transition followed by a passive period
128 µs in length, or
– A passive-to-active transition followed by an active period
64 µs in length
See Figure 20-7(b).
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC MUX Interface
Break Signal (BREAK)
The BREAK signal is defined as a passive-to-active transition
followed by an active period of at least 240 µs (see Figure 20-7(c)).
Start-of-Frame Symbol (SOF)
The SOF symbol is defined as passive-to-active transition followed by
an active period 200 µs in length (see Figure 20-7(d)). This allows the
data bytes which follow the SOF symbol to begin with a passive bit,
regardless of whether it is a logic 1 or a logic 0.
End-of-Data Symbol (EOD)
The EOD symbol is defined as an active-to-passive transition
followed by a passive period 200 µs in length (see Figure 20-7(e)).
End-of-Frame Symbol (EOF)
The EOF symbol is defined as an active-to-passive transition followed
by a passive period 280 µs in length (see Figure 20-7(f)). If no IFR
byte is transmitted after an EOD symbol is transmitted, after another
80 µs the EOD becomes an EOF, indicating completion of the
message.
Inter-Frame Separation Symbol (IFS)
The IFS symbol is defined as a passive period 300 µs in length. The
20-µs IFS symbol contains no transition, since when it is used it
always appends to a 280-µs EOF symbol (see Figure 20-7(g)).
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N O N - D I S C L O S U R E
The NB symbol has the same property as a logic 1 or a logic 0. It is
only used in IFR message responses.
A G R E E M E N T
Normalization Bit (NB)
Idle
An idle is defined as a passive period greater than 300 µs in length.
20.5.4 J1850 VPW Valid/Invalid Bits and Symbols
The timing tolerances for receiving data bits and symbols from the
J1850 bus have been defined to allow for variations in oscillator
frequencies. In many cases, the maximum time allowed to define a data
bit or symbol is equal to the minimum time allowed to define another data
bit or symbol.
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
Since the minimum resolution of the BDLC for determining what symbol
is being received is equal to a single period of the MUX interface clock
(tBDLC), an apparent separation in these maximum time/minimum time
concurrences equals one cycle of tBDLC.
This one clock resolution allows the BDLC to differentiate properly
between the different bits and symbols. This is done without reducing the
valid window for receiving bits and symbols from transmitters onto the
J1850 bus, which has varying oscillator frequencies.
N O N - D I S C L O S U R E
In Huntsinger’s variable pulse width (VPW) modulation bit encoding, the
tolerances for both the passive and active data bits received and the
symbols received are defined with no gaps between definitions. For
example, the maximum length of a passive logic 0 is equal to the
minimum length of a passive logic 1, and the maximum length of an
active logic 0 is equal to the minimum length of a valid SOF symbol.
Invalid Passive Bit
See Figure 20-8(1). If the passive-to-active received transition
beginning the next data bit or symbol occurs between the
active-to-passive transition beginning the current data bit (or symbol)
and a, the current bit would be invalid.
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200 µs
128 µs
64 µs
ACTIVE
(1) INVALID PASSIVE BIT
PASSIVE
a
ACTIVE
(2) VALID PASSIVE LOGIC 0
PASSIVE
(3) VALID PASSIVE LOGIC 1
PASSIVE
b
c
ACTIVE
(4) VALID EOD SYMBOL
PASSIVE
c
d
Figure 20-8. J1850 VPW Received Passive Symbol Times
Valid Passive Logic 0
See Figure 20-8(2). If the passive-to-active received transition
beginning the next data bit (or symbol) occurs between a and b, the
current bit would be considered a logic 0.
Valid Passive Logic 1
See Figure 20-8(3). If the passive-to-active received transition
beginning the next data bit (or symbol) occurs between b and c, the
current bit would be considered a logic 1.
Valid EOD Symbol
See Figure 20-8(4). If the passive-to-active received transition
beginning the next data bit (or symbol) occurs between c and d, the
current symbol would be considered a valid end-of-data symbol
(EOD).
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A G R E E M E N T
b
ACTIVE
N O N - D I S C L O S U R E
a
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC MUX Interface
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
300 µs
280 µs
ACTIVE
(1) VALID EOF SYMBOL
PASSIVE
a
b
ACTIVE
(2) VALID EOF+
IFS SYMBOL
A G R E E M E N T
PASSIVE
c
d
Figure 20-9. J1850 VPW Received Passive
EOF and IFS Symbol Times
Valid EOF and IFS Symbols
In Figure 20-9(1), if the passive-to-active received transition
beginning the SOF symbol of the next message occurs between a
and b, the current symbol will be considered a valid end-of-frame
(EOF) symbol.
N O N - D I S C L O S U R E
See Figure 20-9(2). If the passive-to-active received transition
beginning the SOF symbol of the next message occurs between c
and d, the current symbol will be considered a valid EOF symbol
followed by a valid inter-frame separation symbol (IFS). All nodes
must wait until a valid IFS symbol time has expired before beginning
transmission. However, due to variations in clock frequencies and bus
loading, some nodes may recognize a valid IFS symbol before others
and immediately begin transmitting. Therefore, any time a node
waiting to transmit detects a passive-to-active transition once a valid
EOF has been detected, it should immediately begin transmission,
initiating the arbitration process.
Idle Bus
In Figure 20-9(2), if the passive-to-active received transition
beginning the start-of-frame (SOF) symbol of the next message does
not occur before d, the bus is considered to be idle, and any node
wishing to transmit a message may do so immediately.
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200 µs
128 µs
64 µs
ACTIVE
(1) INVALID ACTIVE BIT
PASSIVE
a
ACTIVE
(2) VALID ACTIVE LOGIC 1
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC MUX Interface
b
(3) VALID ACTIVE LOGIC 0
PASSIVE
b
c
ACTIVE
(4) VALID SOF SYMBOL
PASSIVE
c
d
Figure 20-10. J1850 VPW Received Active Symbol Times
Invalid Active Bit
In Figure 20-10(1), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between the
passive-to-active transition beginning the current data bit (or symbol)
and a, the current bit would be invalid.
Valid Active Logic 1
In Figure 20-10(2), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between a and b, the
current bit would be considered a logic 1.
Valid Active Logic 0
In Figure 20-10(3), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between b and c, the
current bit would be considered a logic 0.
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N O N - D I S C L O S U R E
a
ACTIVE
A G R E E M E N T
PASSIVE
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
Valid SOF Symbol
In Figure 20-10(4), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between c and d, the
current symbol would be considered a valid SOF symbol.
Valid BREAK Symbol
N O N - D I S C L O S U R E
A G R E E M E N T
In Figure 20-11, if the next active-to-passive received transition does
not occur until after e, the current symbol will be considered a valid
BREAK symbol. A BREAK symbol should be followed by a
start-of-frame (SOF) symbol beginning the next message to be
transmitted onto the J1850 bus. See 20.5.2 J1850 Frame Format for
BDLC response to BREAK symbols.
240 µs
ACTIVE
(2) VALID BREAK SYMBOL
PASSIVE
e
Figure 20-11. J1850 VPW Received BREAK Symbol Times
20.5.5 Message Arbitration
Message arbitration on the J1850 bus is accomplished in a
non-destructive manner, allowing the message with the highest priority
to be transmitted, while any transmitters which lose arbitration simply
stop transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that
another message is in progress, it waits until the bus is idle. However, if
multiple nodes begin to transmit in the same synchronization window,
message arbitration will occur beginning with the first bit after the SOF
symbol and continue with each bit thereafter. If a write to the BDR
($003F) (for instance, to initiate transmission) occurred on or before
104 • tBDLC from the received rising edge, then the BDLC will transmit
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The variable pulse width modulation (VPW) symbols and J1850 bus
electrical characteristics are chosen carefully so that a logic 0 (active or
passive type) will always dominate over a logic 1 (active or passive type)
simultaneously transmitted. Hence, logic 0s are said to be dominant and
logic 1s are said to be recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted
a recessive bit, it loses arbitration and immediately stops transmitting.
This is known as bitwise arbitration.
Since a logic 0 dominates a logic 1, the message with the lowest value
will have the highest priority and will always win arbitration. For instance,
a message with priority 000 will win arbitration over a message with
priority 011.
0
1
1
0
1
1
N O N - D I S C L O S U R E
This method of arbitration will work no matter how many bits of priority
encoding are contained in the message.
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
1
ACTIVE
TRANSMITTER A
PASSIVE
0
0
ACTIVE
TRANSMITTER B
PASSIVE
0
1
1
0
0
DATA
DATA
DATA
DATA
DATA
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
TRANSMITTER B WINS
ARBITRATION AND
CONTINUES
TRANSMITTING
ACTIVE
J1850 BUS
PASSIVE
SOF
Figure 20-12. J1850 VPW Bitwise Arbitrations
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A G R E E M E N T
and arbitrate for the bus. If a CPU write to the BDR occurred after
104 • tBDLC from the detection of the rising edge, then the BDLC will not
transmit, but will wait for the next IFS period to expire before attempting
to transmit the byte.
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC MUX Interface
351
During arbitration, or even throughout the transmitting message, when
an opposite bit is detected, transmission is stopped immediately unless
it occurs on the 8th bit of a byte. In this case, the BDLC automatically will
append up to two extra logic 1 bits and then stop transmitting. These two
extra bits will be arbitrated normally and thus will not interfere with
another message. The second logic 1 bit will not be sent if the first loses
arbitration. If the BDLC has lost arbitration to another valid message,
then the two extra logic 1s will not corrupt the current message.
However, if the BDLC has lost arbitration due to noise on the bus, then
the two extra logic 1s will ensure that the current message will be
detected and ignored as a noise-corrupted message.
20.6 BDLC Protocol Handler
The protocol handler is responsible for framing, arbitration, CRC
generation/checking, and error detection. The protocol handler
conforms to SAE J1850 Class B Data Communications Network
Interface.
NOTE:
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
Motorola assumes that the reader is familiar with the J1850 specification
before reading this protocol handler description.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 20-13. BDLC Block Diagram
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20.6.1 Protocol Architecture
The protocol handler contains the state machine, Rx shadow register, Tx
shadow register, Rx shift register, Tx shift register, and loopback
multiplexer as shown in Figure 20-14.
TO PHYSICAL INTERFACE
A G R E E M E N T
ALOOP
BDTxD
CONTROL
LOOPBACK
MULTIPLEXER
RxD
DLOOP FROM BCR2
LOOPBACK CONTROL
BDTxD
STATE MACHINE
Tx SHADOW REGISTER
8
Tx DATA
Rx SHADOW REGISTER
CONTROL
Tx SHIFT REGISTER
Rx DATA
Rx SHIFT REGISTER
8
TO CPU INTERFACE AND Rx/Tx BUFFERS
Figure 20-14. BDLC Protocol Handler Outline
20.6.2 Rx and Tx Shift Registers
The Rx shift register gathers received serial data bits from the J1850 bus
and makes them available in parallel form to the Rx shadow register.
The Tx shift register takes data, in parallel form, from the Tx shadow
register and presents it serially to the state machine so that it can be
transmitted onto the J1850 bus.
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N O N - D I S C L O S U R E
BDRxD
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC Protocol Handler
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
20.6.3 Rx and Tx Shadow Registers
Immediately after the Rx shift register has completed shifting in a byte of
data, this data is transferred to the Rx shadow register and RDRF or
RXIFR is set (see 20.7.4 BDLC State Vector Register). An interrupt is
generated if the interrupt enable bit (IE) in BCR1 is set. After the transfer
takes place, this new data byte in the Rx shadow register is available to
the CPU interface, and the Rx shift register is ready to shift in the next
byte of data. Data in the Rx shadow register must be retrieved by the
CPU before it is overwritten by new data from the Rx shift register.
Once the Tx shift register has completed its shifting operation for the
current byte, the data byte in the Tx shadow register is loaded into the
Tx shift register. After this transfer takes place, the Tx shadow register
is ready to accept new data from the CPU when the TDRE flag in the
BSVR is set.
20.6.4 Digital Loopback Multiplexer
The digital loopback multiplexer connects RxD to either BDTxD or
BDRxD, depending on the state of the DLOOP bit in the BCR2 ($003D)
(See 20.7.3 BDLC Control Register 2).
20.6.5 State Machine
All functions associated with performing the protocol are executed or
controlled by the state machine. The state machine is responsible for
framing, collision detection, arbitration, CRC generation/checking, and
error detection. These subsections describe the BDLC’s actions in a
variety of situations.
20.6.5.1 4X Mode
The BDLC can exist on the same J1850 bus as modules which use a
special 4X (41.6 kbps) mode of J1850 variable pulse width modulation
(VPW) operation. The BDLC cannot transmit in 4X mode, but it can
receive messages in 4X mode, if the RX4X bit is set in BCR2. If the
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Although not a part of the SAE J1850 protocol, the BDLC does allow for
a special block mode of operation of the receiver. As far as the BDLC is
concerned, a block mode message is simply a long J1850 frame that
contains an indefinite number of data bytes. All other features of the
frame remain the same, including the SOF, CRC, and EOD symbols.
Another node wishing to send a block mode transmission must first
inform all other nodes on the network that this is about to happen. This
is usually accomplished by sending a special predefined message.
20.6.5.3 Transmitting a Message in Block Mode
A block mode message is transmitted inherently by simply loading the
bytes one by one into the BDR until the message is complete. The
programmer should wait until the TDRE flag (see 20.7.4 BDLC State
Vector Register) is set prior to writing a new byte of data into the BDR.
The BDLC does not contain any predefined maximum J1850 message
length requirement.
20.6.5.4 J1850 Bus Errors
The BDLC detects several types of transmit and receive errors which
can occur during the transmission of a message onto the J1850 bus.
Transmission Error
If the message transmitted by the BDLC contains invalid bits or
framing symbols on non-byte boundaries, this constitutes a
transmission error. When a transmission error is detected, the BDLC
immediately will cease transmitting. The error condition ($1C) is
reflected in the BSVR (see Table 20-5). If the interrupt enable bit (IE
in BCR1) is set, a CPU interrupt request from the BDLC is generated.
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A G R E E M E N T
20.6.5.2 Receiving a Message in Block Mode
N O N - D I S C L O S U R E
RX4X bit is not set in the BCR2, any 4X message on the J1850 bus is
treated as noise by the BDLC and is ignored.
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC Protocol Handler
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
CRC Error
A cyclical redundancy check (CRC) error is detected when the data
bytes and CRC byte of a received message are processed and the
CRC calculation result is not equal. The CRC code will detect any
single and 2-bit errors, as well as all 8-bit burst errors and almost all
other types of errors. The CRC error flag ($18 in BSVR) is set when
a CRC error is detected. (See 20.7.4 BDLC State Vector Register.)
Symbol Error
A G R E E M E N T
A symbol error is detected when an abnormal (invalid) symbol is
detected in a message being received from the J1850 bus. The ($1C)
invalid symbol is set when a symbol error is detected. (See 20.7.4
BDLC State Vector Register.)
Framing Error
N O N - D I S C L O S U R E
A framing error is detected if an EOD or EOF symbol is detected on a
non-byte boundary from the J1850 bus. A framing error also is
detected if the BDLC is transmitting the EOD and instead receives an
active symbol. The ($1C) symbol invalid, or the out-of-range flag, is
set when a framing error is detected. (See 20.7.4 BDLC State Vector
Register.)
Bus Fault
If a bus fault occurs, the response of the BDLC will depend upon the
type of bus fault.
If the bus is shorted to battery, the BDLC will wait for the bus to fall to
a passive state before it will attempt to transmit a message. As long
as the short remains, the BDLC will never attempt to transmit a
message onto the J1850 bus.
If the bus is shorted to ground, the BDLC will see an idle bus, begin
to transmit the message, and then detect a transmission error ($1C in
BSVR), since the short to ground would not allow the bus to be driven
to the active (dominant) SOF state. The BDLC will abort that
transmission and wait for the next CPU command to transmit.
Advance Information
356
MC68HC708AS48 — Rev. 4.0
Byte Data Link Controller–Digital (BDLC–D)
MOTOROLA
If a BREAK symbol is received while the BDLC is transmitting or
receiving, an invalid symbol ($1C in BSVR) interrupt will be
generated. Reading the BSVR ($0003E) (see 20.7.4 BDLC State
Vector Register) will clear this interrupt condition. The BDLC will wait
for the bus to idle, then wait for a start-of-frame (SOF) symbol.
The BDLC cannot transmit a BREAK symbol. It only can receive a
BREAK symbol from the J1850 bus.
20.6.5.5 Summary
Table 20-1. BDLC J1850 Bus Error Summary
Error Condition
BDLC Function
Transmission error
For invalid bits or framing symbols on non-byte boundaries, invalid
symbol interrupt will be generated. BDLC stops transmission.
Cyclical redundancy check (CRC) error
CRC error interrupt will be generated. The BDLC will wait for EOF.
Invalid symbol: BDLC transmits, but
receives invalid bits (noise)
The BDLC will abort transmission immediately. Invalid symbol
interrupt will be generated.
Framing error
Invalid symbol interrupt will be generated. The BDLC will wait for
end-of-frame (EOF).
Bus short to VDD
The BDLC will not transmit until the bus is idle. Invalid symbol
interrupt will be generated. EOF interrupt also must be seen before
another transmission attempt. Depending on length of the short,
LOA flag also may be set.
Bus short to GND
Thermal overload will shut down physical interface. Fault condition is
seen as invalid symbol flag. EOF interrupt must also be seen
before another transmission attempt.
BDLC receives BREAK symbol
Invalid symbol interrupt will be generated. The BDLC will wait for the
next valid SOF.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Byte Data Link Controller–Digital (BDLC–D)
357
A G R E E M E N T
BREAK — Break
N O N - D I S C L O S U R E
In any case, if the bus fault is temporary, as soon as the fault is
cleared, the BDLC will resume normal operation. If the bus fault is
permanent, it may result in permanent loss of communication on the
J1850 bus. (See 20.7.4 BDLC State Vector Register.)
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC Protocol Handler
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
20.7 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the
BDLC and consists of five user registers.
TO CPU
N O N - D I S C L O S U R E
A G R E E M E N T
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 20-15. BDLC Block Diagram
20.7.1 BDLC Analog and Roundtrip Delay
This register programs the BDLC to compensate for various delays of
different external transceivers. The default delay value is 16 µs. Timing
adjustments from 9 µs to 24 µs in steps of 1 µs are available. The BARD
register can be written only once after each reset, after which they
become read-only bits. The register may be read at any time.
Address:
Read:
Write:
Reset:
$003B
Bit 7
6
ATE
RXPOL
1
1
R
= Reserved
5
4
0
0
R
R
0
0
3
2
1
Bit 0
BO3
BO2
BO1
BO0
0
1
1
1
Figure 20-16. BDLC Analog and Roundtrip Delay Register (BARD)
Advance Information
358
MC68HC708AS48 — Rev. 4.0
Byte Data Link Controller–Digital (BDLC–D)
MOTOROLA
ATE — Analog Transceiver Enable Bit
The analog transceiver enable (ATE) bit is used to select either the
on-board or an off-chip analog transceiver.
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
NOTE:
This device does not contain an on-board transceiver. This bit should be
programmed to a logic 0 for proper operation.
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC CPU Interface
The receive pin polarity (RXPOL) bit is used to select the polarity of
an incoming signal on the receive pin. Some external analog
transceivers invert the receive signal from the J1850 bus before
feeding it back to the digital receive pin.
1 = Select normal/true polarity; true non-inverted signal from the
J1850 bus; for example, the external transceiver does not
invert the receive signal
0 = Select inverted polarity, where an external transceiver inverts
the receive signal from the J1850 bus
BO3–BO0 — BARD Offset Bits
MC68HC708AS48 — Rev. 4.0
MOTOROLA
N O N - D I S C L O S U R E
Table 20-2 shows the expected transceiver delay with respect to
BARD offset values.
Advance Information
Byte Data Link Controller–Digital (BDLC–D)
A G R E E M E N T
RXPOL — Receive Pin Polarity Bit
359
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
Table 20-2. BDLC Transceiver Delay
Corresponding Expected
Transceiver’s Delays (µs)
0000
9
0001
10
0010
11
0011
12
0100
13
0101
14
0110
15
0111
16
1000
17
1001
18
1010
19
1011
20
1100
21
1101
22
1110
23
1111
24
N O N - D I S C L O S U R E
A G R E E M E N T
BARD Offset Bits BO[3:0]
20.7.2 BDLC Control Register 1
This register is used to configure and control the BDLC.
Address:
$003C
Bit 7
6
5
4
IMSG
CLKS
R1
R0
Read:
Write:
Reset:
1
1
R
= Reserved
1
0
3
2
0
0
R
R
0
0
1
Bit 0
IE
WCM
0
0
Figure 20-17. BDLC Control Register 1 (BCR1)
Advance Information
360
MC68HC708AS48 — Rev. 4.0
Byte Data Link Controller–Digital (BDLC–D)
MOTOROLA
This bit is used to disable the receiver until a new start-of-frame (SOF)
is detected.
1 = Disable receiver. When set, all BDLC interrupt requests will be
masked (except $20 in BSVR) and the status bits will be held
in their reset state. If this bit is set while the BDLC is receiving
a message, the rest of the incoming message will be ignored.
0 = Enable receiver. This bit is cleared automatically by the
reception of an SOF symbol or a BREAK symbol. It will then
generate interrupt requests and will allow changes of the
status register to occur. However, these interrupts may still be
masked by the interrupt enable (IE) bit.
CLKS — Clock Bit
For J1850 bus communications to take place, the nominal BDLC
operating frequency (fBDLC) must always be 1.048576 MHz or 1 MHz.
The CLKS register bit allows the user to select the frequency
(1.048576 MHz or 1 MHz) used to automatically adjust symbol timing.
1 = Binary frequency (1.048576 MHz) selected for fBDLC
0 = Integer frequency (1 MHz) selected for fBDLC
A G R E E M E N T
IMSG — Ignore Message Bit
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC CPU Interface
These bits determine the amount by which the frequency of the MCU
CGMXCLK signal is divided to form the MUX interface clock (fBDLC)
which defines the basic timing resolution of the MUX interface. They
may be written only once after reset, after which they become
read-only bits.
The nominal frequency of fBDLC must always be 1.048576 MHz or 1.0
MHz for J1850 bus communications to take place. Hence, the value
programmed into these bits is dependent on the chosen MCU system
clock frequency per Table 20-3.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Byte Data Link Controller–Digital (BDLC–D)
361
N O N - D I S C L O S U R E
R1 and R0 — Rate Select Bits
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
A G R E E M E N T
Table 20-3. BDLC Rate Selection
fXCLK Frequency
R1
R0
Division
fBDLC
1.049 MHz
0
0
1
1.049 MHz
2.097 MHz
0
1
2
1.049 MHz
4.194 MHz
1
0
4
1.049 MHz
8.389 MHz
1
1
8
1.049 MHz
1.000 MHz
0
0
1
1.00 MHz
2.000 MHz
0
1
2
1.00 MHz
4.000 MHz
1
0
4
1.00 MHz
8.000 MHz
1
1
8
1.00 MHz
IE— Interrupt Enable Bit
N O N - D I S C L O S U R E
This bit determines whether the BDLC will generate CPU interrupt
requests in run mode. It does not affect CPU interrupt requests when
exiting the BDLC stop or BDLC wait modes. Interrupt requests will be
maintained until all of the interrupt request sources are cleared by
performing the specified actions upon the BDLC’s registers. Interrupts
that were pending at the time that this bit is cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
If the programmer does not wish to use the interrupt capability of the
BDLC, the BDLC state vector register (BSVR) can be polled
periodically by the programmer to determine BDLC states. See 20.7.4
BDLC State Vector Register for a description of the BSVR.
WCM — Wait Clock Mode Bit
This bit determines the operation of the BDLC during CPU wait mode.
See 20.8.2 Stop Mode and 20.8.1 Wait Mode for more details on its
use.
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
Advance Information
362
MC68HC708AS48 — Rev. 4.0
Byte Data Link Controller–Digital (BDLC–D)
MOTOROLA
Address:
$003D
Bit 7
6
5
4
3
2
1
Bit 0
ALOOP
DLOOP
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
1
1
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 20-18. BDLC Control Register 2 (BCR2)
ALOOP — Analog Loopback Mode Bit
This bit determines whether the J1850 bus will be driven by the
analog physical interface’s final drive stage. The programmer can use
this bit to reset the BDLC state machine to a known state after the
off-chip analog transceiver is placed in loopback mode. When the
user clears ALOOP, to indicate that the off-chip analog transceiver is
no longer in loopback mode, the BDLC waits for an EOF symbol
before attempting to transmit. Most transceivers have the ALOOP
feature available.
1 = Input to the analog physical interface’s final drive stage is
looped back to the BDLC receiver. The J1850 bus is not
driven.
0 = The J1850 bus will be driven by the BDLC. After the bit is
cleared, the BDLC requires the bus to be idle for a minimum of
end-of-frame symbol time (tTRV4) before message reception or
a minimum of inter-frame symbol time (tTRV6) before message
transmission. (See 21.15 BDLC Receiver VPW Symbol
Timings.)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Byte Data Link Controller–Digital (BDLC–D)
363
A G R E E M E N T
This register controls transmitter operations of the BDLC. It is
recommended that BSET and BCLR instructions be used to manipulate
data in this register to ensure that the register’s content does not change
inadvertently.
N O N - D I S C L O S U R E
20.7.3 BDLC Control Register 2
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC CPU Interface
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
DLOOP — Digital Loopback Mode Bit
A G R E E M E N T
This bit determines the source to which the digital receive input
(BDRxD) is connected and can be used to isolate bus fault conditions
(see Figure 20-14). If a fault condition has been detected on the bus,
this control bit allows the programmer to connect the digital transmit
output to the digital receive input. In this configuration, data sent from
the transmit buffer will be reflected back into the receive buffer. If no
faults exist in the BDLC, the fault is in the physical interface block or
elsewhere on the J1850 bus.
1 = When set, BDRxD is connected to BDTxD. The BDLC is now
in digital loopback mode.
0 = When cleared, BDTxD is not connected to BDRxD. The BDLC
is taken out of digital loopback mode and can now drive or
receive the J1850 bus normally (given ALOOP is not set). After
writing DLOOP to 0, the BDLC requires the bus to be idle for a
minimum of end-of-frame symbol (ttv4) time before allowing a
reception of a message. The BDLC requires the bus to be idle
for a minimum of inter-frame separator symbol (ttv6) time
before allowing any message to be transmitted.
RX4XE — Receive 4X Enable Bit
N O N - D I S C L O S U R E
This bit determines if the BDLC operates at normal transmit and
receive speed (10.4 kbps) or receive only at 41.6 kbps. This feature
is useful for fast downloading of data into a J1850 node for diagnostic
or factory programming of the node.
1 = When set, the BDLC is put in 4X receive-only operation.
0 = When cleared, the BDLC transmits and receives at 10.4 kbps.
Reception of a BREAK symbol automatically clears this bit and
sets BDLC state vector register (BSVR $003E) to $001C.
NBFS — Normalization Bit Format Select Bit
This bit controls the format of the normalization bit (NB). (See Figure
20-19.) SAE J1850 strongly encourages using an active long (logic 0)
for in-frame responses containing cyclical redundancy check (CRC)
and an active short (logic 1) for in-frame responses without CRC.
Advance Information
364
MC68HC708AS48 — Rev. 4.0
Byte Data Link Controller–Digital (BDLC–D)
MOTOROLA
1 = NB that is received or transmitted is a 0 when the response part
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 1 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
0 = NB that is received or transmitted is a 1 when the response part
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 0 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC CPU Interface
TSIFR, TMIFR1, and TMIFR0 — Transmit In-Frame Response
Control Bits
These three bits control the type of in-frame response being sent. The
programmer should not set more than one of these control bits to a 1
at any given time. However, if more than one of these three control
bits are set to 1, the priority encoding logic will force these register bits
to a known value as shown in Table 20-4. For example, if 011 is
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Byte Data Link Controller–Digital (BDLC–D)
365
N O N - D I S C L O S U R E
This bit is set by the programmer to indicate the end of a message is
being sent by the BDLC. It will append an 8-bit CRC after completing
transmission of the current byte. This bit also is used to end an
in-frame response (IFR). If the transmit shadow register is full when
TEOD is set, the CRC byte will be transmitted after the current byte in
the Tx shift register and the byte in the Tx shadow register have been
transmitted. (See 20.6.3 Rx and Tx Shadow Registers for a
description of the transmit shadow register.) Once TEOD is set, the
transmit data register empty flag (TDRE) in the BDLC state vector
register (BSVR) is cleared to allow lower priority interrupts to occur.
(See 20.7.4 BDLC State Vector Register.)
1 = Transmit end-of-data (EOD) symbol
0 = The TEOD bit will be cleared automatically at the rising edge of
the first CRC bit that is sent or if an error is detected. When
TEOD is used to end an IFR transmission, TEOD is cleared
when the BDLC receives back a valid EOD symbol or an error
condition occurs.
A G R E E M E N T
TEOD — Transmit End of Data Bit
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
written to TSIFR, TMIFR1, and TMIFR0, then internally they will be
encoded as 010. However, when these bits are read back, they will
read 011.
A G R E E M E N T
Table 20-4. BDLC Transmit In-Frame Response
Control Bit Priority Encoding
Write/Read
TSIFR
Write/Read
TMIFR1
Write/Read
TMIFR0
Actual
TSIFR
Actual
TMIFR1
Actual
TMIFR0
0
0
0
0
0
0
1
X
X
1
0
0
0
1
X
0
1
0
0
0
1
0
0
1
N O N - D I S C L O S U R E
The BDLC supports the in-frame response (IFR) feature of J1850 by
setting these bits correctly. The four types of J1850 IFR are shown in
Figure 20-19. The purpose of the in-frame response modes is to
allow multiple nodes to acknowledge receipt of the data by
responding with their personal ID or physical address in a
concatenated manner after they have seen the EOD symbol. If
transmission arbitration is lost by a node while sending its response,
it continues to transmit its ID/address until observing its unique byte
in the response stream. For VPW modulation, the first bit of the IFR is
always passive; therefore, a normalization bit (active) must be
generated by the responder and sent prior to its ID/address byte.
When there are multiple responders on the J1850 bus, only one
normalization bit is sent which assists all other transmitting nodes to
sync their responses.
Advance Information
366
MC68HC708AS48 — Rev. 4.0
Byte Data Link Controller–Digital (BDLC–D)
MOTOROLA
DATA FIELD
NB
EOF
EOD
SOF
HEADER
ID
TYPE 1 — SINGLE BYTE TRANSMITTED FROM A SINGLE RESPONDER
NB
ID1
ID N
EOF
EOD
CRC
DATA FIELD
EOD
SOF
HEADER
TYPE 2 — SINGLE BYTE TRANSMITTED FROM MULTIPLE RESPONDERS
CRC
NB
IFR DATA FIELD
CRC
(OPTIONAL)
EOF
EOD
DATA FIELD
EOD
SOF
HEADER
TYPE 3 — MULTIPLE BYTES TRANSMITTED FROM A SINGLE RESPONDER
NB = Normalization bit
ID = Identifier, usually the physical address of the responder(s)
Figure 20-19. Types of In-Frame Response (IFR)
TSIFR — Transmit Single Byte IFR with No CRC (Type 1 or 2) Bit
The TSIFR bit is used to request the BDLC to transmit the byte in the
BDLC data register (BDR, $003F) as a single byte IFR with no CRC.
Typically, the byte transmitted is a unique identifier or address of the
transmitting (responding) node. See Figure 20-19.
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received the BDLC will
attempt to transmit the appropriate normalization bit followed
by the byte in the BDR.
0 = The TSIFR bit will be cleared automatically, once the BDLC
has successfully transmitted the byte in the BDR onto the
bus, or TEOD is set, or an error is detected on the bus.
If the programmer attempts to set the TSIFR bit immediately after the
EOD symbol has been received from the bus, the TSIFR bit will remain
in the reset state and no attempt will be made to transmit the IFR byte.
If a loss of arbitration occurs when the BDLC attempts to transmit and
after the IFR byte winning arbitration completes transmission, the BDLC
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Byte Data Link Controller–Digital (BDLC–D)
367
A G R E E M E N T
CRC
TYPE 0 — NO IFR
N O N - D I S C L O S U R E
CRC
EOD
DATA FIELD
EOF
EOD
SOF
HEADER
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC CPU Interface
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
will again attempt to transmit the BDR (with no normalization bit). The
BDLC will continue transmission attempts until an error is detected on
the bus, or TEOD is set, or the BDLC transmission is successful.
If loss of arbitration occurs in the last two bits of the IFR byte, two
additional 1 bits will not be sent out because the BDLC will attempt to
retransmit the byte in the transmit shift register after the IRF byte winning
arbitration completes transmission.
A G R E E M E N T
TMIFR1 — Transmit Multiple Byte IFR with CRC (Type 3) Bit
N O N - D I S C L O S U R E
The TMIFR1 bit requests the BDLC to transmit the byte in the BDLC
data register (BDR) as the first byte of a multiple byte IFR with CRC
or as a single byte IFR with CRC. Response IFR bytes are still subject
to J1850 message length maximums (see 20.5.2 J1850 Frame
Format). See Figure 20-19
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received, the BDLC will
attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last
IFR byte has been written into the BDR. After TEOD has been
set and the last IFR byte has been transmitted, the CRC byte
is transmitted.
0 = The TMIFR1 bit will be cleared automatically, once the BDLC
has successfully transmitted the CRC byte and EOD symbol,
by the detection of an error on the multiplex bus or by a
transmitter underrun caused when the programmer does not
write another byte to the BDR after the TDRE interrupt.
If the TMIFR1 bit is set, the BDLC will attempt to transmit the
normalization symbol followed by the byte in the BDR. After the byte
in the BDR has been loaded into the transmit shift register, a TDRE
interrupt (see 20.7.4 BDLC State Vector Register) will occur similar
to the main message transmit sequence. The programmer should
then load the next byte of the IFR into the BDR for transmission.
When the last byte of the IFR has been loaded into the BDR, the
programmer should set the TEOD bit in the BDLC control register 2
(BCR2). This will instruct the BDLC to transmit a CRC byte once the
byte in the BDR is transmitted, and then transmit an EOD symbol,
indicating the end of the IFR portion of the message frame.
Advance Information
368
MC68HC708AS48 — Rev. 4.0
Byte Data Link Controller–Digital (BDLC–D)
MOTOROLA
If a loss of arbitration occurs when the BDLC is transmitting any byte
of a multiple byte IFR, the BDLC will go to the loss of arbitration state,
set the appropriate flag, and cease transmission.
If the BDLC loses arbitration during the IFR, the TMIFR1 bit will be
cleared and no attempt will be made to retransmit the byte in the
BDR. If loss of arbitration occurs in the last two bits of the IFR byte,
two additional 1 bits will be sent out.
NOTE:
The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
on the J1850 bus from corrupting a message.
TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 3) Bit
The TMIFR0 bit is used to request the BDLC to transmit the byte in
the BDLC data register (BDR) as the first byte of a multiple byte IFR
without CRC. Response IFR bytes are still subject to J1850 message
length maximums (see 20.5.2 J1850 Frame Format). See Figure
20-19.
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received, the BDLC will
attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last
IFR byte has been written into the BDR. After TEOD has been
set, the last IFR byte to be transmitted will be the last byte
which was written into the BDR.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Byte Data Link Controller–Digital (BDLC–D)
369
A G R E E M E N T
If the programmer attempts to set the TMIFR1 bit immediately after
the EOD symbol has been received from the bus, the TMIFR1 bit will
remain in the reset state, and no attempt will be made to transmit an
IFR byte.
N O N - D I S C L O S U R E
However, if the programmer wishes to transmit a single byte followed
by a CRC byte, the programmer should load the byte into the BDR
before the EOD symbol has been received, and then set the TMIFR1
bit. Once the TDRE interrupt occurs, the programmer should then set
the TEOD bit in the BCR2. This will result in the byte in the BDR being
the only byte transmitted before the IFR CRC byte, and no TDRE
interrupt will be generated.
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC CPU Interface
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
0 = The TMIFR0 bit will be cleared automatically, once the BDLC
has successfully transmitted the EOD symbol, by the detection
of an error on the multiplex bus or by a transmitter underrun
caused when the programmer does not write another byte to
the BDR after the TDRE interrupt.
A G R E E M E N T
If the TMIFR0 bit is set, the BDLC will attempt to transmit the
normalization symbol followed by the byte in the BDR. After the byte
in the BDR has been loaded into the transmit shift register, a TDRE
interrupt (see 20.7.4 BDLC State Vector Register) will occur similar
to the main message transmit sequence. The programmer should
then load the next byte of the IFR into the BDR for transmission.
When the last byte of the IFR has been loaded into the BDR, the
programmer should set the TEOD bit in the BCR2. This will instruct
the BDLC to transmit an EOD symbol once the byte in the BDR is
transmitted, indicating the end of the IFR portion of the message
frame. The BDLC will not append a CRC when the TMIFR0 is set.
If the programmer attempts to set the TMIFR0 bit after the EOD
symbol has been received from the bus, the TMIFR0 bit will remain in
the reset state, and no attempt will be made to transmit an IFR byte.
N O N - D I S C L O S U R E
If a loss of arbitration occurs when the BDLC is transmitting, the
TMIFR0 bit will be cleared, and no attempt will be made to retransmit
the byte in the BDR. If loss of arbitration occurs in the last two bits of
the IFR byte, two additional 1 bits (active short bits) will be sent out.
NOTE:
The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
on to the J1850 bus from a corrupted message.
Advance Information
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MC68HC708AS48 — Rev. 4.0
Byte Data Link Controller–Digital (BDLC–D)
MOTOROLA
20.7.4 BDLC State Vector Register
This register is provided to substantially decrease the CPU overhead
associated with servicing interrupts while under operation of a multiplex
protocol. It provides an index offset that is directly related to the BDLC’s
current state, which can be used with a user-supplied jump table to
rapidly enter an interrupt service routine. This eliminates the need for the
user to maintain a duplicate state machine in software.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
I3
I2
I1
I0
0
0
Write:
R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 20-20. BDLC State Vector Register (BSVR)
I0, I1, I2, and I3 — Interrupt Source Bits
These bits indicate the source of the interrupt request that currently is
pending. The encoding of these bits are listed in Table 20-5.
Table 20-5. BDLC Interrupt Sources
BSVR
I3
I2
I1
I0
Interrupt Source
Priority
$00
0
0
0
0
No interrupts pending
0 (lowest)
$04
0
0
0
1
Received EOF
1
$08
0
0
1
0
Received IFR byte (RXIFR)
2
$0C
0
0
1
1
BDLC Rx data register full (RDRF)
3
$10
0
1
0
0
BDLC Tx data register empty (TDRE)
4
$14
0
1
0
1
Loss of arbitration
5
$18
0
1
1
0
Cyclical redundancy check (CRC) error
6
$1C
0
1
1
1
Symbol invalid or out of range
7
$20
1
0
0
0
Wakeup
8 (highest)
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Byte Data Link Controller–Digital (BDLC–D)
371
A G R E E M E N T
$003E
N O N - D I S C L O S U R E
Address:
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC CPU Interface
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the
BDLC data register needs servicing (RDRF, RXIFR, or TDRE
conditions). RXIFR and RDRF can be cleared only by a read of the
BSVR followed by a read of the BDLC data register (BDR) ($003F).
TDRE can either be cleared by a read of the BSVR followed by a write
to the BDLC BDR or by setting the TEOD bit in BCR2.
A G R E E M E N T
Upon receiving a BDLC interrupt, the user can read the value within the
BSVR, transferring it to the CPU’s index register. The value can then be
used to index into a jump table, with entries four bytes apart, to quickly
enter the appropriate service routine. For example:
Service
*
*
JMPTAB
LDX
JMP
BSVR
JMPTAB,X
Fetch State Vector Number
Enter service routine,
(must end in RTI)
JMP
NOP
JMP
NOP
JMP
NOP
SERVE0
Service condition #0
SERVE1
Service condition #1
SERVE2
Service condition #2
JMP
END
SERVE8
Service condition #8
N O N - D I S C L O S U R E
*
NOTE:
The NOPs are used only to align the JMPs onto 4-byte boundaries so
that the value in the BSVR can be used intact. Each of the service
routines must end with an RTI instruction to guarantee correct continued
operation of the device. Note also that the first entry can be omitted since
it corresponds to no interrupt occurring.
The service routines should clear all of the sources that are causing the
pending interrupts. Note that the clearing of a high priority interrupt may
still leave a lower priority interrupt pending, in which case bits I0, I1, and
I2 of the BSVR will then reflect the source of the remaining interrupt
request.
If fewer states are used or if a different software approach is taken, the
jump table can be made smaller or omitted altogether.
Advance Information
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MC68HC708AS48 — Rev. 4.0
Byte Data Link Controller–Digital (BDLC–D)
MOTOROLA
20.7.5 BDLC Data Register
Address:
$003F
Bit 7
6
5
4
3
2
1
Bit 0
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
Read:
Write:
Reset:
Undetermined after Reset
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
BDLC CPU Interface
Data read from this register will be the last data byte received from the
J1850 bus. This received data should only be read after an Rx data
register full (RDRF) interrupt has occurred. (See 20.7.4 BDLC State
Vector Register.)
The BDR is double buffered via a transmit shadow register and a receive
shadow register. After the byte in the transmit shift register has been
transmitted, the byte currently stored in the transmit shadow register is
loaded into the transmit shift register. Once the transmit shift register has
shifted the first bit out, the TDRE flag is set, and the shadow register is
ready to accept the next data byte. The receive shadow register works
similarly. Once a complete byte has been received, the receive shift
register stores the newly received byte into the receive shadow register.
The RDRF flag is set to indicate that a new byte of data has been
received. The programmer has one BDLC byte reception time to read
the shadow register and clear the RDRF flag before the shadow register
is overwritten by the newly received byte.
To abort an in-progress transmission, the programmer should stop
loading data into the BDR. This will cause a transmitter underrun error
and the BDLC automatically will disable the transmitter on the next
non-byte boundary. This means that the earliest a transmission can be
MC68HC708AS48 — Rev. 4.0
MOTOROLA
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Byte Data Link Controller–Digital (BDLC–D)
373
N O N - D I S C L O S U R E
This register is used to pass the data to be transmitted to the J1850 bus
from the CPU to the BDLC. It is also used to pass data received from the
J1850 bus to the CPU. Each data byte (after the first one) should be
written only after a Tx data register empty (TDRE) state is indicated in
the BSVR ($003E).
A G R E E M E N T
Figure 20-21. BDLC Data Register (BDR)
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
halted is after at least one byte plus two extra logic 1s have been
transmitted. The receiver will pick this up as an error and relay it in the
state vector register as an invalid symbol error.
NOTE:
The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
on the J1850 bus from corrupting a message.
20.8 Low-Power Modes
The wait mode and stop mode are discussed here.
20.8.1 Wait Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and the WCM bit in
BDLC control register 1 (BCR1) is previously clear. In BDLC wait mode,
the BDLC cannot drive any data.
A subsequent successfully received message, including one that is in
progress at the time that this mode is entered, will cause the BDLC to
wake up and generate a CPU interrupt request if the interrupt enable (IE)
bit in the BDLC control register 1 (BCR1) is previously set (see 20.7.2
BDLC Control Register 1 for a better understanding of IE). This results
in less of a power saving, but the BDLC is guaranteed to receive
correctly the message which woke it up, since the BDLC internal
operating clocks are kept running.
NOTE:
Ensuring that all transmissions are complete or aborted before putting
the BDLC into wait mode is important.
20.8.2 Stop Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BDLC control register 1
(BCR1) is previously set. This is the lowest power mode that the BDLC
can enter.
Advance Information
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MC68HC708AS48 — Rev. 4.0
Byte Data Link Controller–Digital (BDLC–D)
MOTOROLA
If this mode is entered while the BDLC is receiving a message, the first
subsequent received edge will cause the BDLC to wake up immediately,
generate a CPU interrupt request, and wait for the BDLC internal
operating clocks to restart and stabilize before normal communications
can resume. Therefore, the BDLC is not guaranteed to receive that
message correctly.
It is important to ensure all transmissions are complete or aborted prior
to putting the BDLC into stop mode.
N O N - D I S C L O S U R E
NOTE:
A G R E E M E N T
A subsequent passive-to-active transition on the J1850 bus will cause
the BDLC to wake up and generate a non-maskable CPU interrupt
request. When a STOP instruction is used to put the BDLC in stop mode,
the BDLC is not guaranteed to correctly receive the message which
woke it up, since it may take some time for the BDLC internal operating
clocks to restart and stabilize. If a WAIT instruction is used to put the
BDLC in stop mode, the BDLC is guaranteed to correctly receive the
byte which woke it up, if and only if an end-of-frame (EOF) has been
detected prior to issuing the WAIT instruction by the CPU. Otherwise,
the BDLC will not correctly receive the byte that woke it up.
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
Low-Power Modes
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Byte Data Link Controller–Digital (BDLC–D)
375
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller–Digital (BDLC–D)
Advance Information
376
MC68HC708AS48 — Rev. 4.0
Byte Data Link Controller–Digital (BDLC–D)
MOTOROLA
21.1 Contents
21.2
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
21.3
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .379
21.4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
21.5
5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . .380
21.6
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
21.7
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
21.8
5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing . . . . .383
21.9
CGM Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .386
R E Q U I R E D
Section 21. Electrical Specifications
A G R E E M E N T
Advance Information — MC68HC708AS48
21.11 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . .387
21.12 Timer Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .388
21.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
21.14 BDLC Transmitter VPW Symbol Timings . . . . . . . . . . . . . . . .388
21.15 BDLC Receiver VPW Symbol Timings . . . . . . . . . . . . . . . . . .389
21.16 BDLC Transmitter DC Electrical Characteristics . . . . . . . . . .390
21.17 BDLC Receiver DC Electrical Characteristics . . . . . . . . . . . .390
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Electrical Specifications
377
N O N - D I S C L O S U R E
21.10 CGM Component Information. . . . . . . . . . . . . . . . . . . . . . . . .386
21.2 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 21.5 5.0 Volt DC Electrical Characteristics for
guaranteed operating conditions.
Rating(1)
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +6.0
V
Input voltage
VIn
VSS –0.3 to VDD +0.3
V
I
± 25
mA
Storage temperature
TSTG
–55 to +150
°C
Maximum current out of VSS
IMVSS
100
mA
Maximum current into VDD
IMVDD
100
mA
VPP
VSS –0.3 to +14.0
V
Maximum current per pin
excluding VDD and VSS
Programming voltage
N O N - D I S C L O S U R E
1. Voltages are referenced to VSS.
NOTE:
This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIn and VOut be constrained to the
range VSS ≤ (VIn or VOut) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD.)
Advance Information
378
MC68HC708AS48 — Rev. 4.0
Electrical Specifications
MOTOROLA
Symbol
Value
Unit
TA
–40 to 105
°C
VDD
5.0 ± 10%
V
Symbol
Value
Unit
Thermal resistance
PLCC (52 pins) or QFP (64 pins)
θJA
50
°C/W
I/O pin power dissipation
PI/O
User determined
W
Power dissipation(1)
PD
PD = (IDD x VDD) +
PI/O = K/(TJ + 273 °C)
W
Constant(2)
K
PD x (TA + 273 °C)
+ (PD2 x θJA)
W/°C
Average junction temperature
TJ
Operating temperature range
Operating voltage range
21.4 Thermal Characteristics
Characteristic
Maximum junction temperature
TJM
TA = PD
x θJA
150
°C
°C
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined from a known TA and measured PD. With this
value of K, PD, and TJ can be determined for any value of TA.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Electrical Specifications
379
A G R E E M E N T
Rating
N O N - D I S C L O S U R E
21.3 Functional Operating Range
R E Q U I R E D
Electrical Specifications
Functional Operating Range
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
21.5 5.0 Volt DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage
(ILoad = –2.0 mA) all ports
VOH
VDD –0.8
—
—
V
Output low voltage
(ILoad = 1.6 mA) all ports
VOL
—
—
0.4
V
Input high voltage
All ports, IRQs, RESET, OSC1
VIH
0.7 x VDD
—
VDD
V
Input low voltage
All ports, IRQs, RESET, OSC1
VIL
VSS
—
0.3 x VDD
V
—
—
—
—
30
15
mA
mA
—
—
—
—
—
—
—
—
5
50
400
500
µA
µA
µA
µA
VDD + VDDA/VDDAREF supply current
Run(3)
Wait(4)
Stop(5)
25 °C
–40 °C to +105 °C
25 °C with LVI enabled
–40 °C to +105 °C with LVI enabled
IDD
I/O ports Hi-Z leakage current
IL
—
—
±1
µA
Input current
IIN
—
—
±1
µA
Capacitance
ports (as input or output)
COUT
CIN
—
—
—
—
12
8
pF
Low-voltage reset inhibit
VLVII
3.8
4.0
4.2
V
Low-voltage reset recover
VLVIR
4.0
4.2
4.4
V
Low-voltage reset inhibit/recover hysteresis
HLVI
100
200
500
mV
VPOR
0
—
200
mV
VPORRST
0
—
800
mV
RPOR
0.02
—
—
V/ms
VHI
VDD
—
VDD + 2
V
POR rearm
POR reset
voltage(6)
voltage(7)
POR rise time ramp rate(8)
High COP disable
voltage(9)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +105 °C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (Operating) IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 Vdc from rail. No dc loads.
Less than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait IDD. Measured with all modules enabled.
5. Stop IDD measured with OSC1 = VSS.
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
9. See 13.9 COP Module During Break Interrupts.
Advance Information
380
MC68HC708AS48 — Rev. 4.0
Electrical Specifications
MOTOROLA
Characteristic(1)
Symbol
Min
Max
Unit
fBUS
—
8.4
MHz
RESET pulse width low
tRL
1.5
—
tcyc
IRQ interrupt pulse width low (edge-triggered)
tILHI
1.5
—
tcyc
IRQ interrupt pulse period
tILIL
Note 3
—
tcyc
EPROM programming voltage
VEPGM
13.5
(typical)
—
V
EPROM programming time
tEPGM
1 (typical)
EEPROM programming time per byte
tEEPGM
10
—
ms
EEPROM erasing time per byte
tEBYTE
10
—
ms
EEPROM erasing time per block
tEBLOCK
10
—
ms
EEPROM erasing time per bulk
tEBULK
10
—
ms
EEPROM programming voltage discharge period
tEEFPV
100
—
µs
16-bit timer(2)
Input capture pulse width(3)
Input capture period(4)
tTH, tTL
tTLTL
2
See note 4
—
—
tcyc
Bus operating frequency (4.5–5.5 V, VDD only)
ms/byte
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +105 °C, unless otherwise noted.
2. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
3. Refer to Table 16-2. Mode, Edge, and Level Selection and supporting note.
4. The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt
service routine plus TBD tcyc.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Electrical Specifications
381
N O N - D I S C L O S U R E
21.6 Control Timing
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
Control Timing
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
21.7 ADC Characteristics
Characteristic
Min
Max
Unit
Resolution
8
8
Bits
Absolute accuracy
(VREFL = 0 V, VDDA = VREFH = 5 V ± 10%)
–1
+1
LSB
Includes quantization
VREFL
VREFH
V
VREFL = VSSA
Powerup time
16
17
µs
Conversion time
period
Input leakage(2)
Ports B and D
—
±1
µA
Conversion time
16
17
ADC
clock
cycles
Conversion range(1)
Monotonicity
Comments
Includes sampling
time
Inherent within Total Error
Zero input reading
00
01
Hex
VIN = VREFL
Full-scale reading
FE
FF
Hex
VIN = VREFH
Sample time(3)
5
—
ADC
clock
cycles
Input capacitance
—
8
pF
Not tested
ADC internal clock
500 k
1.048 M
Hz
Tested only at 1 MHz
Analog input voltage
–0.3
VDD + 0.3
V
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, VDDA/VDDAREF = 5.0 Vdc ± 10%, VSSA = 0 Vdc, VREFH = 5.0 Vdc ± 10%
2. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
3. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
Advance Information
382
MC68HC708AS48 — Rev. 4.0
Electrical Specifications
MOTOROLA
21.8 5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing
Characteristic(2)
Min
Max
Unit
Operating frequency(3)
Master
Slave
fBUS(M)
fBUS(S)
fBUS/128
dc
fBUS/2
fBUS
MHz
1
Cycle time
Master
Slave
tcyc(M)
tcyc(S)
2
1
128
—
tcyc
2
Enable lead time
tLEAD
15
—
ns
3
Enable lag time
tLAG
15
—
ns
4
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
100
50
—
—
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
100
50
—
—
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
45
5
—
—
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
0
15
—
—
ns
tA(CP0)
tA(CP1)
0
0
40
20
ns
8
Access time, slave(4)
CPHA = 0
CPHA = 1
9
Slave disable time (hold time to high-impedance
state)(5)
tDIS
—
25
ns
10
Data valid time after enable edge(6)
Master
Slave
tV(M)
tV(S)
—
—
10
40
ns
11
Data hold time (outputs, after enable edge)
Master
Slave
tHO(M)
tHO(S)
0
5
—
—
ns
A G R E E M E N T
Symbol
1. Item numbers refer to dimensions in Figure 21-1 and Figure 21-2.
2. All timing is shown with respect to 30% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI pins.
3. fBUS = the currently active bus frequency for the microcontroller.
4. Time to data active from high-impedance state
5. Hold time to high-impedance state
6. With 100 pF on all SPI pins
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Electrical Specifications
383
N O N - D I S C L O S U R E
Num(1)
R E Q U I R E D
Electrical Specifications
5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing
R E Q U I R E D
Electrical Specifications
SS
(INPUT)
SS pin of master held high.
1
SCK (CPOL = 0)
(OUTPUT)
NOTE
SCK (CPOL = 1)
(OUTPUT)
NOTE
5
4
5
4
6
A G R E E M E N T
MISO
(INPUT)
BITS 6–1
MSB IN
10
11
MOSI
(OUTPUT)
MASTER MSB OUT
7
LSB IN
10
11
BITS 6–1
MASTER LSB OUT
NOTE: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
(INPUT)
SS pin of master held high.
N O N - D I S C L O S U R E
1
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
5
NOTE
4
5
NOTE
4
6
MISO
(INPUT)
10
MOSI
(OUTPUT)
BITS 6–1
MSB IN
11
MASTER MSB OUT
7
LSB IN
10
BITS 6–1
11
MASTER LSB OUT
NOTE: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 21-1. SPI Master Timing
Advance Information
384
MC68HC708AS48 — Rev. 4.0
Electrical Specifications
MOTOROLA
R E Q U I R E D
Electrical Specifications
5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing
SS
(INPUT)
3
1
SCK (CPOL = 0)
(INPUT)
11
5
4
2
SCK (CPOL = 1)
(INPUT)
5
4
9
8
SLAVE
MSB OUT
6
MOSI
(OUTPUT)
BITS 6–1
7
NOTE
11
11
10
MSB IN
SLAVE LSB OUT
A G R E E M E N T
MISO
(INPUT)
BITS 6–1
LSB IN
NOTE: Not defined but normally MSB of character just received.
a) SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
SCK (CPOL = 0)
(INPUT)
5
4
2
8
MISO
(OUTPUT)
N O N - D I S C L O S U R E
3
SCK (CPOL = 1)
(INPUT)
5
4
10
NOTE
MOSI
(INPUT)
9
SLAVE
MSB OUT
6
7
BITS 6–1
11
10
MSB IN
SLAVE LSB OUT
BITS 6–1
LSB IN
NOTE: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 21-2. SPI Slave Timing
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Electrical Specifications
385
R E Q U I R E D
Electrical Specifications
21.9 CGM Operating Conditions
Characteristic
Symbol
Min
Typ
Max
Unit
Crystal reference frequency
fxclk
1
—
8
MHz
Range nominal multiplier
fnom
—
4.9152
—
MHz
4.9152
—
32.8
MHz
4.9152
—
16.4
MHz
VCO center-of-range frequency(1)
fvrs
A G R E E M E N T
medium voltage vco center-of-range frequency
VCO frequency multiplier
N
1
—
15
—
VCO Center-of-range multiplier
L
1
—
15
—
fvclk
fvrsmin
—
fvrsmax
MHz
VCO operating frequency
1. 5.0 V ±10% VDD only
21.10 CGM Component Information
Characteristic
Symbol
Min
Typ
Max
Unit
fxclk
1
4.9152
8
MHz
Crystal load capacitance(2)
CL
—
—
—
pF
Crystal fixed capacitance(2)
C1
—
2 × CL
—
pF
Crystal tuning capacitance(2)
C2
—
2 × CL
—
pF
Feedback bias resistor
RB
—
1
—
MΩ
Series resistor(3)
RS
0
—
3.3
kΩ
Filter capacitor
CF
—
Cfact × (VDDA/fxclk)
—
pF
Cbyp
—
0.1
—
µF
N O N - D I S C L O S U R E
Crystal (X1) frequency (MHz)(1)
Bypass capacitor(4)
1. Fundamental mode crystals only
2. Consult crystal manufacturer’s data.
3. Not required
4. Cbyp must provide low AC impedance from f = fxclk/100 to 100 × fvclk, so series resistance must be considered.
Advance Information
386
MC68HC708AS48 — Rev. 4.0
Electrical Specifications
MOTOROLA
Symbol
Min
Typ
Max
Unit
Filter capacitor multiply factor
Cfact
—
0.0154
—
F/sV
Acquisition mode time factor
Kacq
—
0.1135
—
V
Tracking mode time factor
Ktrk
—
0.0174
—
V
Manual mode time to stable(1)
tacq
—
8 × V DDA
----------------------------f xclk × K acq
—
s
tal
—
4 × V DDA
--------------------------f xclk × K trk
—
s
Manual acquisition time
tLock
—
tacq + tal
—
s
Tracking mode entry frequency tolerance
∆trk
0
—
3.6%
—
Acquisition mode entry frequency tolerance
∆acq
6.3%
—
7.2%
—
Lock entry frequency tolerance
∆Lock
0
—
0.9%
—
Lock exit frequency tolerance
∆unl
0.9%
—
1.8%
—
Reference cycles per acquisition mode measurement
nacq
—
32
—
Cyc
Reference cycles per tracking mode measurement
ntrk
—
128
—
Cyc
Automatic mode time to stable(1)
tacq
n acq
-----------f xclk
8 × V DDA
----------------------------f xclk × K acq
—
s
tal
n trk
---------f xclk
4 × V DDA
--------------------------f xclk × K trk
—
s
tLock
—
tacq+tal
—
s
fJ
0
—
fcrys × 0.025%
× N/4
Hz
Manual stable to lock time(1)
Automatic stable to lock time(1)
Automatic lock time
PLL jitter(2)
1. If CF chosen correctly
2. Deviation of average bus frequency over 2 ms; N = VCO frequency multiplier
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Electrical Specifications
387
A G R E E M E N T
Description
N O N - D I S C L O S U R E
21.11 CGM Acquisition/Lock Time Information
R E Q U I R E D
Electrical Specifications
CGM Acquisition/Lock Time Information
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
21.12 Timer Module Characteristics
Characteristic
Symbol
Min
Max
Unit
tTIH, tTIL
125
—
ns
tTCH, tTCL
(1/fOP) + 5
—
ns
Symbol
Min
Max
Unit
RAM data retention voltage
VRDR
0.7
—
V
EPROM data retention
tEDR
10
Input capture pulse width
Input clock pulse width
21.13 Memory Characteristics
Characteristic
EEPROM write/erase cycles
@ 10 ms write time + 85 °C
EEPROM data retention
after 10,000 write/erase cycles
Years
10,000
—
Cycles
10
—
Years
21.14 BDLC Transmitter VPW Symbol Timings
Characteristic(1)
Number
Symbol
Min
Typ
Max
Unit
Passive logic 0
10
tTVP1
62
64
66
µs
Passive logic 1
11
tTVP2
126
128
130
µs
Active logic 0
12
tTVA1
126
128
130
µs
Active logic 1
13
tTVA2
62
64
66
µs
Start of frame (SOF)
14
tTVA3
198
200
202
µs
End of data (EOD)
15
tTVP3
198
200
202
µs
End of frame (EOF)
16
tTV4
278
280
282
µs
Inter-frame separator (IFS)
17
tTV6
298
300
302
µs
1. fBDLC = 1.048576 or 1.0 MHz, VDD = 5.0 V ± 10%, VSS = 0 V. See Figure 21-3.
Advance Information
388
MC68HC708AS48 — Rev. 4.0
Electrical Specifications
MOTOROLA
21.15 BDLC Receiver VPW Symbol Timings
Characteristic(1) (2)
Symbol
Min
Typ
Max
Unit
Passive logic 0
10
tTRVP1
34
64
96
µs
Passive logic 1
11
tTRVP2
96
128
163
µs
Active logic 0
12
tTRVA1
96
128
163
µs
Active logic 1
13
tTRVA2
34
64
96
µs
Start of frame (SOF)
14
tTRVA3
163
200
239
µs
End of data (EOD)
15
tTRVP3
163
200
239
µs
End of frame (EOF)
16
tTRV4
239
280
320
µs
Break
18
tTRV6
280
—
—
µs
A G R E E M E N T
Number
1. fBDLC = 1.048576 or 1.0 MHz, VDD = 5.0 V ± 10%, VSS = 0 V. See Figure 21-3.
2. The receiver symbol timing boundaries are subject to an uncertainty of 1 tBDLC µs due to sampling considerations.
11
1
1
10
12
SOF
0
0
15
0
N O N - D I S C L O S U R E
13
14
EOD
16
EOF
18
BRK
Figure 21-3. BDLC Variable Pulse Width Modulation (VPW) Symbol Timing
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Electrical Specifications
R E Q U I R E D
Electrical Specifications
BDLC Receiver VPW Symbol Timings
389
R E Q U I R E D
Electrical Specifications
21.16 BDLC Transmitter DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Max
Unit
BDTxD output low voltage
(IBDTxD = 1.6 mA)
VOLTX
—
0.4
V
BDTxD output high voltage
(IBDTx = –800 µA)
VOHTX
VDD –0.8
—
V
21.17 BDLC Receiver DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Max
Unit
BDRxD input low voltage
VILRX
VSS
0.3 x VDD
V
BDRxD input high voltage
VIHRX
0.7 x VDD
VDD
V
BDRxD input low current
IILBDRXI
–1
+1
µA
BDRxD input high current
IHBDRX
–1
+1
µA
1. VDD = 5.0 Vdc + 10%, VSS = 0 Vdc, TA = –40oC to +125oC, unless otherwise noted.
N O N - D I S C L O S U R E
A G R E E M E N T
1. VDD = 5.0 Vdc + 10%, VSS = 0 Vdc, TA = –40oC to +125oC, unless otherwise noted.
Advance Information
390
MC68HC708AS48 — Rev. 4.0
Electrical Specifications
MOTOROLA
22.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
22.3
52-Pin Plastic Leaded Chip Carrier
Package (Case 778) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
22.2 Introduction
This section provides dimensions for the 52-pin plastic leaded chip
carrier (PLCC) package.
22.3 52-Pin Plastic Leaded Chip Carrier Package (Case 778) shows
the latest package at the time of this publication. To make sure that you
have the latest package specifications, contact one of these sources:
•
Local Motorola Sales Office
•
Motorola Fax Back System (Mfax™)
– Phone 1-602-244-6609
– EMAIL [email protected];
http://sps.motorola.com/mfax/
•
Worldwide Web (wwweb) home page at http://motorola.com/sps/
Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.
Mfax is a trademark of Motorola, Inc.
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Mechanical Specifications
391
R E Q U I R E D
22.1 Contents
A G R E E M E N T
Section 22. Mechanical Specifications
N O N - D I S C L O S U R E
Advance Information — MC68HC708AS48
22.3 52-Pin Plastic Leaded Chip Carrier Package (Case 778)
0.007 (0.18)
B
Y BRK
–N–
M
T L–M
0.007 (0.18)
U
M
S
N
S
T L–M
S
N
S
D
Z
–M–
–L–
A G R E E M E N T
R E Q U I R E D
Mechanical Specifications
W
D
52
1
V
A
0.007 (0.18)
M
T L–M
S
N
S
R
0.007 (0.18)
M
T L–M
S
N
S
E
C
0.004 (0.100)
–T– SEATING
J
VIEW S
G
PLANE
N O N - D I S C L O S U R E
G1
S
T L–M
S
H
N
S
0.007 (0.18)
M
T L–M
S
N
S
K1
K
F
0.007 (0.18)
M
T L–M
S
N
S
VIEW S
Advance Information
392
S
T L–M
S
N
S
VIEW D–D
Z
0.010 (0.25)
G1
0.010 (0.25)
X
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE
TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT
MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED
AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING
ANY MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE
H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.785
0.795
0.785
0.795
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
–––
0.025
–––
0.750
0.756
0.750
0.756
0.042
0.048
0.042
0.048
0.042
0.056
–––
0.020
2_
10 _
0.710
0.730
0.040
–––
MILLIMETERS
MIN
MAX
19.94
20.19
19.94
20.19
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
–––
0.64
–––
19.05
19.20
19.05
19.20
1.07
1.21
1.07
1.21
1.07
1.42
–––
0.50
2_
10 _
18.04
18.54
1.02
–––
MC68HC708AS48 — Rev. 4.0
Mechanical Specifications
MOTOROLA
23.1 Contents
23.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
23.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
23.2 Introduction
This section contains ordering information.
23.3 MC Order Numbers
Table 23-1. MC Order Numbers
Operating
Temperature Range
Engrsamphc08(1)
– 40 °C to + 105 °C
MC68HC708AS48CFN(2)
– 40 °C to + 85 °C
N O N - D I S C L O S U R E
MC Order Number
1. Engrsamphc08 = quad flat pack; contact Motorola sales representative
2. FN = plastic leaded chip carrier
MC68HC708AS48 — Rev. 4.0
MOTOROLA
Advance Information
Ordering Information
R E Q U I R E D
Section 23. Ordering Information
A G R E E M E N T
Advance Information — MC68HC708AS48
393
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Ordering Information
Advance Information
394
MC68HC708AS48 — Rev. 4.0
Ordering Information
MOTOROLA
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MC68HC708AS48/D