Intersil ISL9001IRLZ-T Ldo with low isupply, high psrr Datasheet

ISL9001
IGNS
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MENDE L9001A Data Sheet
RECOM
IS
®
March 28, 2008
LDO with Low ISUPPLY, High PSRR
Features
ISL9001 is a high performance Low Dropout linear regulator
capable of sourcing 300mA current. It has a low standby
current and high-PSRR and is stable with an output
capacitance of 1µF to 10µF with an ESR of up to 200mΩ.
• 300mA high performance LDO
The ISL9001 has a very high PSRR of 90dB and outputs
noise less than 30µVRMS. A reference bypass pin allows
connection of a noise-filtering capacitor for low-noise and
high-PSRR applications. When coupled with a no load
quiescent current of 25µA (typical), and 0.1µA shutdown
current, the ISL9001 is an ideal choice for portable wireless
equipment.
The ISL9001 provides a power-good signal with delay time
programmable with an external capacitor.
Several different fixed voltage outputs are standard. Output
voltage options for each LDO range are from 1.5V to 3.3V.
Other output voltage options may be available upon request.
FN9231.2
• Excellent transient response to large current steps
• Excellent load regulation: <0.1% voltage change across
full range of load current
• High PSRR: 90dB @ 1kHz
• Wide input voltage capability: 2.3V to 6.5V
• Extremely low quiescent current: 25µA
• Low dropout voltage: typically 200mV @ 300mA
• Low output noise: typically 30µVRMS @ 100µA (1.5V)
• Stable with 1µF to 10µF ceramic capacitors
• Soft-start to limit input current surge during enable
• Current limit and overheat protection
• Delayed POR, programmable with external capacitor
• ±1.8% accuracy over all operating conditions
Pinout
• Tiny 2mmx3mm 8 Ld DFN package
ISL9001
(8 LD 2x3 DFN)
TOP VIEW
• -40°C to +85°C operating temperature range
• Pb-free (RoHS compliant)
VIN
1
8 VO
EN
2
7 POR
CBYP
3
6 NC
CPOR
4
5 GND
Applications
• PDAs, cell phones and smart phones
• Portable instruments, MP3 players
• Handheld devices, including medical handhelds
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL9001
Ordering Information
PART NUMBER
(Notes 1, 2)
PART MARKING
VO VOLTAGE
(V) (Note 3)
TEMP RANGE (°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL9001IRNZ-T
EAA
3.3
-40 to +85
8 Ld 2x3 DFN
L8.2x3
ISL9001IRMZ-T
EBA
3.0
-40 to +85
8 Ld 2x3 DFN
L8.2x3
ISL9001IRLZ-T
ECA
2.9
-40 to +85
8 Ld 2x3 DFN
L8.2x3
ISL9001IRKZ-T
EDA
2.85
-40 to +85
8 Ld 2x3 DFN
L8.2x3
ISL9001IRJZ-T
EEA
2.8
-40 to +85
8 Ld 2x3 DFN
L8.2x3
ISL9001IRRZ-T
EFA
2.6
-40 to +85
8 Ld 2x3 DFN
L8.2x3
ISL9001IRFZ-T
EGA
2.5
-40 to +85
8 Ld 2x3 DFN
L8.2x3
ISL9001IRCZ-T
EHA
1.8
-40 to +85
8 Ld 2x3 DFN
L8.2x3
ISL9001IRBZ-T
EJA
1.5
-40 to +85
8 Ld 2x3 DFN
L8.2x3
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. Please refer to TB347 for details on reel specifications.
3. For other output voltages, contact Intersil Marketing.
2
FN9231.2
March 28, 2008
ISL9001
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V
VO Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN+0.3)V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2500V
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .200V
Thermal Resistance (Notes 4, 5)
θJA (°C/W)
θJC (°C/W)
8 Ld 2x3 DFN Package . . . . . . . . . . . .
69
10
Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 2.3V;
CIN = 1µF; CO = 1µF.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
6.5
V
DC CHARACTERISTICS
Supply Voltage
2.3
VIN
Ground Current
Quiescent condition: IO = 0µA
IDD
LDO active
25
32
µA
LDO disabled @ +25°C
0.1
1.0
µA
Shutdown Current
IDDS
UVLO Threshold
VUV+
1.9
2.1
2.3
V
VUV-
1.6
1.8
2.0
V
Regulation Voltage Accuracy
Maximum Output Current
IMAX
Internal Current Limit
ILIM
Dropout Voltage (Note 7)
Thermal Shutdown Temperature
Initial accuracy at VIN = VO + 0.5V, IO = 10mA, TJ = +25°C
-0.7
+0.7
%
VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = +25°C
-0.8
+0.8
%
VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = -40°C
to +125°C
-1.8
+1.8
%
Continuous
300
350
mA
475
600
mA
VDO1
IO = 300mA; VO < 2.5V
300
500
mV
VDO2
IO = 300mA; 2.5V ≤ VO ≤ 2.8V
250
400
mV
VDO3
IO = 300mA; VO > 2.8V
200
325
mV
TSD+
145
°C
TSD-
110
°C
@ 1kHz
90
dB
@ 10kHz
70
dB
@ 100kHz
50
dB
IO = 100µA, VO = 1.5V, TA = +25°C, CBYP = 0.1µF
BW = 10Hz to 100kHz
30
µVRMS
AC CHARACTERISTICS
Ripple Rejection (Note 6)
IO = 10mA, VIN = 2.8V (min), VO = 1.8V, CBYP = 0.1µF
Output Noise Voltage (Note 6)
3
FN9231.2
March 28, 2008
ISL9001
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 2.3V;
CIN = 1µF; CO = 1µF. (Continued)
PARAMETER
SYMBOL
MIN
(Note 8)
TEST CONDITIONS
TYP
MAX
(Note 8)
UNITS
DEVICE START-UP CHARACTERISTICS
Device Enable Time
tEN
Time from assertion of the ENx pin to when the output
voltage reaches 95% of the VO (nom)
250
500
µs
LDO Soft-start Ramp Rate
tSSR
Slope of linear portion of LDO output voltage ramp during
start-up
30
60
µs/V
EN PIN CHARACTERISTICS
Input Low Voltage
VIL
-0.3
0.5
V
Input High Voltage
VIH
1.4
VIN + 0.3
V
0.1
µA
Input Leakage Current
IIL, IIH
Pin Capacitance
CPIN
Informative
5
pF
POR PIN CHARACTERISTICS
POR Thresholds
VPOR+
As a percentage of nominal output voltage
VPORPOR Delay
tPLH
CPOR = 0.01µF
91
94
97
%
87
90
93
%
100
200
300
ms
tPHL
POR Pin Output Low Voltage
VOL
POR Pin Internal Pull-up
Resistance
25
@ IOL = 1.0mA
RPOR
78
100
µs
0.2
V
180
kΩ
NOTES:
6. Limits established by characterization and are not production tested.
7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.
8. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
EN
tEN
VPOR+
VPOR-
VPOR+
VPOR-
<tPHL
VO
tPLH
tPHL
POR
FIGURE 1. TIMING PARAMETER DEFINITION
4
FN9231.2
March 28, 2008
ISL9001
Typical Performance Curves
0.8
0.10
VO = 3.3V
ILOAD = 0mA
0.4
0.2
-40°C
0.0
+25°C
-0.2
+85°C
-0.4
0.06
0.04
-40°C
0.02
0.00
+25°C
-0.02
+85°C
-0.04
-0.06
-0.6
-0.08
-0.8
3.4
3.8
4.2
4.6
5.0
5.4
INPUT VOLTAGE (V)
5.8
6.2
-0.10
0
6.6
FIGURE 2. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V
OUTPUT)
50
150
250
100
200
300
LOAD CURRENT - IO (mA)
350
400
FIGURE 3. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
0.10
3.4
VIN = 3.8V
VO = 3.3V
ILOAD = 0mA
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
VO = 3.3V
IO = 0mA
3.3
OUTPUT VOLTAGE, VO (V)
OUTPUT VOLTAGE CHANGE (%)
VIN = 3.8V
VO = 3.3V
0.08
OUTPUT VOLTAGE CHANGE (%)
OUTPUT VOLTAGE, VO (%)
0.6
3.2
IO = 150mA
3.1
IO = 300mA
3.0
-0.06
2.9
-0.08
-0.10
-40
2.8
-25
5
-10
20 35 50 65
TEMPERATURE (°C)
80
95
3.1
110 125
4.1
4.6
5.1
5.6
6.1
6.5
INPUT VOLTAGE (V)
FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V
OUTPUT)
2.9
350
VO = 2.8V
IO = 0mA
DROPOUT VOLTAGE, VDO (mV)
2.8
OUTPUT VOLTAGE, VO (V)
3.6
2.7
IO = 150mA
2.6
IO = 300mA
2.5
2.4
2.3
2.6
300
250
VO = 2.8V
200
VO = 3.3V
150
100
50
0
3.1
3.6
4.1
4.6
5.1
5.6
6.1
INPUT VOLTAGE (V)
FIGURE 6. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.8V
OUTPUT)
5
6.5
0
50
100
150
200
250
300
350
400
OUTPUT LOAD (mA)
FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT
FN9231.2
March 28, 2008
ISL9001
Typical Performance Curves
(Continued)
40
350
VO = 3.3V
35
GROUND CURRENT (µA)
DROPOUT VOLTAGE, VDO (mV)
300
250
+85°C
+25°C
-40°C
200
150
100
+125°C
30
+25°C
25
-40°C
20
VO = 3.3V
15
50
0
0
50
100
150
200
250
300
350
10
400
3.0
3.5
4.0
OUTPUT LOAD (mA)
4.58
5.0
5.5
6.5
6.0
INPUT VOLTAGE (V)
FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE
40
200
180
35
140
GROUND CURRENT (µA)
GROUND CURRENT (µA)
160
+25°C
+85°C
120
-40°C
100
80
60
40
25
20
VIN = 3.8V
VO = 3.3V
20
0
30
0
50
100
150
200
250
300
350
VIN = 3.8V
VO = 3.3V
ILOAD = 0µA
15
10
-40 -25
400
-10
5
LOAD CURRENT (mA)
FIGURE 10. GROUND CURRENT vs LOAD
20 35 50 65
TEMPERATURE (°C)
110 125
VIN = 5.0V
VO = 2.85V
IL = 150mA
5
CL = 1µF
CBYP = 0.01µF
3
4
VO (V)
2
VIN
3
VO
2
POR
1
0
0.5
1
0
VEN (V)
VOLTAGE (V)
95
FIGURE 11. GROUND CURRENT vs TEMPERATURE
VO = 2.85V
IL = 150mA
0
80
1.0
1.5
2.0 2.5
TIME (s)
3.0
3.5
4.0
FIGURE 12. POWER-UP/POWER-DOWN
6
4.5
5.0
5
0
0
0.2
0.4
0.6
0.8
1.0
1.2
TIME (ms)
1.4
1.6
1.8
2.0
FIGURE 13. TURN ON/TURN OFF RESPONSE
FN9231.2
March 28, 2008
ISL9001
Typical Performance Curves
(Continued)
VO = 3.3V
ILOAD = 300mA
VO = 2.8V
ILOAD = 300mA
CLOAD = 1µF
CBYP = 0.01µF
CLOAD = 1µF
CBYP = 0.01µF
4.3V
4.2V
3.6V
3.5V
10mV/DIV
10mV/DIV
400µs/DIV
400µs/DIV
FIGURE 14. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
FIGURE 15. LINE TRANSIENT RESPONSE, 2.8V OUTPUT
VO (25mV/DIV)
VO = 1.8V
VIN = 2.8V
300mA
ILOAD
SPECTRAL NOISE DENSITY (nV/√Hz)
1000
100
10
VIN = 3.6V
VO = 1.8V
ILOAD = 10mA
CBYP = 0.1µF
1
CIN = 1µF
CLOAD = 1µF
100µA
0.1
10
100
1k
10k
FREQUENCY (Hz)
100µs/DIV
FIGURE 16. LOAD TRANSIENT RESPONSE
100k
1M
FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY
100
VIN = 3.6V
VO = 1.8V
IO = 10mA
90
80
CBYP = 0.1µF
CLOAD = 1µF
PSRR (dB)
70
60
50
40
30
20
10
0
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 18. PSRR vs FREQUENCY
7
FN9231.2
March 28, 2008
ISL9001
Pin Description
PIN
NUMBER
PIN NAME
1
VIN
Supply Voltage/LDO Input:
Connect a 1µF capacitor to GND.
2
EN
LDO Enable.
3
CBYP
Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 0.1µF between this pin and GND to achieve lowest noise and
highest PSRR.
4
CPOR
POR Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR output release after the output reaches 94% of
its specified voltage level. (200ms delay per 0.01µF).
5
GND
6
NC
7
POR
8
VO
DESCRIPTION
GND is the connection to system ground. Connect to PCB Ground plane.
Do not connect.
Open-drain POR Output (active-low):
Internally connected to VO through 100kΩ resistor.
LDO Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
Typical Application
ISL9001
8
1
VIN (2.3V TO 5V)
VIN
ON
VO
2
EN
ENABLE
OFF
3
C2
C4
VOUT TOO LOW
CBYP
5
4
C1
POR
VOUT OK
7
CPOR
GND
VOUT
RESET
(200ms DELAY,
C4 = 0.01µF)
C3
C1, C3: 1µF X5R CERAMIC CAPACITOR
C2: 0.1µF X7R CERAMIC CAPACITOR
C4: 0.01µF X7R CERAMIC CAPACITOR
8
FN9231.2
March 28, 2008
ISL9001
Block Diagram
VIN
VO
UVLO
CONTROL
LOGIC
SHORT CIRCUIT,
THERMAL PROTECTION,
SOFT-START
+
EN
+
-
VO
100k
1.0V
GND
POR
BANDGAP AND
TEMPERATURE
SENSOR
VOLTAGE AND
REFERENCE
GENERATOR
CBYP
Functional Description
The ISL9001 contains all circuitry required to implement a
high performance LDO. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9001 adjusts its biasing to achieve the lowest standby
current consumption.
The device also integrates current limit protection, smart
thermal shutdown protection, and soft-start. Smart Thermal
shutdown protects the device against overheating.
Power Control
The ISL9001 has an enable pin (EN) to control power to the
LDO output. When EN is low, the device is in shutdown
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1µA.
When the enable pin is asserted, the device first polls the
output of the UVLO detector to ensure that VIN voltage is at
least about 2.1V. Once verified, the device initiates a start-up
sequence. During the start-up sequence, trim settings are
first read and latched. Then, sequentially, the bandgap,
reference voltage and current generation circuitry power-up.
Once the references are stable, a fast-start circuit quickly
charges the external reference bypass capacitor (connected
to the CBYP pin) to the proper operating voltage. Once the
bypass capacitor has been charged, the LDO powers up.
9
POR
DELAY
1.0V
0.94V
0.9V
CPOR
GND
During operation, whenever the VIN voltage drops below
about 1.84V, the ISL9001 immediately disables the LDO
output. When VIN rises back above 2.1V, the device
re-initiates its start-up sequence and LDO operation will
resume automatically.
Reference Generation
The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter. The filter
includes the external capacitor connected to the CBYP pin.
A 0.01µF capacitor connected to CBYP implements a 100Hz
lowpass filter, and is recommended for most high
performance applications. For the lowest noise application, a
0.1µF CBYP capacitor should be used. This filters the
reference noise to below the 10Hz to 1kHz frequency band,
which is crucial in many noise-sensitive applications.
The bandgap generates a zero temperature coefficient (TC)
voltage for the reference divider. The reference divider
provides the regulation reference, POR detection thresholds,
and other voltage references required for current generation
and over-temperature detection.
The current generator outputs references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.
FN9231.2
March 28, 2008
ISL9001
LDO Regulation and Programmable Output Divider
Overheat Detection
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9001 provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200mΩ. The design is performance-optimized for a 1µF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal.
The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +140°C, if the LDO is
sourcing more than 50mA it shuts down until the die cools
sufficiently. Once the die temperature falls back below about
+110°C, the disabled LDO is re-enabled and soft-start
automatically takes place.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge. The
ISL9001 provides short-circuit protection by limiting the
output current to about 425mA.
The LDO uses an independently trimmed 1V reference as its
input. An internal resistor divider drops the LDO output
voltage down to 1V. This is compared to the 1V reference for
regulation. The resistor division ratio is programmed in the
factory.
Power-On Reset Generation
The ISL9001 has a Power-on Reset signal generation
circuit, which indicates that output power is good. The POR
signal is generated as follows.
A POR comparator continuously monitors the output of the
LDO. The LDO enters a power-good state when the output
voltage is above 94% of the expected output voltage for a
period exceeding the LDO PGOOD entry delay time (see the
following). In the power-good state, the open-drain POR
output is in a high-impedance state. An internal 100kΩ
pull-up resistor pulls the pin up to the LDO output voltage. An
external resistor can be added between the POR output and
the LDO output for a faster rise time, however, the POR
output should not connect through an external resistor to a
supply greater than the LDO voltage.
The power-good state is exited when the LDO output falls
below 90% of the expected output voltage for a period longer
than the PGOOD exit delay time. While power-good is false,
the ISL9001 pulls the POR pin low.
The PGOOD entry and exit delays are determined by the
value of an external capacitor connected to the CPOR pin.
For a 0.01µF capacitor, the entry and exit delays are 200ms
and 25µs respectively. Larger or smaller capacitor values will
yield proportionately longer or shorter delay times. The POR
exit delay should never be allowed to be less than 10µs to
ensure sufficient immunity against transient induced false
POR triggering.
10
FN9231.2
March 28, 2008
ISL9001
Dual Flat No-Lead Plastic Package (DFN)
L8.2x3
2X
0.15 C A
A
D
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
2X
MILLIMETERS
0.15 C B
SYMBOL
E
MIN
A
0.80
A1
-
6
A3
INDEX
AREA
b
TOP VIEW
D2
0.20
0.10
SIDE VIEW
C
SEATING
PLANE
D2
(DATUM B)
0.08 C
A3
7
0.90
1.00
-
-
0.05
-
0.25
0.32
1.50
1.65
1.75
1
7,8
3.00 BSC
-
8
1.65
e
1.80
1.90
7,8
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
N
8
Nd
4
D2/2
6
INDEX
AREA
5,8
C
E2
A
NOTES
2.00 BSC
E
//
MAX
0.20 REF
D
B
NOMINAL
2
3
Rev. 0 6/04
2
NX k
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
(DATUM A)
E2
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
NX L
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
N N-1
NX b
e
8
5
0.10
(Nd-1)Xe
REF.
M C A B
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
BOTTOM VIEW
CL
(A1)
NX (b)
L
5
SECTION "C-C"
C C
TERMINAL TIP
e
FOR EVEN TERMINAL/SIDE
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11
FN9231.2
March 28, 2008