IRF IR3080PBF Xphasetm vrd10 control ic with vccvid & overtemp detect Datasheet

Data Sheet No. PD94705 revB
IR3080PbF
XPHASETM VRD10 CONTROL IC WITH VCCVID & OVERTEMP DETECT
DESCRIPTION
The IR3080 Control IC combined with an IR XPhaseTM Phase IC provides a full featured and flexible way to
implement a complete VRD 10 power solution. The “Control” IC provides overall system control and
interfaces with any number of “Phase ICs” which each drive and monitor a single phase of a multiphase
converter. The XPhaseTM architecture results in a power supply that is smaller, less expensive, and easier
to design while providing higher efficiency than conventional approaches.
The IR3080 is intended for desktop applications and includes the VCCVID and VRHOT functions required
for proper system operation.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
6 bit VR10 compatible VID with 0.5% overall system accuracy
1 to X phases operation with matching phase ICs
On-chip 700Ω VID Pull-up resistors with VID pull-up voltage input
Programmable Dynamic VID Slew Rate
No Discharge of output capacitors during Dynamic VID step-down (can be disabled)
+/-300mV Differential Remote Sense
Programmable 150kHz to 1MHz oscillator
Programmable VID Offset and Load Line output impedance
Programmable Softstart
Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
Simplified Powergood provides indication of proper operation and avoids false triggering
Operates from 12V input with 9.1V Under-Voltage Lockout
6.8V/5mA Bias Regulator provides System Reference Voltage
1.2V @ 150mA VCCVID Linear Regulator with Full Protection
VCCVID Powergood with Programmable delay gates converter operation
Programmable Converter Over-Temperature Detection and Output
Small thermally enhanced 32L MLPQ package
APPLICATION CIRCUIT
RVCC
10 ohm
12V
VRHOT
CVCC
0.1uF
POWERGOOD
25
LGND
27
26
RMPOUT
VRHOT
HOTSET
28
30
29
SS/DEL
PWRGD
VIDPGD
32
31
CSS/DEL
VDRP
24
VBIAS
0.1uF
23
22
RCP
21
20
RDRP1
19
VID4
EA
5 Wire Analog Bus
to Phase ICs
CCP1
17
ISHARE
VDAC
ROCSET
CFB
RVDAC
ROSC
CDRP
CCP
RDRP
18
16
9
VDAC
OCSET
ROSC
VID3
15
8
FB
IIN
TRM3
VID3
VID1
EAOUT
VID2
TRM4
6
7
VID0
VID4
VID1
VID2
IR3080
CONTROL
IC
VID5
14
5
BBFB
13
VID0
RMPOUT
VCC
VBIAS
VOSNS-
4
RHOTSET1
VCCVID
12
VID5
RHOTSET2
VIDPWR
TRM1
3
TRM2
2
3.3V
VIDFB
11
1
10
VCCVID
VIDDEL
CVIDDEL
VID POWERGOOD
CVDAC
RFB1
RFB
VOSENSE+
VOSENSE-
Page 1
Remote Sense
IR3080PbF
ORDERING INFORMATION
Device
Order Quantity
IR3080MTRPbF
3000 per reel
IR3080MPbF
100 piece strips
ABSOLUTE MAXIMUM RATINGS
Operating Junction Temperature……………..150oC
Storage Temperature Range………………….-65oC to 150oC
ESD Rating……………………………………..HBM Class 1C JEDEC standard
PIN #
1
2
3
4-9
10, 11,
13,14
12
15
16
17
18
PIN NAME
VIDFB
VCCVID
VIDPWR
VID0-5
TRM1-4
VMAX
20V
20V
20V
20V
Do Not Connect
VMIN
-0.3V
-0.5V
-0.3V
-0.3V
Do Not Connect
ISOURCE
1mA
400mA
1mA
10mA
Do Not Connect
ISINK
1mA
50mA
400mA
10mA
Do Not Connect
VOSNSROSC
VDAC
OCSET
IIN
0.5V
20V
20V
20V
20V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
10mA
1mA
1mA
1mA
1mA
10mA
1mA
1mA
1mA
1mA
19
20
21
VDRP
FB
EAOUT
20V
20V
10V
-0.3V
-0.3V
-0.3V
5mA
1mA
10mA
5mA
1mA
20mA
22
BBFB
20V
-0.3V
1mA
1mA
23
VBIAS
20V
-0.3V
1mA
1mA
24
VCC
20V
-0.3V
1mA
50mA
25
LGND
n/a
n/a
50mA
1mA
26
RMPOUT
20V
-0.3V
1mA
1mA
27
HOTSET
20V
-0.3V
1mA
1mA
28
VRHOT
20V
-0.3V
1mA
50mA
29
SS/DEL
20V
-0.3V
1mA
1mA
30
PWRGD
20V
-0.3V
1mA
20mA
31
VIDPGD
20V
-0.3V
1mA
20mA
32
VIDDEL
20V
-0.3V
1mA
1mA
Page 2
IR3080PbF
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 9.5V ≤ VCC ≤ 14V, 2.0V ≤ VIDPWR ≤ 5.5V and 0 oC ≤
TJ ≤ 100 oC
PARAMETER
VDAC Reference
System Set-Point Accuracy
Source Current
Sink Current
VID Input Threshold
VID Pull-up Resistors
Regulation Detect Comparator
Input Offset
Regulation Detect to EAOUT
Delay
BBFB to FB Bias Current
Ratio
VID 11111x Blanking Delay
VID Step Down Detect
Blanking Time
VID Down BB Clamp Voltage
VID Down BB Clamp Current
Error Amplifier
Input Offset Voltage
FB Bias Current
DC Gain
Gain-Bandwidth Product
Source Current
Sink Current
Max Voltage
Min Voltage
VDRP Buffer Amplifier
Input Offset Voltage
Input Voltage Range
Bandwidth (-3dB)
Slew Rate
IIN Bias Current
Page 3
TEST CONDITION
-0.3V ≤ VOSNS- ≤ 0.3V, Connect FB to
EAOUT, Measure V(EAOUT) –
V(VOSNS-) deviation from Table 1.
Applies to all VID codes.
RROSC = 41.9kΩ
RROSC = 41.9kΩ
MIN
TYP
MAX
0.5
68
47
500
500
-5
0.95
Measure time until PWRGD drives low
Measure from VID inputs to EAOUT
UNIT
%
80
55
600
700
0
92
63
700
1000
5
µA
µA
mV
Ω
mV
130
200
ns
1.00
1.05
µA/µA
800
1.7
ns
µs
Percent of VDAC voltage
70
3.5
75
6.2
80
12
%
mA
Connect FB to EAOUT, Measure
V(EAOUT) – V(DAC). from Table 1.
Applies to all VID codes and -0.3V ≤
VOSNS- ≤ 0.3V. Note 2
RROSC = 41.9kΩ
Note 1
Note 1
-3
4
8
mV
-31
90
4
0.4
0.7
125
30
-29.5
100
7
0.6
1.2
250
100
-28
105
µA
dB
MHz
mA
mA
mV
mV
-8
0.8
1
0
VBIAS–VEAOUT (referenced to VBIAS)
Normal operation or Fault mode
V(VDRP) – V(IIN), 0.8V ≤ V(IIN) ≤ 5.5V
Note 1
-2.0
6
10
-0.75
0.8
1.7
375
150
8
5.5
0
mV
V
MHz
V/µs
µA
IR3080PbF
PARAMETER
Oscillator
Switching Frequency
Peak Voltage (5V typical,
measured as % of VBIAS)
Valley Voltage (1V typical,
measured as % of VBIAS)
VBIAS Regulator
Output Voltage
Current Limit
Soft Start and Delay
SS/DEL to FB Input Offset
Voltage
Charge Current
Discharge Current
Charge/Discharge Current
Ratio
Charge Voltage
Delay Comparator Threshold
Discharge Comparator
Threshold
Over-Current Comparator
Input Offset Voltage
OCSET Bias Current
PWRGD Output
Output Voltage
Leakage Current
VCCVID Regulator
Output Voltage
Dropout Voltage
Current Limit
VIDFB Bias Current
VCCVID Powergood
VCCVID Threshold Voltage
Charge Current
Discharge Current
Charge Voltage
Delay Comparator Threshold
VIDPGD Output Voltage
VIDPGD Leakage Current
Page 4
TEST CONDITION
MIN
TYP
MAX
UNIT
RROSC = 41.9kΩ
RROSC = 41.9kΩ
255
70
300
71
345
74
kHz
%
RROSC = 41.9kΩ
11
14
16
%
-5mA ≤ I(VBIAS) ≤ 0
6.5
-30
6.8
-15
7.1
-6
V
mA
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
0.85
1.3
1.5
V
40
4
10
70
6
11.5
100
9
13
µA
µA
µA/µA
3.7
70
150
4.0
90
200
4.2
110
250
V
mV
mV
-10
-31
0
-29.5
10
-28
mV
150
0
400
10
mV
µA
1.215
200
1.0
V
mV
V
mA
-225
1.200
130
0.8
-300
-150
1.05
1.10
1.13
V
30
4
3.7
65
66
7
4.0
90
150
0
90
11
4.2
115
400
10
µA
mA
V
mV
mV
µA
Relative to Charge Voltage
RROSC = 41.9kΩ
I(PWRGD) = 4mA
V(PWRGD) = 5.5V
-150mA ≤ I(VCCVID) ≤ 0
I(VCCVID) = -20mA
I(VCCVID) = -150mA
Relative to regulated VCCVID Output
Voltage
Relative to Charge Voltage
I(VIDPGD) = 4mA
V(VIDPGD) = 5.5V
1.145
µA
µA
IR3080PbF
PARAMETER
VCC Under-Voltage Lockout
Start Threshold
Stop Threshold
Hysteresis
General
VCC Supply Current
VIDPWR Supply Current
VOSNS- Current
VRHOT Comparator
HOTSET Bias Current
Output Voltage
VRHOT Leakage Current
Threshold Hysteresis
Threshold Voltage
(increasing temperature)
TEST CONDITION
MIN
TYP
MAX
UNIT
Start – Stop
8.6
8.4
150
9.1
8.9
200
9.6
9.4
300
V
V
mV
VID0-5 Open, I(VCCVID) = 0
-0.3V ≤ VOSNS- ≤ 0.3V, All VID Codes
8
400
-5.5
11
550
-4.5
14
1000
-3.5
mA
µA
mA
-2
-0.5
300
0
6
1
400
10
10
µA
mV
µA
o
C
I(VRHOT) = 29mA
V(VRHOT) = 5.5V
TJ
≥
TJ
≥
3
85oC
o
85 C
MIN
4.73mV/ oC x TJ
+ 1.176V
TYP
4.73mV/ oC x TJ
+ 1.241V
Note 1: Guaranteed by design, but not tested in production
Note 2: VDAC Output is trimmed to compensate for Error Amplifier input offsets errors
Page 5
MAX
4.73mV/ oC x TJ
+ 1.356V
V
IR3080PbF
PIN DESCRIPTION
PIN#
1
2
PIN SYMBOL
VIDFB
VCCVID
3
4-9
VIDPWR
VID0-5
10,
11,
13,14
12
15
TRM1-4
VOSNSROSC
16
VDAC
17
OCSET
18
IIN
19
VDRP
20
FB
21
22
EAOUT
BBFB
23
VBIAS
24
25
26
27
VCC
LGND
RMPOUT
HOTSET
28
29
VRHOT
SS/DEL
30
PWRGD
31
VIDPGD
32
VIDDEL
Page 6
PIN DESCRIPTION
Feedback to the VCCVID regulator. Connect to the VCCVID output.
1.2V/150mA Regulator Output. Can also drive external pass transistor to minimize
on-chip power dissipation
Power for VID Pull-up resistors and VCCVID Regulator
Inputs to VID D to A Converter. On-chip 700 ohm pull-up resistors to VIDPWR pin
are included.
Used for precision post-package trimming of the VDAC voltage. Do not make any
connection to these pins.
Remote Sense Input. Connect to ground at the Load.
Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET,
BBFB, and VDAC bias currents
Regulated voltage programmed by the VID inputs. Current Sensing and PWM
operation are referenced to this pin. Connect an external RC network to VOSNS- to
program Dynamic VID slew rate.
Programs the hiccup over-current threshold through an external resistor tied to
VDAC and an internal current source. Over-current protection can be disabled by
connecting this pin to a DC voltage no greater than 6.5V (do not float this pin as
improper operation will occur).
Current Sense input from the Phase IC(s). To ensure proper operation bias to at
least 250mV (don’t float this pin).
Buffered IIN signal. Connect an external RC network to FB to program converter
output impedance
Inverting input to the Error Amplifier. Converter output voltage is offset from the
VDAC voltage through an external resistor connected to the converter output voltage
at the load and an internal current source.
Output of the Error Amplifier
Input to the Regulation Detect Comparator. Connect to converter output voltage and
VDRP pin through resistor network to program recovery from VID step-down.
Connect to ground to diable Body BrakingTM during transition to a lower VID code.
6.8V/5mA Regulated output used as a system reference voltage for internal circuitry
and the Phase ICs
Power for internal circuitry
Local Ground and IC substrate connection
Oscillator Output voltage. Used by Phase ICs to program Phase Delay
Inverting input to VRHOT comparator. Connect resistor divider from VBIAS to LGND
to program VRHOT threshold. Diode or thermistor may be substituted for lower
resistor for enhanced/remote temperature sensing. Applying a voltage exceeding
approximately 7.5V disables the oscillator for factory testing.
Open Collector output of the VRHOT comparator. Connect external pull-up.
Controls Converter Softstart, Power Good, and Over-Current Delay Timing. Connect
an external capacitor to LGND to program the timing. An optional resistor can be
added in series with the capacitor to reduce the over-current delay time.
Open Collector output that drives low during Softstart and any external fault
condition. Connect external pull-up.
Open Collector output of the VCCVID Power Good circuitry. Connect external pullup.
Connect an external capacitor to LGND to program the VCCVID Power Good delay
IR3080PbF
SYSTEM THEORY OF OPERATION
XPhaseTM Architecture
The XPhaseTM architecture is designed for multiphase interleaved buck converters which are used in applications
requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can
control converters of any phase number where flexibility facilitates the design trade-off of multiphase converters.
The scalable architecture can be applied to other applications which require high current or multiple output voltages.
As shown in Figure 1, the XPhaseTM architecture consists of a Control IC and a scalable array of phase converters
each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5-wire analog bus, i.e.
bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control IC incorporates all
the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault protections etc. The
Phase IC implements the functions required by the converter of each phase, i.e. the gate drivers, PWM comparator
and latch, over-voltage protection, and current sensing and sharing.
There is no unused or redundant silicon with the XPhaseTM architecture compared to others such as a 4 phase
controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus
eliminates the need for point-to-point wiring between the Control IC and each Phase. The critical gate drive and
current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the
parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal.
VCCVID (1.2V@150mA)
POWER GOOD
PHASE FAULT
VR HOT
GATE VOLTAGE
REGULATOR
12V
ENABLE
VID5
IR3080
CONTROL
IC
PHASE FAULT
>> BIAS VOLTAGE
BIAS VOLTAGE
>> PHASE TIMING
PHASE TIMING
VID2
<< CURRENT SENSE
CURRENT SHARE
VID3
>> PWM CONTROL
PWM CONTROL
VID4
>> VID VOLTAGE
VID VOLTAGE
VID0
VID1
CIN
IR3086A
PHASE IC
VOUT+
0.1uF
COUT
VOUT-
PHASE HOT
CCS
RCS
VOUT SENSE-
PHASE FAULT
BIAS VOLTAGE
PHASE TIMING
CURRENT SHARE
PWM CONTROL
IR3086A
PHASE IC
0.1uF
VID VOLTAGE
PHASE HOT
CCS
OC OC OC OC OC OC OC
CONTROL BUS
RCS
ADDITIONAL PHASES
OC OC OC
INPUT/OUTPUT
Figure 1. System Block Diagram
Page 7
VOUT SENSE+
IR3080PbF
PWM Control Method
The PWM block diagram of the XPhaseTM architecture is shown in Figure 2. Feed-forward voltage mode control with
trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used
for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the
slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change
with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change
due to variations in the silver box output voltage or due to wire and PCB-trace voltage drop related to changes in
load current.
VIN
CONTROL IC
VPEAK
RAMPIN+
RMPOUT
RPHS1
VVALLEY
PWM
LATCH
CLOCK
PULSE
GENERATOR
RAMPIN-
-
EAIN
VBIAS
+
-
+
+
-
RVFB
X
0.91
+
ISHARE
FB
10K
CURRENT
SENSE
AMPLIFIER
20mV
IROSC
X34
RDRP
VDRP
AMP
CSIN+
+
IFB
VOSNS-
CSCOMP
-
SHARE
ADJUST
ERROR
AMPLIFIER
BODY
BRAKING
COMPARATOR
+
RAMP
DISCHARGE
CLAMP
SCOMP
+
ERROR
AMP
GND
-
CPWMRMP
EAOUT
GATEL
ENABLE
PWMRMP
VOSNSVDAC
VOUT
COUT
R
+
-
RPWMRMP
VOSNS+
RESET
DOMINANT
+
RPHS2
VDAC
VBIAS
REGULATOR
GATEH
S
PWM
COMPARATOR
-
RAMP GENERATOR
+
50%
DUTY
CYCLE
PHASE IC
SYSTEM
REFERENCE
VOLTAGE
BIASIN
CCS
RCS
CCS
RCS
CSIN-
DACIN
VDRP
+
-
IIN
RAMPIN+
PWM
LATCH
CLOCK
PULSE
GENERATOR
+
RPHS1
PHASE IC
SYSTEM
REFERENCE
VOLTAGE
BIASIN
-
RAMPIN-
GATEH
S
PWM
COMPARATOR
-
EAIN
RESET
DOMINANT
R
GATEL
+
RPHS2
ENABLE
PWMRMP
+
RPWMRMP
-
X
0.91
-
+
SHARE
ADJUST
ERROR
AMPLIFIER
+
ISHARE
10K
20mV
CURRENT
SENSE
AMPLIFIER
-
CSIN+
+
X34
-
CSCOMP
-
CPWMRMP
BODY
BRAKING
COMPARATOR
+
RAMP
DISCHARGE
CLAMP
SCOMP
CSIN-
DACIN
Figure 2. PWM Block Diagram
Frequency and Phase Timing Control
The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external
resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of
approximately 5V and 1V respectively. This signal is used to program both the switching frequency and phase
timing of the Phase ICs. The Phase IC is programmed by resistor divider RPHS1 and RPHS2 connected between the
VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the
oscillator waveform over the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM
cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 3
shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for
phase timing by swapping the RMPIN+ and RMPIN– pins, as shown in Figure 2.
Page 8
IR3080PbF
50% RAMP
DUTY CYCLE
RAMP (FROM
CONTROL IC)
SLOPE = 80mV / % DC
VPEAK (5.0V)
VPHASE4&5 (4.5V)
SLOPE = 1.6mV / ns @ 200kHz
SLOPE = 8.0mV / ns @ 1MHz
VPHASE3&6 (3.5V)
VPHASE2&7 (2.5V)
VPHASE1&8 (1.5V)
VVALLEY (1.00V)
CLK1
PHASE IC CLOCK PULSES
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
Figure 3. 8 Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set; the PWMRMP
voltage begins to increase; the low side driver is turned off, and the high side driver is then turned on after the nonoverlap time. When the PWMRMP voltage exceeds the Error Amplifier’s output voltage, the PWM latch is reset.
This turns off the high side driver and then turns on the low side driver after the non-overlap time; it activates the
Ramp Discharge Clamp, which quickly discharges the PWMRMP capacitor to the VDAC voltage of the Control IC
until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An Error Amplifier output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the Error Amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in
ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.
Figure 4 depicts PWM operating waveforms under various conditions.
Page 9
IR3080PbF
PHASE IC
CLOCK
PULSE
EAIN
PWMRMP
VDAC
91% VDAC
GATEH
GATEL
STEADY-STATE
OPERATION
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCC UV, VCCVID UV, OCP, VID=11111X)
STEADY-STATE
OPERATION
Figure 4. PWM Operating Waveforms
Body BrakingTM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
TSLEW =
L * ( I MAX − I MIN )
VO
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in
response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +
VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient
decrease is now;
TSLEW =
L * ( I MAX − I MIN )
VO + VBODYDIODE
Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be
increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished
through the “0% Duty Cycle Comparator” located in the Phase IC. If the Error Amplifier’s output voltage drops below
91% of the VDAC voltage this comparator turns off the low side gate driver.
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor
and measuring the voltage across the capacitor, as shown in Figure 5. The equation of the sensing network is,
vC ( s) = vL ( s)
1
RL + sL
= iL ( s)
1 + sRCS CCS
1 + sRCS CCS
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR. If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
Page 10
IR3080PbF
vL
iL
Current
Sense Amp
L
RL
RCS
CCS
VO
CO
vCc S
CSOUT
Figure 5. Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with the inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer
from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency
variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and
the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier
bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional
sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the Phase IC, as shown in Figure 5. Its gain decreases
with increasing temperature and is nominally 34 at 25ºC and 29 at 125ºC (-1470 ppm/ºC). This reduction of gain
tends to compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the Phase IC junction is
hotter than the inductors these two effects tend to cancel such that no additional temperature compensation of the
load line is required.
The current sense amplifier can accept positive differential input up to 100mV and negative up to -20mV before
clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC and
other Phases through an on-chip 10KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases
are tied together and the voltage on the share bus represents the average current through all the inductors and is
used by the Control IC for voltage positioning and current limit protection.
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each Phase IC.
The output of the current sense amplifier is compared with the share bus less a 20mV offset. If current in a phase is
smaller than the average current, the share adjust amplifier of the phase will activate a current source that reduces
the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of the
current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact
with the output voltage loop.
Page 11
IR3080PbF
IR3080 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3080 is shown in Figure 6, and specific features are discussed in the following sections.
+
IVTTDEL
0.2V
-
-
+
OVER-CURRENT
COMPARATOR
DELAY
COMPARATOR
SS/DEL
DISCHARGE
IIN
DISABLE
1.3V
+
ON
+
SS/DEL
VDRP
VDRP
AMP
OCSET
-
+
+
4V
70uA
-
OVER
CURRENT
-
+
+
90mV
+
OFF
6uA
R
+
-
66uA
IDISCHG
DISCHARGE
COMPARATOR
SET
DOMINANT
-
-
VIDDEL
ICHG
PWRGD
S
VID DELAY
COMPARATOR
+
VCC
UVLO
COMPARATOR
-
FAULT
LATCH
-
9.1V
8.9V
VIDPGD
START
STOP
+
+
+
VCC
SOFTSTART
CLAMP
EAOUT
ERROR
AMP
FB
-
VIDPWR
VID = 11111X
VID STEP-DOWN
VID3
IROSC
IROSC
IROSC
VID
CONTROL
IROSC
VID4
IROSC
BBFB
IROSC
IROSC
IROSC
VID1
VID2
+
-
VID0
+
IROSC
IROSC
VID5
1.2V
-
VID DAC OUTPUT
VCCVID
REGULATOR
+
1.1V
+
-
VCCVID
COMPARATOR
+
VBIAS
RAMP GENERATOR
IROSC
CURRENT
SOURCE
GENERATOR
IROSC
IOCSET
IFB
IROSC
ROSC
BUFFER
AMP
-
1.0V
6.85V
-
+
5.0V
VBIAS
REGULATOR
LGND
+
-
VBIAS
RMPOUT
VIDFB
VDAC
VOSNS-
50%
DUTY
CYCLE
VCCVID
ROSC
VOLTAGE
PROPORTIONAL
TO ABSOLUTE
TEMPERATURE
+
-
+
START
STOP
-
VRHOT
COMPARATOR
VRHOT
HOTSET
Figure 6. IR3080 Block Diagram
VID Control
A 6-bit VID voltage compatible with VR 10, as shown in Table 1, is available at the VDAC pin. A detailed block
diagram of the VID control circuitry can be found in Figure 7. The VID pins are internally pulled up to VIDPWR pin
through 700Ω resistors. The VID input comparators, with 0.6V reference, monitor the VID pins and control the 6 bit
Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer
amplifier is the VDAC pin. The VDAC voltage is post-package trimmed to compensate for the input offsets of the
Error Amplifier to provide a 0.5% system set-point accuracy. The actual VDAC voltage does not determine the
system accuracy and has a wider tolerance.
Page 12
IR3080PbF
The IR3080 can accept changes in the VID code while operating and vary the DAC voltage accordingly. The
sink/source capability of the VDAC buffer amplifier is programmed by the same external resistor that sets the
oscillator frequency. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between
VDAC pin and the VOSNS- pin. A resistor connected in series with this capacitor is required to compensate the
VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and
converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output
voltage.
It is desirable to prevent negative inductor currents in response to a request for a lower VID code. Negative current
transforms the buck converter into a boost converter and transfers energy from the output capacitors back into the
input voltage. This energy can cause voltage spikes and damage the silver box or other components unless they
are specifically designed to handle it. Furthermore, power is wasted during the transfer of energy from the output
back to the input.
The IR3080 includes circuitry that turns off both control and synchronous MOSFETs in response to a lower VID
code so that the load current instead of the inductor discharges the output capacitors. A lower VID code is detected
by the VID step-down detect comparator which monitors the “fast” output of the DAC (plus 7mV for noise immunity)
compared to the “slow” output of the VDAC pin. If a dynamic VID step down is detected, the body brake latch is set
and the output of the error amplifier is pulled down to 75% of the DAC voltage by the VID body brake clamp. This
triggers the Body BrakingTM function, which turns off both high side and low side drivers in the phase ICs.
The converter’s output voltage needs to be monitored and compared to the VDAC voltage to determine when to
resume normal operation. Unfortunately, the voltage on the FB pin can be pulled down by its compensation network
during the sudden decrease in the Error Amplifier’s output voltage so an additional pin BBFB is provided. The BBFB
pin is connected to the converter output voltage and VDRP pin with resistors of the same value as on the FB pin
and therefore provides an un-corrupted representation of converter output voltage. The regulation detect
comparator compares the BBFB to the VDAC voltage and resets the body brake latch releasing the error amplifier’s
output and allowing normal operation to resume. Body BrakingTM during a transition to a lower VID code can be
disabled by connecting the BBFB pin to ground.
VIDPWR
800ns
BLANKING
700
VID5
VID0
DIGITAL TO
ANALOG
CONVERTER
VID INPUT
COMPARATORS
(1 OF 6 SHOWN)
VID1
VID2
+
VDAC BUFFER
AMP
"FAST" VDAC
+
VID3
"SLOW" VDAC
ISOURCE
VID4
+
+
VID = 11111X DETECT
-
VDAC
ISINK
-
-
0.6V
VOSNS-
-
EAOUT
VID DOWN
BB CLAMP
7mV
+
+
75%
-
ENABLE
VID STEP-DOWN
DETECT
COMPARATOR
+
IBBFB
+
RESET
DOMINANT
S
BODY
BRAKE
LATCH
1.7us
BLANKING
R
REGULATION
DETECT
COMPARATOR
BBFB
-
TO ERROR AMP
IROSC (From Current Source Generator)
Figure 7. VID Control Block Diagram
Page 13
IR3080PbF
Processor Pins (0 = low, 1 = high)
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VID3
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VID2
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
VID1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
VID0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VID5
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Vout
(V)
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
OFF4
OFF4
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
Processor Pins (0 = low, 1 = high)
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VID2
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
VID1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
VID0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VID5
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Vout
(V)
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
Note: 3. Output disabled (Fault mode)
Table 1 - Voltage Identification (VID)
Adaptive Voltage Positioning
Adaptive voltage positioning is needed to reduce the output voltage deviations during load transients and the power
dissipation of the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in
Figure 8. Resistor RFB is connected between the Error Amplifier’s inverting input pin FB and the converter’s output
voltage. An internal current source whose value is programmed by the same external resistor that programs the
oscillator frequency pumps current into the FB pin. The error amplifier forces the converter’s output voltage lower to
maintain a balance at its inputs. RFB is selected to program the desired amount of fixed offset voltage below the
DAC voltage.
The voltage at the VDRP pin is a buffered version of the share bus and represents the sum of the DAC voltage and
the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor RDRP.
Since the Error Amplifier will force the loop to maintain FB to be equal to the VDAC reference voltage, an additional
current will flow into the FB pin equal to (VDRP-VDAC) / RDRP. When the load current increases, the adaptive
positioning voltage increases accordingly. More current flows through the feedback resistor RFB, and makes the
output voltage lower proportional to the load current. The positioning voltage can be programmed by the resistor
RDRP so that the droop impedance produces the desired converter output impedance. The offset and slope of the
converter output impedance are referenced to and therefore independent of the VDAC voltage.
Page 14
IR3080PbF
Control IC
Current Sense
Amplifier
+
ISHARE
+
EAOUT
Vo
10k
VDAC
-
FB
RFB
RDRP
VDRP
Amplifier
CSIN-
Phase IC
VDRP
Current Sense
Amplifier
-
+
ISHARE
VDAC
-
IIN
+
CSIN+
... ...
IFB
-
VDAC
Phase IC
Error
Amplifier
10k
CSIN+
CSIN-
Figure 8. Adaptive voltage positioning
Inductor DCR Temperature Correction
If the thermal compensation of the inductor DCR provided by the temperature dependent gain of the current sense
amplifier is not adequate, a negative temperature coefficient (NTC) thermistor can be used for additional correction.
The thermistor should be placed close to the inductor and connected in parallel with the feedback resistor, as
shown in Figure 9. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor. A
similar network must be placed on the BBFB pin to ensure proper operation during a transition to a lower VID code
with Body BrakingTM.
Control IC
VDAC
Error
Amplifier
+
EAOUT
-
IFB
AVP
Amplifier
Vo
RFB
FB
RFB2
Rt
RDRP
VDRP
+
IIN
Figure 9. Temperature compensation of inductor DCR
Remote Voltage Sensing
To reduce the effect of impedance in the ground plane, the VOSNS- pin is used for remote sensing and connected
directly to the load. The VDAC voltage is referenced to VOSNS- to avoid additional error terms or delay related to a
separate differential amplifier. The capacitor connecting the VDAC and VOSNS- pins ensure that high speed
transients are fed directly into the error amplifier without delay.
Page 15
IR3080PbF
VCC VID Linear Regulator and VID Power Good
The IR3080 integrates a fully protected 1.2V/150mA VCCVID linear regulator with over-current protection. Power for
the VCCVID regulator is drawn from the VIDPWR pin which is typically connected to a 3.3V supply. If the linear
regulator output voltage is above 1.1V for a time period programmed by a capacitor between VIDDEL and LGND,
the VIDPGD pin will send out a VID power good signal and start-up of the converter is allowed. The PWRGD pin is
an open-collector output and should be pulled up to a voltage source through a resistor.
26
25
LGND
HOTSET
27
28
VRHOT
30
29
SS/DEL
PWRGD
RMPOUT
VDRP
24
23
22
21
20
19
18
VDAC
17
16
TRM4
ROSC
15
13
TRM3
IIN
OCSET
14
1uF
FB
VID3
9
0.1uF
VIDPGD
VID1
EAOUT
VID2
VID4
VCCVID
VID5
VID0
VOSNS-
8
BBFB
IR3080
CONTROL
IC
12
7
VIDPWR
TRM1
6
VBIAS
TRM2
5
2.5-3.3V
VCC
VCCVID
11
3
4
VIDFB
VIDDEL
32
1.8V
2
10
1
5 OHM
31
An external NPN transistor can be used to enhance the current capability of the linear regulator, as shown in Figure
10. The 5 ohm resistor provides loop compensation and over-current protection.
VOUT SENSE-
Figure 10. VCC VID linear regulator using external transistor
Soft Start, Over-Current Fault Delay, and Hiccup Mode
The IR3080 has a programmable soft-start function to limit the surge current during the converter start-up. A
capacitor connected between the SS/DEL and LGND pins controls soft start as well as over-current protection delay
and hiccup mode timing. A charge current of 70uA and discharge current of 6uA control the up slope and down
slope of the voltage at the SS/DEL pin respectively
Figure 11 depicts the various operating modes as controlled by the SS/DEL function. If there is no fault, the SS/DEL
capacitor pin will begin to be charged. The error amplifier output is clamped low until SS/DEL reaches 1.3V. The
error amplifier will then regulate the converter’s output voltage to match the SS/DEL voltage less the 1.3V offset
until it reaches the level determined by the VID inputs. The SS/DEL voltage continues to increase until it rises above
3.91V and allows the PWRGD signal to be asserted. SS/DEL finally settles at 4V, indicating the end of the soft start.
Under Voltage Lock Out, a VID=11111x, and VCC VID faults immediately set the fault latch causing SS/DEL to
begin to discharge. The SS/DEL capacitor will continue to discharge down to 0.2V. If the fault has cleared the fault
latch will be reset by the discharge comparator allowing a normal soft start to occur.
A delay is included if an over-current condition occurs after a successful soft start sequence. This is required since
over-current conditions can occur as part of normal operation due to load transients or VID transitions. If an overcurrent fault occurs during normal operation it will initiate the discharge of the capacitor at SS/DEL but will not set
the fault latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to discharge
below the 90mV offset of the delay comparator, the Fault latch will be set pulling the error amplifier’s output low
inhibiting switching in the phase ICs and de-asserting the PWRGD signal. The SS/DEL capacitor will continue to
discharge until it reaches 0.2V and the fault latch is reset allowing a normal soft start to occur. If an over-current
condition is again encountered during the soft start cycle the fault latch will be set without any delay and hiccup
mode will begin. During hiccup mode the charge to discharge current ratio results in a fixed 7.9% hiccup mode duty
cycle regardless of at what point the over-current condition occurs. However, the hiccup frequency is determined by
the load current and over-current set value.
Page 16
IR3080PbF
The over-current delay can be reduced by adding a resistor in series with the SS/DEL capacitor. The delay
comparator’s offset voltage is reduced by the drop in the resistor caused by the discharge current. The value of the
series resistor should be 10KΩ or less to avoid interference with the soft start function.
If SS/DEL pin is pulled below 0.9V, the converter can be disabled.
8.9V
UVLO
VCC
(12V)
VIDPWR
(3.3V)
1.1V
VCCVID
(1.2V)
3.91V
VIDDEL
VIDPGD
3.91V
SS/DEL
1.3V
VOUT
PWRGD
OCP THRESHOLD
IOUT
START-UP
(VCCVID GATES
FAULT MODE)
NORMAL OPERATION
(VOUT CHANGES DUE TO
LOAD AND VID CHANGES)
OCP
DELAY
HICCUP OVER-CURRENT
PROTECTION
RE-START
AFTER OCP
POWER-DOWN
(VCC GATES
FAULT MODE)
Figure 11. Operating Waveforms
Under Voltage Lockout (UVLO)
The UVLO function monitors the IR3080’s VCC supply pin and ensures that IR3080 has a high enough voltage to
power the internal circuit. The IR3080’s UVLO is set higher than the minimum operating voltage of compatible
Phase ICs thus providing UVLO protection for them as well. During power-up the fault latch is reset when VCC
exceeds 9.1V and there is no other fault. If the VCC voltage drops below 8.9V the fault latch will be set. For
converters using a separate 5V supply for gate driver bias an external UVLO circuit can be added to prevent any
operation until adequate voltage is present. A diode connected between the 5V supply and the SS/DEL pin provides
a simple 5V UVLO function. UVLO of the VIDPWR input is provided by the VID Power Good function. Adequate
voltage must be present at VIDPWR pin to allow VCCVID to reach 1.1V.
Over Current Protection (OCP)
The current limit threshold is set by a resistor connected between the OCSET and VDAC pins. If the IIN pin voltage,
which is proportional to the average current plus DAC voltage, exceeds the OCSET voltage, the over-current
protection is triggered.
Page 17
IR3080PbF
VID = 11111X Fault
VID codes of 111111 and 111110 will set the fault latch and disable the error amplifier. An 800ns delay is provided
to prevent a fault condition from occurring during Dynamic VID changes.
Power Good Output
The PWRGD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During
soft start, the PWRGD remains low until the output voltage is in regulation and SS/DEL is above 3.91V. The
PWRGD pin becomes low if the fault latch is set. A high level at the PWRGD pin indicates that the converter is in
operation and has no fault, but does not ensure the output voltage is within the specification. Output voltage
regulation within the design limits can logically be assured however, assuming no component failure in the system.
Load Current Indicator Output
The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current can
be retrieved by a differential amplifier which subtracts the VDAC voltage from the VDRP voltage.
System Reference Voltage (VBIAS)
The IR3081 supplies a 6.8V/5mA precision reference voltage from the VBIAS pin. The oscillator ramp amplitude
tracks the VBIAS voltage, which should be used to program the Phase IC trip points to minimize phase delay errors.
Thermal Monitoring (VRHOT)
The IR3080 senses its own die temperature and produces a voltage at the input of the VRHOT comparator that is
proportional to temperature. An external resistor divider connected from VBIAS to the HOTSET pin and ground can
be used to program the thermal trip point of the VRHOT comparator. The VRHOT pin is an open-collector output
and should be pulled up to a voltage source through a resistor. If the thermal trip point is reached the VRHOT
output drives low. Pulling HOTSET above approximately 7.5V will disable the oscillator (used during factory testing).
Page 18
IR3080PbF
APPLICATION INFORMATIONS
VCCVID
POWERGOOD
VRHOT
VIDPGD
0.1uF
12V
RCS-
VGATE
QGATE
CCS+
RVCC
10 ohm
17
19
20
16
CSIN+
CSIN-
DACIN
BIASIN
18
GATEH
PGND
GATEL
CIN
VOUT SENSE+
15
14
L
13
VOUT+
12
DISTRIBUTION
IMPEDANCE
11
VCC
CVCCL
RVCC
VOUT SENSE-
RPWMRMP
CVCC
RBBDRP
22
21
RCP
20
RCS-
CCP
CCS+
HOTSET
VRHOT
RPHASE23
6
SCOMP
RPHASE22
16
CSIN+
17
CSIN-
19
ISHARE
CSCOMP
GATEH
PGND
GATEL
VCCL
CIN
15
14
L
13
12
11
VCC
4
CBST
VCCH
IR3086A
PHASE
IC
RMPIN-
10
RSHARE
5
CVDAC
RMPIN+
LGND
3
RVDAC
18
20
1
RCS+
DBST
9
ROCSET
CCS-
20k
DACIN
RDRP
RBIASIN
BIASIN
17
CCP1
PHSFLT
RDRP1 CDRP
18
PWMRMP
19
CVCCL
RVCC
RPWMRMP
CVCC
RCSCCS+
CCS-
20k
16
CSIN+
17
CSIN-
19
18
20
PGND
GATEL
CIN
15
14
L
13
12
11
VCC
10
SCOMP
CSCOMP
GATEH
VCCL
LGND
ISHARE
9
VRHOT
6
RPHASE33
DACIN
BIASIN
HOTSET
RPHASE32
5
PWMRMP
4
CBST
VCCH
IR3086A
PHASE
IC
RMPIN-
EAIN
3
RMPIN+
7
2
PHSFLT
RPHASE31
1
RCS+
DBST
CPWMRMP 8
RBIASIN
CVCCL
RVCC
RPWMRMP
CVCC
RCSCCS+
CCS-
20k
16
CSIN+
17
CSIN-
19
18
20
PGND
GATEL
CIN
15
14
L
13
12
11
VCC
10
SCOMP
CSCOMP
GATEH
VCCL
LGND
ISHARE
9
VRHOT
6
RPHASE43
DACIN
BIASIN
HOTSET
RPHASE42
5
CBST
VCCH
IR3086A
PHASE
IC
RMPIN-
PWMRMP
4
RMPIN+
EAIN
3
7
2
PHSFLT
RPHASE41
1
RCS+
DBST
CPWMRMP 8
RBIASIN
CVCCL
RVCC
RPWMRMP
CVCC
RCSCCS+
CCS-
20k
16
CSIN+
17
CSIN-
19
18
20
PGND
GATEL
CIN
15
14
L
13
12
11
VCC
10
SCOMP
CSCOMP
GATEH
VCCL
LGND
ISHARE
9
VRHOT
6
RPHASE53
DACIN
BIASIN
HOTSET
RPHASE52
5
PWMRMP
4
CBST
VCCH
IR3086A
PHASE
IC
RMPIN-
EAIN
3
RMPIN+
7
2
PHSFLT
RPHASE51
1
RCS+
DBST
CPWMRMP 8
RBIASIN
CVCCL
RVCC
RPWMRMP
CVCC
RCSCCS+
16
CSIN+
17
CSIN-
20
19
18
DACIN
BIASIN
PGND
GATEL
CIN
15
14
L
13
12
11
VCC
SCOMP
6
CSCOMP
GATEH
VCCL
10
ISHARE
LGND
VRHOT
9
HOTSET
RPHASE62
5
PWMRMP
4
CBST
VCCH
IR3086A
PHASE
IC
RMPIN-
EAIN
3
RMPIN+
7
2
RCS+
DBST
PHSFLT
RPHASE61
1
RPHASE63
CCS-
20k
CPWMRMP 8
RBIASIN
CVCCL
RVCC
RPWMRMP
CVCC
Figure 12. IR3080/IR3086A Six Phase VRD 10 Converter
Page 19
COUT
VOUT10
LGND
VCCL
9
PWMRMP
SCOMP
6
EAIN
ISHARE
EAIN
ROSC
VRHOT
CSCOMP
2
1uF
HOTSET
RPHASE12
RPHASE13
23
CBST2
VCCH
IR3086A
PHASE
IC
RMPIN-
RPHASE21
ROSC
RFB
24
VDAC
16
15
TRM4
IIN
RFB1
RMPIN+
7
RHOTSETC2
26
VDRP
OCSET
TRM3
5
25
LGND
27
29
30
31
28
VRHOT
SS/DEL
HOTSET
VIDDEL
PWRGD
RMPOUT
FB
VID3
9
VID4
BBFB
EAOUT
VID2
VOSNS-
8
14
VID3
VID1
13
VID2
7
VBIAS
VID0
4
CFB
RBBFB
VCC
IR3080
CONTROL
IC
VID5
12
6
0.1uF
RHOTSETC1
VCCVID
VIDPWR
3
CPWMRMP 8
CSS/DEL RSS/DEL
CVIDDEL
VID1
VIDPGD
32
5
TRM2
4
VID0
TRM1
3
VID5
VID4
3.3V
VIDFB
11
2
2
1nF
10
1
1
RCS+
DBST3
PHSFLT
RPHASE11
CVCC
0.1uF
CCS-
7
DGATE
RGATE
20k
CPWMRMP 8
RBIASIN
IR3080PbF
DESIGN PROCEDURES - IR3080 AND IR3086A CHIPSET
IR3080 EXTERNAL COMPONENTS
Oscillator Resistor Rosc
The oscillator of IR3080 generates a triangle waveform to synchronize the phase ICs, and the switching frequency
of the each phase converter equals the oscillator frequency, which is set by the external resistor ROSC according to
the curve in Figure 13.
VID Delay Capacitor CVIDDEL
After the VID voltage of the integrated linear regulator is above 1.1V, there is a time delay before the soft start of the
converter is initiated. The VID delay time tVID can be programmed by an external capacitor between VIDDEL pin
and LGND, and the capacitance is determined by (1).
CVIDDEL =
66 *10−6 ∗ tVID
3.91
(1)
Soft Start Capacitor CSS/DEL and Resistor RSS/DEL
Because the capacitor CSS/DEL programs four different time parameters, i.e. soft start delay time, soft start time,
over-current latch delay time, and power good delay time, they should be considered together while choosing
CSS/DEL.
The SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 11. After the
VIDDEL pin voltage rises above 3.91V, there is a soft-start delay time tSSDEL, after which the error amplifier output
is released to allow the soft start. The soft start time tSS represents the time during which converter voltage rises
from zero to VO. tSS can be programmed by an external capacitor, which is determined by Equation (2).
C SS / DEL =
I CHG * t SS 70 * 10 −6 * t SS
=
VO
VO
(2)
Once CSS/DEL is chosen, the soft start delay time tSSDEL, the over-current fault latch delay time tOCDEL, and the
delay time tVccPG from output voltage (VO) in regulation to Power Good are fixed and shown in Equations (3), (4)
and (5) respectively.
*1.3 CSS / DEL *1.3
C
(3)
=
tSSDEL = SS / DEL
I CHG
70 *10−6
t OCDEL =
tVccPG =
C SS / DEL * 0.09 C SS / DEL * 0.09
=
I DISCHG
6 *10 −6
CSS / DEL * (3.91 − VO − 1.3) CSS / DEL * (3.91 − VO − 1.3)
=
I CHG
70 *10−6
(4)
(5)
If faster over-current protection is required, a resistor in series with the soft start capacitor CSS/DEL can be used to
reduce the over-current fault latch delay time tOCDEL, and the resistor RSS/DEL is determined by Equation (6).
Equation (2) for soft start capacitor CSS/DEL and Equation (5) for power good delay time tVccPG are unchanged,
while the equation for soft start delay time tSS/DEL (Equation 3) is changed to Equation (7). Considering the worst
case values of charge and discharge current, RSS/DEL should not be greater than 10 kΩ.
*I
t
t
∗ 6 *10−6
0.09 − OCDEL DISCHG 0.09 − OCDEL
CSS / DEL
CSS / DEL
(6)
RSS / DEL =
−
I DISCHG
6 *10−6
Page 20
IR3080PbF
t SSDEL =
C SS / DEL * (1.3 − R SS / DEL * I CHG ) C SS / DEL * (1.3 − R SS / DEL ∗ 70 *10 −6 )
=
I CHG
70 *10 − 6
(7)
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
The slew rate of VDAC down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in
Equation (8), where ISINK is the sink current of VDAC pin as shown in Figure 15. The resistor RVDAC is used to
compensate VDAC circuit and is determined by Equation (9). The slew rate of VDAC up-slope SRUP is proportional
to that of VDAC down-slope and is given by Equation (10), where ISOURCE is the source current of VDAC pin as
shown in Figure15.
CVDAC =
I SINK
SR DOWN
RVDAC = 0.5 +
SRUP =
3.2 ∗ 10 −15
CVDAC 2
I SOURCE
CVDAC
(8)
(9)
(10)
Over Current Setting Resistor ROCSET
The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant
temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from Equation
(11), where RL_MAX and RL_ROOM are the inductor DCR at maximum temperature TL_MAX and room temperature
T_ROOM respectively.
R L _ MAX = R L _ ROOM ∗ [1 + 3850 * 10 −6 ∗ (T L _ MAX − TROOM )]
(11)
The current sense amplifier gain of IR3086A decreases with temperature at the rate of 1470 ppm/°C, which
compensates part of the inductor DCR increase. The phase IC die temperature is only a couple of degrees Celsius
higher than the PCB temperature due to the low thermal impedance of MLPQ package. The minimum current sense
amplifier gain at the maximum phase IC temperature TIC_MAX is calculated from Equation (12).
GCS _ MIN = GCS _ ROOM ∗ [1 − 1470 * 10 −6 ∗ (TIC _ MAX − TROOM )]
(12)
The total input offset voltage (VCS_TOFST) of current sense amplifier in phase ICs is the sum of input offset
(VCS_OFST) of the amplifier itself and that created by the amplifier input bias currents flowing through the current
sense resistors RCS+ and RCS-.
VCS _ TOFST = VCS _ OFST + I CSIN + ∗ RCS + − I CSIN − ∗ RCS −
(13)
The over current limit is set by the external resistor ROCSET as defined in Equation (14), where ILIMIT is the required
over current limit. IOCSET, the bias current of OCSET pin, changes with switching frequency setting resistor ROSC
and is determined by the curve in Figure 14. KP is the ratio of inductor peak current over average current in each
phase and is calculated from Equation (15).
ROCSET = [
KP =
Page 21
I LIMIT
∗ RL _ MAX ∗ (1 + K P ) + VCS _ TOFST ]GCS _ MIN / IOCSET
n
(VI − VO ) ∗ VO /( L ∗ VI ∗ f SW ∗ 2)
IO / n
(14)
(15)
IR3080PbF
No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP
A resistor between FB pin and the converter output is used to create output voltage offset VO_NLOFST, which is the
difference between VDAC voltage and output voltage at no load condition. Adaptive voltage positioning further
lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter.
RFB is not only determined by IFB, the current flowing out of FB pin as shown in Figure 14, but also affected by the
adaptive voltage positioning resistor RDRP and total input offset voltage of current sense amplifiers. RFB and RDRP
are determined by (16) and (17) respectively,
R FB =
R L _ MAX ∗ VO _ NLOFST − VCS _ TOFST ∗ n ∗ RO
R DRP =
I FB ∗ R L _ MAX
R FB ∗ R L _ MAX ∗ GCS _ MIN
n ∗ RO
(16)
(17)
Control IC Over Temperature Setting Resistors RHOTSETC1 and RHOTSETC2
The threshold voltage of VRHOT comparator is proportional to the die temperature TJ (ºC) of control IC IR3080, as
shown in Equation (18). Determine the relationship between the die temperature of IR3080 and the temperature of
the power converter according to the power loss, PCB layout and airflow, etc. Then calculate the VRHOT threshold
voltage corresponding to the temperature.
VVRHOT = 4.73 *10−3 * TJ + 1.241
(18)
Use VBIAS as the reference voltage. If RHOTSETC1 is pre selected, RHOTSETC2 can be calculated according to
Equation (19).
VVRHOT
(19)
RHOTSETC 2 = RHOTSETC1
VVBIAS + VVRHOT
Body BrakingTM Related Resistors RBBFB and RBBDRP
The body brakingTM during Dynamic VID can be disabled by connecting BBFB pin to ground. If the feature is
enabled, Resistors RBBFB and RBBDRP are needed to restore the feedback voltage of the error amplifier after
Dynamic VID step down. Usually RBBFB and RBBDRP are chosen to match RFB and RDRP respectively.
IR3086A EXTERNAL COMPONENTS
PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP
PWM ramp is generated by connecting the resistor RPWMRMP between a voltage source and PWMRMP pin as well
as the capacitor CPWMRMP between PWMRMP and LGND. Choose the desired PWM ramp magnitude VPWMRMP
and the capacitor CPWMRMP in the range of 100pF and 470pF, and then calculate the resistor RPWMRMP from
Equation (20). To achieve feed-forward voltage mode control, the resistor RRAMP should be connected to the input
of the converter.
VO
(20)
RPWMRMP =
VIN * f SW * CPWMRMP * [ln(VIN − VDAC ) − ln(VIN − VDAC − VPWMRMP )]
Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCSThe DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS+ and capacitor
CCS+ in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage
across the capacitor CCS+ represents the inductor current. If the two time constants are not the same, the AC
component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch
does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as well
as the output voltage during the load current transient if adaptive voltage positioning is adopted.
Page 22
IR3080PbF
Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS+ and calculate RCS+ as
follows.
L RL
(21)
RCS + =
C CS +
The bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across
RCS+, which is equivalent to an input offset voltage of the current sense amplifier. The offset affects the accuracy of
converter current signal ISHARE as well as the accuracy of the converter output voltage if adaptive voltage
positioning is adopted. To reduce the offset voltage, a resistor RCS- should be added between the amplifier inverting
input and the converter output. The resistor RCS- is determined by the ratio of the bias current from the non-inverting
input and the bias current from the inverting input.
RCS − =
I CSIN +
∗ RCS +
I CSIN −
(22)
If RCS- is not used, RCS+ should be chosen so that the offset voltage is small enough. Usually RCS+ should be less
than 2 kΩ and therefore a larger CCS+ value is needed.
Over Temperature Setting Resistors RHOTSET1 and RHOTSET2
The threshold voltage of VRHOT comparator is proportional to the die temperature TJ (ºC) of phase IC. Determine
the relationship between the die temperature of phase IC and the temperature of the power converter according to
the power loss, PCB layout and airflow etc, and then calculate HOTSET threshold voltage corresponding to the
allowed maximum temperature from Equation (23).
V HOTSET = 4.73 * 10 −3 * T J + 1.241
(23)
There are two ways to set the over temperature threshold, central setting and local setting. In the central setting,
only one resistor divider is used, and the setting voltage is connected to HOTSET pins of all the phase ICs. To
reduce the influence of noise on the accuracy of over temperature setting, a 0.1uF capacitor should be placed next
to HOTSET pin of each phase IC. In the local setting, a resistor divider per phase is needed, and the setting voltage
is connected to HOTSET pin of each phase. The 0.1uF decoupling capacitor is not necessary. Use VBIAS as the
reference voltage. If RHOTSET1 is pre-selected, RHOTSET2 can be calculated as follows.
RHOTSET 2 =
RHOTSET 1 ∗ VHOTSET
VBIAS − VHOTSET
(24)
Phase Delay Timing Resistors RPHASE1 and RPHASE2
The phase delay of the interleaved multiphase converter is programmed by the resistor divider connected at
RMPIN+ or RMPIN- depending on which slope of the oscillator ramp is used for the phase delay programming of
phase IC, as shown in Figure 3.
If the upslope is used, RMPIN+ pin of the phase IC should be connected to RMPOUT pin of the control IC and
RMPIN- pin should be connected to the resistor divider. When RMPOUT voltage is above the trip voltage at
RMPIN- pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time.
If down slope is used, RMPIN- pin of the phase IC should be connected to RMPOUT pin of the control IC and
RMPIN+ pin should be connected to the resistor divider. When RMPOUT voltage is below the trip voltage at
RMPIN- pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time.
Use VBIAS voltage as the reference for the resistor divider since the oscillator ramp magnitude from control IC
tracks VBIAS voltage. Try to avoid both edges of the oscillator ramp for better noise immunity. Determine the ratio
of the programming resistors corresponding to the desired switching frequencies and phase numbers. If the resistor
RPHASEx1 is pre-selected, the resistor RPHASEx2 is determined as:
R PHASEx 2 =
Page 23
RAPHASEx ∗ R PHASEx1
1 − RAPHASEx
(25)
IR3080PbF
Combined Over Temperature and Phase Delay Setting Resistors RPHASE1, RPHASE2 and RPHASE3
The over temperature setting resistor divider can be combined with the phase delay resistor divider to save one
resistor per phase.
Calculate the HOTSET threshold voltage VHOTSET corresponding to the allowed maximum temperature from
Equation (23). If the over temperature setting voltage is lower than the phase delay setting voltage,
VBIAS*RAPHASEx, connect RMPIN+ or RMPIN- pin between RPHASEx1 and RPHASEx2, and connect HOTSET pin
between RPHASEx2 and RPHASEx3. Pre-select RPHASEx1,
RPHASEx 2 =
( RAPHASEx ∗ VBIAS − VHOTSET ) * RPHASEx1
VBIAS ∗ (1 − RAPHASEx )
(26)
RPHASEx3 =
VHOTSET ∗ RPHASEx1
VBIAS * (1 − RAPHASEx )
(27)
If the over temperature setting voltage is higher than the phase delay setting voltage, VBIAS*RAPHASEx, connect
HOTSET pin between RPHASEx1 and RPHASEx2 and connect RMPIN+ or RMPIN- between RPHASEx2 and RPHASEx3
respectively. Pre-select RPHASEx1,
R PHASEx 2 =
(V HOTSET − RAPHASEx ∗ V BIAS ) ∗ R PHASEx1
V BIAS − V HOTSET
(28)
RPHASEx3 =
RAPHASEx ∗ VBIAS * RPHASEx1
VBIAS − VHOTSET
(29)
Bootstrap Capacitor CBST
Depending on the duty cycle and gate drive current of the phase IC, a 0.1uF to 1uF capacitor is needed for the
bootstrap circuit.
Decoupling Capacitors for Phase IC
0.1uF-1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs.
VOLTAGE LOOP COMPENSATION
The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient
response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning loop
introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the voltage
loop compensation much easier.
Resistors RFB and RDRP are chosen according to Equations (16) and (17), and the selection of compensation types
depends on the output capacitors used in the converter. For the applications using Electrolytic, Polymer or ALPolymer capacitors and running at lower frequency, type II compensation shown in Figure 17(a) is usually enough.
While for the applications using only ceramic capacitors and running at higher frequency, type III compensation
shown in Figure 17(b) is preferred.
For applications where AVP is not required, the compensation is the same as for the regular voltage mode control.
For converter using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero frequency,
type III compensation is required as shown in Figure 17(b) with RDRP and CDRP removed.
Type II Compensation for AVP Applications
Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10
and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the
output inductors matches that of the inductor, and determine RCP and CCP from Equations (30) and (31), where LE
and CE are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors
respectively.
Page 24
IR3080PbF
CCP1
CCP1
RCP
VO+
RFB
CCP
-
VDAC
RDRP
RFB1
CFB
FB
CCP
-
EAOUT
EAOUT
FB
EAOUT
EAOUT
VDRP
RCP
RFB
VO+
VDRP
RDRP
VDAC
+
CDRP
+
(a) Type II compensation
(b) Type III compensation
Figure 17. Voltage loop compensation network
(2π ∗ fC ) 2 ∗ LE ∗ CE ∗ RFB ∗ VPWMRMP
RCP =
VO * 1 + (2π * fC * C * RC ) 2
C CP =
10 ∗ L E ∗ C E
(30)
(31)
RCP
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A
ceramic capacitor between 10pF and 220pF is usually enough.
Type III Compensation for AVP Applications
Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and
capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the
voltage loop can be estimated by Equations (32) and (33), where RLE is the equivalent resistance of inductor DCR.
f C1 =
RDRP
2π * CE ∗ GCS * RFB ∗ RLE
θ C1 = 90 − A tan(0.5) ∗
(32)
180
(33)
π
Choose the desired crossover frequency fc around fc1 estimated by Equation (32) or choose fc between 1/10 and
1/5 of the switching frequency per phase, and select the components to ensure the slope of close loop gain is -20dB
/Dec around the crossover frequency. Choose resistor RFB1 according to Equation (34), and determine CFB and
RDRP from Equations (35) and (36).
1
R FB
2
R FB1 =
CFB =
to
R FB1 =
1
4π ∗ fC ∗ RFB1
C DRP =
( R FB + R FB1 ) ∗ C FB
R DRP
2
R FB
3
(34)
(35)
(36)
RCP and CCP have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency
and transient load response. Determine RCP and CCP from Equations (37) and (38).
Page 25
IR3080PbF
RCP =
(2π ∗ fC ) 2 ∗ LE ∗ CE ∗ RFB ∗ VPWMRMP
VO
10 ∗ L E ∗ C E
C CP =
(37)
(38)
RCP
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A
ceramic capacitor between 10pF and 220pF is usually enough.
Type III Compensation for Non-AVP Applications
Resistor RFB is chosen according to Equations (16), and resistor RDRP and capacitor CDRP are not needed. Choose
the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the desired phase
margin θc. Calculate K factor from Equation (39), and determine the component values based on Equations (40) to
(44),
π
θ
K = tan[ ∗ ( C + 1.5)]
4 180
RCP = RFB ∗
(39)
( 2π ∗ LE ∗ CE ∗ fC ) 2 ∗ VPWMRMP
VO ∗ K
(40)
CCP =
K
2π ∗ fC ∗ RCP
(41)
CCP1 =
1
2π ∗ fC ∗ K ∗ RCP
(42)
CFB =
K
2π ∗ fC ∗ RFB
(43)
R FB1 =
1
2π ∗ f C ∗ K ∗ C FB
(44)
CURRENT SHARE LOOP COMPENSATION
The crossover frequency of the current share loop should be at least one decade lower than that of the voltage loop
in order to eliminate the interaction between the two loops. A capacitor from SCOMP to ground is usually enough
for the share loop compensation. Choose the crossover frequency of current share loop (fCI) based on the
crossover frequency of voltage loop (fC), and determine the CSCOMP,
CSCOMP =
0.65 * RPWMRMP *VI * I O * GCS _ ROOM * RLE * [1 + 2π * fCI * CE * (VO I O )] * FMI
VO ∗ 2π ∗ fCI *1.05 *106
(45)
Where FMI is the PWM gain in the current share loop,
FMI =
Page 26
RPWMRMP * CPWMRMP * f SW *V PWMRMP
(VI − VPWMRMP − VDAC ) * (VI − VDAC )
(46)
IR3080PbF
DESIGN EXAMPLE 1 - VRD 10 CONVERTER
SPECIFICATIONS
Input Voltage: VI=12 V
DAC Voltage: VDAC=1.35 V
No Load Output Voltage Offset: VO_NLOFST=20 mV
Output Current: IO=105 ADC
Maximum Output Current: IOMAX=120 ADC
Output Impedance: RO=0.91 mΩ
VCC Ready to VCC Power Good Delay: tVccPG=0-10mS
VID Delay Time: tVID=2.5mS
Soft Start Time: tSS=2mS
Over Current Delay: tOCDEL=0.5mS
Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS
Over Temperature Threshold: TPCB=115 ºC
POWER STAGE
Phase Number: n=6
Switching Frequency: fSW=400 kHz
Output Inductors: L=220 nH, RL=0.47 mΩ
Output Capacitors: AL-Polymer, C=560uF, RC= 7mΩ, Number Cn=10
IR3080 EXTERNAL COMPONENTS
Oscillator Resistor Rosc
Once the switching frequency is chosen, ROSC can be determined from the curve in Figure 13. For switching
frequency of 400kHz per phase, choose ROSC=30.1kΩ
VID Delay Capacitor CVIDDEL
Given VID delay time tVID =2.5mS, the capacitor can is,
CVIDDEL =
66 *10−6 * tVID 66 *10−6 ∗ 2.5 *10−3
=
= 42nF , choose 47nF
3.91
3.91
Soft Start Capacitor CSS/DEL and Resistor RSS/DEL
Because faster over-current protection is required, the soft start capacitor CSS/DEL in series with the resistor
RSS/DEL is used. Calculate the soft start capacitor from the required soft start time.
C SS / DEL =
I CHG ∗ t SS 70 * 10 −6 ∗ 2 * 10 −3
=
= 0.1uF
VO
1.35 − 20 * 10 −3
Calculate the soft start resistor from the required over current delay time tOCDEL,
0.09 −
RSS / DEL =
tOCDEL ∗ I DISCHG
0.5 *10−3 ∗ 6 *10−6
0.09 −
CSS / DEL
0.1 *10− 6
= 10kΩ
=
I DISCHG
6 *10− 6
The soft start delay time is
tSSDEL =
CSS / DEL ∗ (1.3 − RSS / DEL ∗ I CHG ) 0.1 *10−6 ∗ (1.3 − 10 *103 * 70 *10−6 )
=
= 0.86mS
I CHG
70 *10− 6
Page 27
IR3080PbF
The power good delay time is
tVccPG =
CSS / DEL * (3.91 − VO − 1.3) 0.1*10−6 * (3.91 − 1.33 − 1.3)
=
= 1.8ms
I CHG
70 *10− 6
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
From Figure 15, the sink current of VDAC pin corresponding to 400kHz (ROSC=30.1kΩ) is 76uA. Calculate the
VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate.
CVDAC =
I SINK
76 * 10 −6
=
= 30.4nF , Choose CVDAC=33nF
SR DOWN
2.5 * 10 −3 / 10 −6
Calculate the programming resistor.
RVDAC = 0.5 +
3.2 * 10 −15
CVDAC 2
= 0.5 +
3.2 * 10 −15
(33 * 10 −9 ) 2
= 3.5Ω
From Figure 15, the source current of VDAC pin is 110uA. The VDAC up-slope slew rate is
SRUP =
I SOURCE 110 * 10 −6
=
= 3.3mV / uS
CVDAC
33 * 10 −9
Over Current Setting Resistor ROCSET
The room temperature is 25ºC and the target PCB temperature is 100 ºC. The phase IC die temperature is about 1
ºC higher than that of phase IC, and the inductor temperature is close to PCB temperature.
Calculate Inductor DC resistance at 100 ºC,
RL _ MAX = RL _ ROOM ∗ [1 + 3850*10−6 ∗ (TL _ MAX − TROOM )] = 0.47 *10−3 ∗ [1 + 3850*10−6 ∗ (100 − 25)] = 0.61mΩ
The current sense amplifier gain is 34 at 25ºC, and its gain at 101ºC is calculated as,
G CS _ MIN = G CS _ ROOM ∗ [1 − 1470 *10 −6 ∗ (T IC _ MAX − T ROOM )] = 34 ∗ [1 − 1470 *10 −6 ∗ (101 − 25)] = 30.2
Set the over current limit at 135A. From Figure 14, the bias current of OCSET pin (IOCSET) is 41uA with
ROSC=30.1kΩ. The total current sense amplifier input offset voltage is 0.55mV, which includes the offset created by
the current sense amplifier input resistor mismatch.
Calculate constant KP, the ratio of inductor peak current over average current in each phase,
KP =
(V I − VO ) ∗ VO /( L ∗ V I ∗ f SW ∗ 2) (12 − 1.33) ∗ 1.33 /( 220 *10 −9 ∗ 12 ∗ 400 * 10 3 ∗ 2)
=
= 0.3
I LIMIT / n
135 / 6
ROCSET = [
=(
I LIMIT
∗ RL _ MAX ∗ (1 + K P ) + VCS _ TOFST ] ∗ GCS _ MIN / I OCSET
n
135
∗ 0.61 *10 −3 ∗ 1.3 + 0.55 *10 −3 ) ∗ 30.2 /( 41 *10 − 6 ) = 13.3kΩ
6
No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP
From Figure 14, the bias current of FB pin is 41uA with ROSC=30.1kΩ.
RFB =
RL _ MAX ∗ VO _ NLOFST − VCS _ TOFST ∗ n ∗ RO
Page 28
I FB ∗ RL _ MAX
=
0 .61 * 10 −3 ∗ 20 * 10 −3 − 0 .55 * 10 −3 ∗ 6 ∗ 0 .91 * 10 −3
= 365 Ω
41 * 10 − 6 ∗ 0 .61 * 10 − 3
IR3080PbF
RDRP =
RFB ∗ RL _ MAX ∗ GCS _ MIN
n ∗ RO
=
365 ∗ 0.61 *10−3 ∗ 30.2
= 1.21kΩ
6 ∗ 0.91 *10−3
Control IC Over Temperature Setting Resistors RHOTSETC1 and RHOTSETC2
Set the temperature threshold at 115 ºC, which corresponds to the IC die temperature of 116 ºC. Calculate the
HOTSET threshold voltage corresponding to the temperature thresholds.
V HOTSET = 4.73 * 10 −3 * TJ + 1.241 = 4.73 * 10 −3 ∗ 116 + 1.241 = 1.79V , Choose RHOTSETC1=20.0kΩ,
R HOTSETC 2 =
R HOTSETC1 ∗ V HOTSET 20 *10 3 ∗1.79
= 7.15kΩ
=
6.8 − 1.79
V BIAS − V HOTSET
Body Braking Related Resistors RBBFB and RBBDRP
N/A. The body braking during Dynamic VID is disabled.
IR3086A EXTERNAL COMPONENTS
PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP
Set PWM ramp magnitude VPWMRMP=0.8V. Choose 220pF for PWM ramp capacitor CPWMRMP, and calculate the
resistor RPWMRMP,
VO
RPWMRMP =
VIN ∗ f SW ∗ CPWMRMP ∗ [ln(VIN − VDAC ) − ln(VIN − VDAC − VPWMRMP )]
=
1.33
12 ∗ 400 *10 3 ∗ 220 * 10 −12 ∗ [ln(12 − 1.35) − ln(12 − 1.35 − 0.8)]
= 16.1kΩ , Choose RPWMRMP=16.2kΩ
Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCSChoose CCS+=47nF and calculate RCS+,
RCS + =
L RL 220 *10−9 /(0.47 *10−3 )
=
= 10.0kΩ
CCS +
47 *10−9
The bias currents of CSIN+ and CSIN- are 0.25uA and 0.4uA respectively. Calculate resistor RCS-,
RCS − =
0.25
0.25
∗ RCS + =
∗ 10.0 *103 = 6.2kΩ , Choose RCS-=6.19kΩ
0.4
0.4
Over Temperature Setting Resistors RHOTSET1 and RHOTSET2
Use central over temperature setting and set the temperature threshold at 115 ºC, which corresponds the IC die
temperature of 116 ºC. Calculate the HOTSET threshold voltage corresponding to the temperature thresholds.
V HOTSET = 4.73 * 10 −3 * TJ + 1.241 = 4.73 * 10 −3 ∗ 116 + 1.241 = 1.79V
Pre-slect RHOTSET1=10.0kΩ,
R HOTSET 2 =
R HOTSET 1 ∗ V HOTSET 10 *10 3 ∗1.79
= 3.57 kΩ
=
6.8 − 1.79
V BIAS − V HOTSET
Phase Delay Timing Resistors RPHASE1 and RPHASE2
Use central over temperature setting and set the temperature threshold at 115 ºC, which corresponds the IC die
temperature of 116 ºC. Calculate the HOTSET threshold voltage corresponding to the temperature thresholds.
Page 29
IR3080PbF
The phase delay resistor ratios for phases 1 to 6 at 400kHz of switching frequencies are RAPHASE1=0.628,
RAPHASE2=0.415, RAPHASE3=0.202, RAPHASE4=0.246, RAPHASE5=0.441 and RAPHASE6=0.637 starting from downslope. Pre-select RPHASE11=RPHASE21=RPHASE31=RPHASE41=RPHASE51= RPHASE61=10kΩ,
RPHASE12 =
RAPHASE1
0.628
∗ RPHASE11 =
∗ 10 *103 = 16.9kΩ
1 − RAPHASE1
1 − 0.628
RPHASE22=7.15kΩ, RPHASE32=2.55kΩ, RPHASE42=3.24kΩ, PPHASE52=7.87kΩ, RPHASE62=17.4kΩ
Bootstrap Capacitor CBST
Choose CBST=0.1uF
Decoupling Capacitors for Phase IC and Power Stage
Choose CVCC=0.1uF, CVCCL=0.1uF
VOLTAGE LOOP COMPENSATION
Type II compensation is used for the converter with AL-Polymer output capacitors. Choose the crossover frequency
fc=40kHz, which is 1/10 of the switching frequency per phase, and determine Rcp and CCP.
RCP =
CCP =
(2π ∗ fC )2 ∗ LE ∗ CE ∗ RFB ∗ VRAMP
VO * 1 + (2π * fC * C * RC )2
10 ∗ LE ∗ CE
RCP
=
=
(2π ∗ 40 ∗103 )2 ∗ (220 ∗10−9 / 6) ∗ (560 ∗10−6 ∗10) ∗ 365 ∗ 0.8
(1.35 − 20 ∗10−3 ) * 1 + (2π * 40 *103 * 560 *10−6 * 7 *10−3 )2
10 ∗ (220 ∗ 10−9 / 6) ∗ (560 ∗ 10−6 *10)
2.0 ∗103
= 2.0kΩ
= 71nF , Choose CCP=68nF
Choose CCP1=47pF to reduce high frequency noise.
CURRENT SHARE LOOP COMPENSATION
The crossover frequency of the current share loop fCI should be at least one decade lower than that of the voltage
loop fC. Choose the crossover frequency of current share loop fCI=4kHz, and calculate CSCOMP,
FMI =
RPWMRMP * CPWMRMP * f SW *V PWMRMP 16.2 *103 * 220 *10−12 * 400 *103 * 0.8
=
= 0.011
(VI − VPWMRMP − VDAC ) * (VI − VDAC )
(12 − 0.8 − 1.35) * (12 − 1.35)
CSCOMP =
=
0.65 * RPWMRMP *VI * I O * GCS _ ROOM * RLE * [1 + 2π * fCI * CE * (VO I O )] * FMI
VO ∗ 2π ∗ fCI *1.05 *106
0.65 *16.2 *10 3 *12 *105 * 34 * (0.47 *10 −3 6) * [1 + 2π * 4 *10 3 * 560 *10 −6 *10 * (1.33 − 105 * 9.1*10 −4 ) 105] * 0.011
= 31.4nF
Choose CSCOMP=33nF.
Page 30
(1.33 − 105 * 9.1*10 − 4 ) ∗ 2π ∗ 4 *10 3 *1.05 *10 6
IR3080PbF
DESIGN EXAMPLE 2 - EVRD 10 HIGH FREQUENCY ALL-CERAMIC CONVERTER
SPECIFICATIONS
Input Voltage: VI=12 V
DAC Voltage: VDAC=1.3 V
No Load Output Voltage Offset: VO_NLOFST=20 mV
Output Current: IO=105 ADC
Maximum Output Current: IOMAX=120 ADC
Output Impedance: RO=0.91 mΩ
VCC Ready to VCC Power Good Delay: tVccPG=0-10mS
VID Delay Time: tVID=2.5mS
Soft Start Time: tSS=2.9mS
Over Current Delay: tOCDEL=2.1mS
Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS
Over Temperature Threshold: TPCB=115 ºC
POWER STAGE
Phase Number: n=6
Switching Frequency: fSW=800 kHz
Output Inductors: L=100 nH, RL=0.5 mΩ
Output Capacitors: Ceramic, C=22uF, RC= 2mΩ, Number Cn=62
IR3080 EXTERNAL COMPONENTS
Oscillator Resistor Rosc
Once the switching frequency is chosen, ROSC can be determined from the curve in Figure 13. For switching
frequency of 800kHz per phase, choose ROSC=13.3kΩ
VID Delay Capacitor CVIDDEL
Given VID delay time tVID =2.5mS, the capacitor can is,
CVIDDEL =
66 *10−6 * tVID 66 *10−6 ∗ 2.5 *10−3
=
= 42nF , choose 47nF
3.91
3.91
Soft Start Capacitor CSS/DEL and Resistor RSS/DEL
Because faster over-current protection is required, the soft start capacitor CSS/DEL in series with the resistor
RSS/DEL is used. Calculate the soft start capacitor from the required soft start time.
CSS / DEL =
I CHG ∗ tSS 70 *10−6 ∗ 2.9 *10−3
=
= 0.16uF , choose CSS/DEL=0.15uF
VO
1.3 − 20 *10−3
Calculate the soft start resistor from the required over current delay time tOCDEL,
0.09 −
RSS / DEL =
tOCDEL ∗ I DISCHG
2.1*10−3 ∗ 6 *10−6
0.09 −
CSS / DEL
0.15 *10−6
=
= 1kΩ
I DISCHG
6 *10−6
The soft start delay time is
C
∗ (1.3 − R SS / DEL ∗ I CHG ) 0.15 * 10 −6 ∗ (1.3 − 1 * 10 3 * 70 * 10 −6 )
t SSDEL = SS / DEL
=
= 2.6mS
I CHG
70 * 10 −6
Page 31
IR3080PbF
The power good delay time is
C SS / DEL ∗ (3.91 − VO − 1.3) 0.15 * 10 −6 * (3.91 − 1.28 − 1.3)
=
= 2.85ms
I CHG
70 * 10 −6
tVccPG =
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
From Figure 15, the sink current of VDAC pin corresponding to 800kHz (ROSC=13.3kΩ) is 170uA. Calculate the
VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate.
CVDAC =
I SINK
170 * 10 −6
=
= 68nF
SR DOWN
2.5 * 10 −3 / 10 −6
Calculate the programming resistor.
RVDAC = 0.5 +
3.2 * 10 −15
CVDAC 2
= 0.5 +
3.2 * 10 −15
(68 * 10 −9 ) 2
= 1.2Ω
From Figure 15, the source current of VDAC pin is 250uA. The VDAC up-slope slew rate is
SRUP =
I SOURCE 250 *10 −6
=
= 3.7 mV / uS
CVDAC
68 *10 −9
Over Current Setting Resistor ROCSET
The room temperature is 25ºC and the target PCB temperature is 100 ºC. The phase IC die temperature is about 1
ºC higher than that of phase IC, and the inductor temperature is close to PCB temperature.
Calculate Inductor DC resistance at 100 ºC,
RL _ MAX = RL _ ROOM ∗ [1 + 3850*10−6 ∗ (TL _ MAX − TROOM )] = 0.5 *10−3 ∗ [1 + 3850*10−6 ∗ (100 − 25)] = 0.64mΩ
The current sense amplifier gain is 34 at 25ºC, and its gain at 101ºC is calculated as,
G CS _ MIN = G CS _ ROOM ∗ [1 − 1470 *10 −6 ∗ (T IC _ MAX − T ROOM )] = 34 ∗ [1 − 1470 *10 −6 ∗ (101 − 25)] = 30.2
Set the over current limit at 135A. From Figure 14, the bias current of OCSET pin (IOCSET) is 90uA with
ROSC=13.3kΩ. The total current sense amplifier input offset voltage is 0.55mV, which includes the offset created by
the current sense amplifier input resistor mismatch.
Calculate constant KP, the ratio of inductor peak current over average current in each phase,
KP =
(VI − VO ) ∗ VO /( L ∗ VI ∗ f SW ∗ 2) (12 − 1.28) ∗ 1.28 /(100 *10−9 ∗ 12 ∗ 800 *103 ∗ 2)
=
= 0.32
I LIMIT / n
135 / 6
ROCSET = [
=(
RLIMIT
∗ RL _ MAX ∗ (1 + K P ) + VCS _ TOFST ] ∗ GCS _ MIN / I OCSET
n
135
∗ 0.64 *10 − 3 ∗ 1.32 + 0.55 *10 −3 ) * 30.2 /(90 *10 − 6 ) = 6.34 kΩ
6
No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP
From Figure 14, the bias current of FB pin is 90uA with ROSC=13.3kΩ.
RFB =
RL _ MAX ∗ VO _ NLOFST − VCS _ TOFST ∗ n ∗ RO
Page 32
I FB ∗ RL _ MAX
=
0.64 *10−3 ∗ 20 *10−3 − 0.55 *10−3 ∗ 6 ∗ 0.91 *10−3
= 162Ω
90 *10−6 * 0.64 *10−3
IR3080PbF
RDRP =
RFB ∗ RL _ MAX ∗ GCS _ MIN
n ∗ RO
=
162 ∗ 0.64 *10−3 * 30.2
= 576Ω
6 ∗ 0.91 *10−3
Control IC Over Temperature Setting Resistors RHOTSETC1 and RHOTSETC2
Set the temperature threshold at 115 ºC, which corresponds the IC die temperature of 116 ºC. Calculate the
HOTSET threshold voltage corresponding to the temperature thresholds.
V HOTSET = 4.73 * 10 −3 * TJ + 1.241 = 4.73 * 10 −3 ∗ 116 + 1.241 = 1.79V , choose RHOTSETC1=10.0kΩ,
R HOTSETC 2 =
R HOTSETC1 ∗ V HOTSET 10 *10 3 ∗1.79
=
= 3.57 kΩ
V BIAS − V HOTSET
6.8 − 1.79
Body Braking Related Resistors RBBFB and RBBDRP
N/A. The body braking during Dynamic VID is disabled.
IR3086A EXTERNAL COMPONENTS
PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP
Set PWM ramp magnitude VPWMRMP=0.75V. Choose 100pF for PWM ramp capacitor CPWMRMP, and calculate the
resistor RPWMRMP,
VO
RPWMRMP =
VIN * f SW * CPWMRMP * [ln(VIN − VDAC ) − ln(VIN − VDAC − VPWMRMP )]
=
1.28
= 18.2kΩ
3
−
12
12 ∗ 800 *10 ∗100 *10
∗ [ln(12 − 1.3) − ln(12 − 1.3 − 0.75)]
Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCSChoose 47nF for capacitor CCS+ and calculate RCS+,
RCS + =
L RL 100 *10−9 /(0.5 *10−3 )
=
= 4.22kΩ
CCS +
47 *10−9
The bias currents of CSIN+ and CSIN- are 0.25uA and 0.4uA respectively. Calculate resistor RCS-,
RCS − =
0.25
0.25
∗ RCS + =
∗ 4.22 *10 3 = 2.61kΩ
0.4
0.4
Combined Over Temperature and Phase Delay Setting Resistors RPHASEx1, RPHASEx2 and RPHASEx3
The over temperature setting resistor divider is combined with the phase delay resistor divider. Set the temperature
threshold at 115 ºC, which corresponds the IC die temperature of 116 ºC, and calculate the HOTSET threshold
voltage corresponding to the temperature thresholds.
V HOTSET = 4.73 * 10 −3 ∗ TJ + 1.241 = 4.73 * 10 −3 ∗ 116 + 1.241 = 1.79V
The phase delay resistor ratios for phases 1 to 6 at 800kHz of switching frequencies are RAPHASE1=0.665,
RAPHASE2=0.432, RAPHASE3=0.198, RAPHASE4=0.206, RAPHASE5=0.401 and RAPHASE6=0.597 starting from downslope.
Page 33
IR3080PbF
The over temperature setting voltage of phases 1, 2, 5, and 6 is lower than the phase delay setting voltage,
VBIAS*RAPHASEx. Pre-select RPHASE11=10kΩ,
RPHASEx 2 =
( RAPHASEx ∗ VBIAS − VHOTSET ) * RPHASEx1 (0.665 ∗ 6.8 − 1.79) ∗10 *103
= 12.1kΩ
=
6.8 ∗ (1 − 0.665)
VBIAS ∗ (1 − RAPHASEx )
RPHASEx3 =
VHOTSET ∗ RPHASEx1
1.79 ∗ 12.1 *103
=
= 7.87 kΩ
VBIAS * (1 − RAPHASEx ) 6.8 * (1 − 0.665)
RPHASE21=10kΩ, RPHASE22=2.94kΩ, RPHASE23=4.64kΩ
RPHASE51=10kΩ, RPHASE52=2.32kΩ, RPHASE53=4.42kΩ
RPHASE61=10kΩ, RPHASE62=8.25kΩ, RPHASE63=6.49kΩ
The over temperature setting voltage of Phases 3 and 4 is higher than the phase delay setting voltage,
VBIAS*RAPHASEx. Pre-select RPHASEX1=10kΩ,
R PHASE 32 =
(V HOTSET − RAPHASE 3 ∗ V BIAS ) ∗ R PHASE 31 (1.79 − 0.198 ∗ 6.8) ∗10 *10 3
= 887Ω
=
V BIAS − V HOTSET
6.8 − 1.79
RPHASE 33 =
RAPHASE 3 ∗ VBIAS * RPHASE 31 0.198 ∗ 6.8 ∗ 10 *103
= 2.67 kΩ
=
6.8 − 1.79
VBIAS − VHOTSET
RPHASE41=10kΩ, RPHASE42=768Ω, RPHASE43=2.80kΩ
Bootstrap Capacitor CBST
Choose CBST=0.1uF
Decoupling Capacitors for Phase IC and Power Stage
Choose CVCC=0.1uF, CVCCL=0.1uF
VOLTAGE LOOP COMPENSATION
Type III compensation is used for the converter with only ceramic output capacitors. The crossover frequency and
phase margin of the voltage loop can be estimated as follows.
f C1 =
R DRP
576
=
= 146 kHz
−6
2π ∗ C E ∗ G CS ∗ R FB ∗ R LE
2π ∗ (62 ∗ 22 *10 ) ∗ 34 ∗ 162 ∗ (0.5 *10 − 3 / 6)
θC1 = 90 − A tan(0.5) ∗
Choose RFB1 =
180
π
= 63°
2
2
∗ RFB = ∗ 162 = 110Ω
3
3
Choose the desired crossover frequency fc (=140kHz) around fc1 estimated above, and calculate
CFB =
1
4π ∗ fC ∗ RFB1
CDRP =
=
1
= 5.2nF , Choose CFB=5.6nF
4π ∗ 140 *103 ∗ 110
( RFB + RFB1 ) ∗ CFB (162 + 110) ∗ 5.6 *10−9
=
= 2.7 nF
RDRP
576
Page 34
IR3080PbF
RCP =
CCP =
( 2π ∗ fC ) 2 ∗ LE ∗ CE ∗ RFB ∗ VRAMP (2π ∗140 *103 ) 2 ∗ (100 *10−9 / 6) ∗ (22 *10−6 ∗ 62) ∗162 * 0.75
=
= 1.65kΩ
VO
1.3 − 20 *10−3
10 ∗ LE ∗ CE
RCP
=
10 ∗ (100 *10−9 / 6) ∗ ( 22 *10−6 * 62)
1.65 ∗ 103
= 27 nF
Choose CCP1=47pF to reduce high frequency noise.
CURRENT SHARE LOOP COMPENSATION
The crossover frequency of the current share loop fCI should be at least one decade lower than that of the voltage
loop fC. Choose the crossover frequency of current share loop fCI=3.5kHz, and calculate CSCOMP,
FMI =
RPWMRMP * CPWMRMP * f SW *V PWMRMP 18.2 *103 *100 *10−12 * 800 *103 * 0.75
=
= 0.011
(VI − VPWMRMP − VDAC ) * (VI − VDAC )
(12 − 0.75 − 1.3) * (12 − 1.3)
CSCOMP =
=
0.65 * RPWMRMP *VI * I O * GCS _ ROOM * RLE * [1 + 2π * fCI * CE * (VO I O )] * FMI
VO ∗ 2π ∗ fCI *1.05 *106
0.65 *18.2 *10 3 *12 *105 * 34 * (0.5 *10 −3 6) * [1 + 2π * 3500 * 22 *10 −6 * 62 * (1.33 − 105 * 9.1*10 −4 ) 105] * 0.011
= 20.6nF
Choose CSCOMP=22nF
Page 35
(1.33 − 105 * 9.1*10 − 4 ) ∗ 2π ∗ 3500 *1.05 *10 6
IR3080PbF
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
•
•
•
•
•
•
Dedicate at least one middle layer for a ground plane LGND.
Connect the ground tab under the control IC to LGND plane through a via.
Place the following critical components on the same layer as control IC and position them as close as possible
to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, CVCC, CSS/DEL and RSS/DEL. Avoid using any via for the
connection.
Place the compensation components on the same layer as control IC and position them as close as possible to
EAOUT, FB and VDRP pins. Avoid using any via for the connection.
Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over
the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.
Control bus signals, VDAC, RMPOUT, IIN, VBIAS, and especially EAOUT, should not cross over the fast
transition nodes.
Page 36
IR3080PbF
PCB Metal and Component Placement
• Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should
be ≥ 0.2mm to minimize shorting.
• Lead land length should be equal to maximum part lead length + 0.2 mm outboard extension + 0.05mm
inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard
extension will accommodate any part misalignment and ensure a fillet.
• Center pad land length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥
0.23mm for 3 oz. Copper)
• A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to
minimize the noise effect on the IC.
Page 37
IR3080PbF
Solder Resist
• The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder
resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non
Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.
• The minimum solder resist width is 0.13mm, therefore it is recommended that the solder resist is
completely removed from between the lead lands forming a single opening for each “group” of lead
lands.
• At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a
fillet so a solder resist width of ≥ 0.17mm remains.
• The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto
the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable
to have the solder resist opening for the land pad to be smaller than the part pad.
• Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high
aspect ratio of the solder resist strip separating the lead lands from the pad land.
• The single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than
the diameter of the via.
Page 38
IR3080PbF
Stencil Design
• The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.
Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm
pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower;
openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.
• The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead
land.
• The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit
approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad
the part will float and the lead lands will be open.
• The maximum length and width of the land pad stencil aperture should be equal to the solder resist
opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the
lead lands when the part is pushed into the solder paste.
Page 39
IR3080PbF
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency (kHz)
Figure 13 - Oscillator Frequency versus ROSC
1000
950
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
ROSC (K Ohms)
Figure 14 - IFB, BBFB, & OCSET Bias Currents vs ROSC
125
115
105
95
85
uA
75
65
55
45
35
25
15
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
ROSC (K Ohm)
Figure 15 - VDAC Source & Sink Currents vc ROSC (includes OCSET
Bias Current)
325
300
275
250
225
uA
200
175
ISINK
150
ISOURCE
125
100
75
50
25
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
ROSC (K ohm)
Figure 16 - Bias Current Accuracy versus ROsC (includes
temperature and input voltage variation)
18%
+/-3 Sigma Variation (%)
16%
14%
FB, BBFB, OCSET Bias
Current
12%
10%
VDAC Sink Current
8%
VDAC Source Current
6%
4%
2%
0%
10
20
30
40
50
60
70
80
90 100 110 120 130 140
ROSC (K Ohm)
Page 40
IR3080PbF
PACKAGE INFORMATION
32L MLPQ (5 x 5 mm Body) – θJA = 30oC/W, θJC = 3oC/W
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.www.irf.com 10/4/2005
Page 41
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