Monolithic 12-Bit 2 MHz A/D Converter AD671 a FEATURES 12-Bit Resolution 24-Pin “Skinny DIP” Package Conversion Time: 500 ns max—AD671J/K/S-500 Conversion Time: 750 ns max—AD671J/K/S-750 Low Power: 475 mW Unipolar (0 V to +5 V, 0 V to +10 V) and Bipolar Input Ranges (65 V) Twos Complement or Offset Binary Output Data Out-of-Range Indicator MIL-STD-883 Compliant Versions Available FUNCTIONAL BLOCK DIAGRAM AIN BPO/UPO 20 21 ENCODE REF IN VCC ACOM VEE 16 23 19 RANGE SELECT 3-BIT FLASH 22 V LOGIC DCOM 17 18 24 X4 DAC 3-BIT FLASH 3 8-BIT LADDER MATRIX COARSE 4-BIT FLASH DAC 3 FINE 4-BIT FLASH 4 CORRECTION LOGIC 4 8 LATCHES AD671 12 14 13 OTR MSB 12 1 15 BIT1-12 DAV PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD671 is a high speed monolithic 12-bit A/D converter offering conversion rates of up to 2 MHz (500 ns conversion time). The combination of a merged high speed bipolar/CMOS process and a novel architecture results in a combination of speed and power consumption far superior to previously available hybrid implementations. Additionally, the greater reliability of monolithic construction offers improved system reliability and lower costs than hybrid designs. 1. The AD671 offers a single chip 2 MHz analog-to-digital conversion function in a space saving 24-pin DIP. The AD671 uses a subranging flash conversion technique, with digital error correction for possible errors introduced in the first part of the conversion cycle. An on-chip timing generator provides strobe pulses for each of the four internal flash cycles and assures adequate settling time for the interflash residue amplifier. A single ENCODE pulse is used to control the converter. The performance of the AD671 is made possible by using high speed, low noise bipolar circuitry in the linear sections and low power CMOS for the logic sections. Analog Devices’ ABCMOS-1 process provides both high speed bipolar and 2-micron CMOS devices on a single chip. Laser trimmed thin-film resistors are used to provide accuracy and temperature stability. 2. Input signal ranges are 0 V to +5 V and 0 V to +10 V unipolar, and –5 V to +5 V bipolar, selected by pin strapping. Input resistance is 1.5 kΩ. Power supplies are +5 V and –5 V, and typical power consumption is less than 500 mW. 3. The external +5 V reference can be chosen to suit the dc accuracy and temperature drift requirements of the application. 4. Output data is available in unipolar, bipolar offset or bipolar twos complement binary format. 5. An OUT OF RANGE output bit indicates when the input signal is beyond the AD671’s input range. 6. The AD671 is available in versions compliant with the MILSTD-883. Refer to the Analog Devices Military Products Databook or current AD671/883B data sheet for detailed specifications. The AD671 is available in two conversion speeds and performance grades. The AD671J and K grades are specified for operation over the 0°C to +70°C temperature range. The AD671S grades are specified for operation over the –55°C to +125°C temperature range. All grades are available in a 0.300 inch wide 24-pin ceramic DIP. The J and K grades are also available in a 24-pin plastic DIP. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD671–SPECIFICATIONS (T to T with V MIN MAX CC = +5 V 6 5%, VLOGIC = +5 V 610%, VEE = –5 V 6 5%, VREF = +5.000 V, DC SPECIFICATIONS unless otherwise noted) Parameter Min RESOLUTION 12 ACCURACY (+25°C) Integral Nonlinearity (INL) TMIN to TMAX Differential Nonlinearity (DNL) TMIN to TMAX No Missing Codes Unipolar Offsetl Bipolar Zerol Gain Error2 AD671J/S-500 Typ Input Resistance 10 Volt Range 5 Volt Range Input Capacitance Reference Input Resistance POWER SUPPLIES Power Supply Rejection4 VCC (+5 V ± 0.25 V) VLOGIC (+5 V ± 0.5 V) VEE (–5 V ± 0.25 V) Operating Voltages VCC VLOGIC VEE Operating Current ICC ILOGIC5 IEE Max 10 62 11 10 Bits Guaranteed Bits 0.1 610 615 620 –5 0 0 1.0 0.5 2.4 1.5 0.75 10 3.5 +5 +5 +10 –5 0 0 2.0 1.0 1.0 0.5 4.7 2.4 1.5 0.75 10 3.5 61 61 61 +4.75 +4.5 –5.25 LSB 11 Bits Guaranteed 64 610 0.25 0.1 Units Bits 64 POWER CONSUMPTION TEMPERATURE RANGE Specified (J/K) Specified (S) AD671K-500 Typ Min 12 TEMPERATURE COEFFICIENTS3 Unipolar Offset Bipolar Zero Gain Error ANALOG INPUT Input Ranges Bipolar Unipolar Max +5.25 +5.5 –4.75 +4.75 +4.5 –5.25 64 610 0.25 LSB LSB % FSR 610 615 620 ppm/°C ppm/°C ppm/°C +5 +5 +10 Volts Volts Volts 2.0 1.0 4.7 kΩ kΩ pF kΩ 61 61 61 LSB LSB LSB +5.25 +5.5 –4.75 Volts Volts Volts 46 3 46 56 6 56 46 3 46 56 6 56 mA mA mA 475 621 475 621 mW +70 °C °C 0 –55 +70 +125 0 NOTES 1 Adjustable to zero with external potentiometers. See Offset/Gain Calibration section for additional information. 2 Full-scale range (FSR) is 5 V for the 0 V to 5 V range and 10 V for the 0 V to 10 V and –5 V to +5 V ranges. 3 25°C to TMIN and 25°C to TMAX. 4 Change in gain error as a function of the dc supply voltage. 5 Tested under static conditions. See Figure 12 for typical curves of ILOGIC vs. Conversion Rate and Output Loading. Specifications subject to change without notice. Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at 0, +25 °C and +70°C. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested. –2– REV. B AD671 (TMIN to TMAX with VCC = +5 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –5 V 6 5%, VREF = +5.000 V, DC SPECIFICATIONS unless otherwise noted) Parameter Min RESOLUTION 12 ACCURACY (+25°C) Integral Nonlinearity (INL) TMIN to TMAX (J) TMIN to TMAX (S) Differential Nonlinearity (DNL) TMIN to TMAX No Missing Codes Unipolar Offsetl Bipolar Zerol Gain Error2 AD671J/S-750 Typ Input Resistance 10 Volt Range 5 Volt Range Input Capacitance Reference Input Resistance POWER SUPPLIES Power Supply Rejection4 VCC (+5 V ± 0.25 V) VLOGIC (+5 V ± 0.5 V) VEE (–5 V ± 0.25 V) Operating Voltages Vcc VLOGIC VEE Operating Current ICC ILOGIC5 IEE Max 11 61.5 12 11 Bits Guaranteed Bits 0.1 610 615 620 –5 0 0 1.0 0.5 2.4 1.5 0.75 10 3.5 +5 +5 +10 –5 0 0 2.0 1.0 1.0 0.5 4.7 2.4 1.5 0.75 10 3.5 61 61 61 +4.75 +4.5 –5.25 LSB LSB 12 Bits Guaranteed 64 610 0.25 0.1 Units Bits 62 62.5 POWER CONSUMPTION TEMPERATURE RANGE Specified (J/K) Specified (S) AD671K-750 Typ Min 12 TEMPERATURE COEFFICIENTS3 Unipolar Offset Bipolar Zero Gain Error ANALOG INPUT Input Ranges Bipolar Unipolar Max +5.25 +5.5 –4.75 +4.75 +4.5 –5.25 64 610 0.25 LSB LSB % FSR 610 615 620 ppm/°C ppm/°C ppm/°C +5 +5 +10 Volts Volts Volts 2.0 1.0 4.7 kΩ kΩ pF kΩ 61 61 61 LSB LSB LSB +5.25 +5.5 –4.75 Volts Volts Volts 46 3 46 56 6 56 46 3 46 56 6 56 mA mA mA 475 621 475 621 mW +70 °C °C 0 –55 +70 +125 0 NOTES 1 Adjustable to zero with external potentiometers. See Offset/Gain Calibration section for additional information. 2 Full-scale range (FSR) is 5 V for the 0 V to 5 V range and 10 V for the 0 V to 10 V and –5 V to +5 V ranges. 3 25°C to TMIN and 25°C to TMAX. 4 Change in gain error as a function of the dc supply voltage. 5 Tested under static conditions. See Figure 12 for typical curves of I LOGIC vs. Conversion Rate and Output Loading. Specifications subject to change without notice. Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at 0, +25 °C and +70°C. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested. REV. B –3– AD671–SPECIFICATIONS (For all grades T DIGITAL SPECIFICATIONS 6 5%, V REF MIN to TMAX, with VCC = +5 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –5 V = +5.000 V, unless otherwise noted) Parameter Symbol Min LOGIC INPUT High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = VLOGIC) Low Level Input Current (VIN = 0 V) Input Capacitance VIH VIL IIH IIL CIN +2.0 LOGIC OUTPUTS High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Output Capacitance VOH VOL COUT +2.4 Typ –10 –10 Max Units +0.8 +10 +10 V V µA µA pF +0.4 V V pF 5 5 Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested. Specifications subject to change without notice. (For all grades TMIN to TMAX with VCC = +5 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –5 V IL = 0.8 V, VIH = 2.0 V, VOL = 0.4 V and VOH = 2.4 V) SWITCHING SPECIFICATIONS 6 5%, V Parameter Symbol Conversion Time (AD671-500) (AD671-750) ENCODE Pulse Width High (AD671-500) (AD671-750) ENCODE Pulse Width Low DAV Pulse Width (AD671-500) (AD671-750) ENCODE Falling Edge Delay Start New Conversion Delay Data and OTR Delay from DAV Falling Edge Data and OTR Valid before DAV Rising Edge Min tC tC Typ Max Units 475 725 500 750 ns ns tENC tENC tENCL 20 20 20 30 50 ns ns ns tDAV tDAV tF tR tDD1 tSS2 75 75 0 0 20 20 200 300 ns ns ns ns ns ns 75 75 NOTES 1 tDD is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin. 2 tSS is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin. b. Encode Pulse LOW a. Encode Pulse HIGH Figure 1. AD671 Timing Diagrams –4– REV. B AD671 ABSOLUTE MAXIMUM RATINGS* Parameter VCC VEE VLOGIC ACOM VCC ENCODE REF IN AIN, BPO/UPO Junction Temperature Storage Temperature Lead Temperature (10 sec) Power Dissipation With Respect to Min ACOM ACOM DCOM DCOM VLOGIC DCOM ACOM ACOM Max ORDERING GUIDE Units –0.5 –6.5 –0.5 –1.0 –6.5 –0.5 –0.5 –6.5 +6.5 Volts +0.5 Volts +6.5 Volts +1.0 Volts +6.5 Volts VLOGIC +0.5 Volts VCC +0.5 Volts 11.0 Volts +175 °C –65 +150 °C +300 °C 1000 mW Modell Linearity Temperature Range Package Options2 AD671JD-500 AD671KD-500 AD671JD-750 AD671KD-750 AD671SD-500 AD671SD-750 ± 4 LSB ± 2 LSB ± 2 LSB ± 1.5 LSB ± 4 LSB ± 2.5 LSB 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –55°C to +125°C –55°C to +125°C D-24A D-24A D-24A D-24A D-24A D-24A NOTES 1 For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current AD671/883 data sheet. 2 D = Ceramic DIP. *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD671 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– WARNING! ESD SENSITIVE DEVICE AD671 AD671 PIN DESCRIPTION Symbol Pin Type Name and Function ACOM AIN BIT1 (MSB) BIT2–BIT11 BIT12 (LSB) BPO/UPO 22 20 12 11–2 1 21 P AI DO DO DO AI DAV 15 DO DCOM ENCODE 18 16 P DI MSB 13 DO OTR 14 DO REF IN VCC VEE VLOGIC 19 23 24 17 AI P P P CONNECTION DIAGRAM PINOUT Analog Ground. Analog Input Signal. Most Significant Bit. Data Bits 2–11. Least Significant Bit. Bipolar or Unipolar Configuration Pin. Connect to AIN for 0 V to +5 V Span, to ACOM for 0 V to +10 V Span and to REF IN for –5 V to +5 V Span. Data Available Output. The Rising Edge of DAV Indicates an End of Conversion and Can Be Used to Latch Current Data into an External Register. The Falling Edge of DAV Can Be Used to Latch Previous Data into an External Register. Digital Ground. The AD671 Starts a Conversion on the Rising Edge of the ENCODE Pulse. Inverted Most Significant Bit. Provides Twos Complement Output Data Format. Out of Range Is Active HIGH when the analog input is beyond the input range of the converter. +5 V Reference Input. +5 V Analog Power. –5 V Analog Power. +5 V Digital Power. 1 24 VEE BIT11 2 23 VCC BIT10 3 22 ACOM BIT9 4 21 BPO/UPO BIT12 (LSB) 20 AIN BIT8 5 BIT7 6 AD671 19 REF IN BIT6 7 TOP VIEW (Not to Scale) 18 DCOM BIT5 8 17 VLOGIC BIT4 9 16 ENCODE BIT3 10 15 DAV BIT2 11 14 OTR BIT1 (MSB) 12 13 MSB TYPE: AI = Analog Input DI = Digital Input DO = Digital Output P = Power –6– REV. B AD671 DEFINITIONS OF SPECIFICATIONS GAIN ERROR INTEGRAL NONLINEARITY (INL) The last transition (from 1111 1111 1110 to 1111 1111 1111) should occur for an analog value 1 1/2 LSB below the nominal full scale (9.9963 volts for 10.000 volts full scale). The gain error is the deviation of the actual level at the last transition from the ideal level. The gain error can be adjusted to zero as shown in Figures 7, 8 and 9. Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB (1.22 mV for a 10 V span) before the first code transition (all zeros to only the LSB on). “Full scale” is defined as a level 1 1/2 LSB beyond the last code transition (to all ones). The deviation is measured from the low side transition of each particular code to the true straight line. TEMPERATURE COEFFICIENTS The temperature coefficients for unipolar offset, bipolar zero and gain error specify the maximum change from the initial (+25°C) value to the value at TMIN or TMAX. DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. Guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes represented by Bits 1–10 must be present over all operating ranges. Guaranteed no missing codes to 11- or 12-bit resolution indicates that all 2048 and 4096 codes, respectively, must be present over all operating ranges. POWER SUPPLY REJECTION The only effect of power supply error on the performance of the device will be a small change in gain. The specifications show the maximum full-scale change from the initial value with the supplies at the various limits. SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. UNIPOLAR OFFSET The first transition should occur at a level 1/2 LSB above analog common. Unipolar offset is defined as the deviation of the actual from that point. This offset can be adjusted as discussed later. The unipolar offset temperature coefficient specifies the maximum change of the transition point over temperature, with or without external adjustments. EFFECTIVE NUMBER OF BITS (ENOB) ENOB is calculated from the expression SNR = 6.02N + 1.8 dB, where N is equal to the effective number of bits. BIPOLAR ZERO TOTAL HARMONIC DISTORTION (THD) In the bipolar mode the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 LSB below analog common. The bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error over temperature. THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. PEAK SPURIOUS OR PEAK HARMONIC COMPONENT The peak spurious or peak harmonic component is the largest spectral component excluding the input signal and dc. This value is expressed in decibels relative to the rms value of a fullscale input signal. Theory of Operation The AD671 uses a successive subranging architecture. The analog to digital conversion takes place in four independent steps or flashes. The analog input signal is subranged to an intermediate residue voltage for the final 12-bit result by utilizing multiple flashes with subtraction DACs (see the AD671 functional block diagram). (AD671-500) and less than 50 ns after the falling edge of ENCODE (AD671–750) or after the falling edge of DAV. The time window prevents digitally coupled noise from being introduced during the final stages of conversion. An internal timing generator circuit accurately controls all internal timing. ACOM 22 The AD671 can be configured to operate with unipolar (0 V to +5 V, 0 V to +10 V) or bipolar (± 5 V) inputs by connecting AIN (Pin 20), REFIN (Pin 19) and BPO/UPO (Pin 21) as shown in Figure 2. BPO/UPO 21 AIN 20 The AD671 conversion cycle begins by simply providing an active HIGH pulse on the ENCODE pin (Pin 16). The rising edge of the ENCODE pulse starts the conversion. The falling edge of the ENCODE pulse is specified to operate within a window of time: less than 30 ns after the rising edge of ENCODE REV. B BPO/UPO 21 REF IN 19 AIN + 5V REF 0 TO + 5V BPO/UPO 21 AIN 20 REF IN 19 AIN + 5V REF 0 TO +10V AIN 20 REF IN 19 + 5V REF – 5V TO + 5V Figure 2. Input Range Connections –7– AIN AD671 Upon receipt of an ENCODE command, the first 3-bit flash converts the analog input voltage. The 3-bit result is passed to a correction logic register and a segmented current output DAC. The DAC output is connected through a resistor (within the Range/Span Select Block) to AIN. A residue voltage is created by subtracting the DAC output from AIN, which is less than one eighth of the full-scale analog input. The second flash has an input range that is configured with one bit of overlap with the previous DAC. The overlap allows for errors during the flash conversion. The first residue voltage is connected to the second 3-bit flash and to the noninverting input of a high speed, differential, gain-of-four amplifier. The second flash result is passed to the correction logic register and to the second segmented current output DAC. The output of the second DAC is connected to the inverting input of the differential amplifier. The differential amplifier output is connected to a two step backend 8-bit flash. This 8-bit flash consists of coarse and fine flash converters. The result of the coarse 4-bit flash converter, also configured to overlap one bit of DAC 2, is connected to the correction logic register and selects one of 16 resistors from which the fine 4-bit flash will establish its span voltage. The fine 4-bit flash is connected directly to the output latches. INPUT BUFFER AMPLIFIER The closed-loop output impedance of an op amp is equal to the open loop output impedance (usually a few hundred ohms) divided by the loop gain at the frequency of interest. It is often assumed that loop gain of a follower-connected op amp is sufficiently high to reduce the closed-loop output impedance to a negligibly small value, particularly if the input signal is low frequency. At higher frequencies the open-loop gain is lower, increasing the output impedance which decreases the instantaneous analog input voltage and produces an error. The recommended wideband, fast settling input amplifiers for use with the AD671 are the AD841, AD843, AD845 or the AD847. The AD841 is unity gain stable and recommended as a follower connected op amp. The AD843 and AD845 FET inputs make them ideal for high speed sample-and-hold amplifiers and the AD847 can be used as a low power, high speed buffer. Figure 4 shows the AD841 driving the AD671. As shown in the figure the analog input voltage should be produced with respect to the ACOM pin. 4 11 AD841 10 5 6 + – DRIVING THE AD671 ANALOG INPUT + + 5V REF IIN R – A/D IA/D DAC IDAC AD671 Figure 3. Driving the Analog Input Unlike successive approximation A/Ds, where the input voltage must settle to a fraction of a 12-bit LSB before each successive bit decision is made, the AD671 requires the analog input voltage settle to within 12 bits before the third flash conversion, approximately 200 ns. This “free” 200 ns is useful in applications requiring a sample-and-hold amplifier (SHA), overlapping the SHA’s hold mode settling time within the 200 ns window will increase total system throughput. See the “Discrete Sampleand-Hold” section for a high speed SHA application. VCC BIT1 1 20 AIN BIT12 12 ±5V APPLYING THE AD671 The AD671 uses a very high speed current output DAC to subtract a known voltage from the analog input. This results in very fast steps of current at the analog input. It is important to recognize that the signal source driving the analog input of the AD671 must be capable of maintaining the input voltage under dynamically-changing load conditions. When the AD671 starts its conversion cycle, the subtraction DAC will sink up to 5 mA (see Figure 3) from the source driving the analog input. The source must respond to this current step by settling the input voltage back to a fraction of an LSB before the AD671 makes its final 12-bit decision. 17 24 VEE VLOGIC 23 The AD671 will flag an out-of-range condition when the input voltage exceeds the analog input range. OTR (Pin 14) is active HIGH when an out of range high or low condition exists. Bits 1–12 are HIGH when the analog input voltage is greater than the selected input range and LOW when the analog input is less than the selected input range. 22 ACOM ENCODE 16 18 DCOM DAV 15 19 REF IN OTR 14 21 BPO/UPO MSB 13 AD671 Figure 4. Input Buffer Amplifier REFERENCE INPUT The AD671 uses a standard +5 volt reference. The initial accuracy and temperature stability of the reference can be selected to meet specific system requirements. Like the analog input, fast switching input-dependent currents are modulated at the reference input pin (REF IN–Pin 19). However, unlike the analog input the reference input is held at a constant +5 volts with the use of capacitor. The recommended reference is the AD586, a +5 V precision reference with an output buffer amplifier. Figure 5 shows the AD671 configured in the ± 5 V input range. The 6.8 µF capacitor maintains a constant +5 volts under the dynamically changing load conditions. An optional 1 µF noise reduction capacitor can be connected to the AD586, further reducing broadband output noise. To minimize ground voltage drops the AD586’s ground pin should be tied as close as possible to the AD671’s ACOM pin. See Figures 20, 21 and 22 for PCB layout recommendations. –8– REV. B AD671 23 VCC 20 AIN +15V 8 1µF C14 AD586 U4 ± 5V 2 +VIN VOUT NOISE 6 REDUCTION 6.8µF C15 GND 4 Table I. Grounding and Decoupling Guidelines 24 17 VEE VLOGIC Power Supply Decoupling BIT1 1 U3 BIT12 12 22 ACOM ENCODE 16 18 DCOM DAV 15 19 REF IN OTR 14 21 BPO/UPO MSB 13 Comment 0.1 µF (Ceramic) and 10 µF (Tantalum). (Surface Mount Chip Capacitors Recommended to Reduce Lead Inductance). Capacitor Values Capacitor Locations Directly at Positive and Negative Supply Pins to Respective Ground Plane. AD671 Grounding Analog Ground Ground Plane or Wide Ground Return Connected to the Analog Power Supply. Digital Ground Ground Plane or Wide Ground Return Connected to the Digital Power Supply. Figure 5. AD586 as Reference Input for AD671 GROUNDING AND DECOUPLING RULES Proper grounding and decoupling should be a primary design objective in any high speed, high resolution system. The AD671 separates analog and digital grounds to optimize the management of analog and digital ground currents in a system. The AD671 is designed to minimize the current flowing from ACOM (Pin 22) by directing the majority of the current from VCC (+5 V–Pin 23) to VEE (–5 V–Pin 24). Minimizing analog ground currents hence reduces the potential for large ground voltage drops. This can be especially true in systems that do not utilize ground planes or wide ground runs. ACOM is also configured to be code independent, therefore reducing input dependent analog ground voltage drops and errors. The input current supplied by the external reference (REFIN–Pin 19) and the majority of the full-scale input signal (AIN–Pin 20) are also directed to VÉE. Also critical in any high speed digital design are the use of proper digital grounding techniques to avoid potential CMOS “ground bounce.” Figure 6 is provided to assist in the proper layout, grounding and decoupling techniques. Analog and Digital Ground Connected Together Once at the AD671. UNIPOLAR (0 V TO +10 V) CALIBRATION The AD671 is factory trimmed to minimize offset, gain and linearity errors. In some applications the offset and gain errors of the AD671 need to be externally adjusted to zero. This is accomplished by trimming the voltage at BPO/UPO (Pin 21) and REFIN (Pin 19). In those applications the AD588, a high precision pin programmable voltage reference, is an ideal choice. The AD588 includes a reference cell and three additional amplifiers which can be configured to provide offset and gain trims for the AD671. The circuit in Figure 7 is recommended for calibrating offset and gain errors of the AD671 when configured in the 0 V to +10 V input range. + 5V 10µF Table I is a list of grounding and decoupling guidelines that should be reviewed before laying out a printed circuit board. + 5V 10µF – 5V 10µF 0.1µF 0 TO +10V + 5V 0.1µF 23 VCC 10µF 0.1µF 24 VEE 1µF 7 6 4 3 1 VLOGIC 14 BIT1 12 BIT12 1 16 5 – 22 ACOM 10 ENCODE 16 + 5V REF 18 DCOM DAV 15 19 REF IN OTR 14 21 BPO/UPO MSB 13 8 12 BIT1 12 11 22 ACOM ENCODE 16 18 DCOM DAV 15 19 REF IN OTR 14 21 BPO/UPO MSB 13 0.1µF 10k AD671 150 10µF +15 0.1µF –15 13 R2 100k DGP* 5k 50 Figure 7. Unipolar (0 V to +10 V) Calibration The AD671 is intended to have a nominal 1/2 LSB offset so that the exact analog input for a given code will be in the middle of that code (halfway between the transitions to the codes above it and below it). Thus, the first transition ( from 0000 0000 0000 to 0000 0000 0001) will occur for an input level of +1/2 LSB (1.22 mV for 10 V range). If the offset trim resistor R2 is used, AD671 *GROUND PLANE RECOMMENDED Figure 6. AD671 Grounding and Decoupling REV. B 9 17 VLOGIC BIT12 1 10µF 1µF 15 2 AGP* VEE 50 17 AD588 VIN ± 5V 0.1µF 24 R1 100 150pF + 20 AIN 0.1µF 23 VCC + 5V 10µF 20 AIN +15V 39k 0.1µF –5V 10µF –9– AD671 it should be trimmed as above, although a different offset can be set for a particular system requirement. This circuit will give approximately ± 50 mV of offset trim range. The gain trim is done by applying a signal 1 1/2 LSBs below the nominal full scale (9.9963 for a 10 V range). Trim R1 to give the last transition (1111 1111 1110 to 11111111 1111). Bipolar calibration is similar to unipolar calibration. First, a signal 1/2 LSB above negative full scale (–4.9988 V) is applied and R1 is trimmed to give the first transition (0000 0000 0000 to 0000 0000 0001). Then a signal 1 1/2 LSB below positive full scale (+4.9963) is applied, and R2 is trimmed to give the last transition (1111 1111 1110 to 1111 1111 1111). UNIPOLAR (0 V TO +5 V) CALIBRATION OUTPUT LATCHES The connections for the 0 V to +5 V input range calibration is shown in Figure 8. The AD586, a +5 V precision voltage reference, is an excellent choice for this mode of operation because of its performance, stability and optional fine trim. The AD845 (16 MHz, low power, low cost op amp) is used to maintain the +5 volts under the dynamically changing load conditions of the reference input. +15V 0.1µF 7 2 AD845 0 TO +5V 3 1 4 8 23 VCC 20 AIN 6 24 17 VEE VLOGIC Figure 10 shows the AD671 connected to the 74HC574 Octal D-type edge triggered latches with 3-state outputs. The latch can drive highly capacitive loads (i.e., bus lines, I/O ports) while maintaining the data signal integrity. The maximum set-up and hold times of the 574 type latch must be less than 20 ns (tDD and tSS minimum). To satisfy the requirements of the 574 type latch the recommended logic families are HC, S, AS, ALS, F or BCT. New data from the AD671 is latched on the rising edge of the DAV (Pin 24) output pulse. Previous data can be latched by inverting the DAV output with a 7404 type inverter. See Figures 20, 21 and 22 for PCB layout recommendations. BIT1 12 21 BPO/UPO 1kΩ 74HC574 BIT12 1 +15V 390 –15V 0.1µF 22 ACOM ENCODE 16 0.1µF 18 DCOM DAV 15 6 19 REFIN +15V +15V 7 2 2 +VIN AD845 VOUT 6 3 OTR 14 4 MSB 13 TRIM 5 8 NOISE REDUCTION 10kΩ –15V 0.1µF 1D 2D 3D 4D 5D U6 6D 7D 8D CLK BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 DAV AD671 DATA BUS 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q OC AD586 1µF 4 GND BIT9 BIT10 BIT11 BIT12 Figure 8. Unipolar (0 V to +5 V) Calibration The AD671 offset error must be trimmed within the analog input path, either directly in front of the AD671 or within the signal conditioning chain, eliminating offset errors induced by the signal conditioning circuitry. Figure 8 shows an example of how the offset error can be trimmed in front of the AD671. The AD586 is configured in the optional fine trim mode to provide +6%/–2% (+240 LSBs/–80 LSBs) of gain trim. The procedure for trimming the offset and gain errors is similar to that used for the unipolar 10 V range with the analog input values set to onehalf the 10 V range values. BIPOLAR (65 V) CALIBRATION The connections for the bipolar input range is shown in Figure 9. The AD588 is configured to provide dual +5 V outputs. Providing a +5 V reference voltage for the AD671 gain trim and the +5 V BPO/UPO input for the bipolar offset trim. 23 VCC ±5V 24 VEE 20 AIN 6.2kΩ +15V BIT12 1 150pF 7 6 4 3 10µF 14 150pF AD588 15 2 16 9 10 8 12 11 22 ACOM ENCODE 16 18 DCOM DAV 15 19 REF IN OTR 14 21 BPO/UPO MSB 13 50 +15 10µF 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q OC 3-STATE CONTROL Figure 10. AD671 to Output Latches OUT OF RANGE An Out of Range condition exists when the analog input voltage is beyond the input range (0 V to +5 V, 0 V to +10 V, ± 5 V) of the converter. OTR (Pin 14) is set low when the analog input voltage is within the analog input range. OTR is set HIGH and will remain HIGH when the analog input voltage exceeds the input range by typically 1/2 LSB (OTR transition is tested to ± 6 LSBs of accuracy) from the center of the ± full-scale output codes. OTR will remain HIGH until the analog input is within the input range and another conversion is completed. By logical ANDing OTR with the MSB and its complement overrange high or underrange low conditions can be detected. Table II is a truth table for the over/under range circuit in Figure 11. Systems requiring programmable gain conditioning prior to the AD671 can immediately detect an out of range condition, thus eliminating gain selection iterations. Table II. Out of Range Truth Table 0.1µF R2 100 1D 2D 3D 4D 5D U5 6D 7D 8D CLK AD671 50 1 5 BIT1 12 R1 100 39k 1µF 17 VLOGIC 74HC574 OTR MSB Analog Input Is 0 0 1 1 0 1 0 1 In Range In Range Underrange Overrange AD671 0.1µF –15 13 Figure 9. Bipolar (± 5 V) Calibration –10– REV. B AD671 MSB OVER = "1" OTR UNDER = "1" MSB Figure 11. Overrange or Underrange Logic OUTPUT DATA FORMAT The AD671 provides both MSB and MSB outputs, delivering data in positive true straight binary for unipolar input ranges and positive true offset binary or twos complement for bipolar input ranges. Straight binary coding is used for systems that accept positive-only signals. If straight binary coding is used with bipolar input signals a 0 V input would result in a binary output of 2048. The application software would have to subtract 2048 to determine the true input voltage. Most processors typically perform math on signed integers and assume data is in that format. Twos complement format minimizes software overhead which is especially important in high speed data transfers, such as a DMA operation. The CPU is not bogged down performing data conversion steps, hence increasing the total system throughput. Table III. Output Data Format Input Range Coding Analog Input1 Digital Output OTR2 0 to +5 V Straight Binary ≤ –0.00061 V 0V +5 V >+5.00061 V 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1 0 0 1 0 to +10 V Straight Binary ≤ –0.00122 V 0V +10 V ≥ +10.00122 V 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1 0 0 1 –5 V to +5 V Offset Binary ≤ –5.00122 V –5 V 0V +4.99756 V ≥ +4.99878 V 0000 0000 0000 0000 0000 0000 1000 0000 0000 1111 1111 1111 1111 1111 1111 1 0 0 0 1 –5 V to +5 V 2s Complement (Using MSB) ≤ –5.00122 V –5 V 0V +4.99756 V ≥ +4.99878 V 1000 0000 0000 1000 0000 0000 0000 0000 0000 0111 1111 1111 0111 1111 1111 1 0 0 0 1 NOTES 1 Voltages listed are with offset and gain errors adjusted to zero. 2 Typical performance. ILOGIC vs. CONVERSION RATE Figure 12 shows the typical logic supply current vs. conversion rate for various capacitive loads on the digital outputs. 6.5 6.0 5.5 CL = 50pF 5.0 4.5 mA 4.0 CL = 30pF 3.5 3.0 2.5 2.0 CL = 0pF 1.5 1.0 0.5 1k 10k 100k CONVERSION RATE – Hz 1M 10M Figure 12. ILOGIC vs. Conversion Rate for Various Capacitive Loads on the Digital Outputs REV. B –11– AD671 HIGH PERFORMANCE SAMPLE-AND-HOLD AMPLIFIER (SHA) CROSS COUPLED LATCH In order to take full advantage of the AD671’s high speed capabilities, a sample-and-hold amplifier (SHA) with fast acquisition capabilities and rigid accuracy requirements is essential. One possibility is a hybrid SHA such as the HTC-0300A, but often a cost effective alternative like the one shown in Figure 13 may be a better solution. This discrete SHA requires very few components and is able to acquire signals to 0.01% accuracy in less than 350 nanoseconds. Combined with the AD671, signals with bandwidths up to 500 kHz can be converted with 12-bit accuracy. As noted in the Theory of Operation, the ENCODE pulse is specified to operate within a window of time. The circuit in Figure 14 can be used to generate a valid ENCODE pulse if a clock pulse width of greater than 30 ns is available. 1/4 7402 tw 1/4 7402 1k +15V VIN (5Vp–p) R6 4 2k R10 10k C24 0.1µF 11 U8 10 AD841 6 C25 5 R8 250 D1 1N4148 2 4 IN1 SD5001 OUT1 1 5 IN2 OUT2 8 13 IN3 R11 250 C28 20pF Figure 14. Cross Coupled Latch +15V 2 7 U9 AD845 4 3 0.1µF 6 C27 OUT3 16 OUT4 9 12 IN4 G1 G2 G3 G4 3 6 14 11 –15V 0.1µF C29 20pF R13 1k S/H C34 5pF R14 226 VR2 100k S/H DAV C26 U10 0.1µF –15V 1k –15V ENCODE 1/4 7402 R9 R7 AD671 PEDESTAL ADJ TIMING DESCRIPTION Figure 15 shows the timing requirements for the discrete SHA. The complementary S/H inputs are HCMOS-compatible although larger gate voltages will improve performance by lowering the on resistances of the DMOS switches. It should be noted that a conversion is started before the SHA has settled to 0.01% accuracy. The discrete SHA takes advantage of the fact that the AD671 does not require a 12-bit accurate input until it is 150 ns into its conversion cycle. See Figures 21, 22 and 23 for PCB layout recommendations. Figure 13. Discrete High Speed Sample-and-Hold Amplifier t SAMPLE = 1µs CIRCUIT DESCRIPTION ENCODE The discrete SHA shown in Figure 13 is a closed-loop, noninverting architecture which accepts 5 V p-p inputs. The overall gain of the SHA is +2 in order to accommodate the 10 V input span of the AD671. The AD841, with a 0.01% settling time of 110 ns, is the suggested input buffer to the SHA. The circuit also employs a SD5001 which contains four ultrahigh speed DMOS switches (Q1–Q4). The high CMRR, low input offset current, and fast settling time of the AD845 op amp are all critical features necessary for optimal performance of the discrete SHA. In sample mode, Q1 and Q3 of the SD5001 are closed (Q2 and Q4 are open). C28 is charged to the input voltage level at a rate primarily determined by the time constant, R9 • C28. Simultaneously, C29 is connected to ground through a 250 ohm resistor. If C28 is equal to C29, charge injection from Q1 will be approximately equal to charge injection from Q3 based on the symmetry of the circuit and the inherent matching of the switch capacitances. The resultant pedestal errors appear as a commonmode signal to the AD845. VR2, R13, R14, and C34 may be included if further reduction of pedestal error is required. t CONVERSION = 500ns DAV t ACQUIRE ≈ 350ns t SETTLE 350ns S/H Figure 15. AD671 to Discrete SHA Timing Diagram DYNAMIC PERFORMANCE In most sampling applications the dynamic performance of the system is limited by the performance of the SHA. The SHA’s dynamic performance can be selected to meet the system sampling requirements. Figures 16 and 17 are typical FFT plots using the discrete SHA in Figure 13. In hold mode, Q2 and Q4 are closed (Q1 and Q3 are open) to reduce feedthrough. The input signal is attenuated –78 dB relative to the input signal at frequencies up to 500 kHz. The AD845 buffers the voltage on C28 and also provides the wideband, low-impedance output necessary to drive the input of the AD671. Droop, which occurs as a result of leakage currents, will appear on C28 and will similarly appear on C29. Like pedestal errors, droop appears as a common-mode signal to the AD845 and is greatly reduced by the differential nature of the circuit. Voltage droop is typically 5 µV/µs. Figure 16. Typical FFT Plot of AD671 and Discrete SHA FIN = 100 kHz –12– REV. B AD671 DYNAMIC CHARACTERISTICS (@ +25°C, tested using the discrete SHA in Figure 15 with V CC = +5 V, VLOGIC = +5 V, VEE = –5 V, f SAMPLE = 1 MSPS)1 Model Effective Number of Bits (ENOB) FIN = 100 kHz FIN = 490 kHz Figure 17. Typical FFT Plot of AD671 and Discrete SHA FIN = 500 kHz MULTICHANNNEL DATA ACQUISITION SYSTEM The AD684, a quad high speed sample-and-hold amplifier is ideally suited for multichannel data acquisition applications. Figure 18 shows a typical data acquisition circuit using the AD684 (SHA), ADG201HS (Multiplexer), AD588 (Reference) and the AD671. The AD684 is configured to simultaneously sample four analog inputs. Each held analog input voltage can be selected by the multiplexer and buffered by the AD841. The AD671 is connected in the bipolar input range (± 5 V). 11.3 11.2 Bits Bits Signal-to-Noise and Distortion (S/N+D) Ratio FIN = 100 kHz 70 FIN = 490 kHz 68 dB dB Total Harmonic Distortion (THD) FIN = 100 kHz FIN = 490 kHz –80 –75 dB dB Peak Spurious (dc to 490 kHz) –79 dB Peak Harmonic Component (dc to 490 kHz) –76 dB NOTE 1 fIN amplitude = –0.2 dB @ 100 kHz and –0.9 dB @ 490 kHz, bipolar mode unless otherwise indicated. See Definition of Specifications for additional information. Figure 18. Data Acquisition System Using the AD684 and the AD671 REV. B AD671JD-500 Typ Units –13– AD671 AD671 TO ADSP-2100A INTERFACE Figure 19 demonstrates the AD671 to ADSP-2100A interface. The 2100A with a clock frequency of 12.5 MHz can execute an instruction in one 80 ns cycle. The AD671 is configured to perform continuous time sampling. The DAV output of the AD671 is asserted at the end of each conversion. DAV can be used to latch the conversion result into the two 574 octal D-latches. The falling edge of the sampling clock is used to generate an interrupt (IRQ3) for the processor. Upon interrupt, the ADSP2100A starts a data memory read by providing an address on the DMA bus. The decoded address generates OE for the latches and the processor reads their output over the DMA bus. The conversion result is read within a single processor cycle. DAV DMRD OE DMA0:13 ADDRESS BUS 574 8 AD671 Q0:7 8 DECODE D0:7 ADSP-2100A OE 16 DMA0:15 +5V 4 D0:3 8 DMACK BIT1:12 574 DATA BUS Q0:7 D0:7 4 SAMPLING CLOCK IRQ3 ENCODE Figure 19. AD671 to ADSP-2100A Interface AD671 TO ADSP-2101/ADSP-2102 INTERFACE Figure 20 is identical to the 2100A interface except the sampling clock is used to generate an interrupt (IRQ2) for the processor. Upon interrupt the ADSP-2101A starts a data memory read by providing an address on the Address (A) bus. The decode address generates OE for the D-latches and the processor reads their output over the Data (D) bus. Reading the conversion result is thus completed within a single processor cycle. DAV RD OE A0:13 ADDRESS BUS 574 8 Q0:7 8 DECODE AD671 D0:7 ADSP-2101 OE 16 D0:15 BIT1:12 574 DATA BUS Q0:7 D0:7 IRQ2 SAMPLING CLOCK 4 D0:3 8 4 ENCODE Figure 20. AD671 to ADSP-2101/ADSP-2102 Interface Figure 21. PCB Silkscreen and Component Placement Diagram for Figures 5, 10 and 13 –14– REV. B AD671 Figure 22. PCB Solder Side Layout for Figures 5, 10 and 13 Figure 23. PCB Component Side Layout for Figures 5, 10 and 13 REV. B –15– AD671 OUTLINE DIMENSIONS C1426a–10–9/91 Dimensions shown in inches and (mm). 24-Pin Plastic DIP (Suffix N) 24-Pin Ceramic DIP (Suffix D) 0.295 6 0.01 (7.49 6 0.26) PIN 1 1 0.300 6 0.010 (7.49 6 0.25) 1.200 6 0.012 (30.48 6 0.31) SEATING PLANE 0.085 6 0.009 (2.16 6 0.23) 0.018 6 0.002 (0.46 6 0.05) TYP 0.100 6 0.005 (2.54 6 0.13) 0.05 (1.27) TYP 1.100 6 0.005 (27.94 6 0.13) 0.010 + 0.002 –0.001 + 0.05 0.025 –0.03 ( ) PRINTED IN U.S.A. 0.175 (4.45) TOLL NON ACCUM NOTES 1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. 2. CERAMIC DIP LEADS WILL BE EITHER GOLD OR TIN PLATED IN ACCORDANCE WITH MIL-M-385 TO REQUIREMENTS. –16– REV. B