STMicroelectronics M29W800AT90N5T 8 mbit (1mb x8 or 512kb x16, boot block) low voltage single supply flash memory Datasheet

M29W800AT
M29W800AB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
Low Voltage Single Supply Flash Memory
FEATURES SUMMARY
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2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ
OPERATIONS
ACCESS TIME: 80ns
PROGRAMMING TIME: 10µs typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte or Word-by-Word
– Status Register bits and Ready/Busy
Output
SECURITY PROTECTION MEMORY AREA
INSTRUCTION ADDRESS CODING: 3 digits
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M29W800AT: D7h
– Bottom Device Code, M29W800AB: 5Bh
Figure 1. Packages
FBGA
TSOP48 (N)
12 x 20mm
TFBGA48 (ZA)
8 x 6 solder balls
SO44 (M)
Figure 2. Logic Diagram
VCC
19
15
A0-A18
DQ0-DQ14
W
E
DQ15A–1
M29W800AT
M29W800AB
G
BYTE
RB
RP
VSS
AI02599
March 2004
1/40
M29W800AT, M29W800AB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Top Boot Block Addresses, M29W800AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Bottom Boot Block Addresses, M29W800AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . .
Data Input/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . .
Data Input/Outputs (DQ8-DQ14 and DQ15A–1). . .
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . .
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte/Word Organization Select (BYTE). . . . . . . . . .
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . .
Reset/Block Temporary Unprotect Input (RP). . . . .
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . .
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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DEVICE OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stan-by. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Automatic Stan-by. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Temporary Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. User Bus Operations (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Read Electronic Signature (following AS instruction or with A9 = VID) . . . . . . . . . . . . . . 11
Table 6. Read Block Protection with AS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/40
M29W800AT, M29W800AB
INSTRUCTIONS AND COMMANDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Coded Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read/Reset (RD) Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Auto Select (AS) Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Program (PG) Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Erase (BE) Instruction.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chip Erase (CE) Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase Suspend (ES) Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase Resume (ER) Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Instructions (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . .
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . .
Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9. Polling and Toggle Bits . . . . . . . . . . . . . .
Table 10. Status Register Bits . . . . . . . . . . . . . . . . .
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MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. Absolute Maximum Ratings (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC AND AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. AC Testing Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. AC Testing Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Capacitance (1) (TA = 25 °C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 14. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 15. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 16. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 17. Write AC Characteristics, W Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 18. Write AC Characteristics, W Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 19. Write AC Characteristics, E Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 20. Write AC Characteristics, E Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. Write AC Waveforms, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10.Write AC Waveforms, E Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3/40
M29W800AT, M29W800AB
Figure 11.Read and Write AC Characteristics, RP Related . . . . . . . . . . . . . . . . . . . .
Figure 12.Data Polling and Toggle Bit AC Characteristics (1)
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 21. Data Polling and Toggle Bit AC Characteristics (1)
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13.Data Polling DQ7 AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14.Data Toggle DQ6, DQ2 AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15.Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16.Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C; VCC = 2.7V to 3.6V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Supply Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SECURITY PROTECTION MEMORY AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Read Security Data (RDS) Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 23. Security Block Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17.Security Block Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 18.TSOP48, 48 Lead Plastic Thin Small Outline, 12x20 mm - Package Outline . . . . . . . . . 34
Table 24. TSOP48, 48 Lead Plastic Thin Small Outline, 12x20 mm - Package Mechanical Data . 34
Figure 19.TFBGA48, 6 x 8 Ball Array, 0.8mm Pitch - Bottom View Package Outline . . . . . . . . . . . 35
Table 25. TFBGA48, 6 x 8 Ball Array, 0.8mm Pitch - Package Mechanical Data . . . . . . . . . . . . . . 35
Figure 20.TFBGA48 Daisy Chain Connections (Top view through package) . . . . . . . . . . . . . . . . . 36
Figure 21.TFBGA48 Daisy Chain - PCB Connections (Top view through package) . . . . . . . . . . . . 36
Figure 22.SO44 , Small Outline, 525mm Body Width - Package Outline . . . . . . . . . . . . . . . . . . . . 37
Table 26. SO44 , Small Outline, 525mm Body Width Package Mechanical Data . . . . . . . . . . . . . . 37
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 28. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 29. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4/40
M29W800AT, M29W800AB
DESCRIPTION
The M29W800A is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte or
Word-by-Word basis using only a single 2.7V to
3.6V VCC supply. For Program and Erase operations the necessary high voltages are generated
internally. The device can also be programmed in
standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against programing and erase on programming equipment,
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase,
Erase Suspend and Resume are written to the device in cycles of commands to a Command Interface using standard microprocessor write timings.
The device is offered in TSOP48 (12 x 20mm),
SO44 and TFBGA48 0.8 mm ball pitch packages.
Table 1. Signal Names
A0-A18
Address Inputs
DQ0-DQ7
Data Input/Outputs, Command Inputs
DQ8-DQ14
Data Input/Outputs
DQ15A–1
Data Input/Output or Address Input
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output
BYTE
Byte/Word Organization
VCC
Supply Voltage
VSS
Ground
NC
Not Connected Internally
DU
Don’t Use as Internally Connected
Organisation
The M29W800A is organised as 1M x8 or 512K
x16 bits selectable by the BYTE signal. When
BYTE is Low the Byte-wide x8 organisation is selected and the address lines are DQ15A–1 and
A0-A18. The Data Input/Output signal DQ15A–1
acts as address line A–1 which selects the lower
or upper Byte of the memory word for output on
DQ0-DQ7, DQ8-DQ14 remain at High impedance.
When BYTE is High the memory uses the address
inputs A0-A18 and the Data Input/Outputs DQ0DQ15. Memory control is provided by Chip Enable
E, Output Enable G and Write Enable W inputs.
A Reset/Block Temporary Unprotection RP tri-level input provides a hardware reset when pulled
Low, and when held High (at VID) temporarily unprotects blocks previously protected allowing them
to be programed and erased. Erase and Program
operations are controlled by an internal Program/
Erase Controller (P/E.C.). Status Register data
output on DQ7 provides a Data Polling signal, and
DQ6 and DQ2 provide Toggle signals to indicate
the state of the P/E.C operations. A Ready/Busy
RB output indicates the completion of the internal
algorithms.
Memory Blocks
The devices feature asymmetrically blocked architecture providing system memory integration. Both
M29W800AT and M29W800AB devices have an
array of 19 blocks, one Boot Block of 16 KBytes or
8 KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWords and fifteen Main Blocks of 64 KBytes or
32 KWords. The M29W800AT has the Boot Block
at the top of the memory address space and the
M29W800AB locates the Boot Block starting at the
bottom. The memory maps are showed in Tables
2 and 3.
Each block can be erased separately, any combination of blocks can be specified for multi-block
erase or the entire chip may be erased. The Erase
operations are managed automatically by the P/
E.C. The block erase operation can be suspended
in order to read from or program to any block not
being erased, and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unprotected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electronic Signature, Block Protection Status), Write command, Output Disable, Stan-by, Reset, Block
Protection, Unprotection, Protection Verify, Unprotection Verify and Block Temporary Unprotection.
See Table 5., Read Electronic Signature (following AS instruction or with A9 = VID) and Table
6., Read Block Protection with AS Instruction.
5/40
M29W800AT, M29W800AB
Command Interface
Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and
fifth cycles are used to input Coded cycles to the
C.I. This Coded sequence is the same for all Program/Erase Controller instructions. The 'Command' itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command sequence will reset the device to Read Array mode.
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signature or Block Protection Status), Program, Block
Erase, Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Polling,
Toggle, Error bits and the RB output may be read
at any time, during programming or erase, to monitor the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all instructions (see Table 8).
The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed
data, Electronic Signature or Block Protection Status for Read operations. In order to give additional
data protection, the instructions for Program and
Block or Chip Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be
programmed. For an Erase instruction (Block or
Chip), the fourth and fifth cycles input a further
Coded sequence before the Erase confirm command on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data
from another block or to program data in another
block, and then resumed. When power is first applied or if VCC falls below VLKO, the command interface is reset to Read Array.
Figure 3. TSOP Connections
Figure 4. SO Connections
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
NC
NC
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
12
13
24
48
M29W800T
M29W800B
37
36
25
AI02179
6/40
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
44
2
43
42
3
41
4
5
40
6
39
7
38
8
37
9
36
10
35
11 M29W800T 34
12 M29W800B 33
13
32
14
31
15
30
16
29
28
17
27
18
26
19
25
20
24
21
22
23
AI02181
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
M29W800AT, M29W800AB
Figure 5. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A
A3
A7
RB
W
A9
A13
B
A4
A17
NC
RP
A8
A12
C
A2
A6
A18
NC
A10
A14
D
A1
A5
NC
NC
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
E
DQ8
DQ10
DQ12
DQ14
BYTE
G
G
DQ9
DQ11
VCC
DQ13
DQ15
A–1
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
AI00656
7/40
M29W800AT, M29W800AB
Table 2. Top Boot Block Addresses,
M29W800AT
Table 3. Bottom Boot Block Addresses,
M29W800AB
#
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
#
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
18
16
FC000h-FFFFFh
7E000h-7FFFFh
18
64
F0000h-FFFFFh
78000h-7FFFFh
17
8
FA000h-FBFFFh
7D000h-7DFFFh
17
64
E0000h-EFFFFh
70000h-77FFFh
16
8
F8000h-F9FFFh
7C000h-7CFFFh
16
64
D0000h-DFFFFh
68000h-6FFFFh
15
32
F0000h-F7FFFh
78000h-7BFFFh
15
64
C0000h-CFFFFh
60000h-67FFFh
14
64
E0000h-EFFFFh
70000h-77FFFh
14
64
B0000h-BFFFFh
58000h-5FFFFh
13
64
D0000h-DFFFFh
68000h-6FFFFh
13
64
A0000h-AFFFFh
50000h-57FFFh
12
64
C0000h-CFFFFh
60000h-67FFFh
12
64
90000h-9FFFFh
48000h-4FFFFh
11
64
B0000h-BFFFFh
58000h-5FFFFh
11
64
80000h-8FFFFh
40000h-47FFFh
10
64
A0000h-AFFFFh
50000h-57FFFh
10
64
70000h-7FFFFh
38000h-3FFFFh
9
64
90000h-9FFFFh
48000h-4FFFFh
9
64
60000h-6FFFFh
30000h-37FFFh
8
64
80000h-8FFFFh
40000h-47FFFh
8
64
50000h-5FFFFh
28000h-2FFFFh
7
64
70000h-7FFFFh
38000h-3FFFFh
7
64
40000h-4FFFFh
20000h-27FFFh
6
64
60000h-6FFFFh
30000h-37FFFh
6
64
30000h-3FFFFh
18000h-1FFFFh
5
64
50000h-5FFFFh
28000h-2FFFFh
5
64
20000h-2FFFFh
10000h-17FFFh
4
64
40000h-4FFFFh
20000h-27FFFh
4
64
10000h-1FFFFh
08000h-0FFFFh
3
64
30000h-3FFFFh
18000h-1FFFFh
3
32
08000h-0FFFFh
04000h-07FFFh
2
64
20000h-2FFFFh
10000h-17FFFh
2
8
06000h-07FFFh
03000h-03FFFh
1
64
10000h-1FFFFh
08000h-0FFFFh
1
8
04000h-05FFFh
02000h-02FFFh
0
64
00000h-0FFFFh
00000h-07FFFh
0
16
00000h-03FFFh
00000h-01FFFh
8/40
M29W800AT, M29W800AB
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names.
Address Inputs (A0-A18). The address inputs
for the memory array are latched during a write operation on the falling edge at Chip Enable E or
Write Enable W. In Word-wide organisation the
address lines are A0-A18, in Byte-wide organisation DQ15A–1 acts as an additional LSB address
line. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or Device Code,
Block Protection Status or a Write Block Protection
or Block Unprotection is enabled depending on the
combination of levels on A0, A1, A6, A12 and A15.
Data Input/Outputs (DQ0-DQ7). These Inputs/
Outputs are used in the Byte-wide and Word-wide
organisations. The input is data to be programmed
in the memory array or a command to be written to
the C.I. Both are latched on the rising edge of Chip
Enable E or Write Enable W. The output is data
from the Memory Array, the Electronic Signature
Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit
DQ7, the Toggle Bits DQ6 and DQ2, the Error bit
DQ5 or the Erase Timer bit DQ3. Outputs are valid
when Chip Enable E and Output Enable G are active. The output is high impedance when the chip
is deselected or the outputs are disabled and
when RP is at a Low level.
Data Input/Outputs (DQ8-DQ14 and DQ15A–
1). These Inputs/Outputs are additionally used in
the Word-wide organisation. When BYTE is High
DQ8-DQ14 and DQ15A–1 act as the MSB of the
Data Input or Output, functioning as described for
DQ0-DQ7 above, and DQ8-DQ15 are 'don't care'
for command inputs or status outputs. When
BYTE is Low, DQ0-DQ14 are high impedance,
DQ15A–1 is the Address A–1 input.
Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselects the
memory and reduces the power consumption to
the stan-by level. E can also be used to control
writing to the command register and to the memory array, while W remains at a low level. The Chip
Enable must be forced to VID during the Block Unprotection operation.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read operation. When G is High the outputs are High impedance. G must be forced to VID level during
Block Protection and Unprotection operations.
Write Enable (W). This input controls writing to
the Command Register and Address and Data
latches.
Byte/Word Organization Select (BYTE). The BYTE
input selects the output configuration for the device: Byte-wide (x8) mode or Word-wide (x16)
mode. When BYTE is Low, the Byte-wide mode is
selected and the data is read and programmed on
DQ0-DQ7. In this mode, DQ8-DQ14 are at high
impedance and DQ15A–1 is the LSB address.
When BYTE is High, the Word-wide mode is selected and the data is read and programmed on
DQ0-DQ15.
Ready/Busy Output (RB). Ready/Busy is an
open-drain output and gives the internal state of
the P/E.C. of the device. When RB is Low, the device is Busy with a Program or Erase operation
and it will not accept any additional program or
erase instructions except the Erase Suspend instruction. When RB is High, the device is ready for
any Read, Program or Erase operation. The RB
will also be High when the memory is put in Erase
Suspend or Stan-by modes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and protected block(s) temporary unprotection functions.
Reset of the memory is achieved by pulling RP to
VIL for at least tPLPX. When the reset pulse is given, if the memory is in Read or Stan-by modes, it
will be available for new operations in tPHEL after
the rising edge of RP. If the memory is in Erase,
Erase Suspend or Program modes the reset will
take tPLYH during which the RB signal will be held
at VIL. The end of the memory reset will be indicated by the rising edge of RB. A hardware reset during an Erase or Program operation will corrupt the
data being programmed or the sector(s) being
erased. See Tables 15 and 16, Read AC Characteristics and Figure 13., Data Polling DQ7 AC
Waveforms.
Temporary block unprotection is made by holding
RP at VID. In this condition previously protected
blocks can be programmed or erased. The transition of RP from VIH to VID must slower than tPHPHH. See Tables 17 and 18, Write AC
Characterisics and Figure 13., Data Polling DQ7
AC Waveforms. When RP is returned from VID to
VIH all blocks temporarily unprotected will be again
protected.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
9/40
M29W800AT, M29W800AB
DEVICE OPERATIONS
See Table 4., User Bus Operations (1), Table
5., Read Electronic Signature (following AS instruction or with A9 = VID) and Table 6., Read
Block Protection with AS Instruction.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Signature, the Status Register or the Block Protection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the memory. A new operation is initiated either on the following edge of Chip Enable E or on any address
transition with E at VIL.
Write. Write operations are used to give Instruction Commands to the memory or to latch input
data to be programmed. A write operation is initiated when Chip Enable E is Low and Write Enable
W is Low with Output Enable G High. Addresses
are latched on the falling edge of W or E whichever
occurs last. Commands and Input Data are
latched on the rising edge of W or E whichever occurs first.
Output Disable. The data outputs are high impedance when the Output Enable G is High with
Write Enable W High.
Stan-by. The memory is in stan-by when Chip
Enable E is High and the P/E.C. is idle. The power
consumption is reduced to the stan-by level and
the outputs are high impedance, independent of
the Output Enable G or Write Enable W inputs.
Automatic Stan-by. After 150ns of bus inactivity
(no address transition, CE = VIL) and when CMOS
levels are driving the addresses, the chip automatically enters a pseudo-stan-by mode where consumption is reduced to the CMOS stan-by value,
while outputs still drive the bus (if G = VIL).
Electronic Signature. Two codes identifying the
manufacturer and the device can be read from the
memory. The manufacturer's code for STMicroelectronics is 20h, the device code is D7h for the
M29W800AT (Top Boot) and 5Bh for the
M29W800AB (Bottom Boot). These codes allow
programming equipment or applications to automatically match their interface to the characteristics of the M29W800A. The Electronic Signature is
output by a Read operation when the voltage applied to A9 is at VID and address inputs A1 is Low.
The manufacturer code is output when the Address input A0 is Low and the device code when
this input is High. Other Address inputs are ignored. The codes are output on DQ0-DQ7.
10/40
The Electronic Signature can also be read, without
raising A9 to VID, by giving the memory the Instruction AS. If the Byte-wide configuration is selected the codes are output on DQ0-DQ7 with
DQ8-DQ14 at High impedance; if the Word-wide
configuration is selected the codes are output on
DQ0-DQ7 with DQ8-DQ15 at 00h.
Block Protection. Each block can be separately
protected against Program or Erase on programming equipment. Block protection provides additional data security, as it disables all program or
erase operations. This mode is activated when
both A9 and G are raised to VID and an address in
the block is applied on A12-A18. Block protection
is initiated on the edge of W falling to VIL. Then after a delay of 100µs, the edge of W rising to VIH
ends the protection operations. Block protection
verify is achieved by bringing G, E, A0 and A6 to
VIL and A1 to VIH, while W is at VIH and A9 at VID.
Under these conditions, reading the data output
will yield 01h if the block defined by the inputs on
A12-A18 is protected. Any attempt to program or
erase a protected block will be ignored by the device.
Block Temporary Unprotection. Any previously
protected block can be temporarily unprotected in
order to change stored data. The temporary unprotection mode is activated by bringing RP to VID.
During the temporary unprotection mode the previously protected blocks are unprotected. A block
can be selected and data can be modified by executing the Erase or Program instruction with the
RP signal held at VID. When RP is returned to VIH,
all the previously protected blocks are again protected.
Block Unprotection. All protected blocks can be
unprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protected before the unprotection operation. Block
unprotection is activated when A9, G and E are at
VID and A12, A15 at VIH. Unprotection is initiated
by the edge of W falling to VIL. After a delay of
10ms, the unprotection operation will end. Unprotection verify is achieved by bringing G and E to
VIL while A0 is at VIL, A6 and A1 are at VIH and A9
remains at VID. In these conditions, reading the
output data will yield 00h if the block defined by the
inputs A12-A18 has been successfully unprotected. Each block must be separately verified by giving its address in order to ensure that it has been
unprotected.
M29W800AT, M29W800AB
Table 4. User Bus Operations (1)
DQ0DQ7
DQ8DQ14
DQ15
A–1
A15
Data
Output
Data
Output
Data
Output
A12
A15
Data
Output
Hi-Z
Address
Input
A9
A12
A15
Data
Input
Data
Input
Data
Input
A6
A9
A12
A15
Data
Input
Hi-Z
Address
Input
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
VIL VID VIL Pulse VIH
X
X
X
X
VID
X
X
X
X
X
Blocks
VID VID VIL Pulse VIH
Unprotection (4)
X
X
X
X
VID
VIH
VIH
X
X
X
Block
Protection
Verify (2,4)
VIL
VIL
VIH
VIH
X
VIL VIH VIL VID A12
A15
Block
Protect
Status(3)
X
X
Block
Unprotection
Verify (2,4)
VIL
VIL
VIH
VIH
X
VIL VIH VIH VID A12
A15
Block
Protect
Status(3)
X
X
Block
Temporary
Unprotection
X
X
X
VID
X
X
X
X
X
Operation
E
G
W
RP
BYTE
A0
A1
A6
A9
A12 A15
Read Word
VIL
VIL
VIH
VIH
VIH
A0
A1
A6
A9
A12
Read Byte
VIL
VIL
VIH
VIH
VIL
A0
A1
A6
A9
Write Word
VIL VIH
VIL
VIH
VIH
A0
A1
A6
Write Byte
VIL VIH
VIL
VIH
VIL
A0
A1
Output Disable
VIL VIH
VIH
VIH
X
X
Stan-by
VIH
X
X
VIH
X
X
X
X
VIL
Reset
Block
Protection (2,4)
Note: 1.
2.
3.
4.
X
X
X
X
X
X = VIL or VIH.
Block Address must be given an A12-A18 bits.
See Table 6., Read Block Protection with AS Instruction.
Operation performed on programming equipment.
Table 5. Read Electronic Signature (following AS instruction or with A9 = VID)
Org.
Wordwide
Code
E
G
W
BYTE
A0
A1
Other
Addresses
DQ0DQ7
DQ8DQ14
DQ15
A–1
VIL
VIL
VIH
VIH
VIL
VIL
Don’t Care
20h
00h
0
M29W800AT
VIL
VIL
VIH
VIH
VIH
VIL
Don’t Care
D7h
00h
0
M29W800AB
VIL
VIL
VIH
VIH
VIH
VIL
Don’t Care
5Bh
00h
0
Device
Manufact.
Code
Device
Code
Table 6. Read Block Protection with AS Instruction
E
G
W
A0
A1
A12-A18
Other
Addresses
DQ0-DQ7
Protected Block
VIL
VIL
VIH
VIL
VIH
Block Address
Don’t Care
01h
Unprotected Block
VIL
VIL
VIH
VIL
VIH
Block Address
Don’t Care
00h
Code
11/40
M29W800AT, M29W800AB
INSTRUCTIONS AND COMMANDS
The Command Interface latches commands written to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Read Block Protection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The instructions require from 1 to 6 cycles, the first or first
three of which are always write operations used to
initiate the instruction. They are followed by either
further write cycles to confirm the first command or
execute the command immediately. Command sequencing must be followed exactly. Any invalid
combination of commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum data security. Instructions are initialised by two initial Coded cycles
which unlock the Command Interface. In addition,
for Erase, instruction confirmation is again preceded by the two Coded cycles.
See Table 7., Commands for a summary of Commands.
Coded Cycles
The two Coded cycles unlock the Command Interface. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address AAAh in the
Byte-wide configuration and at address 555h in
the Word-wide configuration during the first cycle.
During the second cycle the Coded cycles consist
of writing the data 55h at address 555h in the Bytewide configuration and at address 2AAh in the
Word-wide configuration. In the Byte-wide configuration the address lines A–1 to A10 are valid, in
Word-wide A0 to A11 are valid, other address lines
are 'don't care'. The Coded cycles happen on first
and second cycles of the command write or on the
fourth and fifth cycles.
Table 7. Commands
Hex Code
12/40
Command
00h
Invalid/Reserved
10h
Chip Erase Confirm
20h
Reserved
30h
Block Erase Resume/Confirm
80h
Set-up Erase
90h
Read Electronic Signature/
Block Protection Status
A0h
Program
B0h
Erase Suspend
F0h
Read Array/Reset
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded cycles. Subsequent read operations will read the memory array addressed and
output the data read. A wait state of 10µs is necessary after Read/Reset prior to any valid read if
the memory was in an Erase mode when the RD
instruction is given. The Read/Reset command is
not accepted during Erase and erase Suspend.
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address AAAh in
the Byte-wide configuration or address 555h in the
Word-wide configuration for command set-up. A
subsequent read will output the manufacturer
code and the device code or the block protection
status depending on the levels of A0 and A1. The
manufacturer code, 20h, is output when the addresses lines A0 and A1 are Low, the device code,
EEh for Top Boot, EFh for Bottom Boot is output
when A0 is High with A1 Low.
The AS instruction also allows access to the block
protection status. After giving the AS instruction,
A0 is set to VIL with A1 at VIH, while A12-A18 define the address of the block to be verified. A read
in these conditions will output a 01h if the block is
protected and a 00h if the block is not protected.
Program (PG) Instruction. This instruction uses
four write cycles. Both for Byte-wide configuration
and for Word-wide configuration. The Program
command A0h is written to address AAAh in the
Byte-wide configuration or to address 555h in the
Word-wide configuration on the third cycle after
two Coded cycles. A fourth write operation latches
the Address on the falling edge of W or E and the
Data to be written on the rising edge and starts the
P/E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing '0' in place of
'1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification
of any possible error. Programming at an address
not in blocks being erased is also possible during
erase suspend. In this case, DQ2 will toggle at the
address being programmed.
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address AAAh
in the Byte-wide configuration or address 555h in
the Word-wide configuration on third cycle after
the two Coded cycles. The Block Erase Confirm
command 30h is similarly written on the sixth cycle
after another two Coded cycles. During the input of
the second command an address within the block
to be erased is given and latched into the memory.
Additional block Erase Confirm commands and
M29W800AT, M29W800AB
block addresses can be written subsequently to
erase other blocks in parallel, without further Coded cycles. The erase will start after the erase timeout period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input
of a new Erase Confirm command will restart the
timeout period. The status of the internal timer can
be monitored through the level of DQ3, if DQ3 is '0'
the Block Erase Command has been given and
the timeout is running, if DQ3 is '1', the timeout has
expired and the P/E.C. is erasing the Block(s). If
the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array.
It is not necessary to program the block with 00h
as the P/E.C. will do this automatically before to
erasing to FFh. Read operations after the sixth rising edge of W or E output the status register status
bits.
During the execution of the erase by the P/E.C.,
the memory accepts only the Erase Suspend ES
instruction. Data Polling bit DQ7 returns '0' while
the erasure is in progress and '1' when it has completed. The Toggle bit DQ2 and DQ6 toggle during
the erase operation. They stop when erase is completed. After completion the Status Register bit
DQ5 returns '1' if there has been an erase failure.
In such a situation, the Toggle bit DQ2 can be
used to determine which block is not correctly
erased. In the case of erase failure, a Read/Reset
RD instruction is necessary in order to reset the P/
E.C.
Chip Erase (CE) Instruction. This
instruction
uses six write cycles. The Erase Set-up command
80h is written to address AAAh in the Byte-wide
configuration or the address 555h in the Wordwide configuration on the third cycle after the two
Coded cycles. The Chip Erase Confirm command
10h is similarly written on the sixth cycle after another two Coded cycles. If the second command
given is not an erase confirm or if the Coded cy-
cles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to
program the array with 00h first as the P/E.C. will
automatically do this before erasing it to FFh.
Read operations after the sixth rising edge of W or
E output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit
DQ7 returns '0', then '1' on completion. The Toggle
bits DQ2 and DQ6 toggle during erase operation
and stop when erase is completed. After completion the Status Register bit DQ5 returns '1' if there
has been an Erase Failure.
Erase Suspend (ES) Instruction. The
Block
Erase operation may be suspended by this instruction which consists of writing the command
B0h without any specific address. No Coded cycles are required. It permits reading of data from
another block and programming in another block
while an erase operation is in progress. Erase suspend is accepted only during the Block Erase instruction execution. Writing this command during
Erase timeout will, in addition to suspending the
erase, terminate the timeout. The Toggle bit DQ6
stops toggling when the P/E.C. is suspended. The
Toggle bits will stop toggling between 0.1µs and
15µs after the Erase Suspend (ES) command has
been written. The device will then automatically be
set to Read Memory Array mode. When erase is
suspended, a Read from blocks being erased will
output DQ2 toggling and DQ6 at '1'. A Read from
a block not being erased returns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instructions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in both DQ2 and DQ6 toggling
when the data is being programmed.
Erase Resume (ER) Instruction. If an Erase
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
Coded cycles.
13/40
M29W800AT, M29W800AB
Table 8. Instructions (1)
Mne.
Instr.
Cyc.
1+
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.
Addr. (3,7)
X
Data
Read/Reset
Memory
RD (2,4)
Array
AAAh
555h
AAAh
Word
555h
2AAh
555h
AAh
55h
F0h
Byte
AAAh
555h
AAAh
Word
555h
2AAh
555h
AAh
55h
90h
Byte
AAAh
555h
AAAh
Word
555h
2AAh
555h
AAh
55h
A0h
Byte
AAAh
555h
AAAh
AAAh
555h
Word
555h
2AAh
555h
555h
AAh
55h
80h
Byte
AAAh
555h
Word
555h
AAh
Addr.
AS (4)
Auto Select 3+
Data
Addr.
(3,7)
PG
Program
4
Data
Addr.
BE
Block Erase
6
(3,7)
Data
Addr.
CE
Chip Erase
6
(3,7)
Data
ES (10)
ER
Erase
Suspend
1
Erase
Resume
1
Addr. (3,7)
Data
Addr. (3,7)
Data
Read Memory Array until a new write cycle
is initiated.
Byte
Data
(3,7)
Read Memory Array until a new write cycle is initiated.
F0h
Addr.
3+ (3,7)
7th Cyc.
X
B0h
X
30h
Read Electronic Signature or Block
Protection Status until a new write cycle is
initiated. See Note 5 and 6.
Program
Address Read Data Polling or Toggle Bit
until Program completes.
Program
Data
2AAh
Block
Address
Additional
Block (8)
AAh
55h
30h
30h
AAAh
AAAh
555h
AAAh
2AAh
555h
555h
2AAh
555h
55h
80h
AAh
55h
10h
Note 9
Read until Toggle stops, then read all the data needed from any
Block(s) not being erased then Resume Erase.
Read Data Polling or Toggle Bits until Erase completes or Erase
is suspended another time.
Note: 1. Commands not interpreted in this table will default to read array mode.
2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new
operation (see Tables 15, 16 and Figure 13).
3. X = Don't Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles.
5. Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Device
code.
6. Block Protection Address: A0, at VIL, A1 at VIH and A15-A18 within the Block will output the Block Protection status.
7. For Coded cycles address inputs A11-A18 are don't care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout statuscan be
verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Toggle bit
until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
14/40
M29W800AT, M29W800AB
STATUS REGISTER
P/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase command execution will automatically output these
five Status Register bits. The P/E.C. automatically
sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other
bits (DQ0, DQ1 and DQ4) are reserved for future
use and should be masked. See Table 10., Status
Register Bits and Table 9., Polling and Toggle
Bits.
Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7.
During Erase operation, it outputs a '0'. After completion of the operation, DQ7 will output the bit last
programmed or a '1' after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. It must be performed at the address being programmed or at an
address within the block being erased. If all the
blocks selected for erasure are protected, DQ7 will
be set to '0' for about 100µs, and then return to the
previous addressed memory data value. See Figure 15., Data Polling Flowchart and Figure
13., Data Polling DQ7 AC Waveforms. DQ7 will
also flag the Erase Suspend mode by switching
from '0' to '1' at the start of the Erase Suspend. In
order to monitor DQ7 in the Erase Suspend mode
an address within a block being erased must be
provided. For a Read Operation in Erase Suspend
mode, DQ7 will output '1' if the read is attempted
on a block being erased and the data value on other blocks. During Program operation in Erase Suspend Mode, DQ7 will have the same behavior as
in the normal program execution outside of the
suspend mode.
Toggle Bit (DQ6). When Programming or Erasing operations are in progress, successive attempts to read DQ6 will output complementary
data. DQ6 will toggle following toggling of either G,
or E when G is low. The operation is completed
when two successive reads yield the same output
data. The next read will output the bit last programmed or a '1' after erasing. The toggle bit DQ6
is valid only during P/E.C. operations, that is after
the fourth W pulse for programming or after the
sixth W pulse for Erase. If the blocks selected for
erasure are protected, DQ6 will toggle for about
100µs and then return back to Read. DQ6 will be
set to '1' if a Read operation is attempted on an
Erase Suspend block. When erase is suspended
DQ6 will toggle during programming operations in
a block different to the block in Erase Suspend. Either E or G toggling will cause DQ6 to toggle. See
Figure 16., Data Toggle Flowchart and Figure
14., Data Toggle DQ6, DQ2 AC Waveforms.
Error Bit (DQ5). This bit is set to '1' by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memory block. In case of an error in block
erase or program, the block in which the error occurred or to which the programmed data belongs,
must be discarded. The DQ5 failure condition will
also appear if a user tries to program a '1' to a location that is previously programmed to '0'. Other
Blocks may still be used. The error bit resets after
a Read/Reset (RD) instruction. In case of success
of Program or Erase, the error bit will be set to '0'.
Erase Timer Bit (DQ3). This bit is set to '0' by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 50µs to 90µs, DQ3 returns
to '1'.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. It can also be used to
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to '1' during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to '1' during program operation and when erase is complete. After erase completion and if the error bit
DQ5 is set to '1', DQ2 will toggle if the faulty block
is addressed.
Table 9. Polling and Toggle Bits
Mode
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Note 1
Erase Suspend Read
(in Erase Suspend
block)
1
1
Toggle
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ6
DQ2
Erase Suspend Program
DQ7
Toggle
N/A
Program
15/40
M29W800AT, M29W800AB
Table 10. Status Register Bits
DQ
7
Name
Logic Level
Definition
’1’
Erase Complete or erase block
in Erase Suspend
’0’
Erase On-going
DQ
Program Complete or data of
non erase block during Erase
Suspend
DQ
Program On-going
Data
Polling
’-1-0-1-0-1-0-1-’
DQ
6
Toggle Bit
’-1-1-1-1-1-1-1-’
5
4
3
2
Erase or Program On-going
Program Complete
Erase Complete or Erase
Suspend on currently
addressed block
Note
Indicates the P/E.C. status, check during
Program or Erase, and on completion before
checking bits DQ5 for program or Erase
Success.
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
’1’
Program or Erase Error
’0’
Program or Erase On-going
’1’
Erase Timeout Period Expired
P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
(ES).
’0’
Erase Timeout Period On-going
An additional block to be erased in parallel
can be entered to the P/E.C.
’-1-0-1-0-1-0-1-’
Chip Erase, Erase or Erase
Suspend on the currently
addressed block.
Erase Error due to the currently
addressed block
(when DQ5 = ‘1’).
Error Bit
This bit is set to ‘1’ in the case of
Programming or Erase failure.
Reserved
Erase
Time Bit
Toggle Bit
1
Reserved
0
Reserved
1
Program on-going, Erase ongoing on another block or
Erase Complete
DQ
Erase Suspend read on non
Erase Suspend block
Indicates the erase status and allows to
identify the erased block
Note: 1. Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
2. Toggle if the address is within a block being erased.
'1' if the address is within a block not being erased.
16/40
M29W800AT, M29W800AB
MAXIMUM RATING
Table 11. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Ambient Operating Temperature
(3)
Value
Unit
–40 to 85
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
VIO (2)
Input or Output Voltage
–0.6 to 5
V
Supply Voltage
–0.6 to 5
V
–0.6 to 13.5
V
VCC
V(A9, E, G, RP) (2)
A9, E, G, RP Voltage
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
3. Depends on range.
17/40
M29W800AT, M29W800AB
DC AND AC CHARACTERISTICS
Figure 6. AC Testing Input Output Waveform
Figure 7. AC Testing Load Circuit
0.8V
3V
1N914
1.5V
0V
3.3kΩ
AI01417
DEVICE
UNDER
TEST
OUT
Table 12. AC Measurement Conditions
CL = 30pF or 100pF
Input Rise and Fall Times
≤10ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
CL includes JIG capacitance
1.5V
AI01968
Table 13. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Symbol
CIN
Parameter
Input Capacitance
COUT
Output Capacitance
Test Condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 14. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol
Parameter
Test Condition
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC1
Supply Current (Read by Word)
E = VIL, G = VIH, f = 6MHz
ICC2
Supply Current (Read by Word)
ICC3
Supply Current (Stan-by)
ICC4 (1)
Supply Current
(Program or Erase)
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
3
10
mA
E = VIL, G = VIL, f = 6MHz
4.5
10
mA
E = VCC ±0.2V
30
100
µA
20
mA
Typ.
Byte program, Block or
Chip Erase in progress
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7 VCC
VCC + 0.3
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage CMOS
VID
A9 Voltage (Electronic Signature)
IID
A9 Current (Electronic Signature)
Supply Voltage (Erase and
VLKO (1) Program lock-out)
Note: 1. Sampled only, not 100% tested.
18/40
IOL = 1.8mA
IOH = –100µA
VCC –0.4V
V
11.5
A9 = VID
30
2.0
12.5
V
100
µA
2.3
V
M29W800AT, M29W800AB
Table 15. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W800AT / M29W800AB
Symbol
Alt
Parameter
Test
Condition
80
90
VCC = 3.0V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 30pF
Min
Max
Min
Unit
Max
tAVAV
tRC
Address Valid to Next
Address Valid
E = VIL,
G = VIL
tAVQV
tACC
Address Valid to Output
Valid
E = VIL,
G = VIL
tAXQX
tOH
Address Transition to
Output Transition
E = VIL,
G = VIL
tBHQV
tFHQV
BYTE Switching High to
Output Valid
50
50
ns
tBLQZ
tFLQZ
BYTE Switching Low to
Output High Z
50
50
ns
tEHQX
tOH
Chip Enable High to Output
Transition
G = VIL
tEHQZ (1)
tHZ
Chip Enable High to Output
Hi-Z
G = VIL
tELBH
tELBL
tELFH
tELFL
tELQV (2)
tCE
Chip Enable Low to Output
Valid
G = VIL
tELQX (1)
tLZ
Chip Enable Low to Output
Transition
G = VIL
0
0
ns
tGHQX
tOH
Output Enable High to
Output Transition
E = VIL
0
0
ns
tGHQZ (1)
tDF
Output Enable High to
Output Hi-Z
E = VIL
30
30
ns
tGLQV (2)
tOE
Output Enable Low to
Output Valid
E = VIL
35
35
ns
tGLQX (1)
tOLZ
Output Enable Low to
Output Transition
E = VIL
tPHEL
tRH
RP High to Chip Enable
Low
tPLYH (1, 3)
tRRB
tREADY
RP Low to Read Mode
tPLPX
tRP
80
80
0
ns
90
ns
ns
0
0
Chip Enable to BYTE
Switching Low or High
RP Pulse Width
90
0
ns
30
30
ns
5
5
ns
80
90
ns
0
0
ns
50
50
ns
10
500
10
500
µs
ns
Note: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.
19/40
M29W800AT, M29W800AB
Table 16. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W800AT / M29W800AB
Symbol
Alt
Parameter
Test
Condition
100
120
VCC = 2.7V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 100pF
Min
Max
Min
Unit
Max
tAVAV
tRC
Address Valid to Next
Address Valid
E = VIL,
G = VIL
tAVQV
tACC
Address Valid to Output
Valid
E = VIL,
G = VIL
tAXQX
tOH
Address Transition to
Output Transition
E = VIL,
G = VIL
tBHQV
tFHQV
BYTE Switching High to
Output Valid
50
60
ns
tBLQZ
tFLQZ
BYTE Switching Low to
Output High Z
50
60
ns
tEHQX
tOH
Chip Enable High to Output
Transition
G = VIL
tEHQZ (1)
tHZ
Chip Enable High to Output
Hi-Z
G = VIL
tELBH
tELBL
tELFH
tELFL
tELQV (2)
tCE
Chip Enable Low to Output
Valid
G = VIL
tELQX (1)
tLZ
Chip Enable Low to Output
Transition
G = VIL
0
0
ns
tGHQX
tOH
Output Enable High to
Output Transition
E = VIL
0
0
ns
tGHQZ (1)
tDF
Output Enable High to
Output Hi-Z
E = VIL
30
30
ns
tGLQV (2)
tOE
Output Enable Low to
Output Valid
E = VIL
40
50
ns
tGLQX (1)
tOLZ
Output Enable Low to
Output Transition
E = VIL
tPHEL
tRH
RP High to Chip Enable
Low
tPLYH (1, 3)
tRRB
tREADY
RP Low to Read Mode
tPLPX
tRP
100
100
0
120
ns
ns
0
ns
30
30
ns
5
5
ns
100
120
ns
0
0
ns
50
50
ns
10
500
Note: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.
20/40
ns
0
0
Chip Enable to BYTE
Switching Low or High
RP Pulse Width
120
10
500
µs
ns
Note: Write Enable (W) = High.
BYTE
DQ0-DQ7/
DQ8-DQ15
G
E
A0-A18/
A–1
ADDRESS VALID
AND CHIP ENABLE
tELBL/tELBH
OUTPUT ENABLE
tGLQX
tGLQV
tELQV
tELQX
tBHQV
tAVQV
VALID
tAVAV
DATA VALID
tBLQZ
VALID
tGHQZ
tGHQX
tEHQX
tEHQZ
tAXQX
AI02182
M29W800AT, M29W800AB
Figure 8. Read Mode AC Waveforms
21/40
M29W800AT, M29W800AB
Table 17. Write AC Characteristics, W Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W800AT / M29W800AB
Symbol
Alt
Parameter
80
90
VCC = 3.0V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 30pF
Min
Max
Min
Unit
Max
tAVAV
tWC
Address Valid to Next Address Valid
80
90
ns
tAVWL
tAS
Address Valid to Write Enable Low
0
0
ns
tDVWH
tDS
Input Valid to Write Enable High
35
45
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
0
0
ns
Output Enable High to Write Enable Low
0
0
ns
500
500
ns
4
4
µs
tGHWL
tPHPHH (1, 2)
tVIDR
RP Rise Time to VID
tPHWL (1)
tRSP
RP High to Write Enable Low
tPLPX
tRP
RP Pulse Width
500
500
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
50
50
µs
tWHDX
tDH
Write Enable High to Input Transition
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
0
0
ns
tWHGL
tOEH
Write Enable High to Output Enable Low
0
0
ns
tWHRL (1)
tBUSY
Program Erase Valid to RB Delay
tWHWL
tWPH
Write Enable High to Write Enable Low
30
30
ns
tWLAX
tAH
Write Enable Low to Address Transition
45
45
ns
tWLWH
tWP
Write Enable Low to Write Enable High
35
35
ns
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
22/40
90
90
ns
M29W800AT, M29W800AB
Table 18. Write AC Characteristics, W Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W800AT / M29W800AB
Symbol
Alt
Parameter
100
120
VCC = 2.7V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 100pF
Min
tAVAV
tWC
Address Valid to Next Address Valid
tAVWL
tAS
tDVWH
tELWL
Max
Min
Unit
Max
100
120
ns
Address Valid to Write Enable Low
0
0
ns
tDS
Input Valid to Write Enable High
45
50
ns
tCS
Chip Enable Low to Write Enable Low
0
0
ns
Output Enable High to Write Enable Low
0
0
ns
500
500
ns
4
4
µs
tGHWL
tPHPHH (1, 2)
tVIDR
RP Rise Time to VID
tPHWL (1)
tRSP
RP High to Write Enable Low
tPLPX
tRP
RP Pulse Width
500
500
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
50
50
µs
tWHDX
tDH
Write Enable High to Input Transition
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
0
0
ns
tWHGL
tOEH
Write Enable High to Output Enable Low
0
0
ns
tWHRL (1)
tBUSY
Program Erase Valid to RB Delay
tWHWL
tWPH
Write Enable High to Write Enable Low
30
30
ns
tWLAX
tAH
Write Enable Low to Address Transition
45
50
ns
tWLWH
tWP
Write Enable Low to Write Enable High
35
50
ns
90
90
ns
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
23/40
M29W800AT, M29W800AB
Table 19. Write AC Characteristics, E Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W800AT / M29W800AB
Symbol
Alt
Parameter
80
90
VCC = 3.0V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 30pF
Min
Max
Min
Unit
Max
tAVAV
tWC
Address Valid to Next Address Valid
80
90
ns
tAVEL
tAS
Address Valid to Chip Enable Low
0
0
ns
tDVEH
tDS
Input Valid to Chip Enable High
35
45
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
30
30
ns
tEHGL
tOEH
Chip Enable High to Output Enable Low
0
0
ns
tEHRL (1)
tBUSY
Program Erase Valid to RB Delay
tEHWH
tWH
Chip Enable High to Write Enable High
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
45
45
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
35
35
ns
Output Enable High Chip Enable Low
0
0
ns
500
500
ns
4
4
µs
tGHEL
80
90
ns
tPHPHH (1, 2)
tVIDR
RP Rise TIme to VID
tPHWL (1)
tRSP
RP High to Write Enable Low
tPLPX
tRP
RP Pulse Width
500
500
ns
tVCHWL
tVCS
VCC High to Write Enable Low
50
50
µs
tWLEL
tWS
Write Enable Low to Chip Enable Low
0
0
ns
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
24/40
M29W800AT, M29W800AB
Table 20. Write AC Characteristics, E Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W800AT / M29W800AB
Symbol
Alt
Parameter
100
120
VCC = 2.7V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 100pF
Min
tAVAV
tWC
Address Valid to Next Address Valid
tAVEL
tAS
tDVEH
Max
Min
Unit
Max
100
120
ns
Address Valid to Chip Enable Low
0
0
ns
tDS
Input Valid to Chip Enable High
45
50
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
30
30
ns
tEHGL
tOEH
Chip Enable High to Output Enable Low
0
0
ns
tEHRL (1)
tBUSY
Program Erase Valid to RB Delay
tEHWH
tWH
Chip Enable High to Write Enable High
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
45
50
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
35
50
ns
Output Enable High Chip Enable Low
0
0
ns
500
500
ns
4
4
µs
tGHEL
90
90
ns
tPHPHH (1,2)
tVIDR
RP Rise TIme to VID
tPHWL (1)
tRSP
RP High to Write Enable Low
tPLPX
tRP
RP Pulse Width
500
500
ns
tVCHWL
tVCS
VCC High to Write Enable Low
50
50
µs
tWLEL
tWS
Write Enable Low to Chip Enable Low
0
0
ns
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
25/40
M29W800AT, M29W800AB
Figure 9. Write AC Waveforms, W Controlled
tAVAV
A0-A18/
A–1
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7/
DQ8-DQ15
tWHDX
VALID
VCC
tVCHEL
RB
tWHRL
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
26/40
AI02183
M29W800AT, M29W800AB
Figure 10. Write AC Waveforms, E Controlled
tAVAV
A0-A18/
A–1
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7/
DQ8-DQ15
tEHDX
VALID
VCC
tVCHWL
RB
tEHRL
AI02184
Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.
Figure 11. Read and Write AC Characteristics, RP Related
E
tPHEL
W
tPHWL
RB
RP
tPLPX
tPHPHH
tPLYH
AI02091
27/40
M29W800AT, M29W800AB
Figure 12. Data Polling and Toggle Bit AC Characteristics (1)
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W800AT / M29W800AB
Symbol
tEHQ7V
tEHQV
tQ7VQV
tWHQ7V
tWHQV
Parameter
80
90
VCC = 3.0V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 30pF
Unit
Min
Max
Min
Max
Chip Enable High to DQ7 Valid
(Program, E Controlled)
10
2400
10
2400
µs
Chip Enable High to DQ7 Valid
(Chip Erase, E Controlled)
1.0
60
1.0
60
sec
Chip Enable High to Output Valid (Program)
10
2400
10
2400
µs
Chip Enable High to Output Valid (Chip Erase)
1.0
60
1.0
60
sec
35
ns
Q7 Valid to Output Valid (Data Polling)
35
Write Enable High to DQ7 Valid
(Program, W Controlled)
10
2400
10
2400
ms
Write Enable High to DQ7 Valid
(Chip Erase, W Controlled)
1.0
60
1.0
60
sec
Write Enable High to Output Valid (Program)
10
2400
10
2400
µs
Write Enable High to Output Valid (Chip Erase)
1.0
60
1.0
60
sec
Note: 1. All other timings are defined in Read AC Characteristics table.
Table 21. Data Polling and Toggle Bit AC Characteristics (1)
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W800AT / M29W800AB
Symbol
tEHQ7V
tEHQV
tQ7VQV
tWHQ7V
tWHQV
Parameter
120
VCC = 2.7V to 3.6V
CL = 30pF
VCC = 2.7V to 3.6V
CL = 100pF
Unit
Min
Max
Min
Max
Chip Enable High to DQ7 Valid
(Program, E Controlled)
10
2400
10
2400
µs
Chip Enable High to DQ7 Valid
(Chip Erase, E Controlled)
1.0
60
1.0
60
sec
Chip Enable High to Output Valid (Program)
10
2400
10
2400
µs
Chip Enable High to Output Valid (Chip Erase)
1.0
60
1.0
60
sec
50
ns
Q7 Valid to Output Valid (Data Polling)
40
Write Enable High to DQ7 Valid
(Program, W Controlled)
10
2400
10
2400
ms
Write Enable High to DQ7 Valid
(Chip Erase, W Controlled)
1.0
60
1.0
60
sec
Write Enable High to Output Valid (Program)
10
2400
10
2400
µs
Write Enable High to Output Valid (Chip Erase)
1.0
60
1.0
60
sec
Note: 1. All other timings are defined in Read AC Characteristics table.
28/40
100
DQ0-DQ6/
DQ8-DQ15
DQ7
W
G
E
A0-A18/
A–1
LAST WRITE
CYCLE OF
PROGRAM
OR ERASE
INSTRUCTION
DATA POLLING
READ CYCLES
tWHQ7V
tEHQ7V
tELQV
tAVQV
tQ7VQV
IGNORE
DQ7
DATA POLLING (LAST) CYCLE
tGLQV
ADDRESS (WITHIN BLOCKS)
VALID
VALID
DATA OUTPUT VALID
AI02185
MEMORY
ARRAY
READ CYCLE
M29W800AT, M29W800AB
Figure 13. Data Polling DQ7 AC Waveforms
29/40
30/40
DATA
TOGGLE
READ CYCLE
Note: All other timings are as a normal Read cycle.
LAST WRITE
CYCLE OF
PROGRAM
OF ERASE
INSTRUCTION
DQ0-DQ1,DQ3-DQ5,DQ7/
DQ8-DQ15
DQ6,DQ2
W
G
E
A0-A18/
A–1
DATA TOGGLE
READ CYCLE
IGNORE
STOP TOGGLE
tWHQV
tEHQV
tAVQV
MEMORY ARRAY
READ CYCLE
VALID
VALID
tGLQV
tELQV
VALID
AI02186
M29W800AT, M29W800AB
Figure 14. Data Toggle DQ6, DQ2 AC Waveforms
M29W800AT, M29W800AB
Figure 15. Data Polling Flowchart
Figure 16. Data Toggle Flowchart
START
START
READ
DQ2, DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
NO
NO
YES
NO
DQ5
=1
DQ5
=1
YES
YES
READ DQ7
DQ7
=
DATA
NO
DQ2, DQ6
=
TOGGLE
YES
READ DQ2, DQ6
YES
DQ2, DQ6
=
TOGGLE
NO
FAIL
NO
YES
PASS
FAIL
PASS
AI01369
AI01873
Table 22. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C; VCC = 2.7V to 3.6V)
M29W800AT / M29W800AB
Parameter
Unit
Typ
Typical after (1)
100k W/E Cycles
Chip Erase (Preprogrammed, VCC = 2.7V)
10
10
sec
Chip Erase (VCC = 2.7V)
15
15
sec
Main Block Erase (VCC = 2.7V)
1.5
Chip Program (Byte) (1)
10
10
sec
Chip Program (Word) (1)
5
5
sec
Byte/Word Program
10
10
µs
Min
Program/Erase Cycles (per Block)
100,000
Max
15
sec
cycles
Note: 1. Excluded the time required to execute bus cycles sequence for program operation.
31/40
M29W800AT, M29W800AB
POWER SUPPLY
Power Up
The memory Command Interface is reset on power up to Read Array. The device does not accept
commands on the first rising edge of W, if both W
and E are at VIL with G at VIH during power-up.
Any write cycle initiation is blocked when VCC is
below VLKO .
32/40
Supply Rails
Normal precautions must be taken for supply voltage decoupling; each device in a system should
have the VCC rail decoupled with a 0.1µF capacitor
close to the VCC and VSS pins. The PCB trace
widths should be sufficient to carry the VCC program and erase currents required.
M29W800AT, M29W800AB
SECURITY PROTECTION MEMORY AREA
The M29W800A features a security protection
memory area. It consists of a memory block of 256
bytes or 128 words which is programmed in the ST
factory to store a unique code that uniquely identifies the part.
This memory block can be read by using the Read
Security Data instruction (RDS) as shown in Table
23.
Read Security Data (RDS) Instruction. This RDS
uses a single write cycle instruction: the command
B8h is written to the address AAh. This sets the
memory to the Read Security mode. Any successive read attempt will output the addressed Security byte until a new write cycle is initiated.
Table 23. Security Block Instruction
Unlock Cycle
Mne.
Instr.
Cyc.
2nd Cyc.
1st Cyc.
RDS
Read
Security
Data
Addr. (1)
AAh
Data (2)
B8h
1
Read OTP Data until a new write cycle is initiated.
Note: 1. Address bits A10-A19 are don't care for coded address inputs.
2. Data bits DQ8-DQ15 are don't care for coded address inputs.
Figure 17. Security Block Address Table
BYTE Organisation (x8)
TOP BOOT BLOCK
BOTTOM BOOT BLOCK
Security
Memory Block
Security
Memory Block
000FFh
0E0FFh
00000h
0E000h
WORD Organisation (x16)
TOP BOOT BLOCK
BOTTOM BOOT BLOCK
Security
Memory Block
Security
Memory Block
0007Fh
0E01Fh
00000h
0E000h
AI02746
33/40
M29W800AT, M29W800AB
PACKAGE MECHANICAL
Figure 18. TSOP48, 48 Lead Plastic Thin Small Outline, 12x20 mm - Package Outline
1
48
e
D1
B
24
L1
25
A2
E1
E
A
A1
DIE
α
L
C
CP
TSOP-G
Table 24. TSOP48, 48 Lead Plastic Thin Small Outline, 12x20 mm - Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.200
Max
0.0472
A1
0.100
0.050
0.150
0.0039
0.0020
0.0059
A2
1.000
0.950
1.050
0.0394
0.0374
0.0413
B
0.220
0.170
0.270
0.0087
0.0067
0.0106
0.100
0.210
0.0039
0.0083
C
CP
34/40
Max
0.080
0.0031
D1
12.000
11.900
12.100
0.4724
0.4685
0.4764
E
20.000
19.800
20.200
0.7874
0.7795
0.7953
E1
18.400
18.300
18.500
0.7244
0.7205
0.7283
e
0.500
–
–
0.0197
–
–
L
0.600
0.500
0.700
0.0236
0.0197
0.0276
L1
0.800
a
3
0
5
0.0315
0
5
3
M29W800AT, M29W800AB
Figure 19. TFBGA48, 6 x 8 Ball Array, 0.8mm Pitch - Bottom View Package Outline
D
D1
FD
FE
SD
SE
BALL "A1"
E
E1
ddd
e
e
b
A
A2
A1
BGA-Z00
Table 25. TFBGA48, 6 x 8 Ball Array, 0.8mm Pitch - Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
A1
0.0472
0.200
A2
Max
0.0079
1.000
0.0394
b
0.400
0.350
0.450
0.0157
0.0138
0.0177
D
6.000
5.900
6.100
0.2362
0.2323
0.2402
D1
4.000
–
–
0.1575
–
–
ddd
0.100
0.0039
E
9.000
8.900
9.100
0.3543
0.3504
0.3583
e
0.800
–
–
0.0315
–
–
E1
5.600
–
–
0.2205
–
–
FD
1.000
–
–
0.0394
–
–
FE
1.700
–
–
0.0669
–
–
SD
0.400
–
–
0.0157
–
–
SE
0.400
–
–
0.0157
–
–
35/40
M29W800AT, M29W800AB
Figure 20. TFBGA48 Daisy Chain Connections (Top view through package)
1
2
3
4
6
5
A
B
C
D
E
F
G
H
AI04893
Figure 21. TFBGA48 Daisy Chain - PCB Connections (Top view through package)
START
POINT
1
2
3
4
5
END
POINT
6
A
B
C
D
E
F
G
H
AI04892
36/40
M29W800AT, M29W800AB
Figure 22. SO44 , Small Outline, 525mm Body Width - Package Outline
A
A2
C
b
e
CP
D
N
E
EH
1
A1
α
L
SO-d
Table 26. SO44 , Small Outline, 525mm Body Width Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
2.80
A1
Max
0.1102
0.10
0.0039
A2
2.30
2.20
2.40
0.0906
0.0866
0.0945
b
0.40
0.35
0.50
0.0157
0.0138
0.0197
C
0.15
0.10
0.20
0.0059
0.0039
0.0079
CP
0.08
0.0030
D
28.20
28.00
28.40
1.1102
1.1024
1.1181
E
13.30
13.20
13.50
0.5236
0.5197
0.5315
EH
16.00
15.75
16.25
0.6299
0.6201
0.6398
e
1.27
–
–
0.0500
–
–
L
0.80
a
N
0.0315
8
44
8
44
37/40
M29W800AT, M29W800AB
PART NUMBERING
Table 27. Ordering Information Scheme
Example:
M29W800AT
80
N
1
T
Device Type
M29
Operating Voltage
W = 2.7 to 3.6V
Device Function
800A = 8 Mbit (1Mb x8 or 512Kb x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
80 = 80 ns
90 = 90 ns
100 = 100 ns
120 = 120 ns
Package
N = TSOP48: 12 x 20 mm
M = SO44
ZA = TFBGA48: 0.8 mm pitch
Temperature Range
1 = 0 to 70 °C
5 = –20 to 85°C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
Table 28. Daisy Chain Ordering Scheme
Example:
M29
DCL1-8
T
Device Type
M29
Daisy Chain
DCL1-8 = Daisy Chain Level 1 for 8 Mbit parts
Option
T = Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
38/40
M29W800AT, M29W800AB
REVISION HISTORY
Table 29. Revision History
Date
Version
Description
November 1998
-01
First issue
February 1999
-02
Removed TSOP48 Package Reverse Pinout
March 1999
-03
Program, Erase Times and Erase Endurance Cycles change
02/09/00
-04
New document template
Document type: from Preliminary Data to Data Sheet
Program, Erase Times and Endurance Cycles change (Table 22)
TFBGA Package Mechanical Data change
TFBGA Package Outline drawing change
03/06/00
-05
Program Erase Times change (Table 22)
6/21/01
-06
TFBGA48 package mechanical ouline and data changed
Daisy Chain commercial code defined (Table 28)
TFBGA48 Daisy Chain diagrams, Package and PCB Connections added (Figure 20
and 21)
24-Jan-2002
-07
-90 version changed to Vcc=2.7 to 3.6V; -120 version changed to CL=100pF
09-Mar-2004
8.0
INSTRUCTIONS AND COMMANDS section: description of Block Erase (BE) and
Erase Suspend (ES) instructions updated.
39/40
M29W800AT, M29W800AB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequ
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is g
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are s
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products a
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectron
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
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40/40