AD ADV7179WBCPZ2 Chip scale pal/ntsc video encoder with advanced power management Datasheet

Chip Scale PAL/NTSC Video Encoder with
Advanced Power Management
ADV7174/ADV7179
FEATURES
Programmable subcarrier frequency and phase
ITU-R1 BT601/BT656 YCrCb to PAL/NTSC video encoder
Programmable LUMA delay
High quality 10-bit video DACs
Individual on/off control of each DAC
SSAF™ (super sub-alias filter)
CCIR and square pixel operation
Advanced power management features
Integrated subcarrier locking to external video source
CGMS (copy generation management system)
Color signal control/burst signal control
WSS (wide screen signaling)
Interlaced/noninterlaced operation
NTSC M, PAL N2, PAL B/D/G/H/I, PAL-M3 , PAL 60
Complete on-chip video timing generator
Single 27 MHz clock required (×2 oversampling)
Programmable multimode master/slave operation
Macrovision 7.1 (ADV7174 only)
Closed captioning support
80 dB video SNR
Teletext insertion port (PAL-WST)
32-bit direct digital synthesizer for color subcarrier
On-board color bar generation
Multistandard video output support:
On-board voltage reference
Composite (CVBS)
2-wire serial MPU interface (I2C® compatible and fast I2C)
Component S-video (Y/C)
Single-supply 2.8 V and 3.3 V operation
Video input data port supports:
Small 40-lead 6 mm × 6 mm LFCSP package
CCIR-656 4:2:2 8-bit parallel input format
−40°C to +85°C at 3.3 V
Programmable simultaneous composite and S-video or RGB
−20°C to +85°C at 2.8 V
(SCART)/YPbPr video outputs
APPLICATIONS
Programmable luma filters low-pass [PAL/NTSC] notch,
Portable video applications
extended SSAF, CIF, and QCIF
Mobile phones
Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz,
Digital still cameras
1.2 MHz, and 2.0 MHz], CIF, and QCIF)
Programmable VBI (vertical blanking interval)
FUNCTIONAL BLOCK DIAGRAM
TTX
ADV7174/ADV7179
VAA
POWER
MANAGEMENT
CONTROL
(SLEEP MODE)
10
TELETEXT
INSERTION
BLOCK
CGMS AND WSS
INSERTION
BLOCK
YUV TO
RBG
MATRIX
10
RESET
COLOR
DATA
P7–P0
HSYNC
FIELD/VSYNC
BLANK
10
8
Y 8
4:2:2 TO
4:4:4
8
INTERPOLATOR
8
YCrCb
TO
U 8
YUV
MATRIX
V 8
ADD 9
SYNC
INTER- 9
POLATOR
10
PROGRAMMABLE
LUMINANCE
FILTER
8
8
10
U
ADD
BURST 8
INTERPOLATOR 8
PROGRAMMABLE
CHROMINANCE 10
FILTER
V
10
VIDEO TIMING
GENERATOR
CLOCK
I2C MPU PORT
SCLOCK
SDATA
ALSB
REAL-TIME
CONTROL
CIRCUIT
SCRESET/RTC
M
U 10
L
T
I 10
P
L
E 10
X
E
R
10-BIT
DAC
DAC A (PIN 29)
10-BIT
DAC
DAC B (PIN 28)
10-BIT
DAC
DAC C (PIN 24)
10
VOLTAGE
REFERENCE
CIRCUIT
SIN/COS
DDS BLOCK
GND
VREF
RSET
COMP
02980-A-001
TTXREQ
Figure 1.
1
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
2
Throughout the document, N is referenced to PAL – Combination – N.
3
ADV7174 only.
The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Contact the sales office for the latest
Macrovision version available.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
ADV7174/ADV7179
TABLE OF CONTENTS
Specifications..................................................................................... 4
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD . 24
2.8 V Specifications ...................................................................... 4
Power-On Reset .......................................................................... 25
2.8 V Timing Specifications ........................................................ 5
SCH Phase Mode ........................................................................ 25
3.3 V Specifications ...................................................................... 6
MPU Port Description............................................................... 25
3.3 V Timing Specifications ........................................................ 7
Register Accesses ........................................................................ 26
Absolute Maximum Ratings............................................................ 9
Register Programming ................................................................... 27
ESD Caution .................................................................................. 9
Subaddress Register (SR7–SR0) ............................................... 27
Pin Configuration and Function Descriptions ........................... 10
Register Select (SR5–SR0) ......................................................... 27
General Description ....................................................................... 11
Mode Register 1 (MR1) ............................................................. 29
Data Path Description................................................................ 11
Mode Register 2 (MR2) ............................................................. 30
Internal Filter Response ............................................................. 11
Mode Register 3 (MR3) ............................................................. 31
Typical Performance Characteristics ........................................... 13
Mode Register 4 (MR4) ............................................................. 32
Features ............................................................................................ 16
Timing Mode Register 0 (TR0) ................................................ 33
Color Bar Generation ................................................................ 16
Timing Mode Register 1 (TR1) ................................................ 34
Square Pixel Mode ...................................................................... 16
Subcarrier Frequency Registers 3–0 ........................................ 35
Color Signal Control .................................................................. 16
Subcarrier Phase Register .......................................................... 35
Burst Signal Control ................................................................... 16
Closed Captioning Even Field Data Registers 1–0 ................ 35
NTSC Pedestal Control ............................................................. 16
Closed Captioning Odd Field Data Registers 1–0 ................. 36
Pixel Timing Description .......................................................... 16
NTSC Pedestal/PAL Teletext Control Registers 3–0 ............. 36
8-Bit YCrCb Mode ................................................................. 16
Teletext Request Control Register (TC07) .............................. 37
Subcarrier Reset .......................................................................... 16
CGMS_WSS Register 0 (C/W0) ............................................... 37
Real-Time Control ..................................................................... 16
CGMS_WSS Register 1 (C/W1) ............................................... 38
Video Timing Description .................................................... 16
CGMS_WSS Register 2 (C/W2) ............................................... 38
Vertical Blanking Data Insertion.......................................... 17
Appendix 1—Board Design and Layout Considerations .......... 39
Mode 0 (CCIR-656): Slave Option ....................................... 17
Ground Planes ............................................................................ 39
Mode 0 (CCIR-656): Master Option ................................... 17
Power Planes ............................................................................... 39
Mode 1: Slave Option HSYNC, BLANK, FIELD ............... 20
Supply Decoupling ..................................................................... 40
Mode 1: Master Option HSYNC, BLANK, FIELD ............ 21
Digital Signal Interconnect ....................................................... 40
Mode 2: Slave Option HSYNC, VSYNC, BLANK ............. 22
Analog Signal Interconnect....................................................... 40
Mode 2: Master Option HSYNC, VSYNC, BLANK .......... 23
Appendix 2—Closed Captioning ................................................. 41
Rev. B | Page 2 of 52
ADV7174/ADV7179
Appendix 3—Copy Generation Management System (CGMS)
............................................................................................................42
Function of CGMS Bits ..............................................................42
Appendix 4—Wide Screen Signaling (WSS) ...............................43
Function of WSS Bits ..................................................................43
Appendix 5—Teletext .....................................................................44
Teletext Insertion.........................................................................44
Teletext Protocol ..........................................................................44
NTSC Waveforms (with Pedestal) ............................................ 45
NTSC Waveforms (without Pedestal) ...................................... 46
PAL Waveforms ........................................................................... 47
Pb Pr Waveforms......................................................................... 48
Appendix 7—Optional Output Filter ........................................... 49
Appendix 8—Recommended Register Values............................. 50
Outline Dimensions ........................................................................ 52
Ordering Guide ........................................................................... 52
Appendix 6—Waveforms ...............................................................45
REVISION HISTORY
4/09—Rev. A to Rev. B
Changes to Power-On Reset Section ............................................25
Changes to Figure 55 ......................................................................40
Changes to Figure 69, Figure 70, and Figure 72 ..........................47
Changes to Figure 81 Caption .......................................................52
Changes to Ordering Guide ...........................................................52
2/04—Changed from Rev. 0 to Rev A.
Added 2.8 V Version .......................................................... Universal
Format Updated.................................................................. Universal
Device Currents Updated on 3.3 V Specification .......... Universal
Added new Table 1 and renumbered Subsequent Tables............. 4
Added new Table 2 and Renumbered Subsequent Tables ........... 5
Change to Figure 54 ........................................................................38
Change to Figure 55 ........................................................................39
Change to Figure 79 ........................................................................48
Changed Ordering Guide Temperature Specifications ..............52
Updated Outline Dimensions ........................................................52
10/02—Revision 0: Initial Version
Rev. B | Page 3 of 52
ADV7174/ADV7179
SPECIFICATIONS
2.8 V SPECIFICATIONS
VAA = 2.8 V, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 1 , unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE 2
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS2
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
DIGITAL OUTPUTS2
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
ANALOG OUTPUTS2
Output Current 3
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
POWER REQUIREMENTS2, 4
VAA
Normal Power Mode
IDAC (Max) 5
ICCT 6
Low Power Mode
IDAC (Max)5
ICCT6
Sleep Mode
IDAC 7
ICCT 8
Power Supply Rejection Ratio
Conditions1
Min
RSET = 300 Ω
Guaranteed monotonic
Typ
Max
Unit
10
Bits
±1
LSB
LSB
±3.0
1.6
VIN = 0.4 V or 2.4 V
0.7
±1
V
V
μA
pF
0.4
10
V
V
μA
pF
10
ISOURCE = 400 μA
ISINK = 3.2 mA
2.4
10
RSET = 150 Ω, RL = 37.5 Ω
33
34.7
2.0
0
37
1.4
30
IOUT = 0 mA
30
2.8
RSET = 150 Ω, RL = 37.5 Ω
COMP = 0.1 μF
1
mA
%
V
kΩ
pF
V
115
30
120
mA
mA
62
30
mA
mA
0.1
0.001
0.01
μA
μA
%/%
0.5
Temperature range TMIN to TMAX: –20°C to +85°C.
Guaranteed by characterization.
3
DACs can output 35 mA typically at 2.8 V (RSET = 150 Ω and RL = 37.5 Ω). Full drive into 37.5 Ω load.
4
Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C.
5
IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all three DACs. Turning off individual DACs
reduces IDAC correspondingly.
6
ICCT (circuit current) is the continuous current required to drive the device.
7
Total DAC current in sleep mode.
8
Total continuous current during sleep mode.
2
Rev. B | Page 4 of 52
ADV7174/ADV7179
2.8 V TIMING SPECIFICATIONS
VAA = 2.8 V, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 1 , unless otherwise noted.
Table 2.
Parameter
MPU PORT 2, 3
SCLOCK Frequency
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS3, 4
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL PORT4, 5
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, tPD 5
TELETEXT3, 4, 6
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL3, 4
RESET Low Time
Conditions1
Min
After this period the first clock is generated
Relevant for repeated start condition
Typ
0
0.6
1.3
0.6
0.6
100
Max
Unit
400
kHz
μs
μs
μs
μs
ns
ns
ns
μs
300
300
0.6
7
0
ns
ns
27
12
8
48
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
23
2
6
ns
ns
ns
8
8
3.5
4
4
3
6
1
ns
Temperature range TMIN to TMAX: –20°C to +85°C.
TTL input values are 0 V to 2.8 V, with input rise/fall times −3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF.
3
Guaranteed by characterization.
4
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
5
See Figure 60.
6
Teletext Port consists of the following:
Teletext Output: TTXREQ
Teletext Input: TTX
2
Rev. B | Page 5 of 52
ADV7174/ADV7179
3.3 V SPECIFICATIONS
VAA = 3.0 V–3.6 V 1 , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 2 , unless otherwise noted.
Table 3.
Parameter
STATIC PERFORMANCE 3
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS3
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN3, 4
Input Capacitance, CIN
DIGITAL OUTPUTS3
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
ANALOG OUTPUTS3
Output Current4, 5
Output Current 6
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
POWER REQUIREMENTS3, 7
VAA
Normal Power Mode
IDAC (Max) 8
IDAC (Min)8
ICCT 9
Low Power Mode
IDAC (Max)8
IDAC (Min)8
ICCT9
Sleep Mode
IDAC 10
ICCT 11
Power Supply Rejection Ratio
Conditions1
Min
RSET = 300 Ω
Guaranteed Monotonic
Typ
Max
Unit
10
Bits
±1
LSB
LSB
± 0.6
2
0.8
±1
10
V
V
μA
pF
0.4
10
10
V
V
μA
pF
VIN = 0.4 V or 2.4 V
ISOURCE = 400 μA
ISINK = 3.2 mA
RSET = 150 Ω, RL = 37.5 Ω
RSET = 1041 Ω, RL = 262.5 Ω
2.4
33
34.7
5
2.0
30
mA
mA
%
V
kΩ
pF
3.3
3.6
V
115
20
35
120
mA
mA
mA
0
37
1.4
30
IOUT = 0 mA
3.0
RSET = 150 Ω, RL = 37.5 Ω
RSET = 1041 Ω, RL = 262.5 Ω
COMP = 0.1 μF
1
62
20
35
mA
mA
mA
0.1
0.001
0.01
μA
μA
%/%
0.5
The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
Temperature range TMIN to TMAX: –40°C to +85°C.
3
Guaranteed by characterization.
4
Full drive into 37.5 Ω load.
5
DACs can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 37.5 Ω), optimum performance obtained at 18 mA DAC current (RSET = 300 Ω and RL = 75 Ω).
6
Minimum drive current (used with buffered/scaled output load).
7
Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C.
8
IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all three DACs. Turning off individual DACs
reduces IDAC correspondingly.
9
ICCT (circuit current) is the continuous current required to drive the device.
10
Total DAC current in sleep mode.
11
Total continuous current during sleep mode.
2
Rev. B | Page 6 of 52
ADV7174/ADV7179
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V–3.6 V 1 , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 2 , unless otherwise noted.
Table 4.
Parameter
MPU PORT 3, 4
SCLOCK Frequency
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL PORT4, 5
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, tPD 6
TELETEXT3, 4
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL3, 4
RESET Low Time
Conditions1
Min
After this period, the first clock is generated
Relevant for repeated start condition
Typ
0
0.6
1.3
0.6
0.6
100
Max
Unit
400
kHz
μs
μs
μs
μs
ns
ns
ns
μs
300
300
0.6
7
0
ns
ns
27
12
8
48
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
23
2
6
ns
ns
ns
8
8
3.5
4
4
3
6
1
ns
The maximum/minimum specifications are guaranteed over this range. The maximum/minimum values are typical over 3.0 V to 3.6 V range.
Temperature range TMIN to TMAX: –40°C to +85°C.
TTL input values are 0 V to 3 V, with input rise/fall times −3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF.
4
Guaranteed by characterization.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
See Figure 60.
2
3
Rev. B | Page 7 of 52
ADV7174/ADV7179
t5
t3
t3
SDATA
t6
SCLOCK
t2
t7
t4
t8
02980-0A-002
t1
Figure 2. MPU Port Timing Diagram
CLOCK
t9
t12
HSYNC,
FIELD/VSYNC,
BLANK
PIXEL INPUT
DATA
Cb
Y
Cr
Y
t11
CONTROL
O/PS
Cb
Y
t13
HSYNC,
FIELD/VSYNC,
BLANK
02980-A-003
CONTROL
I/PS
S
t10
t14
Figure 3. Pixel and Control Data Timing Diagram
TTXREQ
t16
CLOCK
t17
t18
4 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
Figure 4. Teletext Timing Diagram
Rev. B | Page 8 of 52
3 CLOCK
CYCLES
4 CLOCK
CYCLES
02980-A-004
TTX
ADV7174/ADV7179
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
VAA to GND
Voltage on Any Digital Input Pin
Storage Temperature (TS)
Junction Temperature (TJ)
Lead Temperature
Soldering, 10 sec
Analog Outputs to GND1
θJA2
Rating
4V
GND – 0.5 V to VAA + 0.5 V
−65°C to +150°C
150°C
260°C
GND – 0.5 V to VAA
30°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability
__________________________________________________
1
2
Analog output short circuit to any power supply or common can be of an indefinite duration.
With the exposed metal paddle on the underside of LFCSP soldered to GND on the PCB.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 9 of 52
ADV7174/ADV7179
P2
P1
P0
TTX
TTXREQ
SCRESET/
RTC
RSET
39
P3
GND
40
P4
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
38
37
36
35
34
33
32
31
PIN 1
INDICATOR
30
VREF
29
DAC A
P5 3
28
DAC B
4
27
VAA
26
GND
CLOCK 1
VAA 2
P6
ADV7174/ADV7179
LFCSP
P7 5
GND 6
TOP VIEW
(Not to Scale)
GND 7
25
VAA
24
DAC C
15
16
17
18
19
20
02980-A-005
14
GND
13
RESET
12
GND
GND
11
VAA
SCLOCK
GND
21
ALSB
SDATA
VAA 10
BLANK
COMP
22
HSYNC
23
FIELD/VSYNC
8
GND 9
GND
Figure 5. Pin Configurations
Table 6. Pin Function Descriptions
Mnemonic
P7–P0
CLOCK
Input/
Output
I
I
HSYNC
I/O
FIELD/VSYNC
I/O
BLANK
SCRESET/RTC
I/O
I
VREF
RSET
COMP
I/O
I
O
DAC A
DAC B
DAC C
SCLOCK
SDATA
ALSB
RESET
O
O
O
I
I/O
I
I
TTX
TTXREQ
VAA
GND
I
O
P
G
Function
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0). P0 is the LSB.
TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz
(NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (master mode) or accept (slave
mode) sync signals.
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be configured to output
(master mode) or accept (slave mode) these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic 0. This signal is optional.
This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a
subcarrier reset pin, in which case a low-to-high transition on this pin resets the subcarrier to Field 0.
Alternatively, it can be configured as a real-time control (RTC) input.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video signals.
Compensation Pin. Connect a 0.1 μF capacitor from COMP to VAA. For optimum dynamic performance in low
power mode, the value of the COMP capacitor can be lowered to as low as 2.2 nF.
DAC Output (see Table 13)
DAC Output (see Table 13).
DAC Output (see Table 13).
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
TTL Address Input. This signal sets up the LSB of the MPU address.
This input resets the on-chip timing generator and sets the ADV7174/ADV7179 into default mode. This is NTSC
operation, Timing Slave Mode 0, 8-bit operation, 2× composite out signals. DACs A, B, and C are enabled.
Teletext Data.
Teletext Data Request Signal/Defaults to GND when Teletext Not Selected.
Power Supply (2.8 V or 3.3 V).
Ground Pin.
Rev. B | Page 10 of 52
ADV7174/ADV7179
GENERAL DESCRIPTION
The ADV7174/ADV7179 is an integrated digital video encoder
that converts digital CCIR-601 4:2:2 8-bit component video data
into a standard analog baseband television signal compatible
with worldwide standards.
The on-board SSAF (super sub-alias filter) with extended
luminance frequency response and sharp stop-band attenuation
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution.
An advanced power management circuit enables optimal control of power consumption in both normal operating modes
and in power-down or sleep modes.
The ADV7174/ADV7179 supports both PAL and NTSC square
pixel operation. The parts incorporate WSS and CGMS-A data
control generation.
The output video frames are synchronized with the incoming
data timing reference codes. Optionally, the encoder accepts
(and can generate) HSYNC, VSYNC, and FIELD timing signals.
These timing signals can be adjusted to change pulse width and
position while the part is in the master mode. The encoder
requires a signal two times the pixel rate (27 MHz) clock for
standard operation. Alternatively, the encoder requires a
24.5454 MHz clock for NTSC or 29.5 MHz clock for PAL
square pixel mode operation. All internal timing is generated
on-chip.
typically have a range of 128 ± 112; however, it is possible to
input data from 1 to 254 on both Y, Cb, and Cr. The ADV7174/
ADV7179 supports PAL (B/D/G/H/I/M/N) and NTSC (with
and without pedestal) standards. The appropriate SYNC, BLANK,
and burst levels are added to the YCrCb data. Macrovision Antitaping (ADV7174 only), closed-captioning, and Teletext levels
are also added to Y and the resultant data is interpolated to a
rate of 27 MHz. The interpolated data is filtered and scaled by
three digital FIR filters.
The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chrominance signal. The luma (Y) signal can be delayed 1–3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.
The YCrCb data is also used to generate RGB data with
appropriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively,
analog YPbPr data can be generated instead of RGB data.
The three l0-bit DACs can be used to output:
•
•
•
•
Composite Video + Composite Video
S-Video + Composite Video
YPrPb Video
SCART RGB Video
Alternatively, each DAC can be individually powered off if not
required.
A separate Teletext port enables the user to directly input
Teletext data during the vertical blanking interval.
The ADV7174/ADV7179 modes are set up over a 2-wire serial
bidirectional port (I2 C compatible) with two slave addresses.
The ADV7174/ADV7179 is packaged in a 40-lead 6 mm × 6 mm
LFCSP package.
DATA PATH DESCRIPTION
For PAL B/D/G/H/I/M/N and NTSC M and N modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
27 MHz data rate. The pixel data is demultiplexed to form three
data paths. Y typically has a range of 16 to 235, and Cr and Cb
Video output levels are illustrated in Appendix 6.
INTERNAL FILTER RESPONSE
The Y filter supports several different frequency responses,
including two low-pass responses, two notch responses, an
extended (SSAF) response, a CIF response, and a QCIF
response. The UV filter supports several different frequency
responses, including four low-pass responses, a CIF response,
and a QCIF response. These can be seen in Table 7 and Table 8
and Figure 6 to Figure 18.
Rev. B | Page 11 of 52
ADV7174/ADV7179
Table 7. Luminance Internal Filter Specifications
Filter Type
Low-Pass
(NTSC)
Low-Pass
(PAL)
Notch (NTSC)
Notch (PATL)
Extended
(SSAF)
CIF
QCIF
Filter Selection
MR04 MR03 MR02
0
0
0
Pass-Band Ripple
(dB)
3 dB Bandwidth
(MHz)
Stop-Band Cutoff
(MHz)
Stop-Band Attenuation
(dB)
0.091
4.157
7.37
−56
0
0
1
0.15
4.74
7.96
−64
0
0
1
1
1
0
0
1
0
0.015
0.095
0.051
6.54
6.24
6.217
8.3
8.0
8.0
−68
−66
−61
1
1
0
1
1
0
0.018
Monotonic
3.0
1.5
7.06
7.15
−61
−50
Table 8. Chrominance Internal Filter Specifications
Filter Type
1.3 MHz
Low-Pass
0.65 MHz
Low-Pass
1.0 MHz
Low-Pass
2.0 MHz
Low-Pass
Reserved
CIF
QCIF
Filter Selection
MR07 MR06 MR05
0
0
0
Pass-Band Ripple
(dB)
3 dB Bandwidth
(MHz)
Stop-Band Cutoff
(MHz)
Stop-Band Attenuation
(dB)
0.084
1.395
3.01
−45
0
0
1
Monotonic
0.65
3.64
−58.5
0
1
0
Monotonic
1.0
3.73
−49
0
1
1
0.0645
2.2
5.0
−40
1
1
1
0
0
1
0
1
0
0.084
Monotonic
0.7
0.5
3.01
4.08
−45
−50
Rev. B | Page 12 of 52
ADV7174/ADV7179
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
–30
–40
–60
–70
–40
–50
02980-A-006
–50
–30
0
2
4
6
8
FREQUENCY (MHz)
10
02980-A-009
MAGNITUDE (dB)
TYPICAL PERFORMANCE CHARACTERISTICS
–60
–70
12
0
2
0
0
–10
–10
–20
–20
–30
–40
–30
–40
0
2
4
6
8
FREQUENCY (MHz)
10
–60
–70
12
0
Figure 7. PAL Low-Pass Luma Filter
2
4
6
8
FREQUENCY (MHz)
10
12
Figure 10. Extended Mode (SSAF) Luma Filter
0
–10
–10
–20
–20
MAGNITUDE (dB)
0
–30
–40
–30
–40
–50
–60
0
2
4
6
8
FREQUENCY (MHz)
10
02980-A-011
–50
02980-A-008
MAGNITUDE (dB)
12
02980-A-010
–60
–70
10
–50
02980-A-007
–50
–70
6
8
FREQUENCY (MHz)
Figure 9. PAL Notch Luma Filter
MAGNITUDE (dB)
MAGNITUDE (dB)
Figure 6. Chrominance Internal Filter Specifications
4
–60
–70
12
Figure 8. NTSC Notch Luma Filter
0
2
4
6
8
FREQUENCY (MHz)
Figure 11. CIF Luma Filter
Rev. B | Page 13 of 52
10
12
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
–30
–40
–60
–70
–40
–50
02980-A-012
–50
–30
0
2
4
6
8
FREQUENCY (MHz)
10
02980-A-015
MAGNITUDE (dB)
ADV7174/ADV7179
–60
–70
12
0
0
0
–10
–10
–20
–20
–30
–40
12
–30
–40
0
2
4
6
8
FREQUENCY (MHz)
10
–60
–70
12
0
Figure 13. 1.3 MHz Low-Pass Chroma Filter
2
4
6
8
FREQUENCY (MHz)
10
12
Figure 16. 2.0 MHz Low-Pass Chroma Filter
0
–10
–10
–20
–20
MAGNITUDE (dB)
0
–30
–40
–30
–40
–50
–60
0
2
4
6
8
FREQUENCY (MHz)
10
02980-A-017
–50
02980-A-014
MAGNITUDE (dB)
10
02980-A-016
–60
–70
6
8
FREQUENCY (MHz)
–50
02980-A-013
–50
–70
4
Figure 15. 1.0 MHz Low-Pass Chroma Filter
MAGNITUDE (dB)
MAGNITUDE (dB)
Figure 12. QCIF Luma Filter
2
–60
–70
12
Figure 14. 0.65 MHz Low-Pass Chroma Filter
0
2
4
6
8
FREQUENCY (MHz)
Figure 17. CIF Chroma Filter
Rev. B | Page 14 of 52
10
12
ADV7174/ADV7179
0
–10
–30
–40
–50
02980-A-018
MAGNITUDE (dB)
–20
–60
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
Figure 18. QCIF Chroma Filter
Rev. B | Page 15 of 52
ADV7174/ADV7179
FEATURES
COLOR BAR GENERATION
REAL-TIME CONTROL
The ADV7174/ADV7179 can be configured to generate 100/
7.5/75/7.5 color bars for NTSC or 100/0/75/0 for PAL color
bars. These are enabled by setting MR17 of Mode Register 1 to
Logic 1.
Together with the SCRESET/RTC pin and Bits MR22 and MR21
of Mode Register 2, the ADV7174/ADV7179 can be used to
lock to an external video source. The real-time control mode
allows the ADV7174/ADV7179 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
data stream in the RTC format (such as a ADV7183A video
decoder; see Figure 19), the part automatically changes to the
compensated subcarrier frequency on a line-by-line basis. This
digital data stream is 67 bits wide and the subcarrier is contained
in Bits 0 to 21. Each bit is two clock cycles long. 00H should be
written into all four subcarrier frequency registers when using
this mode.
SQUARE PIXEL MODE
The ADV7174/ADV7179 can be used to operate in square pixel
mode. For NTSC operation, an input clock of 24.5454 MHz is
required. Alternatively, for PAL operation, an input clock of
29.5 MHz is required. The internal timing logic adjusts accordingly for square pixel mode operation.
COLOR SIGNAL CONTROL
The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
Video Timing Description
BURST SIGNAL CONTROL
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NTSC PEDESTAL CONTROL
The pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC pedestal control registers.
This allows the pedestals to be controlled during the vertical
blanking interval.
PIXEL TIMING DESCRIPTION
The ADV7174/ADV7179 operates in an 8-bit YCrCb mode.
The ADV7174/ADV7179 is intended to interface with off-theshelf MPEG1 and MPEG2 decoders. Consequently, the
ADV7174/ADV7179 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either a system
master video timing generator or as a slave to the system video
timing generator. The ADV7174/ADV7179 generates all of the
required horizontal and vertical timing periods and levels for
the analog video outputs.
The ADV7174/ADV7179 calculates the width and placement of
analog sync pulses, blanking levels, and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration
and equalization pulses are inserted where required.
8-Bit YCrCb Mode
This default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1, Cb1, Y2, and so on. The Y, Cb, and Cr data are input
on a rising clock edge.
SUBCARRIER RESET
Together with the SCRESET/RTC pin and Bits MR22 and
MR21 of Mode Register 2, the ADV7174/ADV7179 can be used
in subcarrier reset mode. The subcarrier resets to Field 0 at the
start of the following field when a low-to-high transition occurs
on this input pin.
In addition, the ADV7174/ADV7179 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections into the correct
location for the new clock frequencies.
The ADV7174/ADV7179 has four distinct master and four
distinct slave timing configurations. Timing control is
established with the bidirectional HSYNC, BLANK, and
FIELD/VSYNC pins. Timing Mode Register 1 can also be used
to vary the timing pulse widths and where they occur in
relation to each other.
Rev. B | Page 16 of 52
ADV7174/ADV7179
CLOCK
COMPOSITE
VIDEO
(e.g., VCR
OR CABLE)
SCRESET/RTC
VIDEO
DECODER
(e.g., ADV7183A)
GREEN/LUMA/Y
RED/CHROMA/Pr
P7–P0
BLUE/COMPOSITE/Pb
HSYNC
FIELD/VSYNC
AD7174/ADV7179
H/LTRANSITION
COUNT START
LOW
128
13
SEQUENCE
RESERVED
BIT2
RESET
BIT3
5 BITS
RESERVED
4 BITS
RESERVED
14 BITS
RESERVED
0
FSC PLL INCREMENT1
21
0
RTC
14
NOT USED IN THE
ADV7174/ADV7179
67 68
19
VALID
SAMPLE
INVALID
SAMPLE
8/LLC
NOTES
1F
SC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7174/ADV7179 FSC DDS REGISTER IS
FSC PLL INCREMENT BITS 21:0 PLUS BITS 0:9 OF THE SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7174/ADV7179.
2SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
3RESET BIT
RESET ADV7174/ADV7179 DDS
02980-A-019
TIME SLOT: 01
Figure 19. RTC Timing and Connections
Vertical Blanking Data Insertion
It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not bear line sync or pre-/postequalization pulses (see Figure 21 to Figure 32). This mode of
operation is called partial blanking and is selected by setting
MR32 to 1. It allows the insertion of any VBI data (opened VBI)
into the encoded output waveform. This data is present in the
digitized incoming YCbCr data stream, for example. WSS data,
CGMS, VPS, and so on. Alternatively, the entire VBI may be
blanked (no VBI data inserted) on these lines by setting MR32
to 0.
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7174/ADV7179 is controlled by the SAV (start active
video) and EAV (end active video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchro-
nization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace.
Mode 0 is illustrated in Figure 20. The HSYNC, FIELD/VSYNC,
and BLANK (if not used) pins should be tied high during this
mode.
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7174/ADV7179 generates H, V, and F signals required
for the SAV and EAV time codes in the CCIR-656 standard. The
H bit is output on the HSYNC pin, the V bit is output on the
BLANK pin, and the F bit is output on the FIELD/VSYNC pin.
Mode 0 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).
The H, V, and F transitions relative to the video waveform are
illustrated in Figure 23.
Rev. B | Page 17 of 52
ADV7174/ADV7179
ANALOG
VIDEO
EAV CODE
Y
SAV CODE
C
F 0 0 X 8 1 8 1
Y
r
F 0 0 Y 0 0 0 0
ANCILLARY DATA
(HANC)
4 CLOCK
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
8 1 8 1 F 0 0 X C Y C Y C Y C Y C
b
r
b
0 0 0 0 F 0 0 Y b
r
0 F F A A A
0 F F B B B
4 CLOCK
268 CLOCK
1440 CLOCK
4 CLOCK
4 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
280 CLOCK
02980-A-020
INPUT PIXELS
1440 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
Figure 20. Timing Mode 0 (Slave Mode)
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
H
V
F
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
02980-A-021
H
V
F
ODD FIELD
EVEN FIELD
Figure 21. Timing Mode 0 (NTSC Master Mode)
Rev. B | Page 18 of 52
ADV7174/ADV7179
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
309
310
DISPLAY
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
335
334
336
H
ODD FIELD
EVEN FIELD
Figure 22. Timing Mode 0 (PAL Master Mode)
ANALOG
VIDEO
H
F
02980-A-023
F
02980-A-022
V
V
Figure 23. Timing Mode 0 Data Transitions (Master Mode)
Rev. B | Page 19 of 52
ADV7174/ADV7179
Mode 1: Slave Option HSYNC, BLANK, FIELD
input when HSYNC is low indicates a new frame, i.e., vertical
retrace. The BLANK signal is optional. When the BLANK input
is disabled, the ADV7174/ADV7179 automatically blanks all
normally blank lines as per CCIR-624. Mode 1 is illustrated in
Figure 24 (NTSC) and Figure 25 (PAL).
(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode, the ADV7174/ADV7179 accepts horizontal
SYNC and odd/even FIELD signals. A transition of the FIELD
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
3
4
6
5
7
8
10
9
20
11
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
260
VERTICAL BLANK
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
FIELD
ODD FIELD
02980-A-024
BLANK
EVEN FIELD
Figure 24. Timing Mode 1 (NTSC)
DISPLAY
DISPLAY
622
VERTICAL BLANK
623
624
625
1
2
3
4
6
5
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
FIELD
ODD FIELD
02980-A-025
BLANK
EVEN FIELD
Figure 25. Timing Mode 1 (PAL)
Rev. B | Page 20 of 52
ADV7174/ADV7179
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7174/ADV7179 can generate horizontal
SYNC and odd/even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., vertical
retrace. The BLANK signal is optional. When the BLANK input
is disabled, the ADV7174/ADV7179 automatically blanks all
normally blank lines as per CCIR-624. Pixel data is latched on
the rising clock edge following the timing signal transitions.
Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL).
Figure 26 illustrates the HSYNC, BLANK, and FIELD for an
odd or even field transition relative to the pixel data.
HSYNC
FIELD
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
BLANK
Cb
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Rev. B | Page 21 of 52
Cr
Y
02980-A-026
PIXEL
DATA
ADV7174/ADV7179
Mode 2: Slave Option HSYNC, VSYNC, BLANK
transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7174/ADV7179 automatically blanks all
normally blank lines as per CCIR-624. Mode 2 is illustrated in
Figure 27 (NTSC) and Figure 28 (PAL).
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode, the ADV7174/ADV7179 accepts horizontal and
vertical SYNC signals. A coincident low transition of both and
VSYNC inputs indicates the start of an odd field. A VSYNC low
DISPLAY
522
DISPLAY
VERTICAL BLANK
524
523
525
4
3
2
1
7
6
5
8
10
9
22
21
20
11
HSYNC
BLANK
EVEN FIELD
VSYNC
ODD FIELD
DISPLAY
DISPLAY
260
VERTICAL BLANK
261
262
263
264
265
268
267
266
272
271
270
269
273
283
274
284
285
HSYNC
VSYNC
02980-A-027
BLANK
EVEN FIELD
ODD FIELD
Figure 27. Timing Mode 2 (NTSC)
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 28. Timing Mode 2 (PAL)
Rev. B | Page 22 of 52
02980-A-028
HSYNC
ADV7174/ADV7179
Mode 2: Master Option HSYNC, VSYNC, BLANK
BLANK input is disabled, the ADV7174/ADV7179 automatically
blanks all normally blank lines as per CCIR-624. Mode 2 is
illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29
illustrates the HSYNC, BLANK, and VSYNC for an even-toodd field transition relative to the pixel data. Figure 30
illustrates the HSYNC, BLANK, and VSYNC for an odd-toeven field transition relative to the pixel data.
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7174/ADV7179 can generate horizontal
and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A
VSYNC low transition when HSYNC is high indicates the start
of an even field. The BLANK signal is optional. When the
HSYNC
VSYNC
BLANK
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
PIXEL
DATA
Y
Cr
Y
02980-A-029
Cb
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
PAL = 864 × CLOCK/2
NTSC = 858 × CLOCK/2
BLANK
Cb
Y
Cr
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
Rev. B | Page 23 of 52
Cb
02980-A-082
PIXEL
DATA
ADV7174/ADV7179
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
that is, vertical retrace. The BLANK signal is optional. When
the BLANK input is disabled, the ADV7174/ADV7179
automatically blanks all normally blank lines as per CCIR-624.
Mode 3 is illustrated in Figure 31 (NTSC) and Figure 32 (PAL).
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7174/ADV7179 accepts or generates
horizontal SYNC and odd/even FIELD signals. A transition of
the FIELD input when HSYNC is high indicates a new frame,
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
5
7
8
9
10
11
20
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
260
DISPLAY
VERTICAL BLANK
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
FIELD
ODD FIELD
02980-A-030
BLANK
EVEN FIELD
Figure 31. Timing Mode 3 (NTSC)
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
EVEN FIELD
FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
FIELD
ODD FIELD
02980-A-031
BLANK
EVEN FIELD
Figure 32. Timing Mode 3 (PAL)
Rev. B | Page 24 of 52
ADV7174/ADV7179
1
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error and results in very minor
SCH phase jumps at the start of the 4- or 8-field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7174/ADV7179 is
configured in RTC mode (MR21 = 1 and MR22 = 1). Under
these conditions (unstable video), the subcarrier phase reset
should be enabled (MR22 = 0 and MR21 = 1), but no reset
applied. In this configuration, the SCH phase can never be
reset, which means that the output video can now track the
unstable input video. The subcarrier phase reset, when applied,
resets the SCH phase to Field 0 at the start of the next field, for
example, subcarrier phase reset applied in Field 5 (PAL) on the
start of the next field SCH phase is reset to Field 0.
MPU PORT DESCRIPTION
The ADV7174/ADV7179 supports a 2-wire serial (I2C
compatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA) and serial clock (SCLOCK),
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7174/ADV7179 has four possible slave addresses for both
read and write operations. These are unique addresses for each
device and are illustrated in Figure 33 and Figure 34. The LSB
sets either a read or write operation. Logic 1 corresponds to a
read operation, while Logic 0 corresponds to a write operation.
A 1 is set by setting the ALSB pin of the ADV7174/ ADV7179
to Logic 0 or Logic 1.
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 33. ADV7174 Slave Address
0
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
SCH PHASE MODE
The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, 0 SCH phase
error would be maintained forever, but in reality, this is
impossible to achieve due to clock frequency variations. This
effect is reduced by the use of a 32-bit DDS, which generates
this SCH.
0
02980-A-032
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port so that the pixel
inputs, P7–P0, are selected. After reset, the ADV7174/ADV7179
are automatically set up to operate in NTSC mode. Subcarrier
frequency code 21F07C16H is loaded into the subcarrier
frequency registers. All other registers, with the exceptions of
Mode Register 1 and Mode Register 4, are set to 00H. Bit MR44
of Mode Register 4 is set to Logic 1. This enables the 7.5 IRE
pedestal. Bit MR13, DAC A, and Bit MR16, DAC C, are powered
down by default.
1
READ/WRITE
CONTROL
0
1
WRITE
READ
02980-A-033
POWER-ON RESET
Figure 34. ADV7179 Slave Address
To control the various devices on the bus, the following
protocol must be followed: first, the master initiates a data
transfer by establishing a start condition, defined by a high-tolow transition on SDATA while SCLOCK remains high. This
indicates that an address/data stream will follow. All peripherals
respond to the start condition and shift the next eight bits (7-bit
address + R/W bit). The bits transfer from MSB down to LSB.
The peripheral that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This is known as an Acknowledge bit. All other devices
withdraw from the bus at this point and maintain an idle
condition. The idle condition is where the device monitors the
SDATA and SCLOCK lines waiting for the start condition and
the correct transmitted address. The R/W bit determines the
direction of the data. A Logic 0 on the LSB of the first byte
means that the master will write information to the peripheral.
A Logic 1 on the LSB of the first byte means that the master will
read information from the peripheral.
The ADV7174/ADV7179 acts as a standard slave device on the
bus. The data on the SDATA pin is eight bits long, supporting
the 7-bit addresses plus the R/W bit. The ADV7174/ADV7179
has 26 subaddresses to enable access to the internal registers. It
therefore interprets the first byte as the device address and the
second byte as the starting subaddress. The subaddresses’ auto
increment allows data to be written to or read from the starting
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without having to update all the
registers. There is one exception. The subcarrier frequency
registers should be updated in sequence, starting with
Subcarrier Frequency Register 0. The auto increment function
should then be used to increment and access Subcarrier
Rev. B | Page 25 of 52
ADV7174/ADV7179
Frequency Registers 1, 2, and 3. The subcarrier frequency
registers should not be accessed independently.
Figure 35 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 36 shows bus write and read sequences.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high period,
the user should issue only one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADV7174/
ADV7179 cannot issue an acknowledge and returns to the idle
condition. If in auto-increment mode the user exceeds the
highest subaddress, the following action is taken:
2.
S
SLAVE ADDR A(S)
SUB ADDR
A(S)
S
SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
8
9
1–7
8
9
1–7
8
DATA
A(S) S
P
STOP
The MPU can write to or read from all of the ADV7174/
ADV7179 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All communications with the part through the bus start with an access to
the subaddress register. A read/write operation is performed
from to the target address, which then increments to the next
address until a stop command on the bus is performed.
A(S)
DATA
A(S) P
LSB = 1
SUB ADDR
9
ACK
REGISTER ACCESSES
DATA
LSB = 0
READ
SEQUENCE
1–7
Figure 35. Bus Data Transfer
In read mode, the highest subaddress register contents
continues to be output until the master device issues a noacknowledge. This indicates the end of a read. A noacknowledge condition is when the SDATA line is not
pulled low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no-acknowledge is issued by
the ADV7174/ADV7179, and the part returns to the idle
condition.
WRITE
SEQUENCE
S
START ADDR R/W ACK SUBADDRESS ACK
SLAVE ADDR
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S)
DATA
A(M)
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 36. Write and Read Sequences
Rev. B | Page 26 of 52
DATA
A(M) P
02980-A-034
SCLOCK
02980-A-035
1.
SDATA
ADV7174/ADV7179
REGISTER PROGRAMMING
This section describes the configuration of each register,
including the subaddress register, mode registers, subcarrier
frequency registers, the subcarrier phase register, timing
registers, closed captioning extended data registers, closed
captioning data registers, and NTSC pedestal control registers.
Figure 37 shows the various operations under the control of the
subaddress register. Zero should always be written to SR7–SR6.
REGISTER SELECT (SR5–SR0)
These bits are set up to point to the required starting address.
SUBADDRESS REGISTER (SR7–SR0)
The communications register is an 8-bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes
place.
SR7
SR6
SR5
SR4
SR3
SR1
SR2
SR0
SR7 – SR6(000)
ADV7174 SUBADDRESS REGISTER
SR5 SR4 SR3 SR2 SR1 SR0
ADV7179 SUBADDRESS REGISTER
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
MODE REGISTER 4
RESERVED
RESERVED
TIMING MODE REGISTER 0
TIMING MODE REGISTER 1
SUBCARRIER FREQUENCY REGISTER 0
SUBCARRIER FREQUENCY REGISTER 1
SUBCARRIER FREQUENCY REGISTER 2
SUBCARRIER FREQUENCY REGISTER 3
SUBCARRIER PHASE REGISTER
CLOSED CAPTIONING EXTENDED DATA BYTE 0
CLOSED CAPTIONING EXTENDED DATA BYTE 1
CLOSED CAPTIONING DATA BYTE 0
CLOSED CAPTIONING DATA BYTE 1
NTSC PEDESTAL CONTROL REGISTER 0/
PAL TTX CONTROL REGISTER 0
NTSC PEDESTAL CONTROL REGISTER 1/
PAL TTX CONTROL REGISTER 1
NTSC PEDESTAL CONTROL REGISTER 2/
PAL TTX CONTROL REGISTER 2
NTSC PEDESTAL CONTROL REGISTER 3/
PAL TTX CONTROL REGISTER 3
CGMS_WSS_0
CGMS_WSS_1
CGMS_WSS_2
TELETEXT REQUEST CONTROL REGISTER
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Figure 37. Subaddress Register Map
Rev. B | Page 27 of 52
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
MODE REGISTER 4
RESERVED
RESERVED
TIMING MODE REGISTER 0
TIMING MODE REGISTER 1
SUBCARRIER FREQUENCY REGISTER 0
SUBCARRIER FREQUENCY REGISTER 1
SUBCARRIER FREQUENCY REGISTER 2
SUBCARRIER FREQUENCY REGISTER 3
SUBCARRIER PHASE REGISTER
CLOSED CAPTIONING EXTENDED DATA BYTE 0
CLOSED CAPTIONING EXTENDED DATA BYTE 1
CLOSED CAPTIONING DATA BYTE 0
CLOSED CAPTIONING DATA BYTE 1
NTSC PEDESTAL CONTROL REGISTER 0/
PAL TTX CONTROL REGISTER 0
NTSC PEDESTAL CONTROL REGISTER 1/
PAL TTX CONTROL REGISTER 1
NTSC PEDESTAL CONTROL REGISTER 2/
PAL TTX CONTROL REGISTER 2
NTSC PEDESTAL CONTROL REGISTER 3/
PAL TTX CONTROL REGISTER 3
CGMS_WSS_0
CGMS_WSS_1
CGMS_WSS_2
TELETEXT REQUEST CONTROL REGISTER
RESERVED
RESERVED
RESERVED
RESERVED
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
POWER-UP
VALUES
00h
58h
00h
00h
10h
00h
00h
00h
00h
16h
7Ch
F0h
21h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
02980-A-036
ZERO SHOULD BE WRITTEN
TO THESE BITS
ADV7174/ADV7179
MODE REGISTER 0 (MR0)
Bits:
Address:
MR07 – MR00
SR4–SR0 = 00H
Figure 38 shows the various operations under the control of Mode Register 0. This register can be read from as well as written to.
MR06
MR05
MR04
CHROMA FILTER SELECT
MR07 MR06 MR05
0
0
0
1.3 MHz LOW-PASS FILTER
0
0
1
0.65 MHz LOW-PASS FILTER
0
1
0
1.0 MHz LOW-PASS FILTER
0
1
1
2.0 MHz LOW-PASS FILTER
1
0
0
RESERVED
1
0
1
CIF
1
1
0
QCIF
1
1
1
RESERVED
MR03
MR02
MR01
MR00
OUTPUT VIDEO
STANDARD SELECTION
MR01 MR00
0
0
NTSC
0
1
PAL (B, D, G, H, and I)
1
0
PAL (M)
1
1
RESERVED
LUMA FILTER SELECT
MR04 MR03 MR02
0
0
0
LOW-PASS FILTER (NTSC)
0
0
1
LOW-PASS FILTER (PAL)
0
1
0
NOTCH FILTER (NTSC)
0
0
1
NOTCH FILTER (PAL)
1
0
0
EXTENDED MODE
1
0
1
CIF
1
1
0
QCIF
1
1
1
RESERVED
02980-A-037
MR07
Figure 38. Mode Register 0
Table 9. MR0 Bit Description
Bit Name
Output Video Standard
Selection
Bit No.
MR01–MR00
Luminance Filter Control
MR02–MR04
Chrominance Filter Control
MR05–MR07
Description
These bits are used to set up the ENCODE mode. The ADV7174/ADV7179 can be set up to
output NTSC, PAL (B/D/G/H/I), and PAL (M and N) standard video.
PAL M is available on the ADV7174 only.
These bits specify which luminance filter is to be selected. The filter selection is made
independent of whether PAL or NTSC is selected.
These bits select the chrominance filter. A low-pass filter can be selected with a choice of
cutoff frequencies 0.65 MHz, 1.0 MHz, 1.3 MHz, or 2 MHz, along with a choice of CIF or QCIF
filters.
Rev. B | Page 28 of 52
ADV7174/ADV7179
MODE REGISTER 1 (MR1)
Bits:
Address:
MR17–MR10
SR4–SR0 = 01H
Figure 39 shows the various operations under the control of Mode Register 1. This register can be read from as well as written to.
MR16
MR15
DAC A
CONTROL
NORMAL
POWER-DOWN
COLOR BAR
CONTROL
MR17
0
1
DISABLE
ENABLE
MR13
MR12
1 SHOULD BE
WRITTEN TO
THIS BIT
MR11
MR10
CLOSED CAPTIONING
FIELD SELECTION
RESERVED
MR16
0
1
MR14
MR12 MR11
0
0
1
1
0
1
0
1
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
DAC B
CONTROL
DAC C
CONTROL
INTERLACE
CONTROL
MR15
0
NORMAL
1
POWER-DOWN
MR13
0
NORMAL
1
POWER-DOWN
MR10
0
INTERLACED
1
NONINTERLACED
02980-A-039
MR17
Figure 39. Mode Register 1
Table 10. MR1 Bit Description
Bit Name
Interlace Control
Bit No.
MR10
Closed Captioning Field
Selection
DAC Control
MR12–MR11
Reserved
Color Bar Control
MR14
MR17
MR16–MR15
and MR13
Description
This bit is used to set up the output to interlaced or noninterlaced mode. Power-down mode
is relevant only when the part is in composite video mode.
These bits control the fields on which closed captioning data is displayed; closed captioning
information can be displayed on an odd field, even field, or both fields.
These bits can be used to power down the DACs. Power-down can be used to reduce the
power consumption of the ADV7174/ADV7179 if any of the DACs are not required in the
application.
A Logic 1 must be written to this register.
This bit can be used to generate and output an internal color bar test pattern. The color bar
configuration is 100/7.5/75/7.5 for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled, the ADV7174/ADV7179 is configured in a master timing mode.
Rev. B | Page 29 of 52
ADV7174/ADV7179
MODE REGISTER 2 (MR2)
Bits:
Address:
MR27–MR20
SR4–SR0 = 02H
Mode Register 2 is an 8-bit-wide register. Figure 40 shows the various operations under the control of Mode Register 2. This register can
be read from as well as written to.
MR25
MR23
CHROMINANCE
CONTROL
LOW POWER MODE
DISABLE
ENABLE
MR27
0
1
x
0
0
1
ENABLE BURST
DISABLE BURST
0
1
MR20
1
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
ENABLE RTC PIN
ACTIVE VIDEO LINE
DURATION
MR23
MR25
0
1
MR21
GENLOCK CONTROL
ENABLE COLOR
DISABLE COLOR
BURST
CONTROL
RESERVED
MR22
MR22 MR21
MR24
MR26
0
1
MR24
720 PIXELS
710 PIXELS/702 PIXELS
SQUARE PIXEL
CONTROL
MR20
0
1
DISABLE
ENABLE
02980-A-039
MR26
MR27
Figure 40. Mode Register 2
Table 11. MR2 Bit Description
Bit Name
Square Pixel Control
Bit No.
MR20
Genlock Control
MR22–MR21
Active Video Line Duration
MR23
Chrominance Control
Burst Control
Low Power Mode
MR24
MR25
MR26
Reserved
MR27
Description
This bit is used to set up square pixel mode. This is available in slave mode only. For NTSC, a
24.5454 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied.
These bits control the genlock feature of the ADV7174/ ADV7179. Setting MR21 to Logic 1
configures the SCRESET/RTC pin as an input. Setting MR22 to Logic 0 configures the
SCRESET/RTC pin as a subcarrier reset input. Therefore, the subcarrier will reset to Field 0
following a low-to-high transition on the SCRESET/RTC pin. Setting MR22 to Logic 1 configures
the SCRESET/RTC pin as a real-time control input.
This bit switches between two active video line durations. A 0 selects CCIR REC601 (720 pixels
PAL/NTSC), and a 1 selects ITU-R.BT470 standard for active video duration (710 pixels NTSC
and 702 pixels PAL).
This bit enables the color information to be switched on and off the video output.
This bit enables the burst information to be switched on and off the video output.
This bit enables the lower power mode of the ADV7174/ADV7179. This reduces the DAC
current by 45%.
A Logic 0 must be written to this bit.
Rev. B | Page 30 of 52
ADV7174/ADV7179
MODE REGISTER 3 (MR3)
Bits:
Address:
MR37–MR30
SR4–SR0 = 03H
Mode Register 3 is an 8-bit-wide register. Figure 41 shows the various operations under the control of Mode Register 3.
MR35
TTXREQ BIT
MODE CONTROL
MR34
0
1
NORMAL
BIT REQUEST
INPUT DEFAULT
COLOR
MR37
0
1
MR33
CHROMA OUTPUT
SELECT
MR36
0
1
MR34
DISABLE
ENABLE
DISABLE
ENABLE
VBI_OPEN
MR32
0
1
TELETEXT
ENABLE
MR35
0
1
MR31
MR32
DISABLE
ENABLE
MR30
MR30
MR31
RESERVED
DAC OUTPUT
MR33
DISABLE
ENABLE
0
1
DAC A
DAC B
DAC C
COMPOSITE
BLUE/COMP/Pb RED/CHROMA/Pr
GREEN/LUMA/Y BLUE/COMP/Pb RED/CHROMA/Pr
02980-A-040
MR36
MR37
Figure 41. Mode Register 3
Table 12. MR3 Bit Description
Bit Name
Revision Code
VBI Open
Bit No.
MR30–MR31
MR32
DAC Output
MR33
Chroma Output Select
MR34
Teletext Enable
TTXREQ Bit Mode Control
MR35
MR36
Input Default Color
MR37
Description
These bits are read-only and indicate the revision of the device.
This bit determines whether or not data in the vertical blanking interval (VBI) is output to
the analog outputs or blanked. VBI data insertion is not available in Slave Mode 0. Also,
when both BLANK input control and VBI open are enabled, BLANK input control has
priority, i.e., VBI data insertion will not work.
This bit is used to switch the DAC outputs from SCART to a EUROSCART configuration. A
complete list of all DAC output configurations is shown in Table 13.
With this active high bit it is possible to output an extra chrominance signal C, on DAC A
in any configuration that features a CVBS signal.
This bit must be set to 1 to enable Teletext data insertion on the TTX pin.
This bit enables switching of the Teletext request signal from a continuous high signal
(MR36 = 0) to a bitwise request signal (MR36 = 1).
This bit determines the default output color from the DACs for zero input pixel data (or
disconnected). A Logic 0 means that the color corresponding to 00000000 is displayed. A
Logic 1 forces the output color to black for 00000000 pixel input video data.
Table 13. DAC Output Configuration Matrix
MR34
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MR40
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MR41
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MR33
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC A
CVBS
Y
CVBS
Y
CVBS
G
CVBS
Y
C
Y
C
Y
C
G
C
Y
DAC B
CVBS
CVBS
CVBS
CVBS
B
B
Pb
Pb
CVBS
CVBS
CVBS
CVBS
B
B
Pb
Pb
DAC C
C
C
C
C
R
R
Pr
Pr
C
C
C
C
R
R
Pr
Pr
Rev. B | Page 31 of 52
CVBS: Composite Video Baseband Signal
Y: Luminance Component Signal (For YPbPr or Y/C Mode)
C: Chrominance Signal (For Y/C Mode)
Pb: ColorComponent Signal (For YPbPr Mode)
Pr: Color Component Signal (For YPbPr Mode)
R: RED Component Video (For RGB Mode)
G: GREEN Component Video (For RGB Mode)
B: BLUE Component Video (For RGB Mode)
Each DAC can be powered on or off individually
See MR1 Description and Figure 39.
ADV7174/ADV7179
MODE REGISTER 4 (MR4)
Bits:
Address:
MR47–MR40
SR4–SR0 = 04H
Mode Register 4 is an 8-bit-wide register. Figure 42 shows the various operations under the control of Mode Register 4.
SLEEP MODE
CONTROL
MR46
0
1
MR47
(0)
ZERO SHOULD
BE WRITTEN TO
THIS BIT
DISABLE
ENABLE
MR45
MR43
PEDESTAL
CONTROL
0
1
DISABLE
ENABLE
MR41
MR42
MR40
RGB SYNC
OUTPUT SELECT
MR42
MR44
ACTIVE VIDEO
FILTER CONTROL
MR45
0
1
MR44
PEDESTAL OFF
PEDESTAL ON
0
1
MR40
DISABLE
ENABLE
DISABLE
ENABLE
YC OUTPUT
RGB/YPbPr OUTPUT
RGB/YUV
CONTROL
VSYNC_3H
MR43
0
1
0
1
MR41
0
1
RGB OUTPUT
YPbPr OUTPUT
02980-A-041
MR46
MR47
Figure 42. Mode Register 4
Table 14. MR4 Bit Description
Bit Name
Output Select
RGB/YPbPr Control
RGB Sync
Bit No.
MR40
MR41
MR42
VSYNC_3H
MR43
Pedestal Control
MR44
Active Video Filter Control
MR45
Sleep Mode Control
MR46
Reserved
MR47
Description
This bit specifies if the part is in composite video or RGB/YPbPr mode.
This bit enables the output from the RGB DACs to be set to YPbPr output video standard.
This bit is used to set up the RGB outputs with the sync information encoded on all RGB
outputs.
When this bit is enabled (1) in slave mode, it is possible to drive the VSYNC active low
input for 2.5 lines in PAL mode and three lines in NTSC mode. When this bit is enabled in
master mode, the ADV7174/ADV7179 outputs an active low VSYNC signal for three lines
in NTSC mode and 2.5 lines in PAL mode.
This bit specifies whether a pedestal is to be generated on the NTSC composite video
signal. This bit is invalid if the ADV7174/ ADV7179 is configured in PAL mode.
This bit controls the filter mode applied outside the active video portion of the line. This
filter ensures that the sync rise and fall times are always on spec regardless of which luma
filter is selected. A Logic 1 enables this mode.
When this bit is set (1), sleep mode is enabled. With this mode enabled, the
ADV7174/ADV7179 power consumption is reduced to typically 200 nA. The I2C registers
can be written to and read from when the ADV7174/ADV7179 is in sleep mode. If MR46 is
set to a (0) when the device is in sleep mode, the ADV7174/ADV7179 comes out of sleep
mode and resumes normal operation. Also, if the RESET signal is applied during sleep
mode, the ADV7174/ADV7179 comes out of sleep mode and resumes normal operation.
A Logic 0 should be written to this bit.
Rev. B | Page 32 of 52
ADV7174/ADV7179
TIMING MODE REGISTER 0 (TR0)
Bits:
Address:
TR07–TR00
SR4–SR0 = 07H
Figure 43 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to.
TR06
TR05
TR04
TR03
TIMING
REGISTER RESET
TR03
0
1
PIXEL PORT
CONTROL
0
1
8 BIT
FORBIDDEN
TR01
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
SLAVE TIMING
MASTER TIMING
TIMING MODE
SELECTION
LUMA DELAY
0
1
0
1
TR00
0
1
ENABLE
DISABLE
TR05 TR04
0
0
1
1
TR00
MASTER/SLAVE
CONTROL
BLANK INPUT
CONTROL
TR07
TR06
TR02
TR02 TR01
0
0
1
1
0
1
0
1
MODE 0
MODE 1
MODE 2
MODE 3
02980-A-042
TR07
Figure 43. Timing Register 0
Table 15. TR0 Bit Description
Bit Name
Master/Slave Control
Timing Mode Selection
Bit No.
TR00
TR02–TR01
BLANK Input Control
Luma Delay
TR03
TR05–TR04
Pixel Port Control
TR06
Timing Register Reset
TR07
Description
This bit controls whether the ADV7174/ADV7179 is in master or slave mode.
These bits control the timing mode of the ADV7174/ADV7179. These modes are
described in more detail in the 3.3 V Timing Specifications table.
This bit controls whether the BLANK input is used when the part is in slave mode.
These bits control the addition of a luminance delay. Each bit represents a delay of
74 ns.
This bit is used to set the pixel port to accept 8-bit or YCrCb data on Pins P7–P0.
0 must be written here.
Toggling the TR07 from low to high and to low again resets the internal timing
counters. This bit should be toggled after power-up, reset, or changing to a new
timing mode.
Rev. B | Page 33 of 52
ADV7174/ADV7179
TIMING MODE REGISTER 1 (TR1)
Bits:
Address:
TR17–TR10
SR4–SR0 = 08H
Timing Register 1 is an 8-bit-wide register. Figure 44 shows the various operations under the control of Timing Register 1. This register
can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals.
TR17
TR16
TR15
HSYNC TO PIXEL
DATA ADJUST
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
TR17 TR16
0
0
1
1
0
1
0
1
TR14
TR15 TR14
0 × TPCLK
1 × TPCLK
2 × TPCLK
3 × TPCLK
x
x
0
1
TC
TB
TB + 32μs
TR13
TR12
TR11
HSYNC TO
FIELD/VSYNC DELAY
TR13 TR12
0
0
1
1
0
1
0
1
TB
0 × TPCLK
4 × TPCLK
8 × TPCLK
16 × TPCLK
TR10
HSYNC WIDTH
TA
TR11 TR10
0
0
1
1
0
1
0
1
1 × TPCLK
4 × TPCLK
16 × TPCLK
128 × TPCLK
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1
1
0
1
0
1
1 × TPCLK
4 × TPCLK
16 × TPCLK
128 × TPCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
LINE 313
LINE 314
TA
TB
TC
FIELD/VSYNC
02980-A-043
HSYNC
Figure 44. Timing Register 1
Table 16. TR1 Bit Description
Bit Name
HSYNC Width
HSYNC to FIELD/VSYNC
Delay
HSYNC to FIELD Rising
Edge Delay
VSYNC Width
Bit No.
TR11–TR10
TR13–TR12
Description
These bits adjust the HSYNC pulse width.
These bits adjust the position of the HSYNC output relative to the FIELD/VSYNC output.
TR15–TR14
HSYNC to Pixel Data Adjust
TR17–TR16
When the ADV7174/ADV7179 is in Timing Mode 1, these bits adjust the position of the HSYNC
output relative to the FIELD output rising edge.
When the ADV7174/ADV7179 is configured in Timing Mode 2, these bits adjust the VSYNC
pulse width.
This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb
components to be swapped. This adjustment is available in both master and slave timing modes.
TR15–TR14
Rev. B | Page 34 of 52
ADV7174/ADV7179
SUBCARRIER FREQUENCY REGISTERS 3–0
Bits:
Address:
FSC3–FSC0
SR4–SR00 = 09H–0CH
These 8-bit-wide registers are used to set up the subcarrier frequency. The value of these registers is calculated by using the following
equation:
No. of Subcarrier Frequency Values in One Line of Video Line 32
×2 *
No. of 27 MHz Clock Cycles in One Video Line
* Rounded to the nearest integer.
For example, in NTSC mode,
Subcarrier Frequency Value =
227.5 32
× 2 = 569408542 d = 21F 07 C1Eh
1716
Note that on power-up, FSC Register 0 is set to 16h. A value of 1E as derived above is recommended.
Program as
FSC Register 0: 1EH
FSC Register 2: 7CH
FSC Register 3: F0H
FSC Register 4: 21H
Figure 45 shows how the frequency is set up by the four registers.
SUBCARRIER
FREQUENCY
REG 3
FSC31
SUBCARRIER
FREQUENCY
REG 2
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17
FSC16
SUBCARRIER
FREQUENCY
REG 1
FSC15 FSC14 FSC13 FSC12
SUBCARRIER
FREQUENCY
REG 0
FSC7
FSC6
FSC5
FSC11 FSC10
FSC9
FSC8
FSC3
FSC1
FSC0
FSC4
FSC2
02980-A-044
FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
Figure 45. Subcarrier Frequency Register
SUBCARRIER PHASE REGISTER
Bits:
Address:
FP7–FP0
SR4–SR0 = 0DH
This 8-bit-wide register is used to set up the subcarrier phase. Each bit represents 1.41°. For normal operation, this register is set to 00H.
CLOSED CAPTIONING EVEN FIELD DATA REGISTERS 1–0
Bits:
Address:
CED15–CED0
SR4–SR0 = 0EH–0FH
BYTE 1
BYTE 0
CED15 CED14 CED13 CED12 CED11 CED10
CED7
CED6
CED5
CED4
CED3
CED2
CED9
CED1
CED0
Figure 46. Closed Captioning Extended Data Register
Rev. B | Page 35 of 52
CED8
002980-A-045
These 8-bit-wide registers are used to set up the closed captioning extended data bytes on even fields. Figure 46 shows how the high and
low bytes are set up in the registers.
ADV7174/ADV7179
CLOSED CAPTIONING ODD FIELD DATA REGISTERS 1–0
Bits:
Subaddress:
CCD15–CCD0
SR4–SR0 = 10H–11H
BYTE 1
BYTE 0
CCD15 CCD14 CCD13 CCD12 CCD11 CCD10
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD9
CCD1
CCD8
CCD0
002980-A-046
These 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. Figure 47 shows how the high and low bytes
are set up in the registers.
Figure 47. Closed Captioning Data Register
NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0
Bits:
Subaddress:
PCE15–PCE0, PCO15–PCO0/TXE15–TXE0, TXO15–TXO0
SR4–SR0 = 12H–15H
These 8-bit-wide registers are used to enable the NTSC pedestal/ PAL Teletext on a line-by-line basis in the vertical blanking interval for
both odd and even fields. Figure 48 and Figure 49 show the four control registers. A Logic 1 in any of the bits of these registers has the
effect of turning the pedestal off on the equivalent line when used in NTSC. A Logic 1 in any of the bits of these registers has the effect of
turning Teletext on the equivalent line when used in PAL.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 1/3
PCO7
PCO6
PCO5
PCO4
PCO3
PCO2
PCO1
PCO0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 1/3
PCO15 PCO14
PCO13 PCO12 PCO11 PCO10
PCO9
PCO8
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE7
PCE6
PCE5
PCE4
PCE3
PCE2
PCE1
PCE0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4
PCE15
PCE14
PCE13
PCE12
PCE11
PCE10
PCE9
PCE8
02980-A-047
FIELD 2/4
Figure 48. Pedestal Control Registers
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
FIELD 1/3
TXO7
TXO6
TXO5
TXO4
TXO3
TXO2
LINE 8 LINE 7
TXO1
TXO0
FIELD 2/4
TXO15
TXO10
TXO9
TXO8
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 8
LINE 7
TXE1
TXE0
TXE7
TXO14
TXE6
TXO13
TXE5
TXO12
TXE4
TXO11
TXE3
TXE2
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
FIELD 2/4
TXE15
TXE14
TXE13
TXE12
TXE11
TXE10
Figure 49. Teletext Control Registers
Rev. B | Page 36 of 52
TXE9
TXE8
02980-A-048
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
FIELD 1/3
ADV7174/ADV7179
TELETEXT REQUEST CONTROL REGISTER (TC07)
Bits:
Address:
TC07–TC00
SR4–SR0 = 19H
Teletext control register is an 8-bit-wide register (see Figure 50).
Table 17. Teletext Request Control Register
Bit Name
TTXREQ Rising Edge Control
Bit No.
TC07–TC04
TTXREQ Falling Edge Control
TC03–TC00
Description
These bits control the position of the rising edge of TTXREQ. It can be
programmed from 0 CLOCK cycles to a maximum of 15 CLOCK cycles (see
Figure 50).
These bits control the position of the falling edge of TTXREQ. It can be
programmed from zero CLOCK cycles to a max of 15 CLOCK cycles. This controls
the active window for Teletext data. Increasing this value reduces the amount of
Teletext bits below the default of 360. If Bits TC03–TC00 are 00H when Bits TC07–
TC04 are changed, the falling edge of TTXREQ tracks that of the rising edge, i.e.,
the time between the falling and rising edge remains constant (see Figure 49).
CGMS_WSS REGISTER 0 (C/W0)
Bits:
Address:
C/W07–C/W00
SR4–SR0 = 16H
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51 shows the operations under the control of this register.
TC05
TC04
TTXREQ RISING EDGE CONTROL
TC07 TC06 TC05 TC04
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
TC03
TC02
TC01
TC00
TTXREQ FALLING EDGE CONTROL
TC03 TC02 TC01 TC00
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
02980-A-049
TC06
TC07
Figure 50. Teletext Control Register
C/W06
WIDE SCREEN
SIGNAL CONTROL
C/W07
0
1
DISABLE
ENABLE
C/W05
C/W04
C/W03
CGMS ODD FIELD
CONTROL
C/W05
0
1
CGMS EVEN FIELD
CONTROL
C/W06
0
DISABLE
1
ENABLE
C/W02
C/W01
C/W00
C/W03 – C/W00
CGMS DATA BITS
DISABLE
ENABLE
CGMS CRC CHECK
CONTROL
C/W04
0
DISABLE
1
ENABLE
02980-A-050
C/W07
Figure 51. CGMS_WSS Register 0
Table 18. C/W0 Bit Description
Bit Name
CGMS Data Bits
Bit No.
C/W03–C/W00
CGMS CRC Check Control
C/W04
CGMS Odd Field Control
CGMS Even Field Control
WSS Control
C/W05
C/W06
C/W07
Description
These four data bits are the final four bits of the CGMS data output stream. Note it is
CGMS data ONLY in these bit positions, i.e., WSS data does not share this location.
When this bit is enabled (1), the last six bits of the CGMS data, i.e., the CRC check
sequence, are calculated internally by the ADV7174/ADV7179. If this bit is disabled (0), the
CRC values in the register are output to the CGMS data stream.
When this bit is set (1), CGMS is enabled for odd fields. Note this is only valid in NTSC mode.
When this bit is set (1), CGMS is enabled for even fields. Note this is only valid in NTSC mode.
When this bit is set (1), wide screen signaling is enabled. Note this is only valid in PAL mode.
Rev. B | Page 37 of 52
ADV7174/ADV7179
CGMS_WSS REGISTER 1 (C/W1)
Bits:
Address :
C/W17–C/W10
SR4–SR0 = 17H
CGMS_WSS Register 1 is an 8-bit-wide register. Figure 52 shows the operations under the control of this register.
C/W16
C/W15
C/W14
C/W13
C/W12
C/W17 – C/W16
C/W15 – C/W10
CGMS DATA BITS
CGMS/WSS DATA BITS
C/W11
C/W10
02980-A-051
C/W17
Figure 52. CGMS_WSS Register 1
Table 19. C/W1 Bit Description
Bit Name
CGMS/WSS Data Bits
Bit No.
C/W15–C/W10
CGMS Data Bits
C/W17–C/W16
Description
These bit locations are shared by CGMS data and WSS data. In NTSC mode, these bits
are CGMS data. In PAL mode, these bits are WSS data.
These bits are CGMS data bits only.
CGMS_WSS REGISTER 2 (C/W2)
Bits:
Address:
C/W27–C/W20
(SR4–SR00) = 18H
CGMS_WSS Register 2 is an 8-bit-wide register. Figure 53 shows the operations under the control of this register.
C/W26
C/W25
C/W24
C/W23
C/W22
C/W27 – C/W20
CGMS/WSS DATA BITS
C/W21
C/W20
02980-A-052
C/W27
Figure 53. CGMS_WSS Register 2
Table 20. C/W2 Bit Description
Bit Name
CGMS/WSS Data Bits
Bit No.
C/W27–C/W20
Description
These bit locations are shared by CGMS data and WSS data. In NTSC mode, these
bits are CGMS data. In PAL mode, these bits are WSS data.
Rev. B | Page 38 of 52
ADV7174/ADV7179
APPENDIX 1—BOARD DESIGN AND LAYOUT CONSIDERATIONS
POWER PLANES
The ADV7174/ADV7179 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be
applied to the system-level design so that high speed, accurate
performance is achieved. Figure 54 shows the analog interface
between the device and monitor.
The ADV7174/ADV7179 and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (VAA). This power plane should be connected to
the regular PCB power plane (VCC) at a single point through a
ferrite bead. This bead should be located within 3 inches of the
ADV7174/ADV7179.
The metallization gap separating the device power plane and
board power plane should be as narrow as possible to minimize
the obstruction to the flow of heat from the device into the
general board.
The layout should be optimized for lowest noise on the
ADV7174/ADV7179 power and ground lines by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and GND pins should be minimized to
reduce inductive ringing.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7174/ADV7179 power pins and voltage
reference circuitry.
GROUND PLANES
The ground plane should encompass all ADV7174/ADV7179
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7174/ADV7179, the analog output traces,
and all the digital signal traces leading up to the ADV7174/
ADV7179. The ground plane is the board’s common ground
plane.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane unless they can be
arranged so that the plane-to-plane noise is common mode.
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1μF
0.01μF
3.3 V (VAA)
3.3V (VAA)
L1
(FERRITE BEAD)
3.3 V (VAA)
33μF
10μF
0.1μF
0.1μF
23
COMP
30
VREF
3.3 V
(VCC)
GND
VAA
ADV7174/ADV7179
3–5, 35–39
3.3 V (VAA)
DAC C 24
P7–P0
75Ω
4kΩ
RESET
100nF
3.3 V (VCC)
UNUSED
INPUTS
SHOULD BE
GROUNDED
32
SCRESET/RTC
13
HSYNC
14
FIELD/VSYNC
DAC B 28
75Ω
DAC A 29
15 BLANK
100kΩ
5kΩ
20 RESET
TTX
TTXREQ
100Ω
3.3 V (VAA)
10kΩ
MPU BUS
SDATA 22
CLOCK
ALSB
RSET 31
GND
150Ω
16
02980-A-053
1
5kΩ
SCLOCK 21
33 TTXREQ
100kΩ
3.3 V (VCC)
100Ω
34 TTX
TELETEXT PULL-UP AND
PULL-DOWN RESISTORS
SHOULD ONLY BE USED
IF THESE PINS ARE NOT
CONNECTED
3.3 V (VCC)
75Ω
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
Figure 54. Recommended Analog Circuit Layout
Rev. B | Page 39 of 52
ADV7174/ADV7179
SUPPLY DECOUPLING
ANALOG SIGNAL INTERCONNECT
For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable
operation, to reduce the lead inductance. Best performance is
obtained with 0.1 μF ceramic capacitor decoupling. Each group
of VAA pins on the ADV7174/ADV7179 must have at least one
0.1 μF decoupling capacitor to GND. These capacitors should
be placed as close to the device as possible.
The ADV7174/ADV7179 should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
It is important to note that while the ADV7174/ADV7179
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to
reducing power supply noise and consider using a 3-terminal
voltage regulator for supplying power to the analog power
plane.
DIGITAL SIGNAL INTERCONNECT
The digital inputs to the ADV7174/ADV7179 should be
isolated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay the
analog power plane.
Due to the high clock rates involved, long clock lines to the
ADV7174/ADV7179 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC) and not to the
analog power plane.
D
CLOCK
The video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
For best performance, the outputs should each have a 75 Ω load
resistor connected to GND. These resistors should be placed as
close as possible to the ADV7174/ADV7179 to minimize
reflections.
The ADV7174/ADV7179 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
The circuit in Figure 55 can be used to generate a 13.5 MHz
waveform using the 27 MHz clock and the HSYNC pulse. This
waveform is guaranteed to produce the 13.5 MHz clock in
synchronization with the 27 MHz clock. This 13.5 MHz clock
can be used if the 13.5 MHz clock is required by the MPEG
decoder. This guarantees that the Cr and Cb pixel information
is input to the ADV7174/ADV7179 in the correct sequence.
Note that the exposed metal paddle on the bottom side of the
LFCSP package must be soldered to PCB ground for proper
heat dissipation and also for electrical noise and mechanical
strength benefits.
Q
D
CK
Q
13.5MHz
02980-A-054
CK
HSYNC
Figure 55. Circuit to Generate 13.5 MHz
Rev. B | Page 40 of 52
ADV7174/ADV7179
APPENDIX 2—CLOSED CAPTIONING
ADV7174/ADV7179. All pixel inputs are ignored during Lines
21 and 284. FCC Code of Federal Regulations (CFR) 47 Section
15.119 and EIA-608 describe the closed captioning information
for Lines 21 and 284.
The ADV7174/ADV7179 supports closed captioning, conforming to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and Line
284 of even fields.
The ADV7174/ADV7179 uses a single buffering method. This
means that the closed captioning buffer is only one byte deep,
therefore there will be no frame delay in outputting the closed
captioning data unlike other 2-byte deep buffering systems. The
data must be loaded at least one line before (Line 20 or Line 283)
it is outputted on Line 21 and Line 284. A typical implementation
of this method is to use VSYNC to interrupt a microprocessor,
which in turn loads the new data (two bytes) every field. If no
new data is required for transmission, you must insert zeros in
both the data registers; this is called nulling. It is also important
to load control codes, all of which are double bytes, on Line 21,
or a TV cannot recognize them. If you have a message such as
“Hello World,” which has an odd number of characters, it is
important to pad it out to an even number to get the end of the
caption 2-byte control code to land in the same field.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency-locked and phase-locked to the caption data. After
the clock run-in signal, the blanking level is held for 2 data bits
and is followed by a Logic 1 start bit. 16 bits of data follow the
start bit. These consist of two 8-bit bytes, 7 data bits, and 1 odd
parity bit. The data for these bytes is stored in closed captioning
Data Registers 0 and 1.
The ADV7174/ADV7179 also supports the extended closed
captioning operation, which is active during even fields, and is
encoded on scan Line 284. The data for this operation is stored
in closed captioning extended Data Registers 0 and 1.
All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are automatically generated by the
10.5 ± 0.25μs
12.91μs
7 CYCLES
OF 0.5035 MHz
(CLOCK RUN-IN)
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
50 IRE
D0–D6
P
A
R
I
T
Y
D0–D6
P
A
R
I
T
Y
BYTE 1
BYTE 0
40 IRE
10.003μs
33.764μs
27.382μs
Figure 56. Closed Captioning Waveform (NTSC)
Rev. B | Page 41 of 52
02980-A-055
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
ADV7174/ADV7179
APPENDIX 3—COPY GENERATION MANAGEMENT SYSTEM (CGMS)
C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2,
C/W23 = C3, C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27
= C7. If Bit C/W04 is set to a Logic 1, the last six bits, C19–C14,
which comprise the 6-bit CRC check sequence, are calculated
automatically on the ADV7174/ADV7179 based on the lower
14 bits (C0–C13) of the data in the data registers and output
with the remaining 14 bits to form the complete 20 bits of the
CGMS data. The calculation of the CRC sequence is based on
the polynomial X6 + X + 1 with a preset value of 111111. If
C/W04 is set to a Logic 0, all 20 bits (C0–C19) are directly
output from the CGMS registers (no CRC is calculated; it must
be calculated by the user).
The ADV7174/ADV7179 supports the CGMS, conforming to
the standard. CGMS data is transmitted on Line 20 of the odd
fields and on Line 283 of the even fields. Bits C/W05 and
C/W06 control whether or not CGMS data is output on odd
and even fields. CGMS data can only be transmitted when the
ADV7174/ ADV7179 is configured in NTSC mode. The CGMS
data is 20 bits long, the function of each of these bits is as shown
below. The CGMS data is preceded by a reference pulse of the
same amplitude and duration as a CGMS bit (see Figure 57).
The bits are output from the configuration registers in the
following order: C/W00 = C16, C/W01 = C17, C/W02 = C18,
C/W03 = C19, C/W10 = C8, C/ W11 = C9, C/W12 = C10,
C/W13 = C11, C/W14 = C12, C/ W15 = C13, C/W16 = C14,
FUNCTION OF CGMS BITS
Word 0 –6 Bits
Word 1 –4 Bits
Word 2 –4 Bits
CRC –6 Bits CRC Polynomial = X6 + X + 1 (Preset to 111111)
Table 21. Bit 1–Bit 14
Word 1
Word 2
Bit
Function
B1
B2
B3
B4, B5, B6
B7, B8, B9, B10
B11, B12, B13, B14
1
0
Aspect Ratio
16:9
4:3
Display Format
Letterbox
Normal
Undefined
Identification information about video and other signals, for example, audio
Identification signal incidental to Word 0
Identification signal and information incidental to Word 0
100 IRE
CRC SEQUENCE
REF
70 IRE
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
49.1μs ± 0.5μs
–40 IRE
02980-A-056
Word
Word 0
11.2μs
2.235μs ± 20ns
Figure 57. CGMS Waveform Diagram
Rev. B | Page 42 of 52
ADV7174/ADV7179
APPENDIX 4—WIDE SCREEN SIGNALING (WSS)
The ADV7174/ADV7179 supports WSS, conforming to the
standard. WSS data is transmitted on Line 23. WSS data can
only be transmitted when the ADV7174/ ADV7179 is
configured in PAL mode. The WSS data is 14 bits long, the
function of each of these bits is as shown below. The WSS data
is preceded by a run-in sequence and a start code (see Figure 58).
The bits are output from the configuration registers in the
following order: C/W20 = W0, C/W21 = W1, C/W22 = W2,
C/W23 = W3, C/W24 = W4, C/W25 = W5, C/W26 = W6,
C/W27 = W7, C/W10 = W8, C/W11 = W9, C/W12 = W10,
C/W13 = W11, C/W14 = W12, C/W15 = W13. If the Bit
C/W07 is set to a Logic 1, it enables the WSS data to be
transmitted on Line 23. The latter portion of Line 23 (42.5 μs
from the falling edge of HSYNC) is available for the insertion of
video.
FUNCTION OF WSS BITS
Table 22. Bit 0–Bit 2 Bit 3 is the odd parity check of Bit 0–Bit 2
B0
0
B1
0
B2
0
B3
1
Aspect
Ratio
4:3
1
0
1
0
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
0
1
0
1
1
14:9
14:9
16:9
16:9
>16:9
14:9
1
1
1
0
16:9
Format
Full
Format
Letterbox
Letterbox
Letterbox
Letterbox
Letterbox
Full
Format
Not
Applicable
Position
Not
Applicable
Center
Top
Center
Top
Center
Center
Not
Applicable
Table 23. Bit 4–Bit 7
Bit
B4
B5
B6
B7
B8
B9–B10
B11
B12
B13
Value
0
1
0
1
0
1
0
1
0, 0
1, 0
0, 1
1, 1
0
1
Description
Camera Mode
Film Mode
Standard Coding
Motion Adaptive Color Plus
No Helper
Modulated Helper
Reserved
No Teletext Subtitles
Teletext Subtitles
No Open Subtitles
Subtitles in Active Image Area
Subtitles out of Active Image Area
Reserved
No Surround Sound Information
Surround Sound Mode
Reserved
Reserved
500mV
W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13
RUN-IN
SEQUENCE
START
CODE
ACTIVE
VIDEO
02980-A-057
11.0μs
38.4μs
42.5μs
Figure 58. WSS Waveform Diagram
Rev. B | Page 43 of 52
ADV7174/ADV7179
APPENDIX 5—TELETEXT
TELETEXT INSERTION
TELETEXT PROTOCOL
tPD is the time needed by the ADV7174/ADV7179 to interpolate
input data on TTX and insert it onto the CVBS or Y outputs,
such that it appears tSYNTTXOUT = 10.2 μs after the leading edge of
the horizontal signal. Time TTXDEL is the pipeline delay time by
the source that is gated by the TTXREQ signal in order to
deliver TTX data.
The relationship between the TTX bit clock (6.9375 MHz) and
the system clock (27 MHz) for 50 Hz is
With the programmability offered with the TTXREQ signal on
the rising/falling edges, the TTX data is always inserted at the
correct position of 10.2 μs after the leading edge of horizontal
sync pulse, thus enabling a source interface with variable pipeline delays.
Thus, 37 TTX bits correspond to 144 clocks (27 MHz) and each
bit has a width of almost four clock cycles. The ADV7174/
ADV7179 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a
band-limited signal that can be output on the CVBS and Y
outputs.
⎛ 27 MHz ⎞
⎜
4 ⎟ = 6.75 MHz
⎝
⎠
6.9375 × 106 6.75 × 106 = 1.027777
(
The width of the TTXREQ signal must always be maintained to
allow the insertion of 360 (to comply with the Teletext standard
PAL-WST) Teletext bits at a text data rate of 6.9375 Mbits/s.
This is achieved by setting TC03–TC00 to 0. The insertion
window is not open if the Teletext enable bit (MR35) is set to 0.
)
At the TTX input, the bit duration scheme repeats after every
37 TTX bits or 144 clock cycles. The protocol requires that TTX
Bits 10, 19, 28, and 37 are carried by three clock cycles and all
other bits by four clock cycles. After 37 TTX bits, the next bits
with three clock cycles are 47, 56, 65, and 74. This scheme holds
for all following cycles of 37 TTX bits until all 360 TTX bits are
completed. All Teletext lines are implemented in the same way.
Individual control of Teletext lines is controlled by Teletext
setup registers.
45 BYTES (360 BITS) – PAL
RUN-IN CLOCK
02980-A-058
ADDRESS AND DATA
TELETEXT VBI LINE
Figure 59. Teletext VBI Line
tSYNTTXOUT
CVBS/Y
tPD
tPD
HSYNC
10.2μs
TTXDATA
TTXDEL
TTXREQ
PROGRAMMABLE PULSE EDGES
tSYNTTXOUT = 10.2μs
tPD = PIPELINE DELAY THROUGH ADV7174/ADV7179
TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
Figure 60. Teletext Functionality
Rev. B | Page 44 of 52
02980-A-059
TTXST
ADV7174/ADV7179
APPENDIX 6—WAVEFORMS
NTSC WAVEFORMS (WITH PEDESTAL)
130.8 IRE
PEAK COMPOSITE
1268.1mV
100 IRE
REF WHITE
1048.4mV
BLACK LEVEL
BLANK LEVEL
387.6mV
334.2mV
–40 IRE
SYNC LEVEL
48.3mV
REF WHITE
1048.4mV
02980-A-060
714.2mV
7.5 IRE
0 IRE
Figure 61. NTSC Composite Video Levels
100 IRE
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
387.6mV
334.2mV
48.3mV
02980-A-061
714.2mV
Figure 62. NTSC Luma Video Levels
PEAK CHROMA
963.8mV
629.7mV (p-p)
286mV (p-p)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
02980-A-062
335.2mV
0mV
Figure 63. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
Figure 64. NTSC RGB Video Levels
Rev. B | Page 45 of 52
387.5mV
331.4mV
45.9mV
02980-A-063
720.8mV
ADV7174/ADV7179
NTSC WAVEFORMS (WITHOUT PEDESTAL)
130.8 IRE
PEAK COMPOSITE
1289.8mV
100 IRE
REF WHITE
1052.2mV
0 IRE
BLANK/BLACK LEVEL
338mV
–40 IRE
SYNC LEVEL
52.1mV
02980-A-064
714.2mV
Figure 65. NTSC Composite Video Levels
100 IRE
REF WHITE
1052.2mV
0 IRE
BLANK/BLACK LEVEL
SYNC LEVEL
–40 IRE
338mV
52.1mV
02980-A-065
714.2mV
Figure 66. NTSC Luma Video Levels
PEAK CHROMA
978mV
694.9mV (p-p)
286mV (p-p)
650mV
BLANK/BLACK LEVEL
PEAK CHROMA
02980-A-066
299.3mV
0mV
Figure 67. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
0 IRE
BLANK/BLACK LEVEL
SYNC LEVEL
–40 IRE
Figure 68. NTSC RGB Video Levels
Rev. B | Page 46 of 52
336.5mV
51mV
02980-A-067
715.7mV
ADV7174/ADV7179
PAL WAVEFORMS
1288.6mV
PEAK COMPOSITE
1051mV
REF WHITE
351mV
BLANK/BLACK LEVEL
51mV
SYNC LEVEL
02980-A-068
700mV
Figure 69. PAL Composite Video Levels
REF WHITE
1051mV
351mV
BLANK/BLACK LEVEL
51mV
SYNC LEVEL
02980-A-069
700mV
Figure 70. PAL Luma Video Levels
PEAK CHROMA
989.7mV
672mV (p-p)
300mV (p-p)
650mV
BLANK/BLACK LEVEL
PEAK CHROMA
02980-A-070
317.7mV
0mV
Figure 71. PAL Chroma Video Levels
REF WHITE
1051mV
351mV
BLANK/BLACK LEVEL
51mV
SYNC LEVEL
Figure 72. PAL RGB Video Levels
Rev. B | Page 47 of 52
02980-A-071
700mV
ADV7174/ADV7179
BLACK
BLUE
RED
MAGENTA
GREEN
+334mV
CYAN
WHITE
+505mV
YELLOW
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
YELLOW
Pb Pr WAVEFORMS
+505mV
+423mV
+171mV
BETACAM LEVEL
BETACAM LEVEL
+82mV
0mV
0mV
0mV
0mV
–82mV
–171mV
–05mV
–423mV
–505mV
Figure 76. NTSC 100% Color Bars, No Pedestal Pr Levels
BLACK
BLUE
RED
MAGENTA
GREEN
+309mV
CYAN
WHITE
+467mV
YELLOW
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
Figure 73. NTSC 100% Color Bars, No Pedestal Pb Levels
WHITE
02980-A-075
02980-A-072
–334mV
+467mV
+391mV
+158mV
BETACAM LEVEL
BETACAM LEVEL
+76mV
0mV
0mV
0mV
0mV
–76mV
–158mV
–391mV
–467mV
BLACK
BLUE
RED
MAGENTA
+232mV
CYAN
WHITE
+350mV
GREEN
Figure 77. NTSC 100% Color Bars with Pedestal Pr Levels
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Figure 74. NTSC 100% Color Bars with Pedestal Pb Levels
YELLOW
–467mV
02980-A-076
02980-A-073
–309mV
+350mV
+293mV
+118mV
SMPTE LEVEL
SMPTE LEVEL
+57mV
0mV
0mV
0mV
0mV
–57mV
–118mV
–293mV
–350mV
Figure 75. PAL 100% Color Bars, Pb Levels
Figure 78. PAL 100% Color Bars, Pr Levels
Rev. B | Page 48 of 52
02980-A-077
–350mV
02980-A-074
–232mV
ADV7174/ADV7179
APPENDIX 7—OPTIONAL OUTPUT FILTER
22pF
0
10
20
MAGNITUDE (dB)
If an output filter is required for the CVBS, Y, UV, chroma, and
RGB outputs of the ADV7174/ADV7179, the filter shown in
Figure 79 can be used. Plots of the filter characteristics are
shown in Figure 80. An output filter is not required if the
outputs of the ADV7174/ADV7179 are connected to most
analog monitors or analog TVs. However, if the output signals
are applied to a system where sampling is used (e.g., digital
TVs), then a filter is required to prevent aliasing.
30
40
50
60
70
1.8μH
FILTER I/P
270pF
330pF
80
100k
Z0 = 75Ω
75Ω
02980-A-078
75Ω
02980-A-079
DISPLAY DEVICE
Figure 79. Output Filter
Rev. B | Page 49 of 52
1M
10M
FREQUENCY (Hz)
Figure 80. Output Filter Plot
100M
ADV7174/ADV7179
APPENDIX 8—RECOMMENDED REGISTER VALUES
The ADV7174/ADV7179 registers can be set depending on the
user standard required. The power-on reset values can be found
in Figure 37.
The following examples give the various register formats for
several video standards. In each case, the output is set to composite output with all DACs powered up and with the input control
disabled. Additionally, the burst and BLANK color information
is enabled on the output, and the internal color bar generator is
Table 24. PAL B/D/G/H/I (FSC = 4.43361875 MHz)
Address
00H
01H
02H
03H
04H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
Description
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Telext Request Control Register
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
switched off. In the examples shown, the timing mode is set to
Mode 0 in slave format. TR02–TR00 of the Timing Register 0
control the timing modes. For a detailed explanation of each bit
in the command registers, refer to the Register Programming
section. TR07 should be toggled after setting up a new timing
mode. Timing Register 1 provides additional control over the
position and duration of the timing signals. In the examples,
this register is programmed in default mode.
Table 25. PAL N (FSC = 4.43361875 MHz)
Data
05H
10H
00H
00H
00H
00H
00H
CBH
8AH
09H
2AH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Address
00H
01H
02H
03H
04H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
Rev. B | Page 50 of 52
Description
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
Data
05H
10H
00H
00H
00H
00H
00H
CBH
8AH
09H
2AH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
ADV7174/ADV7179
Table 27. NTSC (FSC = 3.5795454 MHz)
Table 26. PAL-60 (FSC = 4.43361875 MHz)
Address
00H
01H
02H
03H
04H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
Description
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
Data
04H
10H
00H
00H
00H
00H
00H
CBH
8AH
09H
2AH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Address
00H
01H
02H
03H
04H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1
Description
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
Data
00H
10H
00H
00H
10H
00H
00H
1EH 1
7CH
F0H
21H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
On power-up, this register is set to 16h. 1Eh should be written here for
correct FSC.
Rev. B | Page 51 of 52
ADV7174/ADV7179
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
5.75
BSC SQ
0.50
0.40
0.30
12° MAX
1.00
0.85
0.80
PIN 1
INDICATOR
31
30
40
1
4.25
4.10 SQ
3.95
BOTTOM
VIEW
21
20
10
11
0.25 MIN
4.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 81. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
Note that the exposed metal paddle on the bottom side of the LFCSP package must be soldered to PCB ground for proper heat dissipation
and also for noise and mechanical strength benefits.
ORDERING GUIDE
Model
ADV7179KCP1
ADV7179KCP-REEL1
ADV7179KCPZ2
ADV7179KCPZ-REEL2
ADV7179BCP1
ADV7179BCP-REEL1
ADV7179BCPZ2
ADV7179BCPZ-REEL2
ADV7179WBCPZ2, 3
ADV7179WBCPZ–REEL2, 3
ADV7174KCP1
ADV7174KCP-REEL1
ADV7174KCPZ2
ADV7174KCPZ-REEL2
ADV7174BCP1
ADV7174BCP-REEL1
ADV7174BCPZ2
ADV7174BCPZ-REEL2
ADV7174WBCPZ2, 3
ADV7174WBCPZ-REEL2, 3
EVAL-ADV7179EBZ2
EVAL-ADV7174EBZ2
1
2
3
Temperature Range
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Evaluation Board
Package Option
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
Not recommended for new designs.
Z = RoHS Compliant Part.
Automotive product.
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Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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D02980-0-4/09(B)
Rev. B | Page 52 of 52