TI CC8520RHAR 2.4 ghz rf soc for wireless digital audio streaming cc8520 - purepathâ ¢ wireless Datasheet

CC8520
www.ti.com
SWRS091A – MARCH 2010
2.4 GHz RF SoC FOR WIRELESS DIGITAL AUDIO STREAMING
CC8520 - PurePath™ Wireless
APPLICATIONS
- Wireless high-quality digital audio
- Wireless point-to-point audio link
- Wireless headphones
- Wireless loudspeakers
-
FEATURES
Built-in audio protocol
- CD-quality uncompressed audio
- Excellent robustness and co-existence
through multiple techniques
- Adaptive Frequency Hopping
- Forward Error Correction
- Buffering and Retransmission
- Error Concealment
- Optional
high
quality
audio
compression
Digital audio support
- Digital I2S audio interface supports 1 or 2
audio channels at sample rates of 32,
40.275, 44.1 and 48 kHz, and supports 16 bit
word-widths
- Audio latency down to 20 ms
- Data side-channel allows data to be sent
alongside the audio between external host
controllers
External system
- Seamless connection and control of
selected TI audio codecs, DACs/ADCs and
digital audio amplifiers using I2S and I2C
- HID functions like power control, binding,
volume control, audio channel selection
can be mapped to I/Os
- RoHS compliant 6mm x 6mm QFN-40
package
Suited for systems targeting compliance
with
worldwide
radio
frequency
regulations: ETSI EN 300 328 and EN
300 440 class 2 (Europe), FCC CFR47 Part
15 (US) and ARIB STD-T66 (Japan)
Development tools
- PC-based PurePath™ Wireless
Configurator (PPW Configurator) for
CC8520 configuration
- CC8520 User’s Guide
- CC85XXDK audio development kit
- No software development needed
RF section
- 5 Mbps over-the-air data rate
- Bandwidth-efficient modulation format
- Excellent link budget with programmable
output power up to +3.5 dBm and -83 dBm
sensitivity
- Seamless support for CC2590 range
extender (+11dBm output power, -86dBm
sensitivity)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath™ is a trademark for Texas Instruments
All other trademarks are the property of their respective owners.
Copyright © 2010, Texas Instruments Incorporated
CC8520
WWW.TI.COM
SWRS091A – MARCH 2010
31
32
SCL
A
R VD
BI D
AS
33
SDA
XLNAEN
34
36
IOVDD
GIO12
37
XPAEN
35
38
DCPL
GIO13
39
D
VD TN
D AN
X
The PurePath™ Wireless platform is a costeffective and low-power solution optimized for
wireless transmission of high-quality digital audio.
40
QFN-40 PACKAGE (TOP VIEW)
DESCRIPTION
AD1
IOVDD
GIO9
18
19
20
WCLK
15
17
BCLK
14
AD0
MCLK
13
16
IOVDD
12
XI VDD
A
The CC8520 operates autonomously, and can be
used with or without an external MCU. An external
host processor can be connected through SPI and
control some aspects of its operation. The CC8520
interfaces easily with other TI audio ICs and DSPs
(using I2S and DSP/TDM interfaces).
IO
R VD
ST D
11 N
The CC8520 includes a robust built-in wireless
audio transmission protocol and can control
selected external audio devices. Utilizing
numerous coexistence mechanisms allows the
CC8520 to avoid interfering with, or being
interfered by other 2.4 GHz radio systems. The
CC8520, which supports 2 audio channels, is the
first device in the PurePath™ Wireless platform.
ABBREVIATIONS
2
ADC
Analog to Digital Converter
LAN
Local Area Network
ARIB
Association of Radio Industries and Businesses
LED
Light Emitting Diode
BER
Bit Error Rate
LNA
Low Noise Amplifier
CODEC
Coder/Decoder
MISO
Master In Slave Out
DAC
Digital to Analog Converter
MOSI
Master Out Slave In
DRC
Dynamic Range Control
MCU
Microcontroller
DSP
Digital Signal Processor
PA
Power Amplifier
EHIF
External Host Interface
PCM
Pulse Code Modulation
ESD
Electro Static Discharge
PER
Packet Error Rate
ETSI
European Telecommunications Standard Institute
PLL
Phase Lock Loop
FCC
Federal Communications Commission
PM
Protocol Master
FEC
Forward Error Correction
PPW
PurePath™ Wireless
FSK
Frequency Shift Keying
PS
Protocol Slave
FW
Firmware
PWM
Pulse Width Modulation
HID
Human Interface Device
RoHS
Restriction of Hazardous Substances
I2C
Inter-Integrated Circuit (serial communications bus)
RF
Radio Frequency
I2S
Inter-IC Sound (serial bus for digital audio signals)
SPI
Serial Peripheral Interface
IEEE
Institute of Electrical and Electronics Engineers
SoC
System-on-Chip
ISM
Industrial, Scientific, Medical
STD
Standard
JEDEC
Joint Electron Device Engineering Council
TDM
Time-Division Multiplexing
Copyright © 2010, Texas Instruments Incorporated
CC8520
WWW.TI.COM
SWRS091A – MARCH 2010
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ABSOLUTE MAXIMUM RATINGS(1)
PARAMETER
TEST CONDITIONS
Min
Max
Unit
Supply voltage
All supply pins must have the same voltage
–0.3
3.9
V
–0.3
min(VDD +
0.3, 3.9)
V
10
dBm
85
°C
According to IPC/JEDEC J-STD-020
260
°C
All pads, according to human-body model
(HBM), JEDEC STD 22, method A114
2000
V
According to charged-device model (CDM),
JEDEC STD 22, method C101E
400
V
Voltage on any digital pin
Input RF level
Storage temperature range
Reflow soldering temperature
ESD
(1)
(2)
-40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
CAUTION: ESD sensitive device. Precaution should be used when handing the device in order to prevent permanent damage.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
3
TEST CONDITIONS
Min
Max
Unit
Operating ambient temperature range, TA
-40
+85
°C
Operating supply voltage
2.0
3.6
V
Copyright © 2010, Texas Instruments Incorporated
CC8520
WWW.TI.COM
SWRS091A – MARCH 2010
GENERAL CHARACTERISTICS
Measured on Texas Instruments CC8520 EM reference designs with TA = 25°C and VDD = 3.3 V, unless otherwise noted.
PARAMETER
TEST CONDITION
RF frequency range
MIN
TYP
2400
MAX
UNIT
2483.5
MHz
Data rate
Shaped 8FSK
5
Mbps
Current consumption,
power down state
Voltage regulator / crystal oscillator off – status
lost (POWERED_DOWN state)
1
µA
Current consumption,
audio sink
Average current for audio sink with I2S interface
active and uncompressed stereo audio link at 48
kHz, 16 bits. (PCM16)
25
mA
29
mA
Average current for audio source with I2S
interface active and uncompressed stereo audio
link at 48 kHz, 16 bits, maximum output power.
(PCM16)
Latency between I2S interface on audio source
and I2S interface on audio sink. Uncompressed
16 bit. Audio latency is programmable using the
PPW Configurator [1].
Current consumption,
audio source
Audio latency
2048
48
44.1
40.275
32
Audio sample rate is programmable using the
(1)
PPW Configurator [1]
Audio sample rate
(1)
768
Samples
kHz
±2000ppm tolerance
RF CHARACTERISTICS, CC8520
Measured on Texas Instruments CC8520 EM reference designs with TA = 25°C and VDD = 3.3 V, unless otherwise noted.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Output power
Maximum output power setting
3.5
dBm
Receiver sensitivity
5 Mbps, 0.1 % BER
-83
dBm
Saturation (maximum input level)
5 Mbps, 0.1 % BER
-2
dBm
Adjacent channel, ±4MHz, wanted 3dB above
sensitivity
8
dB
Alternate channel, ±8MHz, wanted 3dB above
sensitivity
35
dB
99% energy bandwidth
3.8
Selectivity
Occupied bandwidth
MHz
(1)
Suitable for systems targeting compliance with EN 300 328, EN 300 440 , FCC CFR47 Part 15
and ARIB STD-T-66
Spurious emission
(1)
Systems with external antenna connector: Margins for passing conducted requirements at sub 1GHz frequencies can be improved by
using a simple band-pass filter connected between matching network and RF connector (1.6 pF in parallel with 1.6 nH); this filter must be
connected to a good RF ground.
48-MHz CRYSTAL REQUIREMENTS
General parameters with TA = 25°C and VDD = 3.3 V, unless otherwise noted.
PARAMETER
TEST CONDITION
MIN
Crystal frequency
Crystal frequency accuracy requirement
MAX
48
(1)
UNIT
MHz
-50
50
ppm
ESR Equivalent series resistance
-
60
ohm
C0 Crystal shunt capacitance
-
3
pF
CL Crystal load capacitance
15
17
pF
(1)
4
TYP
16
Including aging and temperature dependency
Copyright © 2010, Texas Instruments Incorporated
CC8520
WWW.TI.COM
SWRS091A – MARCH 2010
AUDIO PLL CHARACTERISTICS
TA = 25°C and VDD = 3.3 V, unless otherwise noted.
PARAMETER
TEST CONDITION
MCLK Frequency range
Programmable using the PPW Configurator [1]
32·FWCLK
MIN
512·FWCLK
BCLK Frequency range
Programmable using the PPW Configurator [1]
32·FWCLK
256·FWCLK
31.936
48.096
kHz
200
ps
WCLK Frequency range
RMS jitter
RMS period jitter for 1000 periods
80
MAX
UNIT
38
37
36
35
34
33
32
IOVDD
XLNAEN
GIO13
GIO12
SDA
SCL
MCLK
BCLK
WCLK
AD0
AD1
IOVDD
GIO9
13
14
15
16
17
18
19
20
A
R VD
BI D
AS
31
39
DCPL
XPAEN
IOVDD
12
D
VD TN
D AN
X
XI VDD
A
40
PIN DESCRIPTION
IO
R VD
ST D
11 N
1
TYP
Figure 1 - CC8520 QFN Package Top View
PIN
PIN NAME
PIN TYPE
DESCRIPTION
-
GND
Ground
The exposed die attach pad must be connected to a solid ground plane underneath the
chip
1
XANTN
Digital I/O
1
FW2.0: Controlling external antenna switch (FW1.0/FW1.1: NC)
1
2
XANTP
Digital I/O
FW2.0: Controlling external antenna switch (FW1.0/FW1.1: NC)
3
CS_N
Digital Input
(pull-up)
Serial SPI configuration interface, active low chip select
4
SCLK
Digital I/O
5
MOSI
6
MISO
1
Serial SPI configuration interface, clock input/output
1
Serial SPI configuration interface, master data input, slave data output
Digital I/O
1
Digital I/O
General-purpose digital I/O pin 0
GIO0
7
GIO1
Serial SPI configuration interface, master data output, slave data input GIO0 output when
CS_N is deasserted.
1
Digital I/O
General-purpose digital I/O pin 1
Configurable with PurePath™ Wireless Configurator
8
9
GIO2
GIO3
1
Digital I/O
2
Digital I/O
General-purpose digital I/O pin 2
General-purpose digital I/O pin 3
Configurable with PurePath™ Wireless Configurator
5
Copyright © 2010, Texas Instruments Incorporated
CC8520
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SWRS091A – MARCH 2010
PIN
PIN NAME
PIN TYPE
DESCRIPTION
10
IODVDD
Power
(I/O pads)
Digital power supply for the digital I/Os in the SPI interface and GIO1-GIO3.
11
RSTN
Digital Input
(pull-up)
Active-low device reset
12
IOVDD
Power
(I/O pins)
Digital power supply for the RSTN and MCLK digital I/O pins.
13
MCLK
Digital I/O
1
GIO4
14
BCLK
General-purpose digital I/O pin 4
1
Digital I/O
GIO5
15
WCLK
AD0
Digital I/O
AD1
I2S/DSP audio interface word clock (in/out)
General-purpose digital I/O pin 6
1
Digital I/O
GIO7
17
I2S/DSP audio interface bit clock (in/out)
General-purpose digital I/O pin 5
1
GIO6
16
Master clock output for external audio devices
I2S/DSP audio interface data line 0 (in/out)
General-purpose digital I/O pin 7
1
Digital I/O
I2S/DSP audio interface data line 1 (in/out)
General-purpose digital I/O pin 8
GIO8
18
IOVDD
Power
(I/O pins)
Digital power supply for the digital I/Os in audio interface (BCLK-AD2).
19
AD2
Digital I/O
2
I2S/DSP audio interface data line 2 (in/out)
Configurable with PurePath™ Wireless Configurator
GIO9
20
AVDD
Power (Analog)
2.0-3.6V analog power supply connection
21
XI
Analog I/O
Crystal oscillator pin input, or external clock input (48 MHz)
22
XO
Analog I/O
Crystal oscillator pin output (48 MHz)
23
AVDD
Power (Analog)
Analog power supply connection
24
RF_P
RF I/O
Positive differential RF input signal to LNA in receive mode
Positive differential RF output signal from PA in transmit mode
25
RF_N
RF I/O
Negative differential RF input signal to LNA in receive mode
Negative differential RF output signal from PA in transmit mode
26
AVDD
Power (Analog)
Analog power supply connection
27
AVDD
Power (Analog)
Analog power supply connection
28
AVDD
Power (Analog)
Analog power supply connection
29
VBAT
Analog input
Battery voltage supervisor (threshold level programmable by external resistor to positive
battery terminal)
30
RBIAS
Analog output
External precision bias resistor for reference current. 56 kΩ, ±1%
31
AVDD
Power (Analog)
Analog power supply connection (Guard ring AVDD connection for digital noise isolation)
32
SCL
1
Digital I/O
GIO10
33
SDA
General-purpose digital I/O pin 10
1
Digital I/O
GIO11
34
35
GIO13
I2C master data line. Must be connected to external pull-up
General-purpose digital I/O pin 11
1
General-purpose digital I/O pin 12
1
General-purpose digital I/O pin 13
2
Digital I/O
Digital I/O
36
XLNAEN
Digital I/O
Control external LNA
37
IODVDD
Power (I/O pads)
Digital power supply for SCL-GIO15 pins.
38
6
GIO12
I2C master clock line. Must be connected to external pull-up
XPAEN
2
Digital I/O
Control external PA
Copyright © 2010, Texas Instruments Incorporated
CC8520
WWW.TI.COM
SWRS091A – MARCH 2010
PIN
PIN NAME
PIN TYPE
DESCRIPTION
39
DCPL
Power (Digital)
1.7V-1.85 V linear voltage regulator output to which a 1 uF decoupling capacitor should be
attached. For test-purposes an external digital supply voltage (1.62-1.98 V) can be applied
here, bypassing the voltage regulator.
NOTE: The voltage regulator is intended for use with the CC8520 chip only. It cannot be
used to provide supply voltage to other devices.
40
1
2
DVDD
Power (Digital)
Digital power supply for the linear voltage regulator.
Digital I/O pad with 4 mA source/sink capability, programmable direction and pull-up, pull-down or high-impedance.
Digital I/O pad with 20 mA source/sink capability, programmable direction and pull-up, pull-down or high-impedance.
2.0V-3.6V
Power Supply
R101
RBIAS
30
xANTP
VBAT
29
CSN
AVDD
28
4
SCLK
AVDD
27
5
MOSI
AVDD
26
6
MISO
RF_N
25
7
GIO1
RF_P
24
8
GIO2
AVDD
23
9
GIO3
X0
10
IOVDD
X1
22
21
IOVDD
MCLK
BCLK
WCLK
AD0
AD1
IOVDD
GIO9/
AD2
AVDD
12
13
14
15
16
17
18
19
20
Antenna
(50 Ohm)
C301
C306
L302
L303
C305
L304
C302
L301
C303
C401
RSTN
CC8520
Antenna
(50 Ohm)
Alternative:
CC2590 External LNA/PA
C402
32
SCL
AVDD 31
SDA 33
GIOI2 34
36
GIOI3 35
DCPL 39
CC2590 +
Matching/
Filtering
XTAL
3
IOVDD 37
2
xPAEN
xANTM
11
Audio Device
1
xLNAEN 38
DVDD 40
C391
Figure 2 - CC8520 Application Circuit
7
Copyright © 2010, Texas Instruments Incorporated
CC8520
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2
SWRS091A – MARCH 2010
SYSTEM DESCRIPTION
The CC8520 is a 2.4GHz wireless SoC operating in the 2.4 GHz ISM band designed for streaming digital
audio wirelessly. It is designated to operate autonomously (without any host MCU) but certain aspects of
operation can be controlled by a host MCU.
Before operation, the CC8520 must be programmed with a user-specific FW image, which can be created
using the PPW Configurator [1]. The configuration file can be programmed into the on-chip Flash memory by
using the PPW Configurator and the CC Debugger [2] and is also programmable in a production line. The
configuration image contains information identifying the device as a master or a slave, how many channels are
supported, the direction of the audio channels, HID support, audio device supported and more.
If CC8520 is configured as a slave, it will automatically start searching for a valid audio network. If configured
as a master, it will start a new network. As soon as a network is formed, audio transmission will commence.
The CC8520 will automatically configure an attached supported audio IC (see compatibility list for a list of
supported ICs in chapter 3).
3
SUPPORTED AUDIO DEVICES
Supported ADC/DAC/Codec/Amplifier Devices
The following device drivers will initially be implemented:
Device
DESCRIPTION
Low-Power Stereo Codec with 6 Inputs, 6 Outputs,
Speaker/HP Amp and Enhanced Digital Effects
Low-Power Stereo CODEC with 6 Inputs, 6 Outputs, HP Amp
AIC3104
and Enhanced Digital Effects
ADC3101
92dB SNR Low-Power Stereo ADC with Digital Mic Support
AIC3204: Very Low-Power Stereo Audio CODEC with Power
AIC3204
Tune™ Technology
Note: The complete list of supported devices can be found in the PPW Configurator [1].
AIC3101
Supported SPDIF-RX / SPDIF-TX / DSP Devices
The following device drivers will be implemented:
Device
DESCRIPTION
DIR9001
96 kHz, 24-Bit Digital Audio Interface Receiver
DIT4096
96 kHz, Digital Audio Transmitter
DSP
Generic Digital Audio Device
Note: The complete list of supported devices can be found in the PPW Configurator [1].
Other audio devices
The CC8520 is compatible with any I2S-based audio device that does not need to be configured at power-up
and that is compatible with the requirements listed in the audio interface (Chapter 6). It is also compatible with
a wide range of TI DSPs using an I2S interface.
8
Copyright © 2010, Texas Instruments Incorporated
CC8520
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4
SWRS091A – MARCH 2010
NETWORK TOPOLOGY AND NOMENCLATURE
A CC8520 network consists of one Protocol Master (PM) and one or two Protocol Slave(s) (PS). The PM
provides the audio reference clock and controls network association. The PS regenerate the audio reference
clock based on the packets received. Audio can be transmitted from the PM to a PS. The device receiving the
audio is called an Audio Sink, the device sending the audio is called an Audio Source. A device can be both
Audio Sink and Audio Source at the same time (bidirectional audio will be supported in future revisions of the
firmware). The CC8520 network also includes a Data Side-Channel which is a bi-directional data link between
the PM and all PS in the network. This is further described in chapter 8.
Figure 3 illustrates the different network topologies that can be formed with CC8520 using the different
firmware versions.
Audio channel
PM
FW1.0
FW1.0
PM
PS
PS
Data channel
2 audio channels:
stereo audio PM to PS
1 audio channel:
mono audio PM to PS
PS1
FW1.1
PM
PS1
PM
PS2
PS2
2 channels:
mono audio PM to PS1
mono audio PM to PS2
2 channels:
mono audio PS1 to PM
mono audio PS2 to PM
FW2.0
PM
FW1.1
FW2.0
PS1
PS
PM
PS2
2 channels:
mono audio PM to PS
mono audio PS to PM
2 channels:
mono audio PM to PS1
mono audio PS2 to PM
Figure 3 CC8520 topologies supported for different CC8520 FW revisions
(Yellow arrow = audio channel. Blue arrow = data side channel. PM = Protocol Master. PS = Protocol Slave)
9
Copyright © 2010, Texas Instruments Incorporated
CC8520
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10
SWRS091A – MARCH 2010
Copyright © 2010, Texas Instruments Incorporated
CC8520
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5
SWRS091A – MARCH 2010
COEXISTENCE AND AUDIO COMPRESSION
The CC8520 implements a wide range of techniques to maximize coexistence performance when operating in
an environment with other 2.4 GHz wireless devices. The built-in protocol implements adaptive frequency
hopping. This helps improve coexistence with RF sources that do not move around in frequency, such as IEEE
802.11 (Wireless LAN) devices, as well as providing robust performance in a multipath RF environment. Audio
is buffered in the receiver, and any data which is not correctly received, is retransmitted utilizing the high raw
datarate (5Mbps). When link quality is poor (e.g. when moving out of range), audio is muted until a reliable link
is restored.
Forward Error Correction (FEC) is built into the CC8520 modulation scheme. Furthermore, packets are divided
into independent sections so that an error in one section does not mean the whole packet is lost.
The CC8520 supports uncompressed PCM16 audio, with no modifications made to the digital audio. High
quality audio compression can optionally be enabled and effectively reducing average current consumption by
lowering the radio duty-cycle. Compression improves robustness further, as there is less data sent and more
time available for retransmission.
6
AUDIO INTERFACE
The CC8520 audio interface is I2S compatible and it supports up to 2 audio channels. The audio interface on
the protocol master can be configured as clock master (supplied from the internal audio PLL) or as clock slave
(clock supplied from external audio IC).
The audio interface has 2 data pins. Each of these can be configured as an input, output or unused. The audio
interface can be configured to support I2S. The CC8520 supports word widths of 16 to 24 bits, but over-the-air
16 bits is always used.
7
HUMAN INTERACTION DRIVERS (HID)
The CC8520 supports basic HID functionality without an external MCU. This means that some basic
functionality can be controlled on the slave remotely from the master. The HID functionality supported
includes:
- power control (to turn devices on/off)
- network binding (to pair devices)
- volume control (volume control can be managed locally)
- Status LED (blinking diode to indicate the status of the RF link)
All HID functions are configurable in the PPW Configurator [1] and can be mapped to the CC8520 I/O pins.
8
EXTERNAL HOST INTERFACE (EHIF / Data side channel)
The external host interface (EHIF) allows an external host device, e.g. a microcontroller, to:
•
Control the operation of and poll status from the CC8520, mainly by taking over driver functionality.
•
Communicate with other external host devices through an integrated data side-channel
•
Get access to test functionality for audio, I/O and RF.
The external host interface is available via SPI with a single interrupt pin. The external host will act as SPI
master and CC8520 will act as SPI slave.
User specified data can be transferred between the master EHIF and the slave EHIFs, in both directions using
the data side-channel. The data side-channel establishes robust, ensured-delivery connections in both
directions from any slave to the master or from master to any slave (direct slave to slave communication is not
11
Copyright © 2010, Texas Instruments Incorporated
CC8520
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SWRS091A – MARCH 2010
available). There is no specified minimum throughput for the data side-channel but under normal operating
conditions and data rate of up to 30 kbps is possible in each direction.
More details can be found in the CC8520 User’s Guide [2].
9
REFERENCES
[1] PurePath™ Wireless Configurator
[2] CC8520 product folder
[3] CC-Debugger
12
Copyright © 2010, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
5-Apr-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CC8520RHAR
ACTIVE
VQFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CC8520RHAT
ACTIVE
VQFN
RHA
40
250
CU NIPDAU
Level-3-260C-168 HR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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