ISL6752 ® Data Sheet April 4, 2006 ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control The ISL6752 is a high-performance, low-pin-count alternative zero-voltage switching (ZVS) full-bridge PWM controller. Like Intersil’s ISL6551, it achieves ZVS operation by driving the upper bridge FETs at a fixed 50% duty cycle while the lower bridge FETs are trailing-edge modulated with adjustable resonant switching delays. Compared to the more familiar phase-shifted control method, this algorithm offers equivalent efficiency and improved overcurrent and lightload performance with less complexity in a lower pin count package. The ISL6752 features complemented PWM outputs for synchronous rectifier (SR) control. The complemented outputs may be dynamically advanced or delayed relative to the PWM outputs using an external control voltage. This advanced BiCMOS design features precision deadtime and resonant delay control, and an oscillator adjustable to 2MHz operating frequency. Additionally, Multi-Pulse Suppression ensures alternating output pulses at low duty cycles where pulse skipping may occur. Ordering Information PART NUMBER PART MARKING ISL6752AAZA ISL6752AAZ (Note) TEMP. RANGE (°C) Features • Adjustable Resonant Delay for ZVS Operation • Synchronous Rectifier Control Outputs with Adjustable Delay/Advance • Current-Mode Control • 3% Current Limit Threshold • Adjustable Deadtime Control • 175µA Startup Current • Supply UVLO • Adjustable Oscillator Frequency Up to 2MHz • Internal Over Temperature Protection • Buffered Oscillator Sawtooth Output • Fast Current Sense to Output Delay • Adjustable Cycle-by-Cycle Peak Current Limit • 70ns Leading Edge Blanking • Multi-Pulse Suppression • Pb-Free Plus Anneal Available (RoHS Compliant) • ELV, WEEE, and RoHS Compliant PACKAGE PKG. DWG. # -40 to 105 16 Ld QSOP M16.15A (Pb-free) Add -T suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Applications • ZVS Full-Bridge Converters • Telecom and Datacom Power • Wireless Base Station Power • File Server Power • Industrial Power Systems Pinout ISL6752 (QSOP) TOP VIEW VADJ 1 16 VDD VREF 2 15 OUTLL VERR 3 14 OUTLR CTBUF 4 13 OUTUL RTD 5 12 OUTUR RESDEL 6 11 OUTLLN CT 7 10 OUTLRN CS 8 1 FN9181.2 9 GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Functional Block Diagram VDD VDD VREF UVLO OUTUL 50% OUTUR 2 PWM STEERING LOGIC OVERTEMPERATURE PROTECTION DELAY/ ADVANCE TIMING CONTROL PWM OUTLL OUTLR OUTLLN GND OUTLRN VREF RESDEL VADJ ISL6752 CT OSCILLATOR + RTD - CS 1.00V 70ns LEADING EDGE BLANKING OVERCURRENT COMPARATOR CTBUF 80mV + PWM COMPARATOR 0.33 VREF 1mA VERR FN9181.2 April 4, 2006 Typical Application - High Voltage Input Primary Side Control ZVS Full-Bridge Converter VIN+ CR2 CR3 T3 Q2 R10 Q8A Q1 R11 Q8B Q5A Q5B C9 C8 3 + T1 C1 R12 400 VDC + Vout L1 Q12 C10 Q10A R1 Q9A C7 C15 Q9B Q10B + C12 Q13 R13 RETURN Q4 Q6A Q7A Q6B Q7B C13 Q3 R18 R17 R19 T2 CR1 R8 VDD VREF OUTLL VERR OUTLR CTBUF R2 R20 RTD R3 R16 R23 EL7212 C5 OUTUL C14 EL7212 T4 OUTUR RESDEL OUTLLN CT OUTLRN CS GND R7 R4 ISL6752 VADJ CR4 U5 U4 C11 U1 R15 R24 Q11 R23 R24 Q14 U3 VDD C3 C2 C17 U2 C4 R22 VR1 R21 R5 R6 R14 C16 C6 ISL6752 VIN- FN9181.2 April 4, 2006 Typical Application - High Voltage Input Secondary Side Control ZVS Full-Bridge Converter VIN+ T3 1:1:1 Q1 Q2 Q6 Q5 CR2 R13 CR3 T1 Np:Ns:Ns=9:2:2 R12 4 Ns R15 + Vout Np C10 Q10A L1 Q16 Ns Q9A C12 Q9B Q10B C14 C13 + + 400 VDC C1 R14 Q15 T4 1:1:1 Q4 Q3 CR5 CR4 Q7A C11 Q8A R10 Q7B Q8B R11 C8 RETURN C9 ISL6752 C7 Q11A Q12A Q12B Q11B Q13A VIN- Q13B VREF R7 VADJ T2 CR1 R8 OUTLL VERR OUTLR RTD ISL6752 VREF CTBUF R9 VDD OUTUL OUTLLN CT OUTLRN C17 C16 Q14B OUTUR RESDEL CS R1 R17 Q14A Q17 GND R6 U1 R16 C15 R18 SECONDARY BIAS SUPPLY R20 VREF U3 R22 C2 R5 R2 R3 C3 C4 C5 + R4 C6 R21 R19 C18 FN9181.2 April 4, 2006 ISL6752 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V OUTxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD Signal Pins . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF + 0.3V VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1A ESD Classification Human Body Model (Per MIL-STD-883 Method 3015.7) . . .3000V Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V Thermal Resistance Junction to Ambient (Typical) θJA (°C/W) 16 Lead QSOP (Note 1). . . . . . . . . . . . . . . . . . . . . . 95 Maximum Junction Temperature . . . . . . . . . . . . . . . . -55°C to 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (QSOP- Lead Tips Only) Operating Conditions Temperature Range ISL6752AAxx . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 105°C Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . 9-16 VDC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are with respect to GND. Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA = -40°C to 105°C (Note 3), Typical values are at TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - - 20 V SUPPLY VOLTAGE Supply Voltage Start-Up Current, IDD VDD = 5.0V - 175 400 µA Operating Current, IDD RLOAD, COUT = 0 - 11.0 15.5 mA UVLO START Threshold 8.00 8.75 9.00 V UVLO STOP Threshold 6.50 7.00 7.50 V - 1.75 - V 4.850 5.000 5.150 V - 3 - mV -10 - - mA 5 - - mA VREF = 4.85V -15 - -100 mA Current Limit Threshold VERR = VREF 0.97 1.00 1.03 V CS to OUT Delay Excl. LEB (Note 4) - 35 50 ns Leading Edge Blanking (LEB) Duration (Note 4) 50 70 100 ns CS to OUT Delay + LEB TA = 25°C - - 130 ns CS Sink Current Device Impedance VCS = 1.1V - - 20 Ω Input Bias Current VCS = 0.3V -6.00 - -2.00 µA CS to PWM Comparator Input Offset TA = 25°C 65 80 95 mV Hysteresis REFERENCE VOLTAGE Overall Accuracy IVREF = 0-10mA Long Term Stability TA = 125°C, 1000 hours (Note 4) Operational Current (source) Operational Current (sink) Current Limit CURRENT SENSE PULSE WIDTH MODULATOR VERR Pull-Up Current Source VERR = 2.50V 0.80 1.00 1.30 mA VERR VOH ILOAD = 0mA 4.20 - - V 5 FN9181.2 April 4, 2006 ISL6752 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA = -40°C to 105°C (Note 3), Typical values are at TA = 25°C (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Minimum Duty Cycle VERR < 0.6V - - 0 % Maximum Duty Cycle (per half-cycle) VERR = 4.20V, VCS = 0V (Note 5) - 94 - % RTD = 2.00kΩ, CT = 220pF - 97 - % RTD = 2.00kΩ, CT = 470pF - 99 - % 0.85 - 1.20 V 0.7 0.8 0.9 V 0.31 0.33 0.35 V/V (Note 4) 0 - 4.45 V (Note 4) 165 183 201 kHz -10 - 10 % Zero Duty Cycle VERR Voltage VERR to PWM Comparator Input Offset TA = 25°C VERR to PWM Comparator Input Gain Common Mode (CM) Input Range OSCILLATOR Frequency Accuracy, Overall Frequency Variation with VDD TA = 25°C, (F20V- - F10V)/F10V - 0.3 1.7 % Temperature Stability VDD = 10V, |F-40°C - F0°C|/F0°C - 4.5 - % |F0°C - F105°C|/F25°C (Note 4) - 1.5 - % -193 -200 -207 µA 19 20 23 µA/µA Charge Current TA = 25°C Discharge Current Gain CT Valley Voltage Static Threshold 0.75 0.80 0.88 V CT Peak Voltage Static Threshold 2.75 2.80 2.88 V CT Pk-Pk Voltage Static Value 1.92 2.00 2.05 V 1.97 2.00 2.03 V 0 - 2.00 V RTD Voltage RESDEL Voltage Range CTBUF Gain (VCTBUFp-p/VCTp-p) VCT = 0.8V, 2.6V 1.95 2.0 2.05 V/V CTBUF Offset from GND VCT = 0.8V 0.34 0.40 0.44 V CTBUF VOH ∆V(ILOAD = 0mA, ILOAD = -2mA), VCT = 2.6V - - 0.10 V CTBUF VOL ∆V(ILOAD = 2mA, ILOAD = 0mA), VCT = 0.8V - - 0.10 V High Level Output Voltage (VOH) IOUT = -10mA, VDD - VOH - 0.5 1.0 V Low Level Output Voltage (VOL) IOUT = 10mA, VOL - GND - 0.5 1.0 V Rise Time COUT = 220pF, VDD = 15V (Note 4) - 110 200 ns Fall Time COUT = 220pF, VDD = 15V (Note 4) - 90 150 ns UVLO Output Voltage Clamp VDD = 7V, ILOAD = 1mA (Note 6) - - 1.25 V Output Delay/Advance Range OUTLLN/OUTLRN relative to OUTLL/OUTLR VADJ = 2.50V (Note 4) - - 3 ns VADJ < 2.425V -40 - -300 ns VADJ > 2.575V 40 - 300 ns 2.575 - 5.000 V 0 - 2.425 V OUTPUT Delay/Advance Control Voltage Range OUTLLN/OUTLRN relative to OUTLL/OUTLR 6 OUTLxN Delayed OUTLxN Advanced FN9181.2 April 4, 2006 ISL6752 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, TA = -40°C to 105°C (Note 3), Typical values are at TA = 25°C (Continued) PARAMETER TEST CONDITIONS VADJ Delay Time MIN TYP MAX UNITS VADJ = 0 280 300 320 ns VADJ = 0.5V 92 105 118 ns VADJ = 1.0V 61 70 80 ns VADJ = 1.5V 48 55 65 ns VADJ = 2.0V 41 50 58 ns VADJ = VREF 280 300 320 ns VADJ = VREF - 0.5V 86 100 114 ns VADJ = VREF - 1.0V 59 68 77 ns VADJ = VREF - 1.5V 47 55 62 ns VADJ = VREF - 2.0V 41 48 55 ns TA = 25°C (OUTLx Delayed) TA = 25°C (OUTLxN Delayed) THERMAL PROTECTION Thermal Shutdown (Note 4) 130 140 150 °C Thermal Shutdown Clear (Note 4) 115 125 135 °C Hysteresis, Internal Protection (Note 4) - 15 - °C NOTES: 3. Specifications at -40°C and 105°C are guaranteed by 25°C test with margin limits. 4. Guaranteed by design, not 100% tested in production. 5. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained using other values for these components. See Equations 1 - 3. 6. Adjust VDD below the UVLO stop threshold prior to setting at 7V. Typical Performance Curves CT DISCHARGE CURRENT GAIN NORMALIZED VREF 1.02 1.01 1 0.99 0.98 -40 -25 -10 5 20 35 50 65 80 95 110 TEMPERATURE (°C) FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE 7 25 24 23 22 21 20 19 18 0 200 400 600 800 1000 RTD CURRENT (µA) FIGURE 2. CT DISCHARGE CURRENT GAIN vs RTD CURRENT FN9181.2 April 4, 2006 ISL6752 (Continued) DEADTIME TD (ns) 1-104 CT = 1000pF 680pF 470pF 330pF 220pF 1-103 100pF 100 10 0 10 20 30 40 50 60 RTD (kΩ) 70 80 90 100 FIGURE 3. DEADTIME (DT) vs CAPACITANCE Pin Descriptions VDD - VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. VDD is monitored for supply voltage undervoltage lock-out (UVLO). The start and stop thresholds track each other resulting in relatively constant hysteresis. GND - Signal and power ground connections for this device. Due to high peak currents and high frequency operation, a low impedance layout is necessary. Ground planes and short traces are highly recommended. VREF - The 5.00V reference voltage output having 3% tolerance over line, load and operating temperature. Bypass to GND with a 0.1µF to 2.2µF low ESR capacitor. CT - The oscillator timing capacitor is connected between this pin and GND. It is charged through an internal 200µA current source and discharged with a user adjustable current source controlled by RTD. RTD - This is the oscillator timing capacitor discharge current control pin. The current flowing in a resistor connected between this pin and GND determines the magnitude of the current that discharges CT. The CT discharge current is nominally 20x the resistor current. The PWM deadtime is determined by the timing capacitor discharge duration. The voltage at RTD is nominally 2.00V. CS - This is the input to the overcurrent comparator. The overcurrent comparator threshold is set at 1.00 V nominal. The CS pin is shorted to GND at the termination of either PWM output. Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal clock and the external power switch. This delay may result in CS being discharged prior to the power switching device being turned off. 8 1-103 FREQUENCY (kHz) Typical Performance Curves 100 10 0.1 RTD = 10kΩ 50kΩ 100kΩ 1 CT (nF) 10 FIGURE 4. CAPACITANCE vs FREQUENCY OUTUL and OUTUR - These outputs control the upper bridge FETs and operate at a fixed 50% duty cycle in alternate sequence. OUTUL controls the upper left FET and OUTUR controls the upper right FET. The left and right designation may be switched as long as they are switched in conjunction with the lower FET outputs, OUTLL and OUTLR. RESDEL - Sets the resonant delay period between the toggle of the upper FETs and the turn on of either of the lower FETs. The voltage applied to RESDEL determines when the upper FETs switch relative to a lower FET turning on. Varying the control voltage from 0 to 2.00V increases the resonant delay duration from 0 to 100% of the deadtime. The control voltage divided by 2 represents the percent of the deadtime equal to the resonant delay. In practice the maximum resonant delay must be set lower than 2.00V to ensure that the lower FETs, at maximum duty cycle, are OFF prior to the switching of the upper FETs. OUTLL and OUTLR - These outputs control the lower bridge FETs, are pulse width modulated, and operate in alternate sequence. OUTLL controls the lower left FET and OUTLR controls the lower right FET. The left and right designation may be switched as long as they are switched in conjunction with the upper FET outputs, OUTUL and OUTUR. OUTLLN and OUTLRN - These outputs are the complements of the PWM (lower) bridge FETs. OUTLLN is the complement of OUTLL and OUTLRN is the complement of OUTLR. These outputs are suitable for control of synchronous rectifiers. The phase relationship between each output and its complement is controlled by the voltage applied to VADJ. VADJ - A 0 - 5V control voltage applied to this input sets the relative delay or advance between OUTLL/OUTLR and OUTLLN/OUTLRN. The phase relationship between OUTUL/OUTUR and OUTLL/OUTLR is maintained regardless of the phase adjustment between OUTLL/OUTLR and OUTLLN/OUTLRN. FN9181.2 April 4, 2006 ISL6752 Voltages below 2.425V result in OUTLLN/OUTLRN being advanced relative to OUTLL/OUTLR. Voltages above 2.575V result in OUTLLN/OUTLRN being delayed relative to OUTLL/OUTLR. A voltage of 2.50V ±75mV results in zero phase difference. A weak internal 50% divider from VREF results in no phase delay if this input is left floating. The range of phase delay/advance is either zero or 40 to 300ns with the phase differential increasing as the voltage deviation from 2.5V increases. The relationship between the control voltage and phase differential is non-linear. The gain (∆t/∆V) is low for control voltages near 2.5V and rapidly increases as the voltage approaches the extremes of the control range. This behavior provides the user increased accuracy when selecting a shorter delay/advance duration. VERR - The control voltage input to the inverting input of the PWM comparator. The output of an external error amplifier (EA) is applied to this input, either directly or through an opto-coupler, for closed loop regulation. VERR has a nominal 1mA pull-up current source. CTBUF - CTBUF is the buffered output of the sawtooth oscillator waveform present on CT and is capable of sourcing 2mA. It is offset from ground by 0.40V and has a nominal valley-to-peak gain of 2. It may be used for slope compensation. Functional Description Features The switching period is the sum of the timing capacitor charge and discharge durations. The charge duration is determined by CT and a fixed 200µA internal current source. The discharge duration is determined by RTD and CT. 3 T C ≈ 11.5 ⋅ 10 ⋅ CT S (EQ. 1) T D ≈ ( 0.06 ⋅ RTD ⋅ CT ) + 50 ⋅ 10 1 T SW = T C + T D = -----------F SW S –9 S (EQ. 2) (EQ. 3) where TC and TD are the charge and discharge times, respectively, CT is the timing capacitor in Farads, RTD is the discharge programming resistance in ohms, TSW is the oscillator period, and FSW is the oscillator frequency. One output switching cycle requires two oscillator cycles. The actual times will be slightly longer than calculated due to internal propagation delays of approximately 10ns/transition. This delay adds directly to the switching duration, but also causes overshoot of the timing capacitor peak and valley voltage thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. Additionally, if very small discharge currents are used, there will be increased error due to the input impedance at the CT pin. The maximum recommended current through RTD is 1mA, which produces a CT discharge current of 20mA. The ISL6752 PWM is an excellent choice for low cost ZVS full-bridge applications requiring adjustable synchronous rectifier drive. With its many protection and control features, a highly flexible design with minimal external components is possible. Among its many features are a very accurate overcurrent limit threshold, thermal protection, a buffered sawtooth oscillator output suitable for slope compensation, synchronous rectifier outputs with variable delay/advance timing, and adjustable frequency. The maximum duty cycle, D, and percent deadtime, DT, can be calculated from: If synchronous rectification is not required, please consider the ISL6753 controller. The ISL6752 does not have a soft-start feature. Soft-start can be implemented externally using the components shown below. The RC network governs the rate of rise of the transistor’s base which clamps the voltage at VERR. Oscillator The ISL6752 has an oscillator with a programmable frequency range to 2MHz, which can be programmed with a resistor and capacitor. 9 TC D = ----------T SW (EQ. 4) DT = 1 – D (EQ. 5) Implementing Soft-Start FN9181.2 April 4, 2006 ISL6752 1 R 2 VREF 15 3 VERR 14 4 13 5 C accomplished by summing an external ramp with the current feedback signal or by subtracting the external ramp from the voltage feedback error signal. Adding the external ramp to the current feedback signal is the more popular method. 16 ISL6752 From the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, Fm, without slope compensation, is 12 6 11 7 10 8 9 1 Fm = -------------------SnTsw (EQ. 7) where Sn is the slope of the sawtooth signal and Tsw is the duration of the half-cycle. When an external ramp is added, the modulator gain becomes FIGURE 5. IMPLEMENTING SOFT-START The values of R and C should be selected to control the rate of rise of VERR to the desired soft-start duration. The softstart duration may be calculated from Equation. 6. V SS – V be t = – RC ⋅ ln 1 – ------------------------------------------ 0.001R VREF + ------------------ β (EQ. 8) where Se is slope of the external ramp and Se m c = 1 + ------Sn S (EQ. 9) (EQ. 6) where VSS is the soft-start clamp voltage, Vbe is the baseemitter voltage drop of the transistor, and β is the DC gain of the transistor. If β is sufficiently large, that term may be ignored. The schottky diode discharges the soft-start capacitor so that the circuit may be reset quickly. Gate Drive The ISL6752 outputs are capable of sourcing and sinking 10mA (at rated VOH, VOL) and are intended to be used in conjunction with integrated FET drivers or discrete bipolar totem pole drivers. The typical on resistance of the outputs is 50Ω. Overcurrent Operation The cycle-by-cycle peak current control results in pulse-bypulse duty cycle reduction when the current feedback signal exceeds 1.0V. When the peak current exceeds the threshold, the active output pulse is immediately terminated. This results in a well controlled decrease in output voltage as the load current increases beyond the current limit threshold. The ISL6752 will operate continuously in an overcurrent condition. The propagation delay from CS exceeding the current limit threshold to the termination of the output pulse is increased by the leading edge blanking (LEB) interval. The effective delay is the sum of the two delays and is nominally 105ns. Slope Compensation Peak current-mode control requires slope compensation to improve noise immunity, particularly at lighter loads, and to prevent current loop instability, particularly for duty cycles greater than 50%. Slope compensation may be 10 1 1 Fm = --------------------------------------- = ---------------------------( Sn + Se )Tsw m c SnTsw The criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double-pole located at half the oscillator frequency. The double-pole will be critically damped if the Q-factor is set to 1, and over-damped for Q > 1, and under-damped for Q < 1. An under-damped condition can result in current loop instability. 1 Q = ------------------------------------------------π ( m c ( 1 – D ) – 0.5 ) (EQ. 10) where D is the percent of on time during a half cycle. Setting Q = 1 and solving for Se yields 1 1 S e = S n --- + 0.5 ------------- – 1 1 –D π (EQ. 11) Since Sn and Se are the on time slopes of the current ramp and the external ramp, respectively, they can be multiplied by TON to obtain the voltage change that occurs during TON. 1 1 V e = V n --- + 0.5 ------------- – 1 1 –D π (EQ. 12) where Vn is the change in the current feedback signal during the on time and Ve is the voltage that must be added by the external ramp. Vn can be solved for in terms of input voltage, current transducer components, and output inductance yielding T SW ⋅ V ⋅ R CS N O S 1 V e = ------------------------------------------ ⋅ -------- --- + D – 0.5 N CT ⋅ L O NP π V (EQ. 13) where RCS is the current sense burden resistor, NCT is the current transformer turns ratio, LO is the output inductance, VO is the output voltage, and NS and NP are the secondary and primary turns, respectively. FN9181.2 April 4, 2006 ISL6752 The inductor current, when reflected through the isolation transformer and the current sense transformer to obtain the current feedback signal at the sense resistor yields N S ⋅ R CS D ⋅ T SW NS V CS = ------------------------ I O + --------------------- V IN ⋅ -------- – V O 2L O NP N P ⋅ N CT V peak amplitude of CT (0.4 - 4.4V). A typical application sums this signal with the current sense feedback and applies the result to the CS pin as shown in Figure 6. (EQ. 14) 1 2 where VCS is the voltage across the current sense resistor and IO is the output current at current limit. 4 CTBUF Since the peak current limit threshold is 1.00V, the total current feedback signal plus the external ramp voltage must sum to this value. V e + V CS = 1 ISL6752 3 5 R9 6 7 (EQ. 15) 8 CS R6 Substituting Equations 13 and 14 into Equation 15 and solving for RCS yields N P ⋅ N CT 1 R CS = ------------------------ ⋅ -----------------------------------------------------VO NS 1 D I O + -------- T SW --- + ---- π 2 L Ω RCS C4 (EQ. 16) O FIGURE 6. ADDING SLOPE COMPENSATION For simplicity, idealized components have been used for this discussion, but the effect of magnetizing inductance must be considered when determining the amount of external ramp to add. Magnetizing inductance provides a degree of slope compensation to the current feedback signal and reduces the amount of external ramp required. The magnetizing inductance adds primary current in excess of what is reflected from the inductor current in the secondary. V IN ⋅ DT SW ∆I P = ------------------------------Lm (EQ. 17) A where VIN is the input voltage that corresponds to the duty cycle D and Lm is the primary magnetizing inductance. The effect of the magnetizing current at the current sense resistor, RCS, is ∆I P ⋅ R CS ∆V CS = ------------------------N CT (EQ. 18) V If ∆VCS is greater than or equal to Ve, then no additional slope compensation is needed and RCS becomes N CT R CS = ------------------------------------------------------------------------------------------------------------------------------------NS DT SW NS V IN ⋅ DT SW -------- ⋅ I O + ----------------- ⋅ V IN ⋅ -------- – V O + ------------------------------NP 2L O NP Lm ( D ( V CTBUF – 0.4 ) + 0.4 ) ⋅ R6 V e – ∆V CS = -----------------------------------------------------------------------------R6 + R9 (EQ. 20) V Rearranging to solve for R9 yields ( D ( V CTBUF – 0.4 ) – V e + ∆V CS + 0.4 ) ⋅ R6 R9 = -----------------------------------------------------------------------------------------------------------------V e – ∆V CS Ω (EQ. 21) The value of RCS determined in Equation 16 must be rescaled so that the current sense signal presented at the CS pin is that predicted by Equation 14. The divider created by R6 and R9 makes this necessary. R6 + R9 R′ CS = ---------------------- ⋅ R CS R9 (EQ. 22) Example: VIN = 280V VO = 12V LO = 2.0µH (EQ. 19) If ∆VCS is less than Ve, then Equation 16 is still valid for the value of RCS, but the amount of slope compensation added by the external ramp must be reduced by ∆VCS. Adding slope compensation may be accomplished in the ISL6752 using the CTBUF signal. CTBUF is an amplified representation of the sawtooth signal that appears on the CT pin. It is offset from ground by 0.4V and is 2x the peak-to- 11 Assuming the designer has selected values for the RC filter placed on the CS pin, the value of R9 required to add the appropriate external ramp can be found by superposition. Np/Ns = 20 Lm = 2mH IO = 55A Oscillator Frequency, Fsw = 400kHz Duty Cycle, D = 85.7% NCT = 50 R6 = 499Ω FN9181.2 April 4, 2006 ISL6752 Solve for the current sense resistor, RCS, using Equation 16. and Equation 21 becomes: RCS = 15.1Ω. ( 2D – V e + ∆V CS ) ⋅ R6 R9 = -----------------------------------------------------------V e – ∆V CS Determine the amount of voltage, Ve, that must be added to the current feedback signal using Equation 13. Ve = 153mV Next, determine the effect of the magnetizing current from Equation 18. ∆VCS = 91mV Ω (EQ. 24) The buffer transistor used to create the external ramp from CT should have a sufficiently high gain (>200) so as to minimize the required base current. Whatever base current is required reduces the charging current into CT and will reduce the oscillator frequency. ZVS Full-Bridge Operation Using Equation 21, solve for the summing resistor, R9, from CTBUF to CS. R9 = 30.1kΩ Determine the new value of RCS, R’CS, using Equation 22. R’CS = 15.4Ω The above discussion determines the minimum external ramp that is required. Additional slope compensation may be considered for design margin. If the application requires deadtime less than about 500ns, the CTBUF signal may not perform adequately for slope compensation. CTBUF lags the CT sawtooth waveform by 300-400ns. This behavior results in a non-zero value of CTBUF when the next half-cycle begins when the deadtime is short. The ISL6752 is a full-bridge zero-voltage switching (ZVS) PWM controller that behaves much like a traditional hardswitched topology controller. Rather than drive the diagonal bridge switches simultaneously, the upper switches (OUTUL, OUTUR) are driven at a fixed 50% duty cycle and the lower switches (OUTLL, OUTLR) are pulse width modulated on the trailing edge. CT DEADTIME OUTLL PWM PWM PWM OUTLR Under these situations, slope compensation may be added by externally buffering the CT signal as shown below. OUTUR RESONANT DELAY OUTUL 1 3 R9 RESDEL WINDOW 16 2 VREF 15 ISL6752 FIGURE 8. BRIDGE DRIVE SIGNAL TIMING 14 4 13 5 12 6 11 7 CT 10 8 CS 9 PWM To understand how the ZVS method operates one must include the parasitic elements of the circuit and examine a full switching cycle. VIN+ UL R6 UR D1 VOUT+ LL RCS C4 CT RTN LL LR D2 VIN- FIGURE 7. ADDING SLOPE COMPENSATION USING CT Using CT to provide slope compensation instead of CTBUF requires the same calculations, except that Equations 20 and 21 require modification. Equation 20 becomes: 2D ⋅ R6 V e – ∆V CS = ---------------------R6 + R9 V (EQ. 23) 12 FIGURE 9. IDEALIZED FULL-BRIDGE In Figure 9, the power semiconductor switches have been replaced by ideal switch elements with parallel diodes and capacitance, the output rectifiers are ideal, and the transformer leakage inductance has been included as a discrete element. The parasitic capacitance has been lumped together as switch capacitance, but represents all FN9181.2 April 4, 2006 ISL6752 parasitic capacitance in the circuit including winding capacitance. Each switch is designated by its position, upper left (UL), upper right (UR), lower left (LL), and lower right (LR). The beginning of the cycle, shown in Figure 10, is arbitrarily set as having switches UL and LR on and UR and LL off. The direction of the primary and secondary currents are indicated by IP and IS, respectively. VIN+ UL UR D1 IS VOUT+ LL IP RTN LL LR D2 VIN- FIGURE 10. UL - LR POWER TRANSFER CYCLE The UL - LR power transfer period terminates when switch LR turns off as determined by the PWM. The current flowing in the primary cannot be interrupted instantaneously, so it must find an alternate path. The current flows into the parasitic switch capacitance of LR and UR which charges the node to VIN and then forward biases the body diode of upper switch UR. VIN+ UL UR D1 IS VOUT+ LL IP RTN LL LR D2 VIN- FIGURE 11. UL - UR FREE-WHEELING PERIOD The primary leakage inductance, LL, maintains the current which now circulates around the path of switch UL, the transformer primary, and switch UR. When switch LR opens, the output inductor current free-wheels through both output diodes, D1 and D2. During the switch transition, the output inductor current assists the leakage inductance in charging the upper and lower bridge FET capacitance. The current flow from the previous power transfer cycle tends to be maintained during the free-wheeling period because the transformer primary winding is essentially shorted. Diode D1 may conduct very little or none of the free-wheeling current, depending on circuit parasitics. This behavior is quite different than occurs in a conventional hard-switched full-bridge topology where the free-wheeling current splits nearly evenly between the output diodes, and flows not at all in the primary. During the period when CT discharges, also referred to as the deadtime, the upper switches toggle. Switch UL turns off and switch UR turns on. The actual timing of the upper switch toggle is dependent on RESDEL which sets the resonant delay. The voltage applied to RESDEL determines how far in advance the toggle occurs prior to a lower switch turning on. The ZVS transition occurs after the upper switches toggle and before the diagonal lower switch turns on. The required resonant delay is 1/4 of the period of the LC resonant frequency of the circuit formed by the leakage inductance and the parasitic capacitance. The resonant transition may be estimated from Equation 25. π 1 τ = --- ----------------------------------2 2 R 1 --------------- – ---------2 LL CP 4L L (EQ. 25) where τ is the resonant transition time, LL is the leakage inductance, CP is the parasitic capacitance, and R is the equivalent resistance in series with LL and CP. The resonant delay is always less than or equal to the deadtime and may be calculated using the following equation. V resdel τ resdel = -------------------- ⋅ DT 2 S (EQ. 26) where τresdel is the desired resonant delay, Vresdel is a voltage between 0 and 2V applied to the RESDEL pin, and DT is the deadtime (see Equations 1 - 5). When the upper switches toggle, the primary current that was flowing through UL must find an alternate path. It charges/discharges the parasitic capacitance of switches UL and LL until the body diode of LL is forward biased. If RESDEL is set properly, switch LL will be turned on at this time. The output inductor does not assist this transition. It is VIN+ UL UR D1 IS VOUT+ LL IP RTN LL LR D2 VIN- FIGURE 12. UPPER SWITCH TOGGLE AND RESONANT TRANSITION purely a resonant transition driven by the leakage inductance. The second power transfer period commences when switch LL closes. With switches UR and LL on, the primary and secondary currents flow as indicated in Figure 13. This condition persists through the remainder of the halfcycle. 13 FN9181.2 April 4, 2006 ISL6752 VIN+ UL UR D1 VOUT+ LL RTN LL LR D2 VIN- The first power transfer period commences when switch LR closes and the cycle repeats. The ZVS transition requires that the leakage inductance has sufficient energy stored to fully charge the parasitic capacitances. Since the energy stored is proportional to the square of the current (1/2 LLIP2), the ZVS resonant transition is load dependent. If the leakage inductance is not able to store sufficient energy for ZVS, a discrete inductor may be added in series with the transformer primary. Synchronous Rectifier Outputs and Control FIGURE 13. UR - LL POWER TRANSFER CYCLE The UR - LL power transfer period terminates when switch LL turns off as determined by the PWM. The current flowing in the primary must find an alternate path. The current flows into the parasitic switch capacitance which charges the node to VIN and then forward biases the body diode of upper switch UL. As before, the output inductor current assists in this transition. The primary leakage inductance, LL, maintains the current, which now circulates around the path of switch UR, the transformer primary, and switch UL. When switch LL opens, the output inductor current free-wheels predominantly through diode D1. Diode D2 may actually conduct very little or none of the free-wheeling current, depending on circuit parasitics. This condition persists through the remainder of the half-cycle. VIN+ UL UR D1 The ISL6752 provides double-ended PWM outputs, OUTLL and OUTLR, and synchronous rectifier (SR) outputs, OUTLLN and OUTLRN. The SR outputs are the complements of the PWM outputs. It should be noted that the complemented outputs are used in conjunction with the opposite PWM output, i.e. OUTLL and OUTLRN are paired together and OUTLR and OUTLLN are paired together. CT OUTLL OUTLR OUTLLN (SR1) IS VOUT+ LL OUTLRN (SR2) IP RTN LL LR FIGURE 16. BASIC WAVEFORM TIMING D2 VIN- FIGURE 14. UR - UL FREE-WHEELING PERIOD When the upper switches toggle, the primary current that was flowing through UR must find an alternate path. It charges/discharges the parasitic capacitance of switches UR and LR until the body diode of LR is forward biased. If RESDEL is set properly, switch LR will be turned on at this time. VIN+ UL UR D1 IS VOUT+ LL IP RTN LL Referring to Figure 16, the SRs alternate between being both on during the free-wheeling portion of the cycle (OUTLL/LR off), and one or the other being off when OUTLL or OUTLR is on. If OUTLL is on, its corresponding SR must also be on, indicating that OUTLRN is the correct SR control signal. Likewise, if OUTLR is on, its corresponding SR must also be on, indicating that OUTLLN is the correct SR control signal. A useful feature of the ISL6752 is the ability to vary the phase relationship between the PWM outputs (OUTLL, OUT LR) and the their complements (OUTLLN, OUTLRN) by ±300ns. This feature allows the designer to compensate for differences in the propagation times between the PWM FETs and the SR FETs. A voltage applied to VADJ controls the phase relationship. LR D2 VIN- FIGURE 15. UPPER SWITCH TOGGLE AND RESONANT TRANSITION 14 FN9181.2 April 4, 2006 ISL6752 On/Off Control The ISL6753 does not have a separate enable/disable control pin. The PWM outputs, OUTLL/OUTLR, may be disabled by pulling VERR to ground. Doing so reduces the duty cycle to zero, but the upper 50% duty cycle outputs, OUTUL/OUTUR, will continue operation. Likewise, the SR outputs OUTLLN/OUTLRN will be active high. CT OUTLL If the application requires that all outputs be off, then the supply voltage, VDD, must be removed from the IC. This may be accomplished as shown below. OUTLR OUTLLN (SR1) +Vdd OUTLRN (SR2) ISL6752 FIGURE 17. WAVEFORM TIMING WITH PWM OUTPUTS DELAYED, 0V < VADJ < 2.425V CT VADJ VDD VREF OUTLL VERR OUTLR CTBUF OUTUL RTD OUTUR ON/OFF RESDEL OUTLLN (OPEN = OFF GND = ON) CT OUTLRN CS GND OUTLL FIGURE 19. ON/OFF CONTROL USING VDD OUTLR Fault Conditions OUTLLN (SR1) A fault condition occurs if VREF or VDD fall below their undervoltage lockout (UVLO) thresholds or if the thermal protection is triggered. When a fault is detected the outputs are disabled low. When the fault condition clears the outputs are re-enabled. OUTLRN (SR2) FIGURE 18. WAVEFORM TIMING WITH SR OUTPUTS DELAYED, 2.575V < VADJ < 5.00V Setting VADJ to VREF/2 results in no delay on any output. The no delay voltage has a ±75mV tolerance window. Control voltages below the VREF/2 zero delay threshold cause the PWM outputs, OUTLL/LR, to be delayed. Control voltages greater than the VREF/2 zero delay threshold cause the SR outputs, OUTLLN/LRN, to be delayed. It should be noted that when the PWM outputs, OUTLL/LR, are delayed, the CS to output propagation delay is increased by the amount of the added delay. The delay feature is provided to compensate for mismatched propagation delays between the PWM and SR outputs as may be experienced when one set of signals crosses the primary-secondary isolation boundary. If required, individual output pulses may be stretched or compressed as required using external resistors, capacitors, and diodes. An overcurrent condition is not considered a fault and does not result in a shutdown. Thermal Protection Internal die over temperature protection is provided. An integrated temperature sensor protects the device should the junction temperature exceed 140°C. There is approximately 15°C of hysteresis. Ground Plane Requirements Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. VDD and VREF should be bypassed directly to GND with good high frequency capacitance. References [1] Ridley, R., “A New Continuous-Time Model for Current Mode Control”, IEEE Transactions on Power Electronics, Vol. 6, No. 2, April 1991. When the PWM outputs are delayed, the 50% upper outputs are equally delayed, so the resonant delay setting is unaffected. 15 FN9181.2 April 4, 2006 ISL6752 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP) M16.15A N INDEX AREA H 0.25(0.010) M E 2 INCHES GAUGE PLANE -B1 16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150” WIDE BODY) B M 3 0.25 0.010 SEATING PLANE -A- A D h x 45° -C- e α A1 B 0.17(0.007) M L A2 C 0.10(0.004) C A M B S NOTES: SYMBOL MIN MAX MIN MAX NOTES A 0.061 0.068 1.55 1.73 - A1 0.004 0.0098 0.102 0.249 - A2 0.055 0.061 1.40 1.55 - B 0.008 0.012 0.20 0.31 9 C 0.0075 0.0098 0.191 0.249 - D 0.189 0.196 4.80 4.98 3 E 0.150 0.157 3.81 3.99 4 e 0.025 BSC 0.635 BSC - H 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 L 0.016 0.035 0.41 0.89 6 8° 0° N 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MILLIMETERS α 16 0° 16 7 8° 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. Rev. 2 6/04 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN9181.2 April 4, 2006