LINER LTC3727 High efficiency, 2-phase synchronous step-down switching regulator Datasheet

LTC3727/LTC3727-1
High Efficiency, 2-Phase
Synchronous Step-Down Switching Regulators
FEATURES
DESCRIPTIO
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Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 14V
Out-of-Phase Controllers Reduce Required Input
Capacitance and Power Supply Induced Noise
OPTI-LOOP® Compensation Minimizes COUT
±1% Output Voltage Accuracy
Power Good Output Voltage Monitor
Phase-Lockable Fixed Frequency 250kHz to 550kHz
Latched Short-Circuit Shutdown (LTC3727 Only)
Dual N-Channel MOSFET Synchronous Drive
Wide VIN Range: 4V to 36V Operation
Very Low Dropout Operation: 99% Duty Cycle
Adjustable Soft-Start Current Ramping
Foldback Output Current Limiting
Output Overvoltage Protection
Low Shutdown IQ: 20μA
Selectable Constant Frequency or Burst Mode®
Operation
Small 28-Lead SSOP Package
LTC3727-1 Also Available in the 5mm × 5mm QFN
Package
The LTC®3727/LTC3727-1 are high performance dual
step-down switching regulator controllers that drive all
N-channel synchronous power MOSFET stages. A constant frequency current mode architecture allows phaselockable frequency of up to 550kHz. Power loss and noise
due to the ESR of the input capacitors are minimized by
operating the two controller output stages out of phase.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance and
ESR values. There is a precision 0.8V reference and a power
good output indicator. A wide 4V to 30V (36V maximum)
input supply range encompasses all battery chemistries.
A RUN/SS pin for each controller provides soft-start, and
on the LTC3727GN, optional timed, short-circuit shutdown. Current foldback limits MOSFET heat dissipation
during short-circuit conditions when overcurrent latchoff
is disabled. Output overvoltage protection circuitry latches
on the bottom MOSFET until VOUT returns to normal. The
FCB mode pin can select among Burst Mode, constant
frequency mode and continuous inductor current mode or
regulate a secondary winding.
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APPLICATIO S
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, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst
Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents, including
5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 6304066, 5705919.
Telecom Systems
Automotive Systems
Battery-Operated Digital Devices
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TYPICAL APPLICATIO
+
1μF
CERAMIC
4.7μF
VIN PGOOD INTVCC
M1
TG1
8μH
0.1μF
BOOST2
SW1
M2
BG1
VOUT1
5V
5A
LTC3727/
LTC3727-1
+
47μF
6V
SP
20k
1%
15k
M4
BG2
SENSE1+
SENSE2 +
SENSE1–
SENSE2 –
VOSENSE1
VOSENSE2
1000pF
ITH1
220pF
15μH
PGND
1000pF
105k
1%
0.1μF
SW2
PLLIN
0.015Ω
M3
TG2
BOOST1
VIN
18V TO 28V
22μF
50V
CERAMIC
280k
1%
ITH2
RUN/SS1 SGND RUN/SS2
0.1μF
0.015Ω
0.1μF
220pF
15k
20k
1%
M1, M2, M3, M4: FDS6680A
VOUT2
12V
4A
+ 56μF
15V
SP
3727 F01
Figure 1. High Efficiency Dual 12V/5V Step-Down Converter
3727fc
1
LTC3727/LTC3727-1
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AXI U
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ABSOLUTE
RATI GS (Note 1)
Input Supply Voltage (VIN).........................36V to – 0.3V
Top Side Driver Voltages
(BOOST1, BOOST2) ...................................42V to – 0.3V
Switch Voltage (SW1, SW2) .........................36V to – 5V
INTVCC, EXTVCC, (BOOST1-SW1),
(BOOST2-SW2) ........................................8.5V to – 0.3V
RUN/SS1, RUN/SS2, PGOOD ..................... 7V to – 0.3V
SENSE1+, SENSE2 +, SENSE1–,
SENSE2 – Voltages .....................................14V to – 0.3V
PLLIN, PLLFLTR, FCB Voltages ........... INTVCC to – 0.3V
ITH1, ITH2, VOSENSE1, VOSENSE2 Voltages ...2.7V to – 0.3V
Peak Output Current <10μs (TG1, TG2, BG1, BG2) ... 3A
INTVCC Peak Output Current ................................ 50mA
Operating Temperature Range (Note 2) .. – 40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range ................. – 65°C to 125°C
Lead Temperature
(Soldering, 10 sec, G Package)............................. 300°C
Solder Reflow Temperature (UH Package) ........... 265°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
25 BOOST1
PLLFLTR
5
24 VIN
PLLIN
6
23 BG1
FCB 4
FCB
7
22 EXTVCC
ITH1 5
ITH1
8
21 INTVCC
SGND 6
SGND
9
20 PGND
VOSENSE1 1
24 BOOST1
PLLFLTR 2
23 VIN
22 BG1
PLLIN 3
19 PGND
17 BOOST2
37271
NC
SW2
15 RUN/SS2
TG2
SENSE2 + 14
RUN/SS2
16 TG2
9 10 11 12 13 14 15 16
SENSE2+
SENSE2 – 13
UH PART
MARKING
18 BG2
ITH2 8
18 BOOST2
17 SW2
20 INTVCC
3.3VOUT 7
19 BG2
VOSENSE2 12
21 EXTVCC
33
SENSE2–
ITH2 11
LTC3727EUH-1
32 31 30 29 28 27 26 25
VOSENSE2
3.3VOUT 10
SW1
4
TG1
VOSENSE1
PGOOD
26 SW1
RUN/SS1
3
NC
27 TG1
SENSE1 –
SENSE1+
28 PGOOD
2
SENSE1–
1
SENSE1 +
NC
RUN/SS1
LTC3727EG
LTC3727EG-1
LTC3727IG-1
ORDER PART
NUMBER
TOP VIEW
NC
TOP VIEW
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS SGND
(MUST BE SOLDERED TO PCB)
TJMAX = 125°C, θJA = 95°C/W
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.792
0.800
0.808
V
–5
– 50
nA
0.002
0.02
%/V
Main Control Loops
VOSENSE1, 2
Regulated Feedback Voltage
(Note 4); ITH1, 2 Voltage = 1.2V
IVOSENSE1, 2
Feedback Current
(Note 4)
VREFLNREG
Reference Voltage Line Regulation
VIN = 3.6V to 30V (Note 4)
●
3727fc
2
LTC3727/LTC3727-1
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VLOADREG
Output Voltage Load Regulation
(Note 4)
Measured in Servo Loop; ΔITH Voltage = 1.2V to 0.7V
Measured in Servo Loop; ΔITH Voltage = 1.2V to 2.0V
gm1, 2
Transconductance Amplifier gm
ITH1, 2 = 1.2V; Sink/Source 5μA (Note 4)
gmGBW1, 2
Transconductance Amplifier GBW
ITH1, 2 = 1.2V (Note 4)
IQ
Input DC Supply Current
Normal Mode
Shutdown
(Note 5)
VIN = 15V, EXTVCC Tied to VOUT1, VOUT1 = 8.5V
VRUN/SS1, 2 = 0V
MIN
●
●
Forced Continuous Threshold
IFCB
Forced Continuous Pin Current
VFCB = 0.85V
VBINHIBIT
Burst Inhibit (Constant Frequency)
Threshold
Measured at FCB pin
UVLO
Undervoltage Lockout
VIN Ramping Down
●
VOVL
Feedback Overvoltage Lockout
Measured at VOSENSE1, 2
●
ISENSE
Sense Pins Total Source Current
(Each Channel) VSENSE1–, 2 – = VSENSE1+, 2+ = 0V
DFMAX
Maximum Duty Factor
IRUN/SS1, 2
Soft-Start Charge Current
VRUN/SS1, 2 ON RUN/SS Pin ON Threshold
0.1
– 0.1
MAX
0.5
– 0.5
UNITS
%
%
1.3
mmho
3
MHz
670
20
●
VFCB
TYP
35
μA
μA
0.76
0.800
0.84
V
– 0.30
– 0.18
– 0.05
μA
6.8
7.3
V
3.5
4
V
0.84
0.86
0.88
V
– 85
– 60
In Dropout
98
99.4
%
VRUN/SS1, 2 = 1.9V
0.5
1.2
μA
VRUN/SS1, VRUN/SS2 Rising
1.0
1.5
1.9
4.1
4.5
V
2
4
μA
1.6
5
μA
VRUN/SS1, 2 LT RUN/SS Pin Latchoff Arming Threshold VRUN/SS1, VRUN/SS2 Rising from 3V (LTC3727 Only)
0.5
μA
V
ISCL1, 2
RUN/SS Discharge Current
Soft-Short Condition VOSENSE1, 2 = 0.5V,
VRUN/SS1, 2 = 4.5V (LTC 3727 Only)
ISDLHO
Shutdown Latch Disable Current
VOSENSE1, 2 = 0.5V (LTC3727 Only)
VSENSE(MAX)
Maximum Current Sense Threshold
VOSENSE1, 2 = 0.7V,VSENSE1–, 2 – = 12V
135
165
mV
TG1, 2 tr
TG1, 2 tf
TG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
50
50
90
90
ns
ns
BG1, 2 tr
BG1, 2 tf
BG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
40
40
90
80
ns
ns
TG/BG t1D
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver
90
ns
BG/TG t2D
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver
90
ns
tON(MIN)
Minimum On-Time
Tested with a Square Wave (Note 7)
180
ns
●
105
INTVCC Linear Regulator
VINTVCC
Internal VCC Voltage
8.5V < VIN < 30V, VEXTVCC = 6V
VLDO INT
INTVCC Load Regulation
ICC = 0mA to 20mA, VEXTVCC = 6V
VLDO EXT
EXTVCC Voltage Drop
ICC = 20mA, VEXTVCC = 8.5V
VEXTVCC
EXTVCC Switchover Voltage
ICC = 20mA, EXTVCC Ramping Positive
VLDOHYS
EXTVCC Hysteresis
7.2
●
6.9
7.5
7.8
V
0.2
1.0
%
70
160
mV
7.3
V
0.3
V
Oscillator and Phase-Locked Loop
fNOM
Nominal Frequency
VPLLFLTR = 1.2V
350
380
430
kHz
fLOW
Lowest Frequency
VPLLFLTR = 0V
220
255
290
kHz
fHIGH
Highest Frequency
VPLLFLTR ≥ 2.4V
460
530
580
kHz
3727fc
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LTC3727/LTC3727-1
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
RPLLIN
PLLIN Input Resistance
CONDITIONS
I PLLFLTR
Phase Detector Output Current
Sinking Capability
Sourcing Capability
MIN
TYP
MAX
UNITS
50
kΩ
fPLLIN < fOSC
–15
μA
fPLLIN > fOSC
15
μA
3.3V Linear Regulator
V3.3OUT
3.3V Regulator Output Voltage
No Load
V3.3IL
3.3V Regulator Load Regulation
V3.3VL
3.3V Regulator Line Regulation
VPGL
IPGOOD
VPG
●
3.25
3.35
3.45
V
I3.3 = 0mA to 10mA
0.5
2.5
%
6V < VIN < 30V (LTC3727)
6V < VIN < 30V (LTC3727-1)
0.05
0.05
0.2
0.3
%
%
PGOOD Voltage Low
IPGOOD = 2mA
0.1
0.3
V
PGOOD Leakage Current
VPGOOD = 5V
±1
μA
PGOOD Trip Level, Either Controller
VOSENSE with Respect to Set Output Voltage
VOSENSE Ramping Negative
VOSENSE Ramping Positive
– 9.5
9.5
%
%
PGOOD Output
–6
6
–7.5
7.5
LTC3727EG/LTC3727EG-1/LTC3727IG-1: TJ = TA + (PD • 95 °C/W)
LTC3727EUH-1: TJ = TA + (PD • 34 °C/W)
Note 4: The LTC3727/LTC3727-1 are tested in a feedback loop that servos
VITH1, 2 to a specified voltage and measures the resultant VOSENSE1, 2.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥ 40% of IMAX (see minimum on-time
considerations in the Applications Information section).
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3727E/LTC3727E-1 are guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3727IG-1 is
guaranteed to meet performance specifications over the –40°C to 85°C
operating temperature range.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Output Current
(Figure 13)
Efficiency vs Output Current
and Mode (Figure 13)
100
70
FORCED
CONTINUOUS
MODE
50
30
CONSTANT
FREQUENCY
(BURST DISABLE)
20
10
0
0.001
90
90
60
40
VOUT = 5V
IOUT = 3A
VIN = 7V
80
VIN = 10V
VIN = 15V
EFFICIENCY (%)
EFFICIENCY (%)
80
100
100
Burst Mode
OPERATION
EFFICIENCY (%)
90
Efficiency vs Input Voltage
(Figure 13)
VIN = 20V
70
0.1
0.01
1
OUTPUT CURRENT (A)
10
3727 G01
50
0.001
70
60
60
VIN = 15V
VOUT = 8.5V
80
VOUT = 5V
0.1
0.01
1
OUTPUT CURRENT (A)
10
3727 G02
50
5
25
15
INPUT VOLTAGE (V)
35
3727 G03
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LTC3727/LTC3727-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Input Voltage
and Mode (Figure 13)
Internal 7.5V LDO Line Regulation
EXTVCC Voltage Drop
1000
160
7.7
VEXTVCC = 8.5V
EXTVCC VOLTAGE DROP (mV)
BOTH
CONTROLLERS ON
600
400
200
7.5
120
INTVCC VOLTAGE (V)
SUPPLY CURRENT (μA)
800
ILOAD = 1mA
7.6
140
100
80
60
7.4
7.3
7.2
7.1
40
7.0
20
6.9
SHUTDOWN
0
20
10
INPUT VOLTAGE (V)
0
0
30
0
10
20
30
CURRENT (mA)
40
3727 G04
6.8
50
0
5
10
15
20
25
INPUT VOLTAGE (V)
30
3727 G05
3727 G06
Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)
Maximum Current Sense Threshold
vs Duty Factor
150
35
Maximum Current Sense Threshold
vs VRUN/SS (Soft-Start)
150
150
VSENSE(CM) = 1.6V
135
120
125
75
50
VSENSE (mV)
105
100
VSENSE (mV)
VSENSE (mV)
125
90
75
60
45
100
75
30
25
15
0
0
20
40
60
DUTY FACTOR (%)
80
0
100
50
3727 G07
25
0
5
6
VOSENSE = 0.7V
2.0
–0.1
VITH (V)
NORMALIZED VOUT (%)
50
3
4
VRUN/SS (V)
VITH vs VRUN/SS
2.5
FCB = 0V
VIN = 15V
FIGURE 1
125
75
2
3727 G09
Load Regulation
0.0
150
100
1
3727 G08
Current Sense Threshold
vs ITH Voltage
VSENSE (mV)
0
20
60
80
0
100
40
PERCENT OF NOMINAL OUTPUT VOLTAGE (%)
–0.2
1.5
1.0
–0.3
0.5
–25
–50
0
0.5
1.0
1.5
VITH (V)
2.0
2.5
3727 G10
–0.4
0
1
3
2
LOAD CURRENT (A)
0
4
5
3727 G11
0
1
2
3
4
VRUN/SS (V)
5
6
3727 G12
3727fc
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LTC3727/LTC3727-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Dropout Voltage vs Output Current
(Figure 13)
SENSE Pins Total Source Current
100
1.4
50
RUN/SS Current vs Temperature
1.8
VOUT = 5V
1.6
1.2
ISENSE (μA)
–50
–100
–150
–200
–250
–300
RUN/SS CURRENT (μA)
DROPOUT VOLTAGE (V)
0
1.0
RSENSE = 0.015Ω
0.8
0.6
0.4
0.2
–350
0
10
5
VSENSE COMMON MODE VOLTAGE (V)
15
0
1
2
3
4
1.0
0.8
0.6
0.4
0.2
RSENSE = 0.010Ω
0
–400
1.4
1.2
5
0
–50
OUTPUT CURRENT (A)
3727 G13
0
25
50
75
TEMPERATURE (°C)
100
125
3727 G15
3727 G14
Soft-Start Up (Figure 12)
Load Step (Figure 12)
IOUT*
5A/DIV
–25
Load Step (Figure 12)
VOUT
200mV/DIV
VOUT
200mV/DIV
IOUT*
2A/DIV
IOUT*
2A/DIV
VOUT
5V/DIV
VRUN/SS
5V/DIV
VIN = 20V
VOUT = 12V
50ms/DIV
50μs/DIV
VIN = 15V
VOUT = 12V
LOAD STEP = 0A TO 3A
Burst Mode OPERATION
3727 G16
Input Source/Capacitor
Instantaneous Current (Figure 12)
IIN
1A/DIV
VIN = 15V
50μs/DIV
VOUT = 12V
LOAD STEP = 0A TO 3A
CONTINUOUS MODE
3727 G17
Constant Frequency (Burst Inhibit)
Operation (Figure 12)
Burst Mode Operation (Figure 12)
VOUT
20mV/DIV
3727 G18
VOUT
20mV/DIV
VSW1
20V/DIV
VSW2
20V/DIV
IOUT*
0.5A/DIV
IOUT*
0.5A/DIV
VIN = 15V
VOUT1 = 12V
VOUT2 = 5V
IOUT1 = IOUT2 = 2A
1μs/DIV
3727 G19
VIN = 15V
VOUT = 12V
VFCB = OPEN
IOUT = 20mA
50μs/DIV
3727 G20
VIN = 15V
VOUT = 12V
VFCB = 7.5V
IOUT = 20mA
5μs/DIV
3727 G21
*IOUT ⇒ INDUCTOR CURRENT
3727fc
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LTC3727/LTC3727-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Current Sense Pin Input Current
vs Temperature
EXTVCC Switch Resistance
vs Temperature
10
35
700
VOUT = 5V
33
31
29
27
25
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
600
6
4
500
VPLLFLTR = 1.2V
400
300
VPLLFLTR = 0V
200
2
100
0
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
0
– 50 – 25
50
25
75
0
TEMPERATURE (°C)
3727 G23
3727 G22
Undervoltage Lockout
vs Temperature
100
125
3727 G24
Shutdown Latch Thresholds
vs Temperature
4.5
SHUTDOWN LATCH THRESHOLDS (V)
3.50
UNDERVOLTAGE LOCKOUT (V)
VPLLFLTR = 5V
8
FREQUENCY (kHz)
EXTVCC SWITCH RESISTANCE (Ω)
CURRENT SENSE INPUT CURRENT (μA)
Oscillator Frequency
vs Temperature
3.45
3.40
3.35
3.30
3.25
3.20
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3727 G25
U
U
U
PI FU CTIO S
4.0
LATCH ARMING
3.5
3.0
2.5
LATCHOFF
THRESHOLD
2.0
1.5
1.0
0.5
LTC3727 ONLY
0
0
25
–50 –25
50
75
TEMPERATURE (°C)
100
125
3727 G26
G Package/UH Package
RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13): Combination of Soft-Start, Run Control Inputs and Short-Circuit
Detection Timers (LTC3727 only). A capacitor to ground at
each of these pins sets the ramp time to full output current.
Forcing either of these pins back below 1.0V causes the IC
to shut down the circuitry required for that particular
controller. Latchoff overcurrent protection is also invoked
via this pin as described in the Applications Information
section (LTC3727 only).
SENSE1+, SENSE2+ (Pins 2, 14/Pins 30, 12): The (+)
Input to the Differential Current Comparators. The ITH pin
voltage and controlled offsets between the SENSE– and
SENSE+ pins in conjunction with RSENSE set the current
trip threshold.
SENSE1–, SENSE2– (Pins 3, 13/Pins 31, 11): The (–)
Input to the Differential Current Comparators.
VOSENSE1, VOSENSE2 (Pins 4, 12/Pins 1, 9): Receives the
remotely-sensed feedback voltage for each controller from
an external resistive divider across the output.
3727fc
7
LTC3727/LTC3727-1
U
U
U
PI FU CTIO S
PLLFLTR (Pin 5/Pin 2): The phase-locked loop’s lowpass
filter is tied to this pin. Alternatively, this pin can be driven
with an AC or DC voltage source to vary the frequency of
the internal oscillator.
PLLIN (Pin 6/Pin 3): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with 50kΩ. The phase-locked loop will force the rising top
gate signal of controller 1 to be synchronized with the
rising edge of the PLLIN signal.
FCB (Pin 7/Pin 4): Forced Continuous Control Input. This
input acts on both controllers and is normally used to
regulate a secondary winding. Pulling this pin below 0.8V
will force continuous synchronous operation. Do not
leave this pin floating.
ITH1, ITH2 (Pins 8, 11/Pins 5, 8): Error Amplifier Outputs
and Switching Regulator Compensation Points. Each associated channels’ current comparator trip point increases
with this control voltage.
SGND (Pin 9/Pin 6): Small Signal Ground. Common
to both controllers; must be routed separately from
high current grounds to the common (–) terminals
of the COUT capacitors.
EXTVCC (Pin 22/Pin 21): External Power Input to an
Internal Switch Connected to INTVCC. This switch closes
and supplies VCC power, bypassing the internal low dropout regulator, whenever EXTVCC is higher than 7.3V. See
EXTVCC connection in Applications section. Do not exceed
8.5V on this pin.
BG1, BG2 (Pins 23, 19/Pins 22, 18): High Current Gate
Drives for Bottom (Synchronous) N-Channel MOSFETs.
Voltage swing at these pins is from ground to INTVCC.
VIN (Pin 24/Pin 23): Main Supply Pin. A bypass capacitor
should be tied between this pin and the signal ground pin.
BOOST1, BOOST2 (Pins 25, 18/Pins 24, 17): Bootstrapped
Supplies to the Top Side Floating Drivers. Capacitors are
connected between the boost and switch pins and Schottky diodes are tied between the boost and INTVCC pins.
Voltage swing at the boost pins is from INTVCC to (VIN +
INTVCC).
SW1, SW2 (Pins 26, 17/Pins 25, 15): Switch Node
Connections to Inductors. Voltage swing at these pins is
from a Schottky diode (external) voltage drop below
ground to VIN.
3.3VOUT (Pin 10/Pin 7): Linear Regulator Output. Capable
of supplying 10mA DC with peak currents as high as
50mA.
TG1, TG2 (Pins 27, 16/Pins 26, 14): High Current Gate
Drives for Top N-Channel MOSFETs. These are the outputs
of floating drivers with a voltage swing equal to INTVCC –
0.5V superimposed on the switch node voltage SW.
PGND (Pin 20/Pin 19): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs, anodes of the Schottky rectifiers and the (–) terminal(s) of CIN.
PGOOD (Pin 28/Pin 27): Open-Drain Logic Output. PGOOD
is pulled to ground when the voltage on either VOSENSE pin
is not within ±7.5% of its set point.
INTVCC (Pin 21/Pin 20): Output of the Internal 7.5V Linear
Low Dropout Regulator and the EXTVCC Switch. The driver
and control circuits are powered from this voltage source.
Must be decoupled to power ground with a minimum of 4.7μF
tantalum or other low ESR capacitor.
Exposed Pad (Pin 33, UH Package): Signal Ground. Must
be soldered to the PCB ground for electrical contact and
optimum thermal performance.
3727fc
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LTC3727/LTC3727-1
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FU CTIO AL DIAGRA
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PLLIN
FIN
VIN
INTVCC
PHASE DET
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
50k
BOOST
DB
PLLFLTR
DROP
OUT
DET
CLK1
RLP
OSCILLATOR
CLK2
CLP
–
0.86V
S
Q
R
Q
BOT
VOSENSE1
TOP ON
SWITCH
LOGIC
INTVCC
0.86V
+
0.55V
COUT
PGND
B
–
+
BG
+
–
CIN
SW
BOT
0.74V
+
D1
–
+
CB
FCB
+
PGOOD
TG
TOP
SHDN
VOSENSE2
VOUT
RSENSE
–
+
1.5V
7V
0.18μA
I1
–
+
R6
0.74V
–
BINH
FCB
–
3.3VOUT
+
0.8V
–
++
FCB
SLOPE
COMP
–
+
50k SENSE
+
25k
2.4V
VREF
–
EA
+
OV
VIN
EXTVCC
–
7.5V
LDO
REG
VOSENSE
0.80V
SHDN
RST
4(VFB)
+
R2
R1
0.86V
ITH
1.2μA
6V
INTVCC
VFB
+
–
+
CSEC
25k
VIN
7.3V
DSEC
–
50k SENSE
–
7.5V
INTVCC
I2
–
3mV
0.86V
4(VFB)
+
R5
+
+
VSEC
RUN
SOFT
START
CC
CC2
RC
RUN/SS
SGND
INTERNAL
SUPPLY
CSS
3727 F02
Figure 2
U
OPERATIO (Refer to Functional Diagram)
Main Control Loop
The LTC3727/LTC3727-1 use a constant frequency, current mode step-down architecture with the two controller
channels operating 180 degrees out of phase. During
normal operation, each top MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the main current comparator, I1, resets the RS latch.
The peak inductor current at which I1 resets the RS latch
is controlled by the voltage on the ITH pin, which is the
output of each error amplifier EA. The VOSENSE pin receives
the voltage feedback signal, which is compared to the
internal reference voltage by the EA. When the load current
increases, it causes a slight decrease in VOSENSE relative to
the 0.8V reference, which in turn causes the ITH voltage to
increase until the average inductor current matches the
new load current. After the top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle.
3727fc
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LTC3727/LTC3727-1
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OPERATIO (Refer to Functional Diagram)
The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during
each off cycle through an external diode when the top
MOSFET turns off. As VIN decreases to a voltage close to
VOUT, the loop may enter dropout and attempt to turn on
the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 400ns
every tenth cycle to allow CB to recharge.
The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.2μA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled with the
ITH voltage clamped at approximately 30% of its maximum
value. As CSS continues to charge, the ITH pin voltage is
gradually released allowing normal, full-current operation. When both RUN/SS1 and RUN/SS2 are low, all
LTC3727/LTC3727-1 controller functions are shut down,
including the 7.5V and 3.3V regulators.
Low Current Operation
The FCB pin is a multifunction pin providing two functions: 1) to provide regulation for a secondary winding by
temporarily forcing continuous PWM operation on
both controllers; and 2) to select between two modes of
low current operation. When the FCB pin voltage is below
0.8V, the controller forces continuous PWM current
mode operation. In this mode, the top and bottom
MOSFETs are alternately turned on to maintain the output
voltage independent of direction of inductor current.
When the FCB pin is below VINTVCC – 2V but greater than
0.8V, the controller enters Burst Mode operation. Burst
Mode operation sets a minimum output current level
before inhibiting the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low currents, force the ITH pin below a voltage threshold that will
temporarily inhibit turn-on of both output MOSFETs until
the output voltage drops. There is 60mV of hysteresis in
the burst comparator B tied to the ITH pin. This hysteresis
produces output signals to the MOSFETs that turn them
on for several cycles, followed by a variable “sleep”
interval depending upon the load current. The resultant
output voltage ripple is held to a very small value by
having the hysteretic comparator follow the error amplifier gain block.
Frequency Synchronization
The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the PLLIN pin. The
output of the phase detector at the PLLFLTR pin is also the
DC frequency control input of the oscillator that operates
over a 250kHz to 550kHz range corresponding to a DC
voltage input from 0V to 2.4V. When locked, the PLL
aligns the turn on of the top MOSFET to the rising edge of
the synchronizing signal. When PLLIN is left open, the
PLLFLTR pin goes low, forcing the oscillator to its minimum frequency.
Continuous Current (PWM) Operation
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, current will be
forced back into the main power supply potentially boosting the input supply to dangerous voltage levels—
BEWARE!
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open, an internal 7.5V low
dropout linear regulator supplies INTVCC power. If EXTVCC
is taken above 7.3V, the 7.5V regulator is turned off and an
internal switch is turned on connecting EXTVCC to INTVCC.
This allows the INTVCC power to be derived from a high
efficiency external source such as the output of the regulator itself or a secondary winding, as described in the
Applications Information section.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious conditions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned on
until the overvoltage condition is cleared.
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LTC3727/LTC3727-1
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OPERATIO (Refer to Functional Diagram)
Power Good (PGOOD) Pin
THEORY AND BENEFITS OF 2-PHASE OPERATION
The PGOOD pin is connected to an open drain of an internal
MOSFET. The MOSFET turns on and pulls the pin low when
either output is not within ±7.5% of the nominal output
level as determined by the resistive feedback divider.
When both outputs meet the ±7.5% requirement, the
MOSFET is turned off within 10μs and the pin is allowed to
be pulled up by an external resistor to a source of up to 7V.
The LTC3727 dual high efficiency DC/DC controller brings
the considerable benefits of 2-phase operation to portable
applications. Notebook computers, PDAs, handheld terminals and automotive electronics will all benefit from the
lower input filtering requirement, reduced electromagnetic interference (EMI) and increased efficiency associated with 2-phase operation.
Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff (LTC3727 Only)
Why the need for 2-phase operation? Until recently, constant-frequency dual switching regulators operated both
channels in phase (i.e., single-phase operation). This
means that both switches turned on at the same time,
causing current pulses of up to twice the amplitude of
those for one regulator to be drawn from the input capacitor and battery. These large amplitude current pulses
increased the total RMS current flowing from the input
capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.
The RUN/SS capacitors are used initially to limit the inrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used in a short-circuit time-out
circuit. If the output voltage falls to less than 70% of its
nominal output voltage, the RUN/SS capacitor begins
discharging on the assumption that the output is in an
overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the
size of the RUN/SS capacitor, the controller will be shut
down until the RUN/SS pin(s) voltage(s) are recycled.
This built-in latchoff can be overridden by providing a
>5μA pull-up at a compliance of 5V to the RUN/SS pin(s).
This current shortens the soft start period but also prevents net discharge of the RUN/SS capacitor(s) during an
overcurrent and/or short-circuit condition. Foldback current limiting is also activated when the output voltage falls
below 70% of its nominal level whether or not the shortcircuit latchoff circuit is enabled. Even if a short is present
and the short-circuit latchoff is not enabled, a safe, low
output current is provided due to internal current foldback
and actual power wasted is low due to the efficient nature
of the current mode switching regulator.
PART NUMBER
LTC3727
LTC3727-1
FUNCTION
With Latchoff Function Available
Latchoff Always Disabled
With 2-phase operation, the two channels of the dualswitching regulator are operated 180 degrees out of
phase. This effectively interleaves the current pulses
drawn by the switches, greatly reducing the overlap time
where they add together. The result is a significant reduction in total RMS input current, which in turn allows less
expensive input capacitors to be used, reduces shielding
requirements for EMI and improves real world operating
efficiency.
Figure 3 compares the input waveforms for a representative single-phase dual switching regulator to the new
LTC3727 2-phase dual switching regulator. An actual
measurement of the RMS input current under these conditions shows that 2-phase operation dropped the input
current from 2.53ARMS to 1.55ARMS. While this is an
impressive reduction in itself, remember that the power
losses are proportional to IRMS2, meaning that the actual
power wasted is reduced by a factor of 2.66. The reduced
input ripple voltage also means less power is lost in the
3727fc
11
LTC3727/LTC3727-1
U
OPERATIO (Refer to Functional Diagram)
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
IIN(MEAS) = 2.53ARMS
IIN(MEAS) = 1.55ARMS
3727 F03a
3727 F03b
(b)
(a)
Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for
Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input
Ripple with the LTC3727 2-Phase Regulator Allows Less Expensive Input Capacitors,
Reduces Shielding Requirements for EMI and Improves Efficiency
Of course, the improvement afforded by 2-phase operation is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
voltage VIN (Duty Cycle = VOUT/VIN). Figure 4 shows how
the RMS input current varies for single-phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
It can readily be seen that the advantages of 2-phase
operation are not just limited to a narrow operating range,
but in fact extend over a wide region. A good rule of thumb
for most applications is that 2-phase operation will reduce
the input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
require an oscillator derived “slope compensation” signal
to allow stable operation of each regulator at over 50%
duty cycle. This signal is relatively easy to derive in singlephase dual switching regulators, but required the development of a new and proprietary technique to allow 2-phase
operation. In addition, isolation between the two channels
becomes more critical with 2-phase operation because
switch transitions in one channel could potentially disrupt
the operation of the other channel.
3.0
SINGLE PHASE
DUAL CONTROLLER
2.5
INPUT RMS CURRENT (A)
input power path, which could include batteries, switches,
trace/connector resistances and protection circuitry. Improvements in both conducted and radiated EMI also
directly accrue as a result of the reduced RMS input
current and voltage.
2.0
1.5
2-PHASE
DUAL CONTROLLER
1.0
0.5
A final question: If 2-phase operation offers such an
advantage over single-phase operation for dual switching
regulators, why hasn’t it been done before? The answer is
that, while simple in concept, it is hard to implement.
Constant-frequency current mode switching regulators
0
VO1 = 5V/3A
VO2 = 3.3V/3A
0
10
20
30
INPUT VOLTAGE (V)
40
3727 F04
Figure 4. RMS Input Current Comparison
3727fc
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LTC3727/LTC3727-1
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2.5
PLLFLTR PIN VOLTAGE (V)
Figure 1 on the first page is a basic LTC3727/LTC3727-1
application circuit. External component selection is driven
by the load requirement, and begins with the selection of
RSENSE and the inductor value. Next, the power MOSFETs
and D1 are selected. Finally, CIN and COUT are selected.
The circuit shown in Figure 1 can be configured for
operation up to an input voltage of 28V (limited by the
external MOSFETs).
RSENSE Selection For Output Current
RSENSE is chosen based on the required output current.
The LTC3727 current comparator has a maximum threshold of 135mV/RSENSE and an input common mode range
of SGND to 14V. The current comparator threshold sets
the peak of the inductor current, yielding a maximum
average output current IMAX equal to the peak value less
half the peak-to-peak ripple current, ΔIL.
Allowing a margin for variations in the LTC3727 and
external component values yields:
RSENSE =
90mV
IMAX
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability criterion for buck regulators operating at greater than 50%
duty factor. A curve is provided to estimate this reducton
in peak output current level depending upon the operating
duty factor.
Operating Frequency
The LTC3727 uses a constant frequency phase-lockable
architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to Phase-Locked Loop
and Frequency Synchronization in the Applications Information section for additional information.
A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure 5. As the operating frequency
2.0
1.5
1.0
0.5
0
200
250 300 350 400 450 500
OPERATING FREQUENCY (kHz)
550
3727 F05
Figure 5. PLLFLTR Pin Voltage vs Frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 550kHz.
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current. The
inductor ripple current ΔIL decreases with higher inductance or frequency and increases with higher VIN:
ΔIL =
⎛ V ⎞
1
VOUT ⎜ 1 – OUT ⎟
⎝
( f)(L)
VIN ⎠
Accepting larger values of ΔIL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ΔIL = 0.3(IMAX). The maximum ΔIL
occurs at the maximum input voltage.
3727fc
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The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ΔIL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
The peak-to-peak drive levels are set by the INTVCC
voltage. This voltage is typically 7.5V during start-up (see
EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(VIN < 5V); then, sub-logic level threshold MOSFETs
(VGS(TH) < 3V) should be used. Pay close attention to the
BVDSS specification for the MOSFETs as well; most of the
logic level MOSFETs are limited to 30V or less.
Inductor Core Selection
Selection criteria for the power MOSFETs include the “ON”
resistance RDS(ON), reverse transfer capacitance CRSS,
input voltage and maximum output current. When the
LTC3727 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
Once the inductance value is determined, the type of
inductor must be selected. Actual core loss is independent
of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper (I2R) losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so designers can concentrate on reducing I2R loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with
similar characteristics. The choice of which style inductor
to use mainly depends on the price vs size requirements
and any radiated field/EMI requirements. New designs for
high current surface mount inductors are available from
numerous manufacturers, including Coiltronics, Vishay,
TDK, Pulse, Panasonic, Wuerth, Coilcraft, Toko and Sumida.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for each
controller in the LTC3727: One N-channel MOSFET for the
top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
Main Switch Duty Cycle =
VOUT
VIN
Synchronous Switch Duty Cycle =
VIN – VOUT
VIN
The MOSFET power dissipations at maximum output
current are given by:
PMAIN =
VOUT
2
IMAX ) (1 + δ )RDS(ON) +
(
VIN
k( VIN ) (IMAX )(CRSS )( f)
2
PSYNC =
VIN – VOUT
2
IMAX ) (1 + δ )RDS(ON)
(
VIN
where δ is the temperature dependency of RDS(ON) and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V the
high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CRSS actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
3727fc
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LTC3727/LTC3727-1
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short-circuit when the synchronous switch is on close to
100% of the period.
The term (1+δ) is generally given for a MOSFET in the form
of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.
The Schottky diode D1 shown in Figure 2 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the deadtime and requiring a reverse recovery period that could
cost as much as 3% in efficiency at high VIN. A 1A to 3A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance. Schottky diodes should
be placed in parallel with the synchronous MOSFETs when
operating in pulse-skip mode or in Burst Mode operation.
CIN and COUT Selection
The selection of CIN is simplified by the multiphase architecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
the highest (VOUT)(IOUT) product needs to be used in the
formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease
the input RMS ripple current from this maximum value
(see Figure 4). The out-of-phase technique typically reduces the input capacitor’s RMS ripple current by a factor
of 30% to 70% when compared to a single phase power
supply solution.
The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selection process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 22μF to 47μF is usually sufficient
for a 25W output supply operating at 250kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
input capacitors, but each has drawbacks: ceramic voltage
coefficients are very high and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs
suffer from higher inductance, larger case size and limited
surface-mount applicability; electrolytics’ higher ESR and
dryout possibility require several to be used. Multiphase
systems allow the lowest amount of capacitance overall.
As little as one 22μF or two to three 10μF ceramic capacitors are an ideal choice in a 20W to 35W power supply due
to their extremely low ESR. Even though the capacitance
at 20V is substantially below their rating at zero-bias, very
low ESR loss makes ceramics an ideal candidate for
highest efficiency battery operated systems. Also consider parallel ceramic and high quality electrolytic capacitors as an effective means of achieving ESR and bulk
capacitance goals.
In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current of one channel must
be used. The maximum RMS capacitor current is given by:
1/ 2
VOUT ( VIN − VOUT )]
[
CIN Re quiredIRMS ≅ IMAX
VIN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.
3727fc
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The benefit of the LTC3727 multiphase can be calculated
by using the equation above for the higher power controller and then calculating the loss that would have resulted
if both controller channels switch on at the same time. The
total RMS power lost is lower when both controllers are
operating due to the interleaving of current pulses through
the input capacitor’s ESR. This is why the input capacitor’s
requirement calculated above for the worst-case controller is adequate for the dual controller design. Remember
that input protection fuse resistance, battery resistance
and PC board trace resistance losses are also reduced due
to the reduced peak currents in a multiphase system. The
overall benefit of a multiphase design will only be fully
realized when the source impedance of the power supply/
battery is included in the efficiency testing. The drains of
the two top MOSFETS should be placed within 1cm of each
other and share a common CIN(s). Separating the drains
and CIN may produce undesirable voltage and current
resonances at VIN.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically once the ESR requirement is satisfied the capacitance is adequate for filtering.
The output ripple (ΔVOUT) is determined by:
⎛
1 ⎞
ΔVOUT ≅ ΔIL ⎜ ESR +
⎟
⎝
8 fCOUT ⎠
Where f = operating frequency, COUT = output capacitance, and ΔIL= ripple current in the inductor. The output
ripple is highest at maximum input voltage since ΔIL
increases with input voltage. With ΔIL = 0.3IOUT(MAX) the
output ripple will typically be less than 50mV at max V IN
assuming:
COUT Recommended ESR < 2 RSENSE
and COUT > 1/(8fRSENSE)
The first condition relates to the ripple current into the
ESR of the output capacitance while the second term
guarantees that the output capacitance does not significantly discharge during the operating frequency period
due to ripple current. The choice of using smaller output
capacitance increases the ripple voltage due to the
discharging term but can be compensated for by using
capacitors of very low ESR to maintain the ripple voltage
at or below 50mV. The ITH pin OPTI-LOOP compensation
components can be optimized to provide stable, high
performance transient response regardless of the output
capacitors selected.
Manufacturers such as Nichicon, Nippon Chemi-Con and
Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Special polymer surface mount capacitors offer very low ESR
but have lower storage capacity per unit volume than other
capacitor types. These capacitors offer a very cost-effective output capacitor solution and are an ideal choice when
combined with a controller having high loop bandwidth.
Tantalum capacitors offer the highest capacitance density
and are often used as output capacitors for switching
regulators having controlled soft-start. Several excellent
surge-tested choices are the AVX TPS, AVX TPS Series III
or the KEMET T510 series of surface mount tantalums,
available in case heights ranging from 1.2mm to 4.1mm.
Aluminum electrolytic capacitors can be used in costdriven applications providing that consideration is given
to ripple current ratings, temperature and long term reliability. A typical application will require several to many
aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result in
maximizing performance and minimizing overall cost. Other
capacitor types include Nichicon PL series, NEC Neocap,
Cornell Dubilier ESRE and Sprague 595D series. Consult
manufacturers for other specific recommendations.
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INTVCC Regulator
EXTVCC Connection
An internal P-channel low dropout regulator produces
7.5V at the INTVCC pin from the VIN supply pin. INTVCC
powers the drivers and internal circuitry within the
LTC3727. The INTVCC pin regulator can supply a peak
current of 50mA and must be bypassed to ground with a
minimum of 4.7μF tantalum, 10μF special polymer, or low
ESR type electrolytic capacitor. A 1μF ceramic capacitor
placed directly adjacent to the INTVCC and PGND IC pins
is highly recommended. Good bypassing is necessary to
supply the high transient currents required by the MOSFET
gate drivers and to prevent interaction between channels.
The LTC3727 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
When the voltage applied to EXTVCC rises above 7.3V, the
internal regulator is turned off and the switch closes,
connecting the EXTVCC pin to the INTVCC pin thereby
supplying internal power. The switch remains closed as
long as the voltage applied to EXTVCC remains above 7.0V.
This allows the MOSFET driver and control power to be
derived from the output during normal operation (7.2V <
VOUT < 8.5V) and from the internal regulator when the
output is out of regulation (start-up, short-circuit). If more
current is required through the EXTVCC switch than is
specified, an external Schottky diode can be added between the EXTVCC and INTVCC pins. Do not apply greater
than 8.5V to the EXTVCC pin and ensure that EXTVCC < VIN.
Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3727 to be
exceeded. The system supply current is normally dominated by the gate charge current. Additional external
loading of the INTVCC and 3.3V linear regulators also
needs to be taken into account for the power dissipation
calculations. The total INTVCC current can be supplied by
either the 7.5V internal linear regulator or by the EXTVCC
input pin. When the voltage applied to the EXTVCC pin is
less than 7.3V, all of the INTVCC current is supplied by the
internal 7.5V linear regulator. Power dissipation for the IC
in this case is highest: (VIN)(IINTVCC), and overall efficiency
is lowered. The gate charge current is dependent on
operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC3727 VIN
current is limited to less than 24mA from a 24V supply
when not using the EXTVCC pin as follows:
TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C
Use of the EXTVCC input pin reduces the junction temperature to:
TJ = 70°C + (24mA)(7.5V)(95°C/W) = 87°C
Dissipation should be calculated to also include any added
current drawn from the internal 3.3V linear regulator. To
prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum VIN.
Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 7.5V regulators this
supply means connecting the EXTVCC pin directly to VOUT.
However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTVCC power
from the output.
The following list summarizes the four possible connections for EXTVCC:
1. EXTVCC Left Open (or Grounded). This will cause INTVCC
to be powered from the internal 7.5V regulator resulting in
an efficiency penalty of up to 10% at high input voltages.
2. EXTVCC Connected directly to VOUT. This is the normal
connection for a 7.5V regulator and provides the highest
efficiency.
3. EXTVCC Connected to an External supply. If an external
supply is available in the 7.5V to 8.5V range, it may be used
to power EXTVCC providing it is compatible with the
MOSFET gate drive requirements.
4. EXTVCC Connected to an Output-Derived Boost Network. For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
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Output Voltage
VIN
OPTIONAL EXTVCC
CONNECTION
7.5V < VSEC < 8.5V
+
CIN
VSEC
VIN
+
N-CH
LTC3727
1μF
TG1
RSENSE
VOUT
EXTVCC
SW
FCB
BG1
T1
1:N
R6
+
R5
COUT
N-CH
SGND
The LTC3727 output voltages are each set by an external
feedback resistive divider carefully placed across the
output capacitor. The resultant feedback signal is
compared with the internal precision 0.800V voltage
reference by the error amplifier. The output voltage is
given by the equation:
⎛ R2 ⎞
VOUT = 0.8 V⎜ 1 + ⎟
⎝ R1⎠
PGND
3727 F06
Figure 6. Secondary Output Loop & EXTVCC Connection
than 7.5V. This can be done with the inductive boost
winding as shown in Figure 6.
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors CB connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor CB in the functional diagram is charged though
external diode DB from INTVCC when the SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the CB voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: VBOOST =
VIN + VINTVCC. The value of the boost capacitor CB needs
to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the
input current decreases, then the efficiency has improved.
If there is no change in input current, then there is no
change in efficiency.
where R1 and R2 are defined in Figure 2.
SENSE+/SENSE– Pins
The common mode input range of the current comparator
sense pins is from 0V to 14V. Continuous linear operation
is guaranteed throughout this range allowing output voltage setting from 0.8V to 14V. A differential NPN input
stage is biased with internal resistors from an internal
2.4V source as shown in the Functional Diagram. This
requires that current either be sourced or sunk from the
SENSE pins depending on the output voltage. If the output
voltage is below 2.4V current will flow out of both SENSE
pins to the main output. The output can be easily preloaded
by the VOUT resistive divider to compensate for the current
comparator’s negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:
ISENSE+ + ISENSE– = (2.4V – VOUT)/24k
Since VOSENSE is servoed to the 0.8V reference voltage, we
can choose R1 in Figure 2 to have a maximum value to
absorb this current.
⎛
⎞
0.8 V
R1(MAX) = 24k ⎜
⎟
⎝ 2.4V – VOUT ⎠
for VOUT < 2.4V
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Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32K. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the
VOSENSE feedback current.
Soft-Start/Run Function
The RUN/SS1 and RUN/SS2 pins are multipurpose pins
that provide a soft-start function and a means to shut
down the LTC3727. Soft-start reduces the input power
source’s surge currents by gradually increasing the
controller’s current limit (proportional to VITH). This pin
can also be used for power supply sequencing.
An internal 1.2μA current source charges up the CSS
capacitor. When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.5V
to 3.0V, the internal current limit is increased from 45mV/
RSENSE to 135mV/RSENSE. The output current limit ramps
up slowly, taking an additional 1.25s/μF to reach full
current. The output current thus ramps up slowly, reducing the starting surge current required from the input
power supply. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:
tDELAY
1.5V
=
CSS = (1.25s / μF ) CSS
1.2μA
tIRAMP =
3V − 1.5V
CSS = (1.25s / μF ) CSS
1.2μA
By pulling both RUN/SS pins below 1V, the LTC3727 is
put into low current shutdown (IQ = 20μA). The RUN/SS
pins can be driven directly from logic as shown in Figure 7. Diode D1 in Figure 7 reduces the start delay but
allows CSS to ramp up slowly providing the soft-start
function. Each RUN/SS pin has an internal 6V zener clamp
(See Functional Diagram).
Fault Conditions: Overcurrent Latchoff (LTC3727 Only)
The RUN/SS pins also provide the ability to latch off the
controller(s) when an overcurrent condition is detected.
VIN
3.3V OR 5V
D1
INTVCC
RUN/SS
RSS*
RSS*
RUN/SS
CSS
CSS
*OPTIONAL TO DEFEAT OVERCURRENT
LATCHOFF (NOT NEEDED WITH THE LTC3727-1)
(7a)
3727 F07
(7b)
Figure 7. RUN/SS Pin Interfacing
The RUN/SS capacitor, CSS, is used initially to turn on and
limit the inrush current. After the controller has been
started and been given adequate time to charge up the
output capacitor and provide full load current, the RUN/SS
capacitor is used for a short-circuit timer. If the regulator’s
output voltage falls to less than 70% of its nominal value
after CSS reaches 4.1V, CSS begins discharging on the
assumption that the output is in an overcurrent condition.
If the condition lasts for a long enough period as determined by the size of the CSS and the specified discharge
current, the controller will be shut down until the RUN/SS
pin voltage is recycled. If the overload occurs during startup, the time can be approximated by:
tLO1 ≅ [CSS (4.1 – 1.5 + 4.1 – 3.5)]/(1.2μA)
= 2.7 • 106 (CSS)
If the overload occurs after start-up the voltage on CSS will
begin discharging from the zener clamp voltage:
tLO2 ≅ [CSS (6 – 3.5)]/(1.2μA) = 2.1 • 106 (CSS)
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin as shown
in Figure 7. This resistance shortens the soft-start period
and prevents the discharge of the RUN/SS capacitor
during an over current condition. Tying this pull-up resistor to VIN, as in Figure 7a, defeats overcurrent latchoff.
Diode-connecting this pull-up resistor to INTV CC, as in
Figure 7b, eliminates any extra supply current during
controller shutdown while eliminating the INTV CC loading
from preventing controller start-up. This pull-up resistor
is not needed in LTC3727-1 designs.
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Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem
with noise pickup or poor layout causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature. If latchoff is
not required, the LTC3727-1 can be used.
The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capacitance is given by:
CSS > (COUT )(VOUT) (10 – 4) (RSENSE)
The minimum recommended soft-start capacitor of
CSS = 0.1μF will be sufficient for most applications.
Fault Conditions: Current Limit and Current Foldback
The LTC3727 current comparator has a maximum sense
voltage of 135mV resulting in a maximum MOSFET current of 135mV/RSENSE. The maximum value of current
limit generally occurs with the largest VIN at the highest
ambient temperature, conditions that cause the highest
power dissipation in the top MOSFET.
The LTC3727 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is overridden. If the
output falls below 70% of its nominal output level, then the
maximum sense voltage is progressively lowered from
135mV to 45mV. Under short-circuit conditions with very
low duty cycles, the LTC3727 will begin cycle skipping in
order to limit the short-circuit current. In this situation the
bottom MOSFET will be dissipating most of the power but
less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time tON(MIN) of
the LTC3727 (less than 200ns), the input voltage and
inductor value:
The resulting short-circuit current is:
ISC =
45mV 1
+ ΔIL(SC)
RSENSE 2
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.
A comparator monitors the output for overvoltage conditions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if VOUT returns to a safe level,
normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
open the system fuse. The switching regulator will regulate properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.
Phase-Locked Loop and Frequency Synchronization
The LTC3727 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the
center frequency fO. A voltage applied to the PLLFLTR pin
of 1.2V corresponds to a frequency of approximately
380kHz. The nominal operating frequency range of the
LTC3727 is 250kHz to 550kHz.
ΔIL(SC) = tON(MIN) (VIN/L)
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The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ΔfH, is equal to the capture range, ΔfC:
ΔfH = ΔfC = ±0.5 fO (250kHz-550kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin.
If the external frequency (fPLLIN) is greater than the oscillator frequency f0SC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f0SC, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor CLP holds the voltage. The
LTC3727 PLLIN pin must be driven from a low impedance
source such as a logic gate located close to the pin. When
using multiple LTC3727s for a phase-locked system, the
PLLFLTR pin of the master oscillator should be biased at
a voltage that will guarantee the slave oscillator(s) ability
to lock onto the master’s frequency. A DC voltage of 0.7V
to 1.7V applied to the master oscillator’s PLLFLTR pin is
recommended in order to meet this requirement. The
resultant operating frequency can range from 310kHz to
470kHz.
The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP =10kΩ and CLP is 0.01μF to
0.1μF.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the LTC3727 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that
tON(MIN) <
VOUT
VIN( f)
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3727 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3727 is generally less
than 200ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
300ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger inductor current and output
voltage ripple.
FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced on
both controllers when the FCB pin drops below 0.8V.
During continuous mode, current flows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
When primary load currents are low and/or the VIN/VOUT
ratio is low, the synchronous switch may not be on for a
sufficient amount of time to transfer power from the
output capacitor to the secondary load. Forced continuous
operation will support secondary windings providing there
is sufficient synchronous switch duty factor. Thus, the
FCB input pin removes the requirement that power must
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be drawn from the inductor primary in order to extract
power from the auxiliary windings. With the loop in
continuous mode, the auxiliary outputs may nominally be
loaded without regard to the primary output load.
The secondary output voltage VSEC is normally set as
shown in Figure 6 by the turns ratio N of the transformer:
VSEC ≅ (N + 1) VOUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then VSEC will droop. An external resistive divider from
VSEC to the FCB pin sets a minimum voltage VSEC(MIN):
⎛ R6 ⎞
VSEC(MIN) ≅ 0.8 V⎜ 1 + ⎟
⎝ R5 ⎠
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added to
the LTC3727 by loading the ITH pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage range of the error amplifier, or
1.2V (see Figure 8).
The resistive load reduces the DC loop gain while maintaining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application. A
complete explanation is included in Design Solutions 10
(see www.Linear.com).
INTVCC
where R5 and R6 are shown in Figure 2.
If VSEC drops below this level, the FCB voltage forces
temporary continuous switching operation until VSEC is
again above its minimum.
In order to prevent erratic operation if no external connections are made to the FCB pin, the FCB pin has a 0.18μA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
The following table summarizes the possible states available on the FCB pin:
Table 1
FCB PIN
CONDITION
0V to 0.75V
Forced Continuous Both Controllers
(Current Reversal Allowed—
Burst Inhibited)
0.85V < VFCB < 6.8V
Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
Feedback Resistors
Regulating a Secondary Winding
>7.3V
Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed No
Minimum Peak Current
RT2
ITH
RT1
RC
LTC3727
CC
3727 F08
Figure 8. Active Voltage Positioning Applied to the LTC3727
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Voltage Positioning
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3727 circuits: 1) LTC3727 VIN current (including loading on the 3.3V internal regulator), 2) INTVCC
regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
1. The VIN current has two components: the first is the DC
supply current given in the Electrical Characteristics table,
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which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output. VIN current typically results in a small (<0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTVCC to
ground. The resulting dQ/dt is a current out of INTVCC that
is typically much larger than the control circuit current. In
continuous mode, IGATECHG =f(QT + QB), where QT and QB
are the gate charges of the topside and bottom side
MOSFETs.
Supplying INTVCC power through the EXTVCC switch input
from an output-derived source will scale the VIN current
required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTVCC current results in approximately 2.5mA of VIN current. This reduces the mid-current
loss from 10% or more (if the driver was powered directly
from VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and RSENSE,
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one
MOSFET can simply be summed with the resistances of L,
RSENSE and ESR to obtain I2R losses. For example, if each
RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE = 10mΩ and RESR
= 40mΩ (sum of both input and output capacitance
losses), then the total resistance is 130mΩ. This results in
losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Efficiency varies as the inverse
square of VOUT for the same external components and
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7) VIN2 IO(MAX) CRSS f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has
adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 22μF to 47μF of capacitance having a maximum
of 20mΩ to 50mΩ of ESR. The LTC3727 2-phase architecture typically halves this input capacitance requirement
over competing solutions. Other losses, including Schottky diode conduction losses during dead-time and inductor core losses, generally account for less than 2% total
additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ΔILOAD (ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTILOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
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overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80% of
full-load current having a rise time of 1μs to 10μs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
why it is better to look at the ITH pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing RC and the bandwidth of the loop will be
increased by decreasing CC. If RC is increased by the same
factor that CC is decreased, the zero frequency will be kept
the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability of
the closed-loop system and will demonstrate the actual
overall supply performance.
A second, more severe transient is caused by switching in
loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • CLOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current to
about 200mA.
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging
into the supply from Hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery, and
double-battery.
Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 9 is the most straight forward
approach to protect a DC/DC converter from the ravages
of an automotive power line. The series diode prevents
current from flowing during reverse-battery, while the
transient suppressor clamps the input voltage during
load-dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamp the input voltage below breakdown of the converter.
Although the LTC3727 has a maximum input voltage of
36V, most applications will be limited to 30V by the
MOSFET BVDSS.
50A IPK RATING
12V
VIN
LTC3727
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
3727 F09
Figure 9. Automotive Application Protection
3727fc
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LTC3727/LTC3727-1
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Design Example
As a design example for one channel, assume VIN =
24V(nominal), VIN = 30V(max), VOUT = 12V, IMAX = 5A and
f = 250kHz.
The inductance value is chosen first based on a 40% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLFLTR pin
to the SGND pin for 250kHz operation. The minimum
inductance for 40% ripple current is:
ΔIL =
VOUT ⎛ VOUT ⎞
⎜ 1–
⎟
( f)(L) ⎝
VIN ⎠
A 14μH inductor will result in 40% ripple current. The peak
inductor current will be the maximum DC value plus one
half the ripple current, or 6A, for the 14μH value.
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
RSENSE ≤
90mV
≈ 0.015Ω
6A
Choosing 1% resistors; R1 = 20k and R2 = 280k yields an
output voltage of 12V.
The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Siliconix Si4412DY results
in: RDS(ON) = 0.042Ω, CRSS = 100pF. At maximum input
voltage with T(estimated) = 50°C:
PMAIN =
12V 2
(5) [1+ (0.005)(50°C – 25°C)]
30 V
(0.042Ω) + 1.7(30V)2 (5A)(100pF )(250kHz)
= 664mW
A short-circuit to ground will result in a folded back current
of:
ISC =
45mV 1 ⎛ 200ns(30 V)⎞
+ ⎜
⎟ = 3.2A
0.015Ω 2 ⎝ 14μH ⎠
with a typical value of RDS(ON) and δ = (0.005/°C)(20) = 0.1.
The resulting power dissipated in the bottom MOSFET is:
PSYNC =
30 V – 12V
2
3.2A ) (1.1)(0.042Ω)
(
30 V
= 284mW
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VORIPPLE = RESR (ΔIL) = 0.02Ω(2A) = 40mVP–P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3727. These items are also illustrated graphically in
the layout diagram of Figure 10; Figure 11 illustrates the
current waveforms present in the various branches of the
2-phase synchronous regulators operating in continuous
mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at CIN? Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
3727fc
25
LTC3727/LTC3727-1
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APPLICATIO S I FOR ATIO
2. Are the signal and power grounds kept separate? The
combined LTC3727 signal ground pin and the ground
return of CINTVCC must return to the combined COUT (–)
terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible to the
(–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop
described above.
3. Do the LTC3727 VOSENSE pins resistive dividers connect to the (+) terminals of COUT? The resistive divider
must be connected between the (+) terminal of COUT and
signal ground. The R2 and R4 connections should not be
along the high current input feeds from the input
capacitor(s).
4. Are the SENSE – and SENSE + leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE + and SENSE – should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the SENSE resistor.
5. Is the INTVCC decoupling capacitor connected close to
the IC, between the INTVCC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1μF ceramic capacitor placed immediately
next to the INTVCC and PGND pins can help improve noise
performance substantially.
RPU
3
R2
R1
4
5
fIN
6
7
8
3.3V
10
11
12
R3
R4
13
14
SENSE1 +
TG1
SENSE1 –
SW1
VOSENSE1
BOOST1
PLLFLTR
VIN
PLLIN
BG1
FCB
EXTVCC
LTC3727
ITH1
SGND
3.3VOUT
ITH2
INTVCC
PGND
BG2
BOOST2
VOSENSE2
SW2
SENSE2 –
TG2
SENSE2 +
RUN/SS2
PGOOD
L1
27
VOUT1
RSENSE
26
25
CB1
M1
M2
D1
24
23
COUT1
RIN
22
CIN
CVIN
21
20
CINTVCC
GND
+
9
PGOOD
+
INTVCC
RUN/SS1
VPULL-UP
(<7V)
+
2
28
+
1
VIN
COUT2
19
18
17
D2
CB2
M3
M4
RSENSE
16
15
VOUT2
L2
3727 F10
Figure 10. LTC3727 Recommended Printed Circuit Layout Diagram
3727fc
26
LTC3727/LTC3727-1
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APPLICATIO S I FOR ATIO
SW1
L1
D1
RSENSE1
COUT1
VOUT1
+
RL1
VIN
RIN
CIN
+
SW2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH
D2
L2
RSENSE2
COUT2
VOUT2
+
RL2
3727 F11
Figure 11. Branch Current Waveforms
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the LTC3727 and occupy minimum PC trace area.
7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the
3727fc
27
LTC3727/LTC3727-1
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APPLICATIO S I FOR ATIO
application. The frequency of operation should be maintained over the input voltage range down to dropout and
until the output load drops below the low current operation threshold—typically 10% to 20% of the maximum
designed current level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for its individual
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current comparator trip point when the other channel is turning on its
top MOSFET. This occurs around 50% duty cycle on either
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.
Short-circuit testing can be performed to verify proper
overcurrent latchoff, or 5μA can be provided to the RUN/
SS pin(s) by resistors from VIN to prevent the short-circuit
latchoff from occurring.
Reduce VIN from its nominal level to verify operation of the
regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If problems coincide with high input voltages and low output
currents, look for capacitive coupling between the BOOST,
SW, TG, and possibly BG connections and the sensitive
voltage and current pins. The capacitor placed across the
current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due to
high frequency capacitive coupling. If problems are encountered with high current output loading at lower input
voltages, look for inductive coupling between CIN, Schottky
and the top MOSFET components to the sensitive current
and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still be
maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
3727fc
28
LTC3727/LTC3727-1
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TYPICAL APPLICATIO S
0.1μF
27pF
20k
1%
10k
2
105k
1%
1000pF
3
4
0.01μF
5
1000pF
fSYNC
7
8
220pF
9
33pF
3.3V
10
11
15k
220pF
12
20k
1%
27pF
13
280k
1%
1000pF
14
SENSE1 +
TG1
SENSE1 –
SW1
VOSENSE1
BOOST1
PLLFLTR
VIN
PLLIN
BG1
FCB
EXTVCC
LTC3727
ITH1
INTVCC
SGND
PGND
3.3VOUT
ITH2
BG2
BOOST2
VOSENSE2
SW2
SENSE2 –
TG2
SENSE2 +
RUN/SS2
28
L1
8μH
PGOOD
27
0.015Ω
VOUT1
5V
5A; 6A PEAK
26
M1A
0.1μF
25
M1B
D1
MBRM
140T3
24
COUT1
47μF
6.3V
23
10Ω
22
CMDSH-3
22μF
50V
0.1μF
GND
21
20
19
1μF
10V
+
15k
PGOOD
+
33pF
6
RUN/SS1
+
1
VPULL-UP
(<7V)
4.7μF
COUT2 100μF 16V
CMDSH-3
18
17
0.1μF
M2A
M2B
D2
MBRM
140T3
VOUT2
12V
4A; 5A PEAK
16
15
L2
15μH
VIN
15V TO
28V
0.015Ω
0.1μF
3727 F12
COUT1: PANASONIC EEFCDOJ470R
COUT2: SANYO OS-CON 16SVP100M
VIN: 15V TO 28V
VOUT: 5V, 5A/12V, 4A
SWITCHING FREQUENCY = 250kHz
MI, M2: FAIRCHILD FDS6680A
L1: 8μH SUMIDA CDEP134-8R0
L2: 15μH COILTRONICS UP4B-150
Figure 12. LTC3727 12V/4A, 5V/5A Regulator with External Frequency Synchronization
3727fc
29
LTC3727/LTC3727-1
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TYPICAL APPLICATIO S
0.1μF
27pF
20k
1%
2
105k
1%
1000pF
3
4
5
6
7
8
220pF
9
33pF
3.3V
10
11
15k
220pF
12
20k
1%
27pF
13
192.5k
1%
1000pF
14
SENSE1 +
TG1
SENSE1 –
SW1
VOSENSE1
BOOST1
PLLFLTR
VIN
PLLIN
BG1
FCB
EXTVCC
LTC3727
ITH1
SGND
3.3VOUT
ITH2
INTVCC
PGND
BG2
BOOST2
VOSENSE2
SW2
SENSE2 –
TG2
SENSE2 +
RUN/SS2
28
L1
8μH
PGOOD
27
VOUT1
5V
5A; 6A PEAK
26
M1A
0.1μF
25
M1B
D1
MBRM
140T3
24
COUT1
47μF
6.3V
23
10Ω
22
CMDSH-3
22μF
50V
0.1μF
GND
21
20
19
1μF
10V
4.7μF
COUT2 100μF 16V
CMDSH-3
18
17
0.1μF
M2A
M2B
L2
8μH
15
VIN
10V TO 15V
D2
MBRM
140T3
VOUT2
8.5V
3A; 4A PEAK
16
0.1μF
COUT1: PANASONIC EEFCDOJ470R
COUT2: SANYO OS-CON 16SVP100M
0.015Ω
+
15k
PGOOD
+
33pF
RUN/SS1
+
1
VPULL-UP
(<7V)
0.015Ω
3727 F13
VIN: 10V TO 15V
VOUT: 5V, 5A/8.5V, 3A
SWITCHING FREQUENCY = 250kHz
MI, M2: FAIRCHILD FDS6680A
L1, L2: 8μH SUMIDA CDEP134-8R0
Figure 13. LTC3727 8.5V/3A, 5V/5A Regulator
3727fc
30
LTC3727/LTC3727-1
U
PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
0.42 ±0.03
5.00 – 5.60**
(.197 – .221)
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
2.0
(.079)
MAX
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
0° – 8°
0.65
(.0256)
BSC
0.55 – 0.95
(.022 – .037)
0.09 – 0.25
(.0035 – .010)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
7.40 – 8.20
(.291 – .323)
0.05
(.002)
MIN
0.22 – 0.38
(.009 – .015)
TYP
G28 SSOP 0204
1 2 3 4 5 6 7 8 9 10 11 12 13 14
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
5.50 ±0.05
4.10 ±0.05
3.50 REF
(4 SIDES)
3.45 ± 0.05
3.45 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
R = 0.05
TYP
0.00 – 0.05
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.115
TYP
31 32
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 ± 0.10
3.45 ± 0.10
(UH32) QFN 0406 REV D
0.25 ± 0.05
0.200 REF
0.50 BSC
3727fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC3727/LTC3727-1
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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PolyPhase is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
3727fc
32 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LT 0507 REV C • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2001