AD AD9288 Dual a/d converter Datasheet

8-Bit, 40/80/100 MSPS
Dual A/D Converter
AD9288
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AINA
T/H
AINA
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
I and Q communications
ADC
8
REFINA
REFOUT
AINB
ENCB
8
T/H
ADC
SELECT 2
8
TIMING
VD
D7A–D0A
SELECT 1
REF
REFINB
AINB
APPLICATIONS
AD9288
TIMING
GND
DATA FORMAT
SELECT
8
VDD
D7B–D0B
00585-001
ENCA
OUTPUT REGISTER
VDD
OUTPUT REGISTER
Dual 8-bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC
Low power: 90 mW at 100 MSPS per channel
On-chip reference and track-and-hold
475 MHz analog bandwidth each channel
SNR = 47 dB @ 41 MHz
1 V p-p analog input range each channel
Single 3.0 V supply operation (2.7 V to 3.6 V)
Standby mode for single-channel operation
Twos complement or offset binary output mode
Output data alignment mode
Pin-compatible 10-bit upgrade available
Figure 1.
GENERAL DESCRIPTION
The AD9288 is a dual 8-bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits. It is
optimized for low cost, low power, small size, and ease of use.
The product operates at a 100 MSPS conversion rate with
outstanding dynamic performance over its full operating range.
Each channel can be operated independently.
The Encode input is TTL/CMOS-compatible, and the 8-bit
digital outputs can be operated from 3.0 V (2.5 V to 3.6 V)
supplies. User-selectable options offer a combination of standby
modes, digital data formats, and digital data timing schemes. In
standby mode, the digital outputs are driven to a high
impedance state.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and an Encode clock for full-performance operation. No
external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS-compatible,
and a separate output power supply pin supports interfacing
with 3.3 V or 2.5 V logic.
Fabricated on an advanced CMOS process, the AD9288 is
available in a 48-lead surface-mount plastic package (7 mm ×
7 mm, 1.4 mm LQFP) specified over the industrial temperature
range (–40°C to +85°C). The AD9288 is pin-compatible with
the 10-bit AD9218, facilitating future system migrations.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD9288* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DOCUMENTATION
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Data Sheet
• AD9288: 8-Bit, 40/80/100 MSPS Dual A/D Converter Data
Sheet
TOOLS AND SIMULATIONS
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REFERENCE MATERIALS
SAMPLE AND BUY
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Technical Articles
DOCUMENT FEEDBACK
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• DNL and Some of its Effects on Converter Performance
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AD9288
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing ......................................................................................... 14
Explanation of Test Levels ........................................................... 4
User-Selectable Options ............................................................ 14
Timing Diagrams.......................................................................... 5
AD9218/AD9288 Customer PCB BOM...................................... 15
Absolute Maximum Ratings............................................................ 7
Evaluation Board ............................................................................ 16
ESD Caution.................................................................................. 7
Power Connector........................................................................ 16
Pin Configuration and Function Descriptions............................. 8
Analog Inputs ............................................................................. 16
Typical Performance Characteristics ............................................. 9
Voltage Reference ....................................................................... 16
Test Circuits..................................................................................... 12
Clocking....................................................................................... 16
Terminology .................................................................................... 13
Data Outputs............................................................................... 16
Theory of Operation ...................................................................... 14
Data Format/Gain ...................................................................... 16
Using the AD9288 ...................................................................... 14
Timing ......................................................................................... 16
Encode Input............................................................................... 14
Troubleshooting.......................................................................... 20
Digital Outputs ........................................................................... 14
Outline Dimensions ....................................................................... 21
Analog Input ............................................................................... 14
Ordering Guide .......................................................................... 21
Voltage Reference ....................................................................... 14
REVISION HISTORY
12/04—Rev. B to Rev. C
Change to Absolute Maximum Ratings......................................... 7
Replaced Evaluation Board Section ............................................. 16
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
2/02—Rev. A to Rev. B
Edits to ABSOLUTE MAXIMUM RATINGS .............................. 3
1/01—Rev. 0 to Rev. A
2/99—Revision 0: Initial Version
Rev. C | Page 2 of 24
AD9288
SPECIFICATIONS
VDD = 3.0 V; VD = 3.0 V, differential input; external reference, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
Gain Error1
Gain Tempco1
Gain Matching
Voltage Matching
ANALOG INPUT
Input Voltage Range (with
Respect to AIN)
Common-Mode Voltage
Input Offset Voltage
Reference Voltage
Reference Tempco
Input Resistance
Input Capacitance
Analog Bandwidth, Full
Power
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulse Width High (tEH)
Encode Pulse Width Low (tEL)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Valid Time (tV)2
Output Propagation Delay
(tPD)2
DIGITAL INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
DIGITAL OUTPUTS3
Logic 1 Voltage
Logic 0 Voltage
POWER SUPPLY
Power Dissipation4
Standby Dissipation4, 5
Power Supply Rejection
Ratio (PSRR)
Temp
Test
Level
25°C
Full
25°C
Full
Full
25°C
Full
Full
25°C
25°C
I
VI
I
VI
VI
I
VI
VI
V
V
Full
V
Full
V
25°C
Full
Full
Full
25°C
Full
25°C
25°C
I
VI
VI
VI
I
VI
V
V
Full
25°C
25°C
25°C
25°C
25°C
Full
Full
VI
IV
IV
IV
V
V
VI
VI
Full
Full
Full
Full
25°C
VI
VI
VI
VI
V
2.0
Full
Full
VI
VI
2.45
Full
Full
25°C
VI
VI
I
Min
AD9288BST-100
Typ
Max
8
± 0.5
+1.25
1.50
+1.25
1.50
± 0.50
–6
–8
0.3 ×
VD
–0.2
–35
–40
1.2
7
5
Min
Guaranteed
± 2.5
± 0.5
± 0.50
± 0.50
Guaranteed
± 2.5
LSB
LSB
LSB
LSB
+6
+8
±512
±512
±512
mV p-p
1.25
± 130
10
0.3 ×
VD
–0.2
–35
–40
1.2
13
16
7
5
0.3 × VD
± 10
1.25
± 130
10
0.3 ×
VD
+0.2
+35
+40
1.3
0.3 ×
VD
–0.2
–35
–40
1.2
13
16
7
5
2
475
100
300
5
3.0
4.5
2
300
5
3.0
4.5
1.25
± 130
10
2
300
5
3.0
4.5
2.0
2.45
2.45
0.05
218
11
20
Rev. C | Page 3 of 24
6.0
0.8
±1
±1
2.0
0.05
171
6
8
207
11
20
156
6
8
V
mV
mV
V
ppm/°C
kΩ
pF
MHz
2.0
0.8
±1
±1
2.0
13
16
1
1000
1000
8.0
8.0
6.0
2.0
0.8
±1
±1
180
6
8
± 10
0.3 ×
VD
+0.2
+35
+40
1.3
40
1
1000
1000
5.0
5.0
6.0
0.3 × VD
2
475
80
1
1000
1000
4.3
4.3
–6
–8
+1.25
1.50
+1.25
1.50
80
±1.5
±15
0.3 ×
VD
+0.2
+35
+40
1.3
+6
+8
± 0.5
Unit
Bits
80
±1.5
±15
2
475
2
Guaranteed
± 2.5
+1.25
1.50
+1.25
1.50
AD9288BST-40
Typ
Max
8
80
±1.5
±15
±10
–6
–8
Min
% FS
% FS
ppm/°C
% FS
mV
0.3 × VD
+6
+8
AD9288BST-80
Typ
Max
8
MSPS
MSPS
ns
ns
ps
ps rms
ns
ns
V
V
µA
µA
pF
0.05
V
V
189
11
20
mW
mW
mV/V
AD9288
Parameter
DYNAMIC PERFORMANCE6
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
(without Harmonics)
fIN = 10.3 MHz
fIN = 26 MHz
fIN = 41 MHz
Signal-to-Noise Ratio
(SINAD) (with Harmonics)
fIN = 10.3 MHz
fIN = 26 MHz
fIN = 41 MHz
Effective Number of Bits
fIN = 10.3 MHz
fIN = 26 MHz
fIN = 41 MHz
Second Harmonic Distortion
fIN = 10.3 MHz
fIN = 26 MHz
fIN = 41 MHz
Third Harmonic Distortion
fIN = 10.3 MHz
fIN = 26 MHz
fIN = 41 MHz
Two-Tone Intermod
Distortion (IMD)
fIN = 10.3 MHz
Temp
Test
Level
25°C
25°C
V
V
2
2
25°C
25°C
25°C
I
I
I
44
44
47.5
47.5
47.0
25°C
25°C
25°C
I
I
I
44
47
47
47
25°C
25°C
25°C
I
I
I
25°C
25°C
25°C
I
I
I
25°C
25°C
25°C
I
I
I
25°C
V
Min
AD9288BST-100
Typ
Max
Min
AD9288BST-80
Typ
Max
Min
2
2
AD9288BST-40
Typ
Max
2
2
Unit
ns
ns
47.5
47
44
47.5
47
47
47
44
47
44
dB
dB
dB
7.5
7.5
7.5
7.0
7.5
7.0
7.0
7.5
7.5
7.5
Bits
Bits
Bits
70
70
70
55
70
55
55
70
70
70
dBc
dBc
dBc
60
60
60
55
60
55
52
60
60
60
dBc
dBc
dBc
60
60
60
dB
dB
dB
dBc
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference).
tV and tPD are measured from the 1.5 V level of the Encode input to the 10%/90% levels of the digital outputs swing. The digital output load during test is not to exceed
an ac load of 10 pF or a dc current of ±40 µA.
3
Digital supply current based on VDD = 3.0 V output drive with < 10 pF loading under dynamic test conditions.
4
Power dissipation measured under the following conditions: fS = 100 MSPS, analog input is –0.7 dBFS, both channels in operation.
5
Standby dissipation calculated with Encode clock in operation.
6
SNR/harmonics based on an analog input voltage of –0.7 dBFS referenced to a 1.024 V full-scale input range.
2
EXPLANATION OF TEST LEVELS
Level
I
II
III
IV
V
VI
Description
100% production tested.
100% production tested at 25°C and sample tested at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range;
100% production tested at temperature extremes for military devices.
Rev. C | Page 4 of 24
AD9288
TIMING DIAGRAMS
SAMPLE N
SAMPLE N + 1
SAMPLE N + 5
AINA, AINB
tA
SAMPLE N + 2
tEH
tEL
SAMPLE N + 3
SAMPLE N + 4
1/fs
ENCODE A, B
tPD
D7A–D0A
DATA N – 4
DATA N – 3
DATA N – 2
DATA N – 1
DATA N
DATA N + 1
D7B–D0B
DATA N – 4
DATA N – 3
DATA N – 2
DATA N – 1
DATA N
DATA N + 1
00585-003
tV
Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
SAMPLE SAMPLE
N
N+1
SAMPLE
N+2
SAMPLE
N+3
SAMPLE
N+4
AINA, AINB
tA
tEH
tEL
1/fs
ENCODE A
tPD
tV
ENCODE B
D7B–D0B
DATA N – 8
DATA N – 6
DATA N – 7
DATA N – 4
DATA N – 5
DATA N – 2
DATA N – 3
DATA N
DATA N – 1
DATA N + 2
DATA N + 1
Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
Rev. C | Page 5 of 24
DATA N + 3
00585-004
D7A–D0A
AD9288
SAMPLE SAMPLE
N
N+1
SAMPLE
N+2
SAMPLE
N+3
SAMPLE
N+4
AINA, AINB
tA
tEH
tEL
1/fs
ENCODE A
tPD
tV
D7A–D0A
DATA N – 8
DATA N – 6
DATA N – 4
DATA N – 2
DATA N
DATA N + 2
D7B–D0B
DATA N – 9
DATA N – 7
DATA N – 5
DATA N – 3
DATA N – 1
DATA N + 1
Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing
Rev. C | Page 6 of 24
00585-005
ENCODE B
AD9288
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VD, VDD
Analog Inputs
Digital Inputs
VREF IN
Digital Output Current
Operating Temperature
Storage Temperature
Maximum Junction Temperature
Maximum Case Temperature
Thermal Impedance θja
Rating
4V
–0.5 V to VD + 0.5 V
–0.5 V to VDD + 0.5 V
–0.5 V to VD + 0.5 V
20 mA
–55°C to +125°C
–65°C to +150°C
150°C
150°C
57°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 7 of 24
AD9288
D0A
D1A
D2A
D3A
D4A
D6A
D5A
GND
D7A (MSB)
VDD
ENCA
VD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
GND 1
PIN 1
IDENTIFIER
AINA 2
AINA 3
36
NC
35
NC
34
GND
33 VDD
DFS 4
REFINA 5
31
GND
VD
30
VD
32
AD9288
REFOUT 6
TOP VIEW
(Not to Scale)
REFINB 7
S1 8
GND
28 VDD
29
S2 9
AINB 10
27
GND
AINB 11
26
NC
GND 12
25
NC
00585-002
D0B
D1B
D2B
D3B
D4B
D5B
D6B
GND
(MSB) D7B
VDD
VD
NC = NO CONNECT
ENCB
13 14 15 16 17 18 19 20 21 22 23 24
Figure 5. Pin Configuration
Table 3.
Pin No.
1, 12, 16, 27, 29,
32, 34, 45
2
3
4
5
6
7
8
9
10
11
13, 30, 31, 48
14
15, 28, 33, 46
17–24
25, 26, 35, 36
37–44
47
Name
GND
Description
Ground
AINA
AINA
DFS
REFINA
REFOUT
REFINB
S1
S2
AINB
AINB
VD
ENCB
VDD
D7B–D0 B
NC
D0A–D7 A
ENC A
Analog Input for Channel A.
Analog Input for Channel A (Complementary).
Data Format Select. Offset binary output available if set low. Twos complement output available if set high.
Reference Voltage Input for Channel A.
Internal Reference Voltage.
Reference Voltage Input for Channel B.
User Select 1. Refer to Table 4. Tied with respect to VD.
User Select 2. Refer to Table 4. Tied with respect to VD.
Analog Input for Channel B (Complementary).
Analog Input for Channel B.
Analog Supply (3 V).
Clock Input for Channel B.
Digital Supply (3 V).
Digital Output for Channel B.
Do Not Connect.
Digital Output for Channel A.
Clock Input for Channel A.
Rev. C | Page 8 of 24
AD9288
TYPICAL PERFORMANCE CHARACTERISTICS
0
–10
–20
72
ENCODE = 100MSPS
AIN = 10.3MHz
SNR = 48.52dB
SINAD = 48.08dB
SECOND HARMONIC = –62.54dBc
THIRD HARMONIC = –63.56dBc
ENCODE RATE = 100MSPS
68
64
2ND
–30
60
dB
dB
–40
56
–50
3RD
52
–60
48
–70
–90
40
SAMPLE
00585-009
44
00585-006
–80
0
10
20
30
40
50
60
70
80
90
MHz
Figure 9. Harmonic Distortion vs. AIN Frequency
Figure 6. Spectrum: fS = 100 MSPS, fIN = 10 MHz, Single-Ended Input
0
0
–10
–20
ENCODE = 100MSPS
AIN = 41MHz
SNR = 47.87dB
SINAD = 46.27dB
SECOND HARMONIC = –54.10dBc
THIRD HARMONIC = –55.46dBc
ENCODE = 100MSPS
AIN1 = 9.3MHz
AIN2 = 10.3MHz
IMD = –60.0dBc
–10
–20
–30
–40
–40
–50
–60
–60
–70
–70
–80
–80
00585-007
–50
–90
00585-010
dB
dB
–30
–90
SAMPLE
SAMPLE
Figure 10. Two-Tone Intermodulation Distortion
Figure 7. Spectrum: fS = 100 MSPS, fIN = 41 MHz, Single-Ended Input
50
0
–10
–20
–30
ENCODE = 100MSPS
AIN = 76MHz
SNR = 47.1dB
SINAD = 43.2dB
SECOND
HARMONIC = –52.2dBc
THIRD HARMONIC = –51.5dBc
ENCODE RATE = 100MSPS
48
SNR
46
SINAD
44
dB
dB
–40
–50
42
–60
40
–70
–90
36
SAMPLE
00585-011
38
00585-008
–80
0
10
20
30
40
50
60
70
MHz
Figure 8. Spectrum: fS = 100 MSPS, fIN = 76 MHz, Single-Ended Input
Figure 11. SINAD/SNR vs. AIN Frequency
Rev. C | Page 9 of 24
80
90
AD9288
49
190
AIN = 10.3MHz
AIN = 10.3MHz
SNR
185
SINAD
180
48
POWER (mW)
dB
175
47
170
165
160
155
46
45
30
40
50
60
70
80
90
100
00585-015
00585-012
150
145
140
110
0
10
20
MSPS
30
40
50
Figure 12. SINAD/SNR vs. Encode Rate
50
70
80
90
100
Figure 15. Analog Power Dissipation vs. Encode Rate
48.0
AIN = 10.3MHz
SNR
ENCODE RATE = 100MSPS
AIN = 10.3MHz
47.5
SINAD
46
60
MSPS
47.0
SNR
46.5
SINAD
42
dB
dB
46.0
45.5
38
45.0
00585-013
30
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
00585-016
44.5
34
44.0
43.5
3.0
–40
ENCODE HIGH PULSE WIDTH (ns)
25
85
TEMPERATURE (°C)
Figure 13. SINAD/SNR vs. Encode Pulse Width High
Figure 16. SINAD/SNR vs. Temperature
0.5
0.6
ENCODE RATE = 100MSPS
ENCODE RATE = 100MSPS
AIN = 10.3MHz
0
0.4
–0.5
0.2
–1.0
–1.5
0
% GAIN
–3dB
–2.5
–3.0
–0.2
–0.4
–3.5
–0.6
–4.0
–4.5
0
100
200
300
400
500
–1.0
600
BANDWIDTH (MHz)
Figure 14. ADC Frequency Response: fS = 100 MSPS
00585-017
–5.0
–5.5
–0.8
00585-014
dB
–2.0
–40
25
85
TEMPERATURE (°C)
Figure 17. ADC Gain vs. Temperature (with External 1.25 V Reference)
Rev. C | Page 10 of 24
AD9288
1.3
2.0
ENCODE = 100MSPS
VD = 3.0V
TA = 25°C
1.5
1.2
1.0
1.1
VREFOUT (V)
LSB
0.5
0
–0.5
1.0
0.9
–1.0
00585-018
–2.0
1.00
0.75
0.50
0.25
0
–0.25
–0.50
00585-019
LSB
0.25
0.50
0.75
1.00
LOAD (mA)
1.25
1.50
Figure 20. Voltage Reference Out vs. Current Load
Figure 18. Integral Nonlinearity
–1.00
0.7
0
CODE
–0.75
00585-020
0.8
–1.5
CODE
Figure 19. Differential Nonlinearity
Rev. C | Page 11 of 24
1.75
AD9288
TEST CIRCUITS
VD
VDD
28kΩ
28kΩ
OUT
AIN
12kΩ
00585-021
12kΩ
00585-024
AIN
Figure 21. Equivalent Analog Input Circuit
Figure 24. Equivalent Digital Output Circuit
VD
VD
VBIAS
REFIN
00585-025
00585-022
OUT
Figure 22. Equivalent Reference Input Circuit
Figure 25. Equivalent Reference Output Circuit
VD
00585-023
ENCODE
Figure 23. Equivalent Encode Input Circuit
Rev. C | Page 12 of 24
AD9288
TERMINOLOGY
Analog Bandwidth (Small Signal)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between a 50% crossing of Encode and the instant at
which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
The deviation of any code from an ideal 1 LSB step.
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
Encode pulse should be left in Logic 1 state to achieve rated
performance; pulse width low is the minimum time Encode
pulse should be left in low state. At a given clock rate, these
specs define an acceptable Encode duty cycle.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The Encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The Encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a 50% crossing of Encode and the time
when all output data bits are within valid logic levels.
Two-Tone Intermodulation Distortion Rejection
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Worst Harmonic
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in
dBc.
Rev. C | Page 13 of 24
AD9288
THEORY OF OPERATION
The AD9288 ADC architecture is a bit-per-stage pipeline-type
converter utilizing switch capacitor techniques. These stages
determine the 5 MSBs and drive a 3-bit flash. Each stage
provides sufficient overlap and error correction, allowing
optimization of comparator accuracy. The input buffers are
differential, and both sets of inputs are internally biased. This
allows the most flexible use of ac or dc and differential or
single-ended input modes. The output staging block aligns the
data, carries out the error correction, and feeds the data to
output buffers. The set of output buffers are powered from a
separate supply, allowing adjustment of the output voltage
swing. There is no discernible difference in performance
between the two channels.
USING THE AD9288
Good high speed design practices must be followed when
using the AD9288. To obtain maximum benefit, decoupling
capacitors should be physically as close as possible to the chip,
minimizing trace and via inductance between chip pins and
capacitor (0603 surface-mount capacitors are used on the
AD9288/PCB evaluation board). It is recommended to place a
0.1 µF capacitor at each power-ground pin pair for high
frequency decoupling, and to include one 10 µF capacitor for
local low frequency decoupling. The VREF IN pin should also
be decoupled by a 0.1 µF capacitor. It is also recommended to
use a split power plane and a contiguous ground plane (see the
Evaluation Board section). Data output traces should be short
(< 1 inch), minimizing on-chip noise at switching.
ENCODE INPUT
Any high speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A track-andhold circuit is essentially a mixer. Any noise, distortion, or
timing jitter on the clock is combined with the desired signal at
the A/D output. For that reason, considerable care has been
taken in the design of the Encode (Clock) input of the AD9288,
and the user is advised to give commensurate thought to the
clock source. The Encode input is fully TTL/CMOS-compatible.
DIGITAL OUTPUTS
The digital outputs are TTL/CMOS-compatible for lower power
consumption. During standby, the output buffers transition to a
high impedance state. A data format selection option supports
either twos complement (set high) or offset binary output (set
low) formats.
ANALOG INPUT
The analog input to the AD9288 is a differential buffer. For best
dynamic performance, impedance at AIN and AIN should match.
Special care was taken in the design of the analog input stage of
the AD9288 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is 1.024 V p-p
centered at VD × 0.3.
VOLTAGE REFERENCE
A stable and accurate 1.25 V voltage reference is built into the
AD9288 (REFOUT). In normal operation, the internal reference
is used by strapping Pins 5 (REFINA) and 7 (REFINB) to Pin 6
(REFOUT). The input range can be adjusted by varying the
reference voltage applied to the AD9288. No appreciable
degradation in performance occurs when the reference is
adjusted ±5%. The full-scale range of the ADC tracks reference
voltage, which changes linearly.
TIMING
The AD9288 provides latched data outputs, with four pipeline
delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the Encode command (see Figure 2,
Figure 3, and Figure 4). The length of the output data lines and
loads placed on them must be minimized to reduce transients
within the AD9288. These transients can detract from the
converter’s dynamic performance.
The minimum guaranteed conversion rate of the AD9288 is
1 MSPS. At clock rates below 1 MSPS, dynamic performance
degrades. Typical power-up recovery time after standby mode is
15 clock cycles.
USER-SELECTABLE OPTIONS
Two pins are available for a combination of operational modes.
These options allow the user to place both channels, excluding
the reference, into standby mode, or just the B channel. Both
modes place the output buffers and clock inputs into high
impedance states.
The other option allows the user to skew the B channel output
data by 1/2 of a clock cycle. In other words, if two clocks are fed
to the AD9288 and are 180° out of phase, enabling the data
align allows Channel B output data to be available at the rising
edge of Clock A. If the same Encode clock is provided to both
channels and the data align pin is enabled, then output data
from Channel B is 180° out of phase with respect to Channel A.
If the same Encode clock is provided to both channels and the
data align pin is disabled, both outputs are delivered on the
same rising edge of the clock.
Table 4. User-Selectable Options
S1
S2
Option
0
0
Standby Both Channels A and B.
0
1
1
1
0
1
Standby Channel B Only.
Normal Operation (Data Align Disabled).
Data Align Enabled (data from both channels available on rising edge of Clock A. Channel B data is
delayed a 1/2 clock cycle).
Rev. C | Page 14 of 24
AD9288
AD9218/AD9288 CUSTOMER PCB BOM
Table 5. Bill of Materials
No.
Qty.
Reference Designator
Device
Package
Value
1
29
Capacitor
0603
0.1 µF
2
3
4
2
7
28
Capacitor
Capacitor
W-HOLE
0603
TAJD
W-HOLE
15 pF
10 µF
5
6
7
8
4
5
3
3
C1, C3-C15, C20, C21, C24,
C25, C27, C30–C35, C39–C42
C2, C36
C16–C19, C26, C37, C38
E1, E2, E3, E4, E12–E30,
E34–E38
H1, H2, H3, H4
J1, J2, J3, J4, J5
P1, P4, P11
P1, P4, P11
MTHOLE
SMA
4-pin power connector
4-pin power connector
MTHOLE
SMA
Post
Detachable
Connector
9
1
P2, P31
80-pin rt. angle male
10
4
R1, R2, R32, R34
Resistor
0603
TSW-140-08L-D-RA
36 Ω
11
9
R3, R7, R11, R14, R22, R23,
R24, R30, R51
Resistor
0603
50 Ω
12
17
Resistor
0603
Zero Ω
13
2
R4, R5, R8, R9, R10, R12, R13,
R20, R33, R35, R36, R37, R40,
R42, R43, R50, R53
R6, R38
Resistor
0603
25 Ω
14
6
R15, R16, R18, R26, R29, R31
Resistor
0603
500 Ω
15
16
17
2
2
12
R17, R25
R19, R27
R21, R28, R39, R41, R44,
R46–R49, R52, R54, R55
Resistor
Resistor
Resistor
0603
0603
0603
525 Ω
4 kΩ
1 kΩ
18
19
20
21
22
23
2
1
2
2
4
2
T1, T2
U1
U2, U3
U5, U6
U7, U8, U9, U10
U11, U12
Transformer
AD92882
74LCX821
SN74VCX86
Resistor array
AD8138 op amp3
ADT1-1WT
LQFP48
1
P2, P3 are implemented as one physical 80-pin connector SAMTEC TSW-140-08-L-D-RA.
AD9288/PCB populated with AD9288-100.
3
To use optional amp: place R22, R23, R30, R24, R16, R29, remove R4, R36.
2
Rev. C | Page 15 of 24
CTS
Z5.531.3425.0
25.602.5453.0
Comments
8138 out
J2, J3, not placed
Wieland
Wieland
Samtec
R1, R2, R32, R34,
not placed
R11, R22, R23,
R24, R30, R51
not placed
R43, R50
not placed
R6, R38
not placed
R16, R29
not placed
Minicircuits
47 Ω
768203470G
AD9288
EVALUATION BOARD
The AD9218/AD9288 customer evaluation board offers an easy
way to test the AD9218 or the AD9288. The compatible pinout
of the two parts facilitates the use of one PCB for testing either
part. The PCB requires power supplies, a clock source, and a
filtered analog source for most ADC testing required.
CLOCKING
POWER CONNECTOR
DATA OUTPUTS
Power is supplied to the board via a detachable 12-lead power
strip. The minimum 3 V supplies required to run the board are
VDD, VDL, and VDD. To allow the use of the optional amplifier
path, ±5 V supplies are required.
The data outputs are latched on-board by two 10-bit latches and
drive an 8-pin connector which is compatible with the dualchannel FIFO board available from Analog Devices. This board,
together with ADC analyzer software, can greatly simplify ADC
testing.
ANALOG INPUTS
Each channel has an independent analog path that uses a
wideband transformer to drive the ADC differentially from a
single-ended sine source at the input SMAs. The transformer
paths can be bypassed to allow the use of a dc-coupled path by
using two AD8138 op amps with a simple board modification.
The analog input should be band-pass filtered to remove any
harmonics in the input signal and to minimize aliasing.
VOLTAGE REFERENCE
The AD9288 has an internal 1.25 V voltage reference; an
external reference for each channel can be used instead by
connecting two external voltage references at the power
connector and setting jumpers at E18 and E19. The evaluation
board is shipped configured for internal reference mode.
Each channel can be clocked by a common clock input at SMA
input ENCODE A/B. The channels can also be clocked
independently by a simple board modification. The clock input
should be a low jitter sine source for maximum performance.
DATA FORMAT/GAIN
The DFS/Gain pin can be biased for desired operation at the DFS
jumper located at the S1, S2 jumpers.
TIMING
Timing on each channel can be controlled if needed on the
PCB. Clock signals at the latches or the data ready signals that
go to the output 80-pin connector can be inverted if required.
Jumpers also allow for biasing of Pins S1 and S2 for powerdown and timing alignment control.
Rev. C | Page 16 of 24
GND
P1
C31
0.1µF
C14
0.1µF
R5
00Ω
R4
00Ω
AMPOUTAB
R2
36Ω
GND
GND
R1
36Ω
AMPOUTA
5
4
2
3
2
3
4
VDD
GND
VD
2
3
4
P4
1
VDL
R35
00Ω
6
R36
00Ω
R37
00Ω
1
2
3
4
VREFA
GND
GND
P11
R38
25Ω
C39
0.1µF
GND
+5V
–5V
E1
VDD
VDL
P7
C17 +
10µF
P6
AINB
AINB
10
11
C18 +
10µF
VDL
C5
0.1µF
C8
0.1µF
GND
GND
GND
R54
1kΩ
R52
1kΩ
VDL
C42
0.1µF
TIEB
R50
51Ω
AD9218/AD9288
U1
VREFB
C6
0.1µF
C26 +
10µF
VREFA
C19 +
10µF
S2
9
GND
S1
8
12
REFINB
REFOUT
REFINA
DFS/GAIN
AINA
AINA
GND
GND
7
6
5
4
VDD
GND
VD
C16 +
10µF
VD
GND
E19
E17
E18
P5
+5V
C38 +
+ 10µF
–5V
E20
3
2
1
C7
0.1µF
VDL
E15
VDL
E12
GND
GND
GND
R47
1kΩ
E14
GND
E13
R46
1kΩ
GND
VREFA
CLKLATA
DRA
VD E29 E24
E22
GND
C37
10µF
GND
C30
0.1µF
GND
E30
E25
E27
VD
E2
REFOUT
GND
R9
00Ω
C9
0.1µF
VD E28 E23
E26
R6
25Ω
3Y 8
R10
00Ω
C10
0.1µF
3A 9
GND
3B 10
2Y
VREFB
AMPOUTB
R32
36Ω
GND
GND
R34
36Ω
AMPOUTBB
R SINGLE-ENDED
1
T1
GND
7
R SINGLE-ENDED
4
5
2
3
6
1
R33
00Ω
6
GND
2B
4Y 11
2A
4
5
4A 12
4B 13
VCC 14
1Y
1B
1A
3
2
1
ENCXA
GND
R44
1kΩ
E4
1
C15
0.1µF
C13
0.1µF
C12
0.1µF
E3
T2
R43
00Ω
VDL
C11
0.1µF
GND
AMPINB
GND
GND
AMPINA
R7
50Ω
GND
AIN B
GND
J1
GND
R41
1kΩ
R39
1kΩ
VDL
R3
50Ω
GND
C40
0.1µF
AIN A
GND
J4
GND
R11
50Ω
ENCODE A
J3
TIEA
ENCODE B
J2
VD
VD 48
VDL
ENCA
ENCA 47
C25
0.1µF
GND
ENCA
VDD
VDD 46
VDD
VDD
R42
00Ω
VDL
GND
GND
GND
REFINA
C27
0.1µF
GND
R49
1kΩ
E36
GND
GND 32
D0B
D1B
D0B 26
D1B 25
REFINB
C24
0.1µF
GND
GND
GND 27
VDD 28
GND 29
VD 30
VD 31
GND
GND
VDD 33
D0A
GND
GND
J5
VDD
C3
0.1µF
VD
GND
MTHOLE6
H4
MTHOLE6
H2
MTHOLE6
H1
MTHOLE6
H3
R14
50Ω
R8
00Ω
R40
00Ω
R20
00Ω
ENCB
TIEB
TIEA
GND
TO TIE CLOCKS TOGETHER
ENCA
GND
C1
0.1µF
VDD
GND
R55
1kΩ
E37
GND
E34
R48
1kΩ
DRB
CLKLATB
GND R12
00Ω
VDL
E38
VDL
E16
**DUT CLOCK SELECTABLE**
**TO BE DIRECT OR BUFFERED**
R13
00Ω
C4
0.1µF
1A 1
VCC
14
D0A 35
GND 34
1B 2
4B
13
GND
1Y 3
4A
12
D1A
2A 4
2B 5
3B
10
4Y
2Y 6
3A
9
11
GND 7
3Y
8
U5
74LCX86
ENCB
D1A 36
GND
C41
0.1µF
VDL
E35
ENCXB
R50
00Ω
D9A (MSB)
16
GND
ENCXA
D8A
D9A 44
D9B
17
(MSB) D9B
D8B
18
D8B
GND
D7A
D8A 43
D7A 42
D7B
19
D7B
U6
74LCX86
D6A
D6A 41
D6B
20
D6B
GND
R53
00Ω
D5A
D5A 40
D5B
21
D5B
VD
13
VD
D4A
D4A 39
22
D4B
ENCB
14
ENCB
D3A
D3A 38
D4B
D2A
D2A 37
D3B
23
D2B
24
D3B
Rev. C | Page 17 of 24
D2B
Figure 26. PCB Schematic
15
GND 45
ENCXB
00585-026
**DUT CLOCK SELECTABLE**
**TO BE DIRECT OR BUFFERED**
AD9288
R31
500Ω
R15
500Ω
Rev. C | Page 18 of 24
Figure 27. PCB Schematic (Continued)
C34
0.1µF
–5V
R29
500Ω
5
5
V+ 3
R22
50Ω
R30
50Ω
GND
C35
0.1µF
R21
1kΩ
R19
4kΩ
+5V
GND
R28
1kΩ
R27
4kΩ
GND
+5V
R25
525Ω
GND
AMPOUTBB
U12
+OUT 4
C36
15pF
–OUT
V–
VOCM 2
NC
7
6
–IN 1
+IN
AD8138
C32
0.1µF
GND
+5V
+5V
R16
525Ω
AMPINA
AMPOUTA
U11
8
AMPOUTB
R24
50Ω
V+ 3
+OUT 4
C2
15pF
–OUT
V–
VOCM 2
NC
7
6
–IN 1
+IN
AD8138
8
AMPOUTAB
R23
50Ω
AMPINB
C33
0.1µF
–5V
R17
500Ω
GND
OPAMP INPUT OFF PIN ONE OF TRANSFORMER
R26
500Ω
R18
500Ω
3 3
4 4
D7A
D6A
3 3
4 4
D2B
D3B
8 8
9 9
10 10
D8B
D9B
7 7
D6B
D7B
6 6
D5B
5 5
2 2
D4B
1 1
D1B
10 10
D0A
D0B
9 9
D1A
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
U8
CTS20
VALUE = 50
8 8
7 7
D3A
D2A
6 6
D4A
5 5
2 2
D8A
D5A
1 1
D9A
U7
CTS20
VALUE = 50
D9N
D8N
D7N
D6N
D5N
D4N
D3N
D2N
D1N
D0N
D0M
D1M
D2M
D3M
D4M
D5M
D6M
D7M
D8M
D9M
12 GND
GND
10 X8
11 X9
12 GND
D9N
GND
9 X7
8 X6
7 X5
6 X4
5 X3
4 X2
3 X1
2 X0
1 OE
D8N
D7N
D6N
D5N
D4N
D3N
D2N
D1N
D0N
GND
11 X9
D0M
CLK 13
Y9 14
Y8 15
Y7 16
Y6 17
Y5 18
Y4 19
Y3 20
Y2 21
Y1 22
Y0 23
VCC 24
CLK 13
Y9 14
Y8 15
Y7 16
Y6 17
Y5 18
Y4 19
Y3 20
Y2 21
Y1 22
Y0 23
VCC 24
U3
74LCX821
10 X8
9 X7
8 X6
7 X5
6 X4
5 X3
4 X2
3 X1
2 X0
1 OE
D1M
D2M
D3M
D4M
D5M
D6M
D7M
D8M
D9M
GND
U2
74LCX821
D0X
D1X
D2X
D3X
D4X
D5X
D6X
D7X
D0Y
D9Y
D8Y
D7Y
D6Y
D5Y
D4Y
D3Y
D2Y
D1Y
CLKLATB
D9Y
D8Y
D7Y
D6Y
D5Y
D4Y
D3Y
D2Y
D1Y
D0Y
VDL
C20
0.1µF
GND
D9X
D8X
CLKLATA
D0X
D1X
D2X
D3X
D4X
D5X
D6X
D7X
D8X
D9X
VDL
C21
0.1µF
GND
10 10
9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
U10
CTS20
VALUE = 50
10 10
9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
U9
CTS20
VALUE = 50
GND
D9Q
D8Q
D7Q
D6Q
D5Q
D4Q
D3Q
D2Q
D1Q
D0Q
GND
D0P
D1P
D2P
D3P
D4P
D5P
D6P
D7P
D8P
D9P
GND
11 11
9 9
12 12
10 10
3 3
1 1
4 4
2 2
3 3
1 1
4 4
2 2
9 9
10 10
5 5
11 11
12 12
6 6
13 13
14 14
7 7
15 15
16 16
8 8
17 17
19 19
21 21
23 23
25 25
27 27
29 29
31 31
33 33
35 35
37 37
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
39 39
5 5
6 6
40 40
7 7
8 8
P2
HEADER40
GND
13 13
14 14
GND
GND
GND
GND
GND
GND
GND
D0Q
D1Q
D2Q
D3Q
D4Q
D5Q
D6Q
D7Q
D8Q
D9Q
GND
DRB
GND
GND
GND
GND
GND
GND
D0P
15 15
16 16
D1P
D2P
D3P
D4P
D5P
D6P
D7P
D8P
D9P
GND
DRA
GND
17 17
19 19
21 21
23 23
25 25
27 27
29 29
31 31
33 33
35 35
37 37
39 39
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
P3
HEADER40
AD9288
00585-027
00585-031
00585-028
AD9288
00585-032
Figure 31. Split Power Plane
00585-029
Figure 28. Top Silkscreen
Figure 32. Bottom Routing
00585-030
00585-033
Figure 29. Top Routing
Figure 33. Bottom Silkscreen
Figure 30. Ground Plane
Rev. C | Page 19 of 24
AD9288
TROUBLESHOOTING
If the board does not seem to be working correctly, try the
following:
The AD9218/AD9288 evaluation board is provided as a design
example for customers of Analog Devices, Inc. ADI makes no
warranties, express, statutory, or implied, regarding
merchantability or fitness for a particular purpose.
•
Verify power at the IC pins.
•
Check that all jumpers are in the correct position for the
desired mode of operation.
•
Verify that VREF is at 1.23 V.
•
Try running Encode clock and analog inputs at low speeds
(20 MSPS/1 MHz) and monitor LCX821 outputs, DAC
outputs, and ADC outputs for toggling.
Rev. C | Page 20 of 24
AD9288
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
37
48
36
1
1.45
1.40
1.35
0.15
0.05
PIN 1
SEATING
PLANE
10°
6°
2°
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
0.20
0.09
VIEW A
7°
3.5 °
0°
0.08 MAX
COPLANARITY
SEATING
PLANE
25
12
13
24
0.50
BSC
VIEW A
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
Figure 34. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9288BST-40
AD9288BSTZ-401
AD9288BSTZRL-401
AD9288BST-80
AD9288BSTZ-801
AD9288BST-100
AD9288BSTZ-1001
AD9288/PCB
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
48-Lead Low Profile Quad Flat Package
48-Lead Low Profile Quad Flat Package
48-Lead Low Profile Quad Flat Package
48-Lead Low Profile Quad Flat Package
48-Lead Low Profile Quad Flat Package
48-Lead Low Profile Quad Flat Package
48-Lead Low Profile Quad Flat Package
Evaluation Board
Z = Pb-free part.
Rev. C | Page 21 of 24
Package Options
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
AD9288
NOTES
Rev. C | Page 22 of 24
AD9288
NOTES
Rev. C | Page 23 of 24
AD9288
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00585–0–12/04(C)
Rev. C | Page 24 of 24