A4930 Single Phase Fan Pre-Driver Features and Benefits Description ▪ Synchronous rectification for low power dissipation ▪ Drives four N-channel MOSFETs ▪ Internal UVLO and thermal shutdown circuitry ▪ Hall element input ▪ PWM current limiting ▪ Dead time protection ▪ FG output ▪ RD output ▪ Lock detect protection ▪ High VBB absolute maximum ▪ Soft start Designed for pulse width modulated (PWM) current control of single phase brushless fans, the A4930 minimizes external component count and integrates all the key features required for high-current fans. Internal synchronous rectification control circuitry is provided to improve power dissipation in the external MOSFETs during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, rotor lock, and dead time protection. The A4930 is supplied in a 0.90 nominal overall height, 5 mm × 5 mm, 28-pin QFN with exposed thermal pad, (suffix ET). It is lead (Pb) free with 100% matte tin leadframe plating. Package: 28-pin QFN with exposed thermal pad (suffix ET) Approximate size Functional Block Diagram Hall VREG5 500 Ω 5V CP1 CP2 0.1 μF VREG8 0.1 μF 8V 0.1 μF CHARGE PUMP VCP CLD 0.1 μF 0.1 μF RD Lock Detect VBB FGO +12V 0.22 μF Hall Hall HP 10 μF HN VCP VREG8 GHA 3.5v VREG5 HP HN SA PWM Hall GATE DRIVE 1.5v SIN VREG5 0.1 μF Control Logic 5 kΩ Fan GHB SB GLB GLA SMIN 8.2 kΩ SENSE vref /5 CPWM VREF 51 kΩ 1.24 kΩ CDEL GND SS GND 4930-DS, Rev. 1 100 mΩ 5 kΩ 470 pF 0.47 μF VREG5 A4930 Single Phase Fan Pre-Driver Selection Guide Part Number Ambient Operating Temperature, TA (°C) A4930GETTR-T A4930METTR-T Packing –40 to 105 –20 to 105 1500 pieces per 7-in. reel Absolute Maximum Ratings Rating Units Load Supply Voltage Characteristic Symbol VBB 36 V Hall Input VHx –0.3 to 6 V Logic Input Voltage Range VIN –0.3 to 6 V Operating Temperature Range TA Junction Temperature Notes Range G –40 to 105 ºC Range M –20 to 105 ºC TJ(max) 150 ºC Tstg –55 to 150 ºC Storage Temperature Range THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Test Conditionsa Symbol Package Thermal Resistance (Junction to Ambient) RθJA 4-layer PCB based on JEDEC standard 2-layer PCB with 0.7 in.2 copper area Power Dissipation, PD (m W) Package Thermal Resistance RθJC (Junction to Case) aAdditional thermal information available on Allegro website. bEstimated. Power Dissipation versus Ambient Temperature 4000 3750 3500 3250 3000 2750 2500 2250 2000 1750 1500 1250 1000 750 500 250 0 25 Value Units 32 ºC/W 65 ºC/W 20b ºC/W (R QJ (R QJA 50 =6 A = 5º 32 ºC C/W /W ) ) 75 100 Temperature (°C) 125 150 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4930 Single Phase Fan Pre-Driver ELECTRICAL CHARACTERISTICS1 valid at TA = 25°C, VBB = 12 V, unless noted otherwise Characteristic Symbol Test Conditions Min. Typ.2 Max. Units Load Supply Voltage Range VBB Operating 8 12 36 V Motor Supply Current IBB fPWM < 30 kHz, Cload = 1000 pf – 5 7 mA V5 Iload = 10 mA 4.7 5 5.3 V 15 – – mA – 12 30 mV VIN(1) 2 – – V VIN(0) – – 0.8 V VREG5 VREG5 Current Limit IREG5 VREG5 Load Regulation VREG5 IREG5 = 1 to 10 mA Control Logic Logic Input Voltage PWM Pin Input Current IIN(0) VIN = 0, 50 kΩ pull-up – –100 – μA Other Logic Pin Input Current IIN(1) VIN = 3.3 – –34 – μA High Side Gate Drive Output VGHx Relative to VBB, VBB = 12 V Low Side Gate Drive Output VGLx Gate Drive Gate Drive Current Turn-on IG GHx = GLx = 4 V 7 – – V 7 – 8.5 V – 20 – mA Gate Drive Pulldown RDS – 40 – Ω Dead Time tDEAD 700 1000 1300 ns Control tSS CLD = 0.47 μF – 300 – ms Internal PWM Frequency fPWM CPWM = 470 pF 15 21 27 kHz CPWM Output Voltage VPP CPWM = 470 pF – 2 – V CPWM Low Threshold VLO – 1.5 – V CPWM High Threshold VHI – 3.5 – V SIN Input Impedance ZIN – 200 – kΩ TJTSD – 165 – °C TJTSDhys – 15 – °C Soft Start Time Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4930 Single Phase Fan Pre-Driver ELECTRICAL CHARACTERISTICS1 (continued) valid at TA = 25°C, VBB = 12 V, unless noted otherwise Characteristic Symbol VBB Undervoltage Lockout Enable Threshold VBBUV VBB Undervoltage Lockout Hysteresis VCP Undervoltage Lockout Enable Threshold Test Conditions Rising VBB VBBUVhys VCPUV Min. Typ.2 Max. Units – 7.5 7.85 V 0.3 0.8 – V Relative to VBB, VBB rising – 5.4 – V Lock Detect On-Time tLDon CLD = 0.1 μF – 1 – s Lock Detect Off-Time tLDoff CLD = 0.1 μF – 15 – s Hall Input Current IHALL VIN = 1.2 V –1 0 1 μA Common Mode Input Range VCMR 0.2 – 3 V AC Input Voltage Range VHALL 60 – – mVp-p – 10 – mV 5 20 35 mV Hall Logic Hall Threshold Hysteresis Width Vth Difference in Halls at FG transition VHYS Pulse Reject Filter tCD 1 2 3 μs Commutation Delay VPU RCDEL = 50 kΩ – 50 – mV Output Saturation Voltage VOL I = 2 mA – 0.27 0.4 V Leakage Current VOH V=5V – – 1 μA FG and RD Outputs 1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4930 Single Phase Fan Pre-Driver Functional Description VREG5 This pin should be decoupled with a 0.1 μF capacitor to ground. VREG5 can supply up to 15 mA, which can used to power the external Hall element. VREG8 This pin should be decoupled with a 0.1 μF capacitor to ground. VREG8 is used to power the low-side gate drive circuits. Charge Pump The charge pump is used to generate a supply above VBB to drive the high-side MOSFETs. The VCP voltage is internally monitored, and in the case of a fault condition, the outputs of the device are disabled. Lock Detect The IC detects a locked rotor condition by checking to ensure that the FG output signal is continuously changing. The length of time allowed for a stoppage before evaluating a locked condition, tLD, is set by capacitor connected to CLD pin. CLD produces a triangle waveform with a frequency that is linearly related to the capacitor value. The definition of tLD is defined as 8 cycles of this triangle waveform, and its value can be calculated as: tLD = CLD × (10 s / μF) . (1) If an FG transition is not detected within tLD, the IC will disable the appropriate source driver and hold both sink drivers on. The circuit will automatically retry with a 15:1 ratio of off-time to ontime. An RD pin logic high indicates this fault condition. Current Limit and Soft Start To minimize demand on the power supply, peak current is controlled. Initially, with the fan at a stand-still, the turn-on of the bridge results in current rising according to the L/R time constant of the motor. To prevent overstress, this peak current is regulated by an internal PWM control circuit. When the outputs of the full-bridge are turned on, current increases in the motor winding until it reaches a value given by: ITRIP = VREF / 5 × RSENSE . (2) The RSENSE value should be chosen to keep the peak sense voltage within the range of 200 to 500 mV, according to the relationship: RSENSE < 500 mV / ITRIP . (3) At the trip point, the sense comparator resets the source enable latch, turning off the source driver. At this point, load inductance causes the current to recirculate for 50 μs. A soft start capacitor, CSS, can be connected to the SS pin to set the rate for slowly ramping-up the load current to the maximum value, according to the relationship: tSS = (CSS × VREF) / 3.3E–6 . (4) In this case the current limit will likely not be achieved and there will be less demand on the input power supply. If this feature is not utilized, the SS pin should be left open. Synchronous Rectification When a PWM off-cycle is triggered, load current recirculates. The A4930 synchronous rectification feature turns on the appropriate MOSFETs during current decay, and effectively shorts out the body diodes of the low RDS(on) driver. TSD If the die temperature exceeds approximately 165°C, the outputs will be disabled until the internal temperature falls below a hysteresis level of 15°C. Shutdown In the event of a fault due to excessive junction temperature, or low voltage on VCP or VBB, the outputs of the device are disabled until the fault condition is removed. At power-up the UVLO circuit disables the drivers until the UVLO threshold is reached. CPWM This capacitor sets the frequency of the internal PWM circuit. The value is typically from 15 to 30 kHz. PWM The IC accepts a direct input PWM signal with a level in the range from 0 to 6 V. The duty cycle, DC, of the input to this pin is converted to an analog voltage that is output on the SIN terminal as follows: VSIN = 3.5 V –2 × DC . (5) If the PWM input is not used, then leave this pin open circuit. Direct external PWM control can be utilized by applying the signal to the SIN input (refer to the Applications Information section). This can be implemented to create different PWM input to PWM output transfer functions. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4930 Single Phase Fan Pre-Driver SIN An analog voltage input to this pin sets the duty cycle applied to the fan winding. For temperature-based systems, connect SIN to a thermistor output. For systems with direct input to the PWM pin, the pin should be decoupled with a 0.1 μF capacitor. If variable fan speed is not required, for 100% duty cycle, connect this pin to GND. The input impedance is 200 kΩ (referenced to a 3.5 or 1.5 V rail). SMIN An analog voltage input to this pin sets the minimum speed duty cycle to the fan winding. The PWM comparator chooses either SIN or SMIN to determine the output duty cycle, which- ever is set to a lower voltage. For 100% duty cycle applications, connect this pin to GND. CDEL A resistor connected between this pin and GND sets the level at which the A4930 switches to slow decay mode in advance of the Hall zero crossing as shown here: VCDEL = (2950 / RCDEL) – 7 mV . (mV) (6) The resistor should be 25 to 100 kΩ. If this feature is not used, the CDEL pin should be pulled up to VREG5 with a 5 kΩ resistor. LD FG HP 0 VCDEL(1) VCDEL(2) Vth(1) Vth(2) Vth(1) = VHP – VHN = 10 mV (Typical) Vth(2) = VHN – VHP = 10 mV (Typical) VHYS = Vth(1) + Vth(2) = 20 mV (Typical) HN SA SB tCDEL Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4930 Single Phase Fan Pre-Driver Applications Information Overvoltage In a typical fan application, there is a blocking diode that prevents currents from flowing back out of the fan assembly to the 12 V supply. When the fan commutates before the current has decayed to zero, the current charges up the VBB bypass capacitor. The larger the bypass capacitor, the less the voltage overshoot. Typically, a clamp diode is required to dissipate energy from the inductive kickback to avoid exceeding the maximum rating for VBB , 36 V. Layout Small form factor PCBs present a layout challenge for the application. The layout would be restricted by the placement of the Hall element, the location of the motor connectors, and the common requirement that all components be placed on one side of the PCB. For optimum results, consider the following recommendations: • Place the external MOSFET bridge close to the power connector. The bridge includes two dual N-channel MOSFETs, a sense resistor, and a power supply capacitor. This will keep the large current flows in one area of the PCB and avoid ground loop problems. • Keep the sense connection to the power bridge as short as possible. This can be achieved by positioning the MOSFETs next to each other, and by connecting the source of the sink side MOSFETs via a short trace, preferably on the surface of the PCB, under the MOSFETs. A short trace here would minimize voltage spikes due to inductance in the path, where currents switch at high di/dt. • Place the power traces from the MOSFETs to the motor connector on the opposite side of the PCB. If possible, on that side isolate the power traces by ground traces in order to minimize interference with other signal traces due to the high dv/dt of the power traces. • Locate the A4930 to minimize the length of the GHx/GLx/Sx traces to the power stage. • Connect the GND pins of the A4930 to the exposed pad. Use vias under the IC case to connect the exposed pad to the ground plane on the opposite face of the PCB. External PWM Refering to the figure below, if external PWM control is being used, the high voltage level is set by R1, R2, and R3. The low voltage level is set by R1 and R3. VREG5 0.1 μF PWM R1 10 kΩ PWM Duty In + 0.47 μF R2 R3 Control Logic SIN 5 kΩ SMIN – CPWM 8.2 kΩ PWM control using External PWM input Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4930 Single Phase Fan Pre-Driver 22 GHA 23 GND 24 CP1 25 CP2 26 VCP 27 VBB 28 NC Pin-out Diagram VREG5 1 21 SA CLD 2 20 GHB FG 3 RD 4 HP 5 17 GLA HN 6 16 GLB CDEL 7 15 SENSE 19 SB GND 14 VREF 13 18 VREG8 SS 12 SMIN 11 9 SIN 10 8 PWM CPWM PAD Terminal List Number Name 1 VREG5 Number Name Description Regulator decoupling terminal 2 CLD 3 Description 16 GLB Low-side drive for external N-channel MOSFET Capacitor to set Lock Detect Time 17 GLA Low-side drive for external N-channel MOSFET FG FG output, fan speed indicator (open drain) 18 VREG8 4 RD RD output, high for locked rotor condition (open drain) 19 SB 5 HP Hall input positive 20 GHB Gate drive supply High-side source connection High-side drive for external N-channel MOSFET 6 HN Hall input negative 21 SA 7 CDEL Commutation delay 22 GHA PWM input 23 GND Ground Capacitor to set internal frequency 24 CP1 Charge pump capacitor terminal 8 PWM 9 CPWM 10 SIN 11 SMIN 12 SS 13 14 15 SENSE High-side source connection High-side drive for external N-channel MOSFET Speed analog input/adjusted PWM output 25 CP2 Charge pump capacitor terminal Minimum speed analog input 26 VCP Reservoir capacitor terminal Connection for soft start capacitor 27 VBB Supply voltage VREF Current limit setpoint 28 NC Not connected GND Ground – Pad Thermal pad, connect to GND plane with vias to bottom of PCB Sense resistor connection Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4930 Single Phase Fan Pre-Driver Package ET 28-Pin QFN with Exposed Thermal Pad 0.30 5.00 ±0.15 1.15 28 1 2 0.50 28 1 A 5.00 ±0.15 3.15 4.80 3.15 29X D SEATING PLANE 0.08 C C 4.80 C +0.05 0.25 –0.07 PCB Layout Reference View 0.90 ±0.10 0.50 For Reference Only (reference JEDEC MO-220VHHD-1) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown +0.20 0.55 –0.10 A Terminal #1 mark area B 3.15 2 1 28 3.15 B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V1M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Copyright ©2008-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9