ICST ICS9248-168 Amd - k7â ¢ clock generator for mobile system Datasheet

Integrated
Circuit
Systems, Inc.
ICS9248-168
AMD - K7™ Clock Generator for Mobile System
Pin Configuration
VDDREF
X1
X2
*FS2/PCICLK_F
*FS1/PCICLK0
VDDPCI
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK6
*SDRAM_STOP#
*PCI_STOP#
BUFFER_IN
AVDD
GND
GND
*FS0/48MHZ
*SEL24_48#/24_48MHz
VDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9248-168
Recommended Application:
VIA KT133 style chipset
Output Features:
•
1 - Differential pair open drain CPU clocks
•
1 - CPU clock @ 3.3V
•
7 - SDRAM @ 3.3V
•
8 - PCI @ 3.3V,
•
1 - 48MHz, @ 3.3V fixed.
•
1 - 24/48MHz @ 3.3V
•
3 - REF @ 3.3V, 14.318MHz.
Features:
•
Up to 153MHz frequency support
•
Support power management: CPU stop and Power down
Mode from I2C programming.
•
Spread spectrum for EMI control
(± 0.25% to ± 0.6% center, or 0 to -0.5% or -1.0% down
spread).
•
Uses external 14.318MHz crystal
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
REF0
REF1
REF2
GND
GND
VDD
2
CPUCLK
2
CPUCLKT0
2
CPUCLKC0
CPU_STOP#*
PD#*
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
GND
VDDSDR
SDRAM4
SDRAM5
SDRAM_F
SCLK
SDATA
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
1
These outputs have double strength to drive 2 loads.
2
These outputs can be set to 1.5X strength through I2C
Functionality
Block Diagram
PLL2
/2
X1
X2
FS2
FS1
FS0
CPU
PCI
S p re a d Pe rc e n t a g e
0
0
0
100.00
33.33
+/- 0.35% Center Spread
24_48MHz
0
0
1
133.33
33.33
+/- 0.35% Center Spread
REF (2:0)
0
1
0
100.00
33.33
0 to - 0.5% Down Spread
0 to - 0.5% Down Spread
48MHz
XTAL
OSC
0
1
1
133.33
33.33
1
0
0
100.00
33.33
+/- 0.6% Center Spread
CPUCLKC0
1
0
1
133.33
33.33
+/- 0.6% Center Spread
1
1
0
90.00
30.00
+/- 0.25% Center Spread
CPUCLKT0
1
1
1
120.00
30.00
+/- 0.25% Center Spread
CPUCLK
PLL1
Spread
Spectrum
SEL24_48#
SDATA
SCLK
FS (2:0)
PD#
CPU_STOP#
PCI_STOP#
SDRAM_STOP#
BUFFER_IN
Control
CPU
DIVDER
PCI
DIVDER
Stop
Stop
Logic
PCICLK (6:0)
PCICLK_F
SDRAM
DRIVER
Stop
Config.
SDRAM (5:0)
SDRAM_F
Reg.
9248-168 Rev B 01/09/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-168
Pin Descriptions
PIN NUMBER
1, 6, 14, 24,
30, 35, 43
P I N NA M E
VDD
TYPE
PWR
FS1
PCICLK0
IN
OUT
GND
PWR
Ground
PCICLK (6:1)
OUT
PCI clock outputs.
Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level,
when input low
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
Input to Fanout Buffers for SDRAM outputs.
Supply for core, & CPU 3.3V
Frequency select pin. Latched Input
48MHz output clock
Logic input to select 24 or 48MHz for pin 25 output
24MHz/48MHz clock output
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Free running SDRAM clock not affected by SDRAM_STOP# for
power management.
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
Powers down chip, active low
This asynchronous input halts CPUCLKT, CPUCLKC & SDRAM at
logic "0" level when driven low.
"Complementory" clock of differential pair CPU output. This open
drain outputs needs an external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
3.3V CPU clock output powered by VDDA
14.318 Mhz reference clock.
X1
IN
3
X2
OUT
FS21, 2
PCICLK_F
1, 2
5
7, 13, 20, 21, 31, 34,
44, 45
15, 12, 11, 10, 9, 8
IN
OUT
16
SDRAM_STOP#
IN
17
PCICLK_STOP#
IN
18
26
BUFFER IN
AVDD
FS01, 2
48MHz
SEL24_48#1, 2
24_48MHz
SDATA
SCLK
IN
PWR
IN
OUT
IN
OUT
I/O
IN
27
SDRAM_F
OUT
19
22
23
25
28, 29, 32, 33, 36, 37 SDRAM (5:0)
OUT
38
PD#
IN
39
CPU_STOP#1,
IN
40
CPUCLKC0
OUT
41
CPUCLKT0
OUT
42
CPUCLK
REF0 (2:0)
OUT
OUT
46, 47, 48
Power supply, nominal 3.3V
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
Frequency select pin. Latched Input. Internal Pull-up to VDD
Free running PCI clock not affected by PCI_STOP# for power
management.
Frequency select pin. Latched Input. Internal Pull-up to VDD
PCI clock output
2
4
DESCRIPTION
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9248-168
General Description
The ICS9248-168 is a main clock synthesizer chip for AMD-K7 based note book systems with VIA style chipset. This provides
all clocks required for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-168
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDD48 = 48MHz, Fixed PLL
VDDA = VDD for Core PLL
VDDREF = REF, Xtal
Third party brands and names are the property of their respective owners.
3
ICS9248-168
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 2,
Bit 7:4
Bit 3
Bit 1
Bit 0
Description
Bit Bit Bit Bit Bit
CPUCLK
PCICLK
2
7
6
5
4
(MHz)
(MHz)
0
0
0
0
0
100.00
33.33
0
0
0
0
1
133.33
33.33
0
0
0
1
0
100.00
33.33
0
0
0
1
1
133.33
33.33
0
0
1
0
0
100.00
33.33
0
0
1
0
1
133.33
33.33
0
0
1
1
0
90.00
30.00
0
0
1
1
1
120.00
30.00
0
1
0
0
0
100.30
33.43
0
1
0
0
1
133.73
33.43
0
1
0
1
0
100.30
33.43
0
1
0
1
1
133.73
33.43
0
1
1
0
0
101.00
33.67
0
1
1
0
1
134.66
33.67
0
1
1
1
0
102.00
34.00
0
1
1
1
1
136.00
34.00
1
0
0
0
0
103.00
34.33
1
0
0
0
1
137.33
34.33
1
0
0
1
0
104.00
34.67
1
0
0
1
1
138.66
34.67
1
0
1
0
0
105.00
35.00
1
0
1
0
1
140.00
35.00
1
0
1
1
0
107.00
35.67
1
0
1
1
1
142.66
35.67
1
1
0
0
0
110.00
36.67
1
1
0
0
1
146.66
36.67
1
1
0
1
0
115.00
38.33
1
1
0
1
1
153.33
38.33
1
1
1
0
0
100.00
33.33
1
1
1
0
1
133.33
33.33
1
1
1
1
0
100.00
33.33
1
1
1
1
1
133.33
33.33
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread Spectrum Enabled ±0.25% Center Spread
0 - Running
1- Tristate all outputs
PWD
Spread
Precentage
+/- 0.35% Center Spread
+/- 0.35% Center Spread
0 to - 0.5% Down Spread
0 to - 0.5% Down Spread
+/- 0.6% Center Spread
+/- 0.6% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.60% Center Spread
+/- 0.60% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.50% Center Spread
+/- 0.50% Center Spread
0 to -1.0% Down Spread
0 to -1.0% Down Spread
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Third party brands and names are the property of their respective owners.
4
Reserved
00101
0
1
0
ICS9248-168
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
PWD
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN#
DESCRIPTION
Bit 7
22
1
FS0
Bit 7
4
1
PCICLK_F
Bit 6
5
1
FS1
Bit 6
15
1
PCICLK6
12
1
PCICLK5
BIT
PIN#
PWD
DESCRIPTION
Bit 5
4
1
FS2
Bit 5
Bit 4
42
1
CPUCLK 0=1.5X 1=1X
Bit 4
11
1
PCICLK4
Bit 3
-
1
Reserved
Bit 3
10
1
PCICLK3
Bit 2
41, 40
1
CPUCLKT/C 0=1.5X 1=1X
Bit 2
9
1
PCICLK2
Bit 1
-
1
Reserved
Bit 1
8
1
PCICLK1
Bit 0
42
1
CPUCLK
Bit 0
5
1
PCICLK0
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN#
PWD
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT
DESCRIPTION
PIN# PWD
DESCRIPTION
Bit 7
-
1
Reserved
Bit 7
-
1
Reserved
Bit 6
23
1
SEL24_48#
Bit 6
27
1
SDRAM_F
28
1
SDRAM5
Bit 5
22
1
48MHz
Bit 5
Bit 4
23
1
24_48MHz
Bit 4
29
1
SDRAM4
Bit 3
48
1
REF0
Bit 3
32
1
SDRAM3
Bit 2
47
1
REF1
Bit 2
33
1
SDRAM2
Bit 1
46
1
REF2
Bit 1
36
1
SDRAM1
Bit 0
-
1
Reserved
Bit 0
37
1
SDRAM0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN# PWD
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
DESCRIPTION
PIN# PWD
DESCRIPTION
Bit 7
-
1
Reserved
Bit 7
-
0
Reserved
Bit 6
-
1
Reserved
Bit 6
-
0
Reserved
-
0
Reserved
Bit 5
-
1
Reserved
Bit 5
Bit 4
-
1
Reserved
Bit 4
-
0
Reserved
Bit 3
-
1
Reserved
Bit 3
-
0
Reserved
Bit 2
-
1
Reserved
Bit 2
-
1
Reserved
Bit 1
-
1
Reserved
Bit 1
-
1
Reserved
Reserved
Bit 0
-
0
Reserved
Bit 0
-
1
Note: Don’t write into this register, writing into this
register can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
5
ICS9248-168
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
IIH
VIN = VDD
Input Low Current
IIL1
VIN = 0 V; Inputs with no pull-up resistors
Input Low Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
Operating Supply Current
IDD3.3OP
C L =20 pF; SDRAM not running
Power Down
PD
Input frequency
Fi
VDD = 3.3 V
C IN
C INX
TSTAB
Input Capacitance1
Clk Stabilization 1
12
MAX UNITS
VDD+0.3
V
0.8
V
5
uA
uA
uA
75
180
mA
280
600
uA
14.318
16
MHz
27
5
45
pF
pF
3
ms
500
ps
-5
-200
From VDD = 3.3 V to ±1% target Freq.
TCPU-PCI window Vt=50% CPU - 1.5V PCI; CPU Leads
Skew window1
1
Logic Inputs
X1 & X2 pins
MIN
2
VSS-0.3
TYP
250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
1
Output Impedance
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
20
24
RDSN5B
VOH5
VOL5
IOH5
IOL5
VO=VDD*(0.5)
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
20
2.4
44
1
1
tf5
1
dt5
1
Duty Cycle
1
Jitter, Cycle-to-Cycle
TYP
VO=VDD*(0.5)
1
tr5
Fall Time
MIN
RDSP5B
1
Rise Time
CONDITIONS
1
tjcyc-cyc5
MAX UNITS
Ω
60
60
Ω
0.4
-22
V
V
mA
mA
16
VOL = 0.4 V, VOH = 2.4 V
1.7
4.0
ns
VOH = 2.4 V, VOL = 0.4 V
1.5
4.0
ns
VT = 1.5 V
45
VT = 1.5 V
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
52.8
55
%
770
1000
ps
ICS9248-168
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified)
PARAMETER
Output High Voltage
Output Low Voltage
Output Low Current
Output Low Current
SYMBOL
VOH2B
VOL2B
IOL2B
IOL2B
1
1
tr2B
1
tf2B
1
dt2B
Rise Time
1
Fall Time
1
Duty Cycle
Skew window
1
Jitter, Cycle-to-cycle
1
tsk2B
1
1
tjcyc-cyc2B
1
tjabs2B
1
Jitter, Absolute
CONDITIONS
IOH = -12.0 mA
IOH = 12.0 mA
VOL = 1.7 V
VOL = 0.7 V
VOL = 0.4 V, VOL = 2.0V
VOH = 2.0 V, VOL = 0.4V
VT = 1.5V
MIN
1
TYP
MAX
1.8
0.8
0.9
0.8
1.6
1.6
UNITS
V
V
mA
mA
ns
ns
51.5
55
%
200
ps
300
ps
250
ps
MAX
UNITS
Ω
18
18
45
VT = 1.5V
VT = 1.5V
125
VT = 1.5V
Notes:
1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
Output Impedance
Output High Voltage
Output Low Voltage
Output Low Current
1
ZO
Rise Time
1
Fall Time
1
Differential voltage-AC
Differential voltage-DC
Diff Crossover Voltage
Duty Cycle
1
Skew window
1
Jitter, Cycle-to-cycle
1
Jitter, Absolute
1
1
tr2B
1
tf2B
VO=VX
Termination to Vpull-up(external)
Termination to Vpull-up(external)
VOL = 0.3 V
VOH = 1.2 V, VOL = 0.3V
VOL = 0.3 V, VOH = 1.2V
VDIF
Note 2
VDIF
VX
VOH2B
VOL2B
IOL2B
1
1
1
CONDITIONS
TYP
60
1.8
0.8
0.9
0.9
V
V
mA
ns
ns
0.4
Vpull-up(ext) + 0.6
V
Note 2
0.2
Vpull-up(ext) + 0.6
V
Note 3
1.2
1
dt2B
VT = 50%
1
tsk2B
VT = 50%
1
tjcyc-cyc2B
1
tjabs2B
MIN
1
18
0.5
0.3
45
VT = VX
0.82
51.5
125
VT = 50%
1.8
V
55
%
200
ps
300
ps
250
ps
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input Level
and VCP is the "complement" input level.
3 - Vpull-up(external) = 2.7V, Min=Vpull-up(external)/2-150mV; Max=Vpull-up(external)/2 +150mV
Third party brands and names are the property of their respective owners.
7
ICS9248-168
Electrical Characteristics - SDRAM_OUT
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
1
Output Impedance
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
CONDITIONS
MIN
TYP
RDSP3
VO=VDD*(0.5)
10
11
RDSN3
VOH3
VOL3
IOH3
IOL3
VO=VDD*(0.5)
IOH = -11 mA
IOL = 11 mA
VOH = 2.0 V
VOL = 0.8 V
10
12
MAX UNITS
Ω
24
24
Ω
0.4
-12
V
V
mA
mA
2
12
1
1
tr3
VOL = 0.4 V, VOH = 2.4 V
0.9
1.5
ns
1
1
tf3
1
dt3
VOH = 2.4 V, VOL = 0.4 V
0.8
1.5
ns
51.5
55
%
tsk3A
VT = 1.5 V
220
250
ps
tsk3B
VT = 1.5 V
3
Rise Time
Fall Time
1
Duty Cycle
Skew (ouput to output)
1
Skew (Buffer In to output)
1
VT = 1.5 V
45
ns
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
Output Impedance
1
RDSP2B
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
1
Skew window
Jitter, Cyc-to-Cyc
1
RDSN2B
VOH1
VOL1
IOH1
IOL1
CONDITIONS
MIN
TYP
VO=VDD*(0.5)
12
24
VO=VDD*(0.5)
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
2.6
23
MAX UNITS
Ω
55
55
Ω
0.4
-16
V
V
mA
mA
19
tr1
VOL = 0.4 V, VOH = 2.4 V
1.29
2.5
ns
tf1
dt1
VOH = 2.4 V, VOL = 0.4 V
1.29
2.5
ns
50.2
55
%
280
86
400
200
ps
ps
tsk1
tjcyc-cyc1
VT = 1.5 V
45
VT = 1.5 V
VT = 1.5 V
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-168
Electrical Characteristics - PCICLK_F
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
SYMBOL
1
1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
1
1
Duty Cycle
1
Skew window
1
1
Jitter, Cycle-to-Cycle
CONDITIONS
MIN
TYP
RDSP1B
VO=VDD*(0.5)
12
14
RDSN1B
VOH1
VOL1
IOH1
IOL1
VO=VDD*(0.5)
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
2.6
13
MAX UNITS
Ω
55
55
Ω
0.4
-12
V
V
mA
mA
12
tr1
VOL = 0.4 V, VOH = 2.4 V
1.4
2.0
ns
tf1
dt1
VOH = 2.4 V, VOL = 0.4 V
1.3
2.0
ns
50.2
55
%
tsk1
VT = 1.5 V
280
400
ps
tjcyc-cyc1
VT = 1.5 V
200
ps
VT = 1.5 V
45
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
Output Impedance
1
Output Impedance
1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
MIN
TYP
RDSP5B
VO=VDD*(0.5)
20
24
RDSN5B
VOH5
VOL5
IOH5
IOL5
VO=VDD*(0.5)
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
20
2.4
44
MAX UNITS
Ω
60
60
Ω
0.4
-22
V
V
mA
mA
16
1
1
tr5
VOL = 0.4 V, VOH = 2.4 V
1.8
4.0
ns
1
1
tf5
1
dt5
VOH = 2.4 V, VOL = 0.4 V
1.8
4.0
ns
53
55
%
150
500
ps
Rise Time
Fall Time
CONDITIONS
Duty Cycle
1
Jitter, Cycle-to-Cycle
1
tjcyc-cyc5
VT = 1.5 V
1
24 48 MHz
VT = 1.5 V
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
45
ICS9248-168
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ICS (Slave/Receiver)
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
10
ICS9248-168
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9248168 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Fig. 1
Third party brands and names are the property of their respective owners.
11
ICS9248-168
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. CPU_STOP# is considered
to be a don't care during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state
as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may
require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-168 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
12
ICS9248-168
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-168. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than
4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-168.
3. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
13
ICS9248-168
SYMBOL
In Millimeters
COMMON DIMENSIONS
MIN
MAX
In Inches
COMMON DIMENSIONS
MIN
MAX
A
2.413
2.794
.095
A1
0.203
0.406
.008
.016
b
0.203
0.343
.008
.0135
c
D
0.127
0.254
SEE VARIATIONS
.005
.010
SEE VARIATIONS
E
10.033
10.668
.395
.420
E1
7.391
7.595
.291
.299
e
0.635 BASIC
h
0.381
L
0.508
1.016
SEE VARIATIONS
N
α
0.635
0°
.110
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
8°
0°
8°
MIN
MAX
MIN
MAX
28
9.398
9.652
.370
.380
34
11.303
11.557
.445
.455
48
15.748
16.002
.620
.630
56
18.288
18.542
.720
.730
64
20.828
21.082
.820
.830
VARIATIONS
D mm.
N
D (inch)
Ordering Information
ICS9248yF-168-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
14
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.