Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs ADN2817/ADN2818 Data Sheet FEATURES GENERAL DESCRIPTION Serial data input: 10 Mbps to 2.7 Gbps Exceeds ITU-T jitter specifications Integrated limiting amplifier 5 mV p-p sensitivity (ADN2817 only) Adjustable slice level: ±100 mV (ADN2817 only) Patented dual-loop clock recovery architecture Programmable LOS detect (ADN2817 only) Integrated PRBS generator and detector No reference clock required Loss of lock indicator Supports double data rate Bit error rate monitor (BERMON) or sample phase adjust options Rate selectivity without the use of a reference clock I2C interface to access optional features Single-supply operation: 3.3 V Low power 650 mW (ADN2817) 600 mW (ADN2818) 5 mm × 5 mm 32-lead LFCSP The ADN2817/ADN2818 provide the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/ ADN2818 automatically lock to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, and low power fiber optic receiver. The ADN2817/ADN2818 have many optional features available through an I2C interface. For example, the user can read back the data rate onto which the ADN2817 or ADN2818 is locked, or the user can set the device to lock only to one particular data rate if provisioning of data rates is required. A BERMON circuit provides an estimate of the received bit error rate (BER) without interruption of the data. Alternatively, the user can adjust the data sampling phase to optimize the received BER. APPLICATIONS The ADN2817/ADN2818 are available in a compact 5 mm × 5 mm, 32-lead, lead frame chip scale package. SONET OC-1, OC-3, OC-12, OC-48, and all associated FEC rates Fibre Channel, 2× Fibre Channel, GbE, HDTV WDM transponders Regenerators/repeaters Test equipment FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN (OPTIONAL) LOL CF1 CF2 VCC VEE ADN2817/ADN2818 SLICEP/ SLICEN SLICE ADJUST (ADN2817 ONLY) FREQ/ LOCK DET LOOP FILTER PIN PHASE SHIFTER PHASE DET LOOP FILTER VCO NIN LOS DETECT (ADN2817 ONLY) THRADJ LOS DATA RETIMING ΔФ BERMON DATAOUTP/ DATAOUTN I2C REGISTERS CLKOUTP/ VBER BERMODE SCK CLKOUTN SDA 06001-001 VREF Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADN2817/ADN2818 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Jitter Tolerance ............................................................................ 19 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 20 General Description ......................................................................... 1 Functional Description .................................................................. 22 Functional Block Diagram .............................................................. 1 Frequency Acquisition ............................................................... 22 Revision History ............................................................................... 3 Lock Detector Operation .......................................................... 22 Specifications..................................................................................... 4 Harmonic Detector .................................................................... 23 Jitter Specifications ....................................................................... 5 Limiting Amplifier (ADN2817 Only) ..................................... 23 Output and Timing Specifications ............................................. 6 Slice Level Adjust (ADN2817 Only) ........................................ 23 Bit Error Rate Monitor Specifications ....................................... 8 Loss of Signal (LOS) Detector (ADN2817 Only) .................. 23 Timing Characteristics ................................................................ 9 Sample Phase Adjust .................................................................. 24 Absolute Maximum Ratings.......................................................... 10 Bit Error Rate (BER) Monitor................................................... 24 Thermal Characteristics ............................................................ 10 Squelch Mode ............................................................................. 25 ESD Caution ................................................................................ 10 I2C Interface ................................................................................ 25 Pin Configuration and Function Descriptions ........................... 11 Reference Clock (Optional) ...................................................... 26 Typical Performance Characteristics ........................................... 12 Additional Features Available via the I2C Interface ............... 28 I C Interface Timing and Internal Register Description ........... 14 Applications Information .............................................................. 30 Terminology .................................................................................... 18 PCB Design Guidelines ............................................................. 30 Input Sensitivity and Input Overdrive ..................................... 18 DC-Coupled Application .......................................................... 32 Single-Ended vs. Differential .................................................... 18 Coarse Data Rate Readback Look-Up Table ............................... 33 LOS Response Time ................................................................... 18 HI_CODE and LO_CODE Look-Up Table ................................ 35 Jitter Specifications ......................................................................... 19 Outline Dimensions ....................................................................... 38 Jitter Generation ......................................................................... 19 Ordering Guide .......................................................................... 38 2 Jitter Transfer............................................................................... 19 Rev. E | Page 2 of 40 Data Sheet ADN2817/ADN2818 REVISION HISTORY 1/13 Rev. D to Rev. E Moved Revision History Section ..................................................... 3 Change to Table 8 ............................................................................ 15 Changes to Table 15 ........................................................................ 17 Changes to Rate Selectivity Section .............................................. 28 Changes to Table 19 ........................................................................ 32 Changes to Table 20 ........................................................................ 34 2/09—Rev. A to Rev. B Updated Outline Dimensions........................................................ 37 Changes to Ordering Guide ........................................................... 37 1/12—Rev. C to Rev. D 8/08—Rev. 0 to Rev. A Changes to Figure 14 ...................................................................... 12 Updated Outline Dimensions ........................................................ 37 Changes to Features Section, General Description Section, and Figure 1 ............................................................................................... 1 Added Bit Rate Monitor Specifications Section and Table 4; Renumbered Sequentially ................................................................ 7 Changes to Figure 5 and Table 6 ................................................... 10 Changes to Table 7 and Table 8 ..................................................... 14 Changes to Table 14 ........................................................................ 15 Added Table 15 ................................................................................ 15 Added Table 16 ................................................................................ 16 Added Sample Phase Adjust Section and Bit Error Rate (BER) Monitor Section ............................................................................... 23 Added Figure 32; Renumbered Sequentially ............................... 24 Changes to Figure 36 ...................................................................... 29 Added Exposed Pad Notation to Outline Dimensions .............. 37 3/10—Rev. B to Rev. C Changes to Features Section and Applications Section ............... 1 Changes to Thermal Resistance Section ........................................ 9 Added Table 6; Renumbered Sequentially ..................................... 9 Changes to Table 7 ..........................................................................10 Changes to Table 8 ..........................................................................14 Changes to Table 14 ........................................................................15 Deleted Table 16; Renumbered Sequentially ...............................16 Changes to Table 16 ........................................................................16 Changes to I2C Interface Section...................................................24 Changed fREF Ratio to DIV_FREF Ratio .......................................25 Changes to Initiate Frequency Acquisition, Rate Selectivity, Double Data Rate Mode, and PRBS Generator/Detector Sections .............................................................................................27 7/07—Revision 0: Initial Version Rev. E | Page 3 of 40 ADN2817/ADN2818 Data Sheet SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 1. Parameter QUANTIZER—DC CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Input Common-Mode Level Differential Input Sensitivity QUANTIZER—AC CHARACTERISTICS Data Rate S11 Input Resistance Input Capacitance QUANTIZER—SLICE ADJUSTMENT Gain Differential Control Voltage Input Control Voltage Range Slice Threshold Offset LOSS OF SIGNAL DETECT (LOS) Loss of Signal Detect Range (See Figure 6) Hysteresis (Electrical) OC-48 OC-1 LOS Assert Time LOS Deassert Time LOSS OF LOCK DETECT (LOL) VCO Frequency Error for LOL Assert VCO Frequency Error for LOL Deassert LOL Response Time OC-48 OC-12 10 Mbps ACQUISITION TIME Lock to Data Mode OC-48 OC-12 OC-3 OC-1 10 Mbps Optional Lock to REFCLK Mode DATA RATE READBACK ACCURACY Coarse Readback Fine Readback Conditions Min Typ Max Unit At PIN or NIN, dc-coupled PIN − NIN DC-coupled (see Figure 40, Figure 41, and Figure 42) 223 − 1 PRBS, ac-coupled, 1 BER = 1 × 10−10 ADN2817 ADN2818 1.8 2.3 2.5 2.8 2.0 2.8 V V V 10 200 5 10 mV p-p mV p-p 2700 Mbps dB Ω pF 0.13 +0.95 0.95 V/V V V mV 14.2 2.1 20.0 5.0 mV mV 6.2 4.7 4.9 3.0 8.2 7.7 7.5 7.3 450 500 dB dB dB dB ns ns 1000 250 ppm ppm 1.0 1.0 500 µs µs µs 1.3 2.0 3.4 9.8 40.0 10.0 ms ms ms ms ms ms At 2.5 GHz Differential −15 100 0.65 ADN2817 only SLICEP − SLICEN = ±0.5 V SLICEP − SLICEN DC level @ SLICEP or SLICEN 0.10 −0.95 VEE 0.11 ±1 ADN2817 only RThresh = 0 Ω RThresh = 100 kΩ RThresh = 0 Ω RThresh = 100 kΩ RThresh = 0 Ω RThresh = 10 kΩ DC-coupled 2 DC-coupled2 With respect to nominal With respect to nominal See Table 19 In addition to REFCLK accuracy Rev. E | Page 4 of 40 10 100 % ppm Data Sheet Parameter POWER SUPPLY Voltage Current ADN2817 ADN2818 OPERATING TEMPERATURE RANGE 1 2 ADN2817/ADN2818 Conditions Min Typ Max Unit 3.0 3.3 3.6 V 210 180 247 217 +85 mA mA °C −40 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity. When ac-coupled, the LOS assert and deassert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the ADN2817 input stage. JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 2. Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer Bandwidth OC-48 OC-12 OC-3 Jitter Peaking OC-48 OC-12 OC-3 Jitter Generation OC-48 Min 12 kHz to 20 MHz OC-12 12 kHz to 5 MHz OC-3 12 kHz to 1.3 MHz Jitter Tolerance OC-48 OC-12 OC-3 1 Conditions 223 − 1 PRBS 600 Hz 1 6 kHz1 100 kHz 1 MHz1 20 MHz 30 Hz1 300 Hz1 25 kHz 250 kHz1 5 MHz 30 Hz1 300 Hz1 6500 Hz 65 kHz1 130 kHz 92.0 20.0 7.0 1.00 0.53 100.0 44.0 7.35 1.00 0.52 50.0 23.5 6.71 1.00 0.54 Jitter tolerance of the ADN2817/ADN2818 at these jitter frequencies is better than what the test equipment is able to measure. Rev. E | Page 5 of 40 Typ Max Unit 548 93 30 839 137 40 kHz kHz kHz 0 0 0 0.03 0.03 0.03 dB dB dB 0.001 0.02 0.001 0.01 0.001 0.01 0.003 0.046 0.004 0.036 0.004 0.023 UI rms UI p-p UI rms UI p-p UI rms UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p UI p-p ADN2817/ADN2818 Data Sheet OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter CML OUPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Single-Ended Output Swing, VSE Differential Output Swing, VDIFF Output Voltage High, VOH Low, VOL CML Outputs Timing Rise Time Fall Time Setup Time, tS Hold Time, tH Setup Time, tDDRS Hold Time, tDDRH I2C INTERFACE DC CHARACTERISTICS Input Voltage High, VIH Low, VIL Input Current Output Low Voltage I2C INTERFACE TIMING SCK Clock Frequency SCK Pulse Width High High, tHIGH Low, tLOW Start Condition Hold Time, tHD;STA Setup Time, tSU;STA Data Setup Time, tSU;DAT Hold Time, tHD;DAT SCK/SDA Rise/Fall Time, tR/tF Stop Condition Setup Time, tSU;STO Bus Free Time Between a Stop and a Start, tBUF REFCLK CHARACTERISTICS Input Voltage Range VIL VIH Minimum Differential Input Drive Reference Frequency Required Accuracy Conditions Min Typ Max Unit See Figure 3 See Figure 3 300 600 350 700 600 1200 mV mV VCC − 0.6 VCC − 0.35 VCC VCC − 0.3 V V 150 150 140 200 80 80 200 200 170 230 112 123 250 250 200 260 ps ps ps ps ps ps 0.3 VCC +10.0 0.4 V V µA V 400 kHz 20% to 80% 80% to 20% See Figure 2, OC-48 See Figure 2, OC-48 See Figure 4, OC-48 See Figure 4, OC-48 LVCMOS 0.7 VCC VIN = 0.1 VCC or VIN = 0.9 VCC VOL, IOL = 3.0 mA See Figure 22 −10.0 600 1300 ns ns 600 600 ns ns 100 300 20 + 0.1 Cb 600 1300 ns ns ns ns ns 300 Optional lock to REFCLK mode At REFCLKP or REFCLKN 0 VCC 100 10 200 100 Rev. E | Page 6 of 40 V V mV p-p MHz ppm Data Sheet Parameter LVTTL DC INPUT CHARACTERISTICS Input Voltage High, VIH Low, VIL Input Current High Low LVTTL DC OUTPUT CHARACTERISTICS Output Voltage High Low ADN2817/ADN2818 Conditions Min Typ Max Unit 0.8 V V 2.0 IIH, VIN = 2.4 V IIL, VIN = 0.4 V VOH, IOH = −2.0 mA VOL, IOL = +2.0 mA Rev. E | Page 7 of 40 +5 −5 2.4 0.4 µA µA V V ADN2817/ADN2818 Data Sheet BIT ERROR RATE MONITOR SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 4. Parameter BERMON Extrapolation Mode Final Computed BER Accuracy Number of Bits (NUMBITS) Pseudo BER (PBER) Measurement Time BER Range Sample Phase Adjust Resolution Sample Phase Adjust Accuracy Sample Phase Adjust Range Minimum Input Signal Level Power Increase BERMON Voltage Output Mode BER Accuracy NUMBITS Measurement Time VBER Voltage Range Minimum Input Signal Level Power Increase Sample Phase Adjust Mode Sample Phase Adjust Step Size Sample Phase Adjust Accuracy Sample Phase Adjust Range Power Increase Conditions I2C-controlled eye profiling Input BER range 1 × 10−3 to 1 × 10−12, input deterministic jitter (DJ) < 0.4 UI, DJ ceiling > 1 × 10−2; asymmetry < 0.1 UI; requires external data processing algorithms to implement Q factor extrapolation Number of data bits to collect pseudo errors; user programmable in increment factors of 23 over the range 218 to 239 Min Typ Max ±1 218 Decades 239 5 × 10−2 160 77 BER Degrees Degrees UI mV mW mW ±1 Decades +1/−2 Decades 227 0.054 0.134 0.865 1.34 UI sec sec sec sec V mV mW 6 <6 −0.5 4 +0.5 0.1 4 0.9 160 Monotonic 6 <6 With respect to normal sampling instant −0.5 +0.5 160 Rev. E | Page 8 of 40 UI sec NUMBITS/ data rate With respect to normal sampling instant Differential peak to peak BER enabled BER standby Analog voltage output Input BER range 1 × 10−3 to 1 × 10−9, input DJ = 0 UI, DJ ceiling > 1 × 10−2; asymmetry = 0 UI; BER is read as a voltage on the VBER pin, when the BER mode pin = VEE Input BER range 1 × 10−3 to 1 × 10−9, input DJ = 0.2 UI, DJ ceiling > 1 × 10−2; asymmetry = 0 UI; BER is read as a voltage on the VBER pin, when the BER mode pin = VEE Number of data bits to collect pseudo errors 2.5 Gbps 1 Gbps 155 Mbps 10 Mbps Via 3 kΩ resistor to VEE Differential peak to peak BER voltage mode Unit Degrees Degrees UI mW Data Sheet ADN2817/ADN2818 TIMING CHARACTERISTICS CLKOUTP tH 06001-002 tS DATAOUTP/ DATAOUTN Figure 2. Default Mode Output Timing OUTP VCML VSE OUTN OUTP – OUTN VDIFF 06001-003 VSE 0V Figure 3. Single-Ended vs. Differential Output Specifications tDDRS tDDRH DATAOUTP/ CLKOUTN Figure 4. Double Data Rate Mode Output Timing Rev. E | Page 9 of 40 06001-042 CLKOUTP/ CLKOUTN ADN2817/ADN2818 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, unless otherwise noted. Thermal Resistance θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages, on a 4-layer board with the exposed paddle soldered to VEE. Table 5. Parameter Supply Voltage (VCC) Input Voltage (All Inputs) Minimum Maximum Junction Temperature, Maximum Storage Temperature Range THERMAL CHARACTERISTICS Rating 4.2 V VEE − 0.4 V VCC + 0.4 V 125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Thermal Resistance Package Type 32-Lead LFCSP ESD CAUTION Rev. E | Page 10 of 40 θJA 28 Unit °C/W Data Sheet ADN2817/ADN2818 32 31 30 29 28 27 26 25 VBER VCC VEE DATAOUTP DATAOUTN SQUELCH CLKOUTP CLKOUTN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADN2817/ ADN2818 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 VCC VEE LOS SDA SCK SADDR5 VCC VEE NOTES 1. EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE CONNECTED TO VEE. 06001-004 THRADJ REFCLKP REFCLKN VCC VEE CF2 CF1 LOL 9 10 11 12 13 14 15 16 BERMODE VCC VREF NIN PIN SLICEP SLICEN VEE Figure 5. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 EP 1 Mnemonic BERMODE VCC VREF NIN PIN SLICEP SLICEN VEE THRADJ REFCLKP REFCLKN VCC VEE CF2 CF1 LOL VEE VCC SADDR5 SCK SDA LOS VEE VCC CLKOUTN CLKOUTP SQUELCH DATAOUTN DATAOUTP VEE VCC VBER EPAD Type1 DI P AO AI AI AI AI P AI DI DI P P AO AO DO P P DI DI DI DO P P DO DO DI DO DO P P AO P Description Set this pin to logic low to enable analog voltage output mode for BER monitor. Power for Input Stage, LOS. Internal VREF Voltage. Decouple to ground with a 0.1 µF capacitor. Differential Data Input. CML. Differential Data Input. CML. Differential Slice Level Adjust Input. Differential Slice Level Adjust Input. GND for the Limiting Amplifier, LOS. LOS Threshold Setting Resistor. Differential REFCLK Input. 10 MHz to 200 MHz. Differential REFCLK Input. 10 MHz to 200 MHz. VCO Power. VCO Ground. Frequency Loop Capacitor. Frequency Loop Capacitor. Loss of Lock Indicator. Active high, LVTTL. FLL Detector Ground. FLL Detector Power. Slave Address Bit 5. I2C Clock Input. I2C Data Input. Loss of Signal Detect Output. Active high, LVTTL. Output Buffer, I2C Ground. Output Buffer, I2C Power. Differential Recovered Clock Output. CML. Differential Recovered Clock Output. CML. Disable Clock and Data Outputs. Active high, LVTTL. Differential Recovered Data Output. CML. Differential Recovered Data Output. CML. Phase Detector, Phase Shifter Ground. Phase Detector, Phase Shifter Power. This pin represents BER when analog BERMON is enabled with 3 kΩ to VEE. Exposed Paddle. The Exposed paddle on the bottom of the package must be connected to VEE. P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output. Rev. E | Page 11 of 40 ADN2817/ADN2818 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.020 0.018 0.014 0.012 200mV/DIV TRIP POINT (mV p-p) 0.016 0.010 0.008 0.006 06001-040 0.004 0 1 10 1k RTH (Ω) 100 10k 100k 1M 06001-005 0.002 50ps/DIV Figure 9. Output Eye, OC-48 Figure 6. LOS Comparator Trip Point Programming 5 100 JITTER AMPLITUDE (UI) 0 GAIN (dB) SONET –5 –10 ADN2817 10 1 –15 10k 100k 1M JITTER FREQUENCY (Hz) 0.1 10 100 1k 10k 100k 1M 06001-039 1k 06001-032 –20 100 10M 06001-038 ADN2817 EQUIPMENT LIMIT SONET GR-253 CORE 004 JITTER FREQUENCY (Hz) Figure 7. Jitter Transfer, OC-1 Figure 10. Jitter Tolerance, OC-1 5 100 JITTER AMPLITUDE (UI) SONET ADN2817 –5 –10 10 1 –15 ADN2817 EQUIPMENT LIMIT SONET GR-253 CORE 004 –20 100 1k 10k 100k JITTER FREQUENCY (Hz) 1M 10M 06001-034 GAIN (dB) 0 Figure 8. Jitter Transfer, OC-3 0.1 10 100 1k 10k 100k JITTER FREQUENCY (Hz) Figure 11. Jitter Tolerance, OC-3 Rev. E | Page 12 of 40 1M Data Sheet ADN2817/ADN2818 1000 5 0 JITTER AMPLITUDE (UI) GAIN (dB) SONET –5 ADN2817 –10 100 10 1 –15 10k 100k 1M 10M JITTER FREQUENCY (Hz) 0.1 10 100 1k 10k 100k 1M 10M 06001-037 1k 06001-033 –20 100M 06001-036 ADN2817 EQUIPMENT LIMIT SONET GR-253 CORE 004 JITTER FREQUENCY (Hz) Figure 12. Jitter Transfer, OC-12 Figure 15. Jitter Tolerance, OC-12 1000 5 JITTER AMPLITUDE (UI) 0 –5 ADN2817 –10 100 10 1 –15 ADN2817 EQUIPMENT LIMIT SONET GR-253 CORE 004 100k 1M 10M 100M JITTER FREQUENCY (Hz) 0.1 10 06001-035 –20 10k 100 1 0.65 0.1 1M 10M 0.01 0.60 0.001 BIT ERROR RATE 0.55 0.50 0.45 0.40 0.0001 0.00001 0.000001 0.0000001 CLKOUTP ADN2817 CLKOUTN ADN2817 600M 1.1G 0.00000001 1.6G 2.1G 2.6G DATA RATE (Hz) 3.1G 06001-043 OUTPUT SWING (V) 100k Figure 16. Jitter Tolerance, OC-48 0.70 0.30 100M 10k JITTER FREQUENCY (Hz) Figure 13. Jitter Transfer, OC-48 0.35 1k 0.000000001 1.0 1.5 2.0 2.5 3.0 3.5 INPUT LEVEL (mV) Figure 17. Bit Error Rate vs. Input Level Figure 14. Output Swing vs. Data Rate Rev. E | Page 13 of 40 4.0 4.5 06001-041 GAIN (dB) SONET ADN2817/ADN2818 Data Sheet I2C-INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION R/W CTRL. SLAVE ADDRESS [6:0] A5 SET BY PIN 19 0 0 0 0 0 X 06001-007 1 MSB = 1 0 = WR 1 = RD S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P 06001-008 Figure 18. Slave Address Configuration Figure 19. I2C Write Data Transfer SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A(S) S SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M) DATA A(M) P P = STOP BIT A(M) = LACK OF ACKNOWLEDGE BY MASTER A(M) = ACKNOWLEDGE BY MASTER 06001-009 S Figure 20. I2C Read Data Transfer SDA SLAVE ADDRESS A6 SUB ADDRESS A5 A7 STOP BIT DATA A0 D7 D0 SCK S WR ACK ACK SLADDR[4:0] ACK SUB ADDR[6:1] DATA[6:1] Figure 21. I2C Data Transfer Timing tF tSU;DAT tHD;STA tBUF SDA tR tR tSU;STO tF tLOW tHIGH tHD;STA S tSU;STA tHD;DAT 2 S Figure 22. I C Port Timing Diagram Rev. E | Page 14 of 40 P S 06001-011 SCK P 06001-010 START BIT Data Sheet ADN2817/ADN2818 Table 8. Internal Register Map 1 Reg Name FREQ0 FREQ1 FREQ2 Rate MISC R/W R R R R R Addr 0x00 0x01 0x02 0x03 0x04 CTRLA W 0x08 CTRLA_RD CTRLB R W 0x05 0x09 CTRLB_RD CTRLC R W 0x06 0x11 CTRLD W CTRLE/BERCTLB 2 D7 MSB MSB 0 D6 X X D5 D4 LOS status COARSE_RD[8:1] LOL status Data rate measurement complete Data rate/DIV_FREF ratio Static LOL Config LOL Reset MISC[4] Initiate freq acquisition 0 0 0 0 0 0x22 CDR bypass 0x1F 0 Disable CLKOUT buffer Enable BERMON 0 W Disable DATAOUT buffer 0 SEL_MODE W 0x34 0 0 0 HI_CODE LO_CODE CODE_LSB W W W 0x35 0x36 0x39 BERCTLA W 0x1E BERSTS R 0x20 X BER_RES BER_DAC Phase R R W 0x21 0x24 0x37 X 0 1 2 D2 D1 D0 LSB LSB LSB X COARSE_RD[0] (LSB) Measure data rate Lock to REFCLK 0 0 MSB fREF range 0 D3 0 0 BER stdby mode 0 0 Readback CTRLA Reset 0 MISC[2] Readback CTRLB 0 Config LOS Initiate PRBS sequence 0 Limited rate mode Squelch 0 mode PRBS mode PRBS/DDR enable and output mode 0 CLK holdover mode 0 HI_CODE[8:1] LO_CODE[8:1] 0 0 HI_CODE[0] LO_CODE[0] (LSB) (LSB) BER timer (NUMBITS) 0 BER start Error count byte select, for example, 011 = Byte 3 pulse of 5 (NUMERRORS[39:0]) X X X X X X End of BER measurement (EOBM) BER_RES[7:0], one byte of pseudo BER measurement result (NUMERRORS[39:0]) X BER_DAC[5:0], input to BER DAC in analog BERMON mode 0 Phase[5:0], twos complement sample phase adjustment, phase code range is from −30 decimal to +30 decimal, which gives a sampling phase offset range from −0.5 UI to +0.5 UI; for example, phase = 111010 is−6 decimal, which gives a sampling phase offset of −6/+60 = −0.1 UI X = don’t care. Both CTRLE and BERCTLB registers are used, depending on the application. Table 9. Miscellaneous Register, MISC D7 X D6 X LOS Status D5 0 = no loss of signal 1 = loss of signal Static LOL D4 0 = waiting for next LOL 1 = static LOL until reset LOL Status D3 0 = locked 1 = acquiring Rev. E | Page 15 of 40 Data Rate Measurement Complete D2 0 = measuring data rate 1 = measurement complete D1 X COARSE_RD[0] (LSB) D0 COARSE_RD[0] ADN2817/ADN2818 Data Sheet Table 10. Control Register, CTRLA D7 Set to 0 Set to 0 Set to 1 Set to 1 fREF Range D6 Range Set to 0 10 MHz to 25 MHz Set to 1 25 MHz to 50 MHz Set to 0 50 MHz to 100 MHz Set to 1 100 MHz to 200 MHz Data Rate/DIV_FREF Ratio D5 D4 D3 D2 Ratio 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 n 2n 1 0 0 0 256 Measure Data Rate D1 Set to 1 to measure data rate Lock to REFCLK D0 0 = lock to input data 1 = lock to reference clock Table 11. Control Register, CTRLB Config LOL D7 0 = LOL pin normal operation 1 = LOL pin is static LOL Reset MISC[4] D6 Write a 1 followed by 0 to reset MISC[4] Initiate Freq Acquisition D5 Write a 1 followed by 0 to initiate a frequency acquisition D4 Set to 0 Reset MISC[2] D3 Write a 1 followed by 0 to reset MISC[2] D2 Set to 0 D1 Set to 0 D0 Set to 0 Table 12. Control Register, CTRLC D7 Set to 0 D6 Set to 0 D5 Set to 0 D4 Set to 0 D3 Set to 0 Configure LOS D2 0 = active high LOS 1 = active low LOS Squelch Mode D1 0 = squelch CLK and DATA 1 = squelch CLK or DATA D0 Set to 0 Table 13. Control Register, CTRLD CDR Bypass D7 0 = CDR enabled 1 = CDR disabled Disable DATAOUT Buffer D6 0 = data buffer enabled 1 = data buffer disabled Disable CLKOUT Buffer D5 0 = CLK buffer enabled 1 = CLK buffer disabled D4 Set to 0 Initiate PRBS Sequence D3 Write a 1 followed by 0 to initiate a PRBS generate sequence D2 0 0 1 D1 0 0 0 PRBS Mode D0 Function 0 Power-down PRBS 1 Generate mode 0 Detect mode Table 14. Control Registers, CTRLE/BERCTLB D7 Set to 0 1 D6 Set to 0 Enable BERMON D5 BER Stdby Mode D4 1 = BERMON enabled 0 = BERMON disabled 1 = place BERMON in low power standby mode 0 = BERMON ready D3 Set to 0 PRBS/DDR Enable and Output Mode D2 D1 D0 Function 0 0 0 Normal data rate output mode 0 0 1 Offset decision circuit (ODC) output mode 1 0 1 0 Enable DDR mode (double data rate mode) 0 1 1 Offset decision circuit (ODC) output in DDR mode1 1 0 1 Enable PRBS detector/generator All other combinations reserved See AN-941 Application Note, BER Monitor User Guide. Rev. E | Page 16 of 40 Data Sheet ADN2817/ADN2818 Table 15. Mode Select Register, SEL_MODE D7 Set to 0 D6 Set to 0 D5 Set to 0 D4 Set to 0 D3 Default 0 Limited rate enable = 1 D2 Set to 0 CLK Holdover Mode D1 Set to 1 for clock holdover mode D0 Set to 0 Table 16. BER Control Register, BERCTLA BER Timer (NUMBITS) D7 D6 D5 No. of Bits 0 0 0 218 bits 0 0 1 221 bits 0 1 0 224 bits 0 1 1 227 bits 1 0 0 230 bits 1 0 1 233 bits 1 1 0 236 bits 1 1 1 239 bits D4 Set to 0 BER Start Pulse D3 Write a 1 followed by a 0 to initiate BER measurement Rev. E | Page 17 of 40 D2 0 0 0 0 1 Error Count Byte Select (NUMERRORS[39:0]) D1 D0 Byte Selection 0 0 Byte 0 0 1 Byte 1 1 0 Byte 2 1 1 Byte 3 0 0 Byte 4 ADN2817/ADN2818 Data Sheet TERMINOLOGY 10mV p-p INPUT SENSITIVITY AND INPUT OVERDRIVE OUTPUT NOISE 1 0 VREF PIN + QUANTIZER – 50Ω VREF INPUT (V p-p) 2.5V 3kΩ Figure 24. Single-Ended Sensitivity Measurement Differentially driving the ADN2817 (see Figure 25), sensitivity seems to improve from observing the quantizer input with an oscilloscope probe. This is an illusion caused by the use of a singleended probe. A 5 mV p-p signal appears to drive the ADN2817 quantizer. However, the single-ended probe measures only half the signal. The true quantizer input signal is twice this value because the other quantizer input is a complementary signal to the signal being observed. 5mV p-p OFFSET 50Ω 06001-013 Sensitivity and overdrive specifications for the quantizer involve offset voltage, gain, and noise. The relationship between the logic output of the quantizer and the analog voltage input is shown in Figure 23. For sufficiently large positive input voltages, the output is always Logic 1 and, similarly for negative inputs, the output is always Logic 0. However, the transitions between Output Logic Level 1 and Output Logic Level 0 are not at precisely defined input voltage levels but occur over a range of input voltages. Within this range of input voltages, the output may be either 1 or 0, or it may even fail to attain a valid logic state. The width of this zone is determined by the input voltage noise of the quantizer. The center of the zone is the quantizer input offset voltage. Input overdrive is the magnitude of signal required to guarantee the correct logic level with 1 × 10−10 confidence level. SCOPE PROBE SCOPE PROBE VREF PIN + Figure 23. Input Sensitivity and Input Overdrive QUANTIZER NIN SINGLE-ENDED vs. DIFFERENTIAL AC coupling is typically used to drive the inputs to the quantizer. The inputs are internally dc biased to a common-mode potential of ~2.5 V. Driving the ADN2817/ADN2818 single-ended and observing the quantizer input with an oscilloscope probe at the point indicated in Figure 24 shows a binary signal with an average value equal to the common-mode potential and instantaneous values both above and below the average value. It is convenient to measure the peak-to-peak amplitude of this signal and call the minimum required value the quantizer sensitivity. Referring to Figure 24, because both positive and negative offsets need to be accommodated, the sensitivity is twice the overdrive. The ADN2817 quantizer typically has 5 mV p-p sensitivity. The ADN2818 does not have a limiting amplifier at its input. The input sensitivity for the ADN2818 is 200 mV p-p. – 50Ω VREF 50Ω VREF 5mV p-p 3kΩ 2.5V 06001-014 SENSITIVITY (2× OVERDRIVE) 06001-012 OVERDRIVE Figure 25. Differential Sensitivity Measurement LOS RESPONSE TIME The LOS response time is the delay between the removal of the input signal and the indication of the loss of signal at the LOS output, Pin 22. When the inputs are dc-coupled, the LOS assert time of the ADN2817 is 450 ns typically and the deassert time is 500 ns typically. In practice, the time constant produced by the ac coupling at the quantizer input and the 50 Ω on-chip input termination determine the LOS response time. Rev. E | Page 18 of 40 Data Sheet ADN2817/ADN2818 JITTER SPECIFICATIONS JITTER GENERATION The jitter generation specification limits the amount of jitter that can be generated by the device with no jitter and wander applied at the input. For OC-48 devices, the band-pass filter has a 12 kHz high-pass cutoff frequency with a roll-off of 20 dB/decade and a low-pass cutoff frequency of at least 20 MHz. The jitter generated must be less than 0.01 UI rms and must be less than 0.1 UI p-p. JITTER TRANSFER The jitter transfer function is the ratio of the jitter on the output signal to the jitter applied on the input signal vs. the frequency. This parameter measures the limited amount of the jitter on an input signal that can be transferred to the output signal (see Figure 26). SLOPE = –20dB/DECADE ACCEPTABLE RANGE 06001-015 fC JITTER FREQUENCY (kHz) Figure 26. Jitter Transfer Curve JITTER TOLERANCE The jitter tolerance is defined as the peak-to-peak amplitude of the sinusoidal jitter applied on the input signal, which causes a 1 dB power penalty. This is a stress test intended to ensure that no additional penalty is incurred under the operating conditions (see Figure 27). 15.00 SLOPE = –20dB/DECADE 1.50 0.15 f0 f1 f2 f3 JITTER FREQUENCY (kHz) Figure 27. SONET Jitter Tolerance Mask Rev. E | Page 19 of 40 f4 06001-016 The following sections briefly summarize the specifications of jitter generation, transfer, and tolerance in accordance with the Telcordia document (GR-253-CORE, Issue 3, September 2000) for the optical interface at the equipment level and the ADN2817/ADN2818 performance with respect to those specifications. JITTER GAIN (dB) Jitter is the dynamic displacement of digital signal edges from their long-term average positions, measured in unit intervals (UI), where 1 UI = 1 bit period. Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. Jitter on the recovered clock causes jitter on the retimed data. 0.1 INPUT JITTER AMPLITUDE (UI p-p) The ADN2817/ADN2818 CDR is designed to achieve the best bit error rate (BER) performance and exceeds the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH equipment defined in the Telcordia® Technologies specification. ADN2817/ADN2818 Data Sheet THEORY OF OPERATION Another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second-order phase-locked loop, and this zero is placed in the feedback path and, thus, does not appear in the closed-loop transfer function. Jitter peaking in a conventional second-order phase-locked loop is caused by the presence of this zero in the closed-loop transfer function. Because this circuit has no zero in the closed-loop transfer, jitter peaking is minimized. The delay- and phase-locked loops together simultaneously provide wideband jitter accommodation and narrow-band jitter filtering. The linearized block diagram in Figure 28 shows that the jitter transfer function, Z(s)/X(s), is second-order low-pass, providing excellent filtering. Note that the jitter transfer has no zero, unlike an ordinary second-order phase-locked loop. This means that the main PLL loop has virtually zero jitter peaking (see Figure 29). This makes this circuit ideal for signal regenerator applications, where jitter peaking in a cascade of regenerators can contribute to hazardous jitter accumulation. The error transfer, e(s)/X(s), has the same high-pass form as an ordinary phase-locked loop. This transfer function is free to be optimized to give excellent wideband jitter accommodation, because the jitter transfer function, Z(s)/X(s), provides the narrow-band jitter filtering. INPUT DATA X(s) e(s) o/s d/sc 1/n Z(s) RECOVERED CLOCK d = PHASE DETECTOR GAIN o = VCO GAIN c = LOOP INTEGRATOR psh = PHASE SHIFTER GAIN n = DIVIDE RATIO JITTER TRANSFER FUNCTION Z(s) 1 = n psh cn X(s) +1 s2 +s o do TRACKING ERROR TRANSFER FUNCTION 06001-017 e(s) s2 = X(s) d psh do + s2 + s c cn Figure 28. ADN2817/ADN2818 PLL/DLL Architecture JITTER PEAKING IN ORDINARY PLL ADN28xx Z(s) X(s) o n psh d psh c FREQUENCY (kHz) 06001-018 The delay- and phase-locked loops together track the phase of the input data signal. For example, when the clock lags input data, the phase detector drives the VCO to a higher frequency and increases the delay through the phase shifter; both of these actions serve to reduce the phase error between the clock and data. The faster clock picks up phase, while, simultaneously, the delayed data loses phase. Because the loop filter is an integrator, the static phase error is driven to zero. psh JITTER GAIN (dB) The ADN2817/ADN2818 are delay- and phase-locked loop circuits for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter. A separate phase control loop, composed of the VCO, tracks the low frequency components of input jitter. The initial frequency of the VCO is set by a third loop, which compares the VCO frequency with the input data frequency and sets the coarse tuning voltage. The jitter tracking phaselocked loop controls the VCO by the fine-tuning control. Figure 29. ADN2817/ADN2818 Jitter Response vs. Conventional PLL The delay- and phase-locked loops contribute to overall jitter accommodation. At low frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error. In this case, the VCO is frequency modulated and jitter is tracked as in an ordinary phase-locked loop. The amount of low frequency jitter that can be tracked is a function of the VCO tuning range. A wider tuning range gives larger accommodation of low frequency jitter. The internal loop control voltage remains small for small phase errors, so the phase shifter remains close to the center of its range and thus contributes little to the low frequency jitter accommodation. Rev. E | Page 20 of 40 Data Sheet ADN2817/ADN2818 At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of its tuning range or the other. The size of the VCO tuning range, therefore, has only a small effect on the jitter accommodation. The delay-locked loop control voltage is now larger, and so the phase shifter takes on the burden of tracking the input jitter. The phase shifter range, in UI, can be seen as a broad plateau on the jitter tolerance curve. The phase shifter has a minimum range of 2 UI at all data rates. The gain of the loop integrator is small for high jitter frequencies, so that larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. Large phase errors at high jitter frequencies cannot be tolerated. In this region, the gain of the integrator determines the jitter accommodation. Because the gain of the loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. At the highest frequencies, the loop gain is very small, and little tuning of the phase shifter can be expected. In this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. The jitter accommodation is roughly 0.5 UI in this region. The corner frequency between the declining slope and the flat region is the closed-loop bandwidth of the delay-locked loop, which is roughly 3 MHz at OC-48. Rev. E | Page 21 of 40 ADN2817/ADN2818 Data Sheet FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION Once LOL is deasserted, the frequency-locked loop is turned off. The phase- and delay-locked loop (PLL/DLL) pulls in the VCO frequency until the VCO frequency equals the data frequency. The frequency loop requires a single external capacitor between CF1 and CF2, Pin 14 and Pin 15. A 0.47 µF ± 20%, X7R ceramic chip capacitor with <10 nA leakage current is recommended. Leakage current of the capacitor can be calculated by dividing the maximum voltage across the 0.47 µF capacitor, ~3 V, by the insulation resistance of the capacitor. The insulation resistance of the 0.47 μF capacitor should be greater than 300 MΩ. LOCK DETECTOR OPERATION The lock detector on the ADN2817/ADN2818 has three modes of operation: normal mode, REFCLK mode, and static LOL mode. Normal Mode In normal mode, the ADN2817/ADN2818 function as continuous rate CDRs that lock onto any data rate from 10 Mbps to 2.7 Gbps without the use of a reference clock as an acquisition aid. In this mode, the lock detector monitors the frequency difference between the VCO and the input data frequency, and deasserts the loss of lock signal that appears on LOL (Pin 16) when the VCO is within 250 ppm of the data frequency. This enables the delay- and phaselocked loop (DLL/PLL), which pulls the VCO frequency in the remaining amount and acquires phase lock. When locked, if the input frequency error exceeds 1000 ppm (0.1%), the loss of lock signal is reasserted and control returns to the frequency loop, which begins a new frequency acquisition starting at the lowest point in the VCO operating range, 10 MHz. The LOL pin remains asserted until the VCO locks onto a valid input data stream to within 250 ppm frequency error. This hysteresis is shown in Figure 30. LOL 1 –1000 –250 0 250 1000 fVCO ERROR (ppm) 06001-019 The ADN2817/ADN2818 acquire frequency from the data over a range of data frequencies from 10 Mbps to 2.7 Gbps. The lock detector circuit compares the frequency of the VCO and the frequency of the incoming data. When these frequencies differ by more than 1000 ppm, LOL is asserted. This initiates a frequency acquisition cycle. The VCO frequency is reset to the bottom of its range, which is 10 MHz. The frequency detector compares this VCO frequency and the incoming data frequency and increments the VCO frequency, if necessary. Initially, the VCO frequency is incremented in large steps to aid fast acquisition. As the VCO frequency approaches the data frequency, the step size is reduced until the VCO frequency is within 250 ppm of the data frequency, at which point LOL is deasserted. Figure 30. Transfer Function of LOL LOL Detector Operation Using a Reference Clock In this mode, a reference clock is used as an acquisition aid to lock the ADN2817/ADN2818 VCO. Lock to reference mode is enabled by setting CTRLA[0] to 1. The user also needs to write to the CTRLA[7:6] and CTRLA[5:2] bits to set the reference frequency range and the divide ratio of the data rate with respect to the reference frequency. For more details, see the Reference Clock (Optional) section. In this mode, the lock detector monitors the difference in frequency between the divided down VCO and the divided down reference clock. The loss of lock signal, which appears on LOL (Pin 16), is deasserted when the VCO is within 250 ppm of the desired frequency. This enables the DLL/ PLL, which pulls the VCO frequency in the remaining amount with respect to the input data and acquires phase lock. Once locked, if the input frequency error exceeds 1000 ppm (0.1%), the loss of lock signal is reasserted and control returns to the frequency loop, which reacquires with respect to the reference clock. The LOL pin remains asserted until the VCO frequency is within 250 ppm of the desired frequency. This hysteresis is shown in Figure 30. Static LOL Mode The ADN2817/ADN2818 implement a static LOL feature, which indicates if a loss of lock condition has ever occurred and remains asserted, even if the ADN2817/ADN2818 regain lock, until the static LOL bit is manually reset. I2C Register Bit MISC[4] is the static LOL bit. If there is ever an occurrence of a loss of lock condition, this bit is internally asserted to logic high. The MISC[4] bit remains high even after the ADN2817/ADN2818 reacquire lock to a new data rate. This bit can be reset by writing a 1 followed by 0 to I2C Register Bit CTRLB[6]. When reset, the MISC[4] bit remains deasserted until another loss of lock condition occurs. Writing a 1 to I2C Register Bit CTRLB[7] causes the LOL pin, Pin 16, to become a static LOL indicator. In this mode, the LOL pin mirrors the contents of the MISC[4] bit and has the functionality described previously. The CTRLB[7] bit defaults to 0. In this mode, the LOL pin operates in the normal operating mode, that is, it is asserted only when the ADN2817/ ADN2818 are in acquisition mode and deasserts when the ADN2817/ADN2818 reacquire lock. Rev. E | Page 22 of 40 Data Sheet ADN2817/ADN2818 HARMONIC DETECTOR SLICE LEVEL ADJUST (ADN2817 ONLY) The ADN2817/ADN2818 provide a harmonic detector, which detects whether the input data has changed to a lower harmonic of the data rate onto which the VCO is currently locked. For example, if the input data instantaneously changes from an OC-48, 2.488 Gbps to an OC-12, 622.080 Mbps bit stream, this could be perceived as a valid OC-48 bit stream, because the OC-12 data pattern is exactly 4× slower than the OC-48 pattern. Therefore, if the change in data rate is instantaneous, a 101 pattern at OC-12 is perceived by the ADN2817/ADN2818 as a 111100001111 pattern at OC-48. If the change to a lower harmonic is instantaneous, a typical CDR could remain locked at the higher data rate. The quantizer slicing level can be offset by ±100 mV to mitigate the effect of amplified spontaneous emission (ASE) noise or duty cycle distortion by applying a differential voltage input of up to ±0.95 V to SLICEP/SLICEN inputs. If no adjustment of the slice level is needed, SLICEP/SLICEN should be tied to VEE. The gain of the slice adjustment is ~0.1 V/V. The ADN2817/ADN2818 implement a harmonic detector that automatically identifies whether the input data has switched to a lower harmonic of the data rate onto which the VCO is currently locked. When a harmonic is identified, the LOL pin is asserted and a new frequency acquisition is initiated. The ADN2817/ ADN2818 automatically lock onto the new data rate, and the LOL pin is deasserted. However, the harmonic detector does not detect higher harmonics of the data rate. If the input data rate switches to a higher harmonic of the data rate onto which the VCO is currently locked, the VCO loses lock, the LOL pin is asserted, and a new frequency acquisition is initiated. The ADN2817/ADN2818 automatically lock onto the new data rate. The time to detect lock to harmonic is 16,384 × (Td/ρ) LOSS OF SIGNAL (LOS) DETECTOR (ADN2817 ONLY) The receiver front-end LOS detector circuit detects when the input signal level has fallen below a user-adjustable threshold. The threshold is set with a single external resistor from Pin 9, THRADJ, to VEE. The LOS comparator trip point vs. resistor value is shown in Figure 6. If the input level to the ADN2817 drops below the programmed LOS threshold, the output of the LOS detector, Pin 22 (LOS), is asserted to a Logic 1. The LOS detector response time is 450 ns by design but is dominated by the RC time constant in accoupled applications. The LOS pin defaults to active high. However, by setting Bit CTRLC[2] to 1, the LOS pin is configured as active low. There is typically 6 dB of electrical hysteresis designed into the LOS detector to prevent chatter on the LOS pin. This means that, if the input level drops below the programmed LOS threshold causing the LOS pin to assert, the LOS pin is not deasserted until the input level has increased to 6 dB (2×) above the LOS threshold (see Figure 31). INPUT LEVEL HYSTERESIS LOS THRESHOLD LIMITING AMPLIFIER (ADN2817 ONLY) The limiting amplifier on the ADN2817 has differential inputs (PIN/NIN) that internally terminate with 50 Ω to an on-chip voltage reference (VREF = 2.5 V typically). The inputs are typically ac-coupled externally, although dc coupling is possible as long as the input common-mode voltage remains above 2.5 V (see Figure 40, Figure 41, and Figure 42). Input offset is factory trimmed to achieve better than 6 mV typical sensitivity with minimal drift. The limiting amplifier can be driven differentially or single-ended. t 06001-020 where: 1/Td is the new data rate. For example, if the data rate is switched from OC-48 to OC-12, then Td = 1/622 MHz. ρ is the data transition density. Most coding schemes seek to ensure that ρ = 0.5, for example, PRBS or 8b/10b encoding. When the ADN2817/ADN2818 is placed in lock to reference mode, the harmonic detector is disabled. INPUT VOLTAGE (VDIFF) LOS OUTPUT Figure 31. ADN2817 LOS Detector Hysteresis The LOS detector and the slice level adjust can be used simultaneously on the ADN2817. This means that any offset added to the input signal by the slice adjust pins does not affect the LOS detector measurement of the absolute input level. Rev. E | Page 23 of 40 ADN2817/ADN2818 Data Sheet SAMPLE PHASE ADJUST If the user is not using the BER monitoring function, sample phase adjustment can be used to optimize the horizontal sampling point of the incoming data eye. The ADN2817 automatically centers the sampling point to the best of its ability. However, sample phase adjustment can be used to compensate for any static phase offset of the CDR and data eye jitter profile asymmetry. Sample phase adjustment is applied to the incoming eye via the phase register. The sampling phase can be adjusted by ±0.5 UI, in 6 degree steps, relative to the normal CDR data sampling instant. Using the sample phase adjustment capability uses an additional 160 mW of power. The AN-941 application note gives additional information on the use of this feature. BIT ERROR RATE (BER) MONITOR In BER on mode (BERCTLB[5] = 1), the internal BER circuitry is powered up. The user can perform pseudo BER measurements through the I2C. In BER standby mode (BERCTLB[5:4] = 11b), the BER is placed into a lower power mode. This setting can only be set after applying the BER on setting. These modes are defined to allow optimal power saving opportunities. It is not possible to switch between the BER off setting and the BER on setting without losing lock. Switching between the BER standby setting and the BER on setting is achieved without interrupting data recovery. The incremental power between the BER off setting and the BER standby setting is 77 mW and between the BER off setting and the BER on setting it is 160 mW. The ADN2817 has a BER measurement feature that estimates the actual bit error rate of the IC. This feature also allows data eye jitter profiling and Q-factor estimation. BER On Mode By knowing the BER at a sampling phase offset from the ideal sampling phase (known as pseudo BER [PBER] values), it is possible to extrapolate to obtain an estimate of the BER at the actual sampling instant. This extrapolation relies on the assumption that the input jitter is composed of deterministic and random (Gaussian) components. The implementation requires off-chip control and data processing to estimate the actual BER. A lower accuracy voltage output mode is also supported that requires no data processing or I2C control. The following is a brief overview of user protocol: Brief Overview of Modes of Operation The following two modes of operation are available for the BER feature: the BER extrapolation mode and the voltage output mode. Only one mode can be operational at a time. The BER extrapolation mode scans the input eye in the range of ±0.5 UI of the data center and reads the measured PBER over the I2C. The user then applies a data processing algorithm to determine the BER. Using the BER feature in this way provides for the greatest accuracy in BER estimation as the magnitude of both random (Gaussian) jitter and deterministic jitter can be estimated and used to predict the actual BER. In the voltage output mode, the part autonomously samples the PBER at 0.1 UI offset and decodes this value to provide an estimate of the input BER. This estimate is output via a DAC as an analog current output. The AN-941 application note gives detailed information on the use of the BER monitor features. BER Extrapolation Mode Power Saving The following three power settings are available in BER extrapolation mode: BER off, BER on, and BER standby. In BER off mode (BERCTLB[5] = 0), the BER circuitry is powered down with the ADN2817 providing normal CDR operation. The BER on mode allows the user to scan the incoming data eye in the time dimension and build up a profile of the BER statistics. • • • • • • • • The user powers up BER circuitry through the I2C. The user initiates the PBER measurement. Sample phase offset and number of data bits to be counted (NUMBITS is a choice among 218, 221, 224, 227, 230, 233, 236, and 239) are supplied by the user through the I2C. The user initiates the pseudo BER measurement by writing a 1-to-0 transition on BERCTLA[3]. BER logic indicates the end of the BER measurement with an EOBM signal and updates the number of counted errors on NUMERRORS[39:0]. The user must poll the I2C to determine if the EOBM bit, BERSTS[0], has been asserted. The user reads back NUMERRORS[39:0] through the I2C. NUMERRORS[39:0] is read back through the 8-bit register BER_RES at Address 0x21. The user sets BERCTLA[2:0] to address one of the five NUMERRORS bytes and then reads the selected byte from BER_RES. PBER for programmed sample phase is calculated as NUMERRORS/NUMBITS. The user initiates another PBER measurement. The user sweeps the phase over −0.5 UI to +0.5 UI with respect to the normal sampling instant to obtain the BER profile required. The ADN2817 does not output the BER at the normal decision instant. It outputs PBER measurements to the left and right of the normal decision instants from which the user must calculate what the BER is at the normal decision instant. A microprocessor is required to parse the data and to use the remaining data for BER estimation. Suitable algorithms are suggested in the AN-941 Application Note, BER Monitor User Guide. Rev. E | Page 24 of 40 Data Sheet ADN2817/ADN2818 Voltage Output Mode of Operation I2C INTERFACE A second mode of operation is the voltage output mode. This mode is to give easy access to a coarse estimate of the BER. The functionality is similar to that already described in the Brief Overview of Modes of Operation section except that the measurement is performed autonomously by the ADN2817, and the result is output as a voltage on a pin from which the actual BER can be inferred. Because this mode does not perform scanning of the eye to separate out deterministic jitter from random jitter effects, this method is less accurate under normal applied jitter conditions. The ADN2817/ADN2818 support a 2-wire, I2C-compatible serial bus driving multiple peripherals. Two inputs, serial data (SDA) and serial clock (SCK), carry information between any devices connected to the bus. Each slave device is recognized by a unique address. The ADN2817/ADN2818 have two possible 7-bit slave addresses for both read and write operations. The MSB of the 7-bit slave address is factory programmed to 1. Bit 5 of the slave address is set by Pin 19, SADDR5. Slave Address Bits[4:0] are defaulted to all 0s. The slave address consists of the 7 MSBs of an 8-bit word. The LSB of the word either sets a read or write operation (see Figure 18). Logic 1 corresponds to a read operation and Logic 0 corresponds to a write operation. 0.9 0.7 VBER VOLTAGE IS GUARANTEED TO SATURATE FOR INPUT BERs LESS THAN 0.000000001 0.5 0.3 VBER VOLTAGE IS GUARANTEED TO SATURATE FOR INPUT BERs GREATER THAN 0.001 0.1 0.001 0.00001 0.0000001 0.000000001 LOG (BER) 06001-024 VBER PIN VOLTAGE RELATIVE TO VEE (V) The user merely has to bring the BERMODE pin low and read the voltage on the VBER pin (see Figure 32). Alternatively, a 6-bit value can be read over the I2C. Figure 32. VBER vs. Bit Error Rate SQUELCH MODE Two squelch modes are available with the ADN2817/ADN2818: squelch DATAOUT and CLKOUT mode, and squelch DATAOUT or CLKOUT mode. Squelch DATAOUT and CLKOUT mode is selected when CTRLC[1] = 0 (default mode). In this mode, when the squelch input, Pin 27, is driven to a TTL high state, both the clock and data outputs are set to the zero state to suppress downstream processing. If the squelch function is not required, Pin 27 should be tied to VEE. Squelch DATAOUT or CLKOUT mode is selected when CTRLC[1] is 1. In this mode, when the squelch input is driven to a high state, the DATAOUT pins are squelched. When the squelch input is driven to a low state, the CLKOUT pins are squelched. This is especially useful in repeater applications, where the recovered clock may not be needed. To control the device on the bus, the following protocol must be used. First, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCK remains high. This indicates that an address/data stream follows. All peripherals respond to the start condition and shift the next eight bits (the 7-bit address and the R/W bit). The bits are transferred from MSB to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCK lines waiting for the start condition and correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADN2817/ADN2818 act as standard slave devices on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADN2817/ADN2818 have eight subaddresses to enable the user-accessible internal registers (see Table 8 through Table 16). It, therefore, interprets the first byte as the device address and the second byte as the starting subaddress. Auto-increment mode is supported, allowing data to be read from, or written to, the starting subaddress and each subsequent address without manually addressing the subsequent subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all registers. Stop and start conditions can be detected at any stage of the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCK high period, the user should issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADN2817/ADN2818 do not issue an acknowledge and return to the idle condition. Rev. E | Page 25 of 40 ADN2817/ADN2818 Data Sheet ADN2817/ADN2818 If the user exceeds the highest subaddress while reading back in auto-increment mode, the highest subaddress register contents continue to be output until the master device issues a no acknowledge. This indicates the end of a read. In a no acknowledge condition, the SDA line is not pulled low on the ninth pulse. See Figure 19 and Figure 20 for sample read and write data transfers and Figure 21 for a more detailed timing diagram. VCC REFCLKP 10 BUFFER REFCLKN 11 A reference clock is not required to perform clock and data recovery with the ADN2817/ADN2818. However, support for an optional reference clock is provided. The reference clock can be driven differentially or single-ended. If the reference clock is not used, tie REFCLKP to VCC, and either leave REFCLKN floating or tie it to VEE (the inputs are internally terminated to VCC/2). See Figure 33 through Figure 35 for sample configurations. The REFCLK input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mV (for example, LVPECL or LVDS) or a standard single-ended low voltage TTL input, providing maximum system flexibility. Phase noise and duty cycle of the reference clock are not critical and 100 ppm accuracy is sufficient. ADN2817/ADN2818 VCC/2 Figure 35. No REFCLK Configuration The two uses of the reference clock are mutually exclusive. The reference clock can be used either as an acquisition aid for the ADN2817/ADN2818 to lock onto data, or to measure the frequency of the incoming data to within 0.01%. (There is the capability to measure the data rate to approximately ±10% without the use of a reference clock.) The modes are mutually exclusive because, in the first use, the user knows exactly what the data rate is and wants to force the part to lock onto only that data rate; in the second use, the user does not know what the data rate is and wants to measure it. Lock to reference mode is enabled by writing 1 to I2C Register Bit CTRLA[0]. Data rate readback mode is enabled by writing 1 to I2C Register Bit CTRLA[1]. Writing a 1 to both of these bits at the same time causes an indeterminate state and is not supported. REFCLKP 10 BUFFER Using the Reference Clock to Lock onto Data 11 Writing CTRLA[0] = 1 puts the ADN2817/ADN2818 into lock to REFCLK (LTR) mode. In this mode, the ADN2817/ADN2818 lock onto a frequency derived from the reference clock according to the following equation: REFCLKN 100kΩ 100kΩ 06001-021 VCC/2 Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6] The user must know exactly what the data rate is and provide a reference clock that is a function of this rate. The ADN2817/ ADN2818 can still be used as continuous rate devices in this configuration if a reference clock with a variable frequency is provided (see the AN-632 Application Note). Figure 33. Differential REFCLK Configuration ADN2817/ADN2818 VCC CLK OSC OUT REFCLKP 10 BUFFER REFCLKN 11 100kΩ VCC/2 Figure 34. Single-Ended REFCLK Configuration 06001-022 100kΩ 100kΩ 06001-023 100kΩ REFERENCE CLOCK (OPTIONAL) The reference clock can be anywhere between 10 MHz and 200 MHz. By default, the ADN2817/ADN2818 expect a reference clock of between 10 MHz and 25 MHz. If it is between 25 MHz and 50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user needs to configure the ADN2817/ADN2818 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6]. Table 17. CTRLA[7:6] (fREF Range) with CTRLA[5:2] (DIV_FREF Ratio) Settings CTRLA[7:6] 00 01 10 11 Rev. E | Page 26 of 40 Range (MHz) 10 to 25 25 to 50 50 to 100 100 to 200 CTRLA[5:2] 0000 0001 n 1000 Ratio 1 2 2n 256 Data Sheet ADN2817/ADN2818 The user can specify a fixed integer multiple of the reference clock to lock onto using CTRLA[5:2], where CTRLA should be set to the data rate/DIV_FREF and DIV_FREF represents the divided-down reference referred to the 10 MHz to 25 MHz band. For example, if the reference clock frequency is 38.88 MHz and the input data rate is 622.08 Mbps, then CTRLA[7:6] is set to 01 to give a divided-down reference clock of 19.44 MHz. CTRLA[5:2] is set to 0101, that is, 5, because Prior to reading back the data rate using the reference clock, the CTRLA[7:6] bits must be set to the appropriate frequency range with respect to the reference clock being used. A fine data rate readback is then executed as follows: 1. 2. 622.08 Mbps/19.44 MHz = 25 When the CTRLA[7:2] value is correct and CTRLA[0] has been written to a Logic 1, it is recommended that a 1-to-0 transition be written to CTRLB[5] to initiate a new frequency acquisition with respect to the reference clock. In this mode, if the ADN2817/ADN2818 lose lock for any reason, they relock onto the reference clock and continue to output a stable clock. 3. 4. Though the ADN2817/ADN2818 operate in LTR mode, if the user ever changes the reference frequency, the fREF range (CTRLA[7:6]), or the DIV_FREF ratio (CTRLA[5:2]), this must be followed by writing a 1-to-0 transition into the CTRLB[5] bit to initiate a new frequency acquisition. A frequency acquisition can also be initiated in LTR mode by writing a 0-to-1 transition into CTRLA[0]; however, it is recommended that a frequency acquisition be initiated by writing a 1-to-0 transition into CTRLB[5], as explained previously. Write a 1 to CTRLA[1]. This enables the fine data rate measurement capability of the ADN2817/ADN2818. This bit is level sensitive and does not need to be reset to perform subsequent frequency measurements. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. Read back MISC[2]. If it is 0, the measurement is not complete. If it is 1, the measurement is complete and the data rate can be read back on FREQ[22:0]. The time for a data rate measurement is typically 80 ms. Read back the data rate from the FREQ2[6:0], FREQ1[7:0], and FREQ0[7:0] registers. Use the following equation to determine the data rate: fDATARATE = (FREQ[22..0] × fREFCLK)/2(14 + SEL_RATE) where: FREQ[22:0] is the reading from FREQ2[6:0] (most significant byte), FREQ1[7:0], and FREQ0[7:0] (least significant byte). See Table 18. fDATARATE is the data rate (Mbps). fREFCLK is the REFCLK frequency (MHz). SEL_RATE is the setting from CTRLA[7:6]. Using the Reference Clock to Measure Data Frequency Table 18. The user can also provide a reference clock to measure the recovered data frequency. In this case, the user provides a reference clock, and the ADN2817/ADN2818 compare the frequency of the incoming data to the incoming reference clock and return a ratio of the two frequencies to 0.01% (100 ppm). The accuracy error of the reference clock is added to the accuracy of the ADN2817/ADN2818 data rate measurement. For example, if a 100 ppm accuracy reference clock is used, the total accuracy of the measurement is within 200 ppm. D22 The reference clock can range from 10 MHz to 200 MHz. The ADN2817/ADN2818 expects a reference clock between 10 MHz and 25 MHz by default. If it is between 25 MHz and 50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user needs to configure the ADN2817/ADN2818 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6]. Using the reference clock to determine the frequency of the incoming data does not affect the manner in which the part locks onto data. In this mode, the reference clock is used only to determine the frequency of the data. For this reason, the user does not need to know the data rate to use the reference clock in this manner. (1) D21:D17 FREQ2[6:0] D16 D15 D14:D9 FREQ1[7:0] D8 D7 D6:D1 D0 FREQ0[7:0] For example, if the reference clock frequency is 32 MHz, it falls within the 25 MHz to 50 MHz range; therefore, the CTRLA[7:6] setting is 01 resulting in SEL_RATE = 1. For this example, the input data rate is 2.488 Gbps (OC-48). After following Step 1 through Step 4, the value that is read back on FREQ[22:0] = 0x26E010, which is equal to 2.5477 × 106. Plugging this value into Equation 1 yields ((2.5477 × 106) × (32 × 106))/(2(14 + 1)) = 2.488 Gbps If subsequent frequency measurements are required, CTRLA[1] should remain set to 1. It does not need to be reset. The measurement process is reset by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. Follow Step 2 through Step 4 to read back the new data rate. Note that a data rate readback is valid only if LOL is low. If LOL is high, the data rate readback is invalid. Rev. E | Page 27 of 40 ADN2817/ADN2818 Data Sheet ADDITIONAL FEATURES AVAILABLE VIA THE I2C INTERFACE Coarse Data Rate Readback The data rate can be read back over the I2C interface to approximately ±10% without needing an external reference clock. A 9-bit register, COARSE_RD[8:0], can be read back when LOL is deasserted. The eight MSBs of this register are the contents of the Rate[7:0] register. The LSB of the COARSE_RD register is Bit MISC[0]. Table 19 is a look-up table (LUT) that provides coarse data rate readback values to within ±10%. LOS Configuration The LOS detector output, Pin 22 (LOS), can be configured as either active high or active low. If CTRLC[2] is set to Logic 0 (default), the LOS pin is active high when a loss of signal condition is detected. Writing a 1 to CTRLC[2] configures the LOS pin to be active low when a loss of signal condition is detected. Initiate Frequency Acquisition A frequency acquisition can be initiated by writing a 1 followed by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new frequency acquisition while keeping the ADN2817/ADN2818 in the operating mode that was previously programmed in the CTRLA, CTRLB, CTRLC, CTRLD, and CTRLE registers. Rate Selectivity The ADN2817/ADN2818 can operate in a limited range mode in situations where the user wants to restrict the data rates to which the device can lock. In this mode, the frequency acquisition range of the device is limited to a specific range of data rates. The acquisition range is determined by programming an upper and lower 9-bit code into the HI_CODE[8:1], LO_CODE[8:1], and CODE_LSB[1:0] I2C registers. See Table 20 for a look-up table (LUT) showing the correct register settings for each data rate. Table 20 has three columns: code, high limit, and low limit. The user programs the code value for the high limit data rate into HI_CODE and the code value for the low limit data rate into LO_CODE to set the appropriate range. For example, if the user wants to limit the acquisition range of the ADN2817/ADN2818 to lock between 1 Gbps and 1.25 Gbps, the following steps must be taken: 1. 2. 3. 4. 5. Find the first code in Table 20 that corresponds to a data rate below 1.0 Gbps in the low limit column, that is, Code 236 or 011101100b. Set LO_CODE[8:1] = 01110110b (LO_CODE[0] is set in Register Bit CODE_LSB[0].) Find the first code in Table 20 that corresponds to a data rate above 1.25 Gbps in the high limit column, that is, Code 258 or 100000010b. Set HI_CODE[8:1] = 10000001b (HI_CODE[0] is set in Register Bit CODE_LSB[1].) Set CODE_LSB = 00000000b given that the HI_CODE[0] = 0 and LO_CODE[0] = 0. Set SEL_MODE[3] = 1. When there is a valid input to the device between 1.0 Gbps and 1.25 Gbps, write a 1-to-0 transition into CTRLB[5] to initiate a new frequency acquisition. Double Data Rate Mode Setting CTRLE = 0x02 puts the ADN2817/ADN2818 clock output through divide-by-two circuitry allowing direct interfacing to FPGAs that support data clocking on both rising and falling edges. PRBS Generator/Detector The ADN2817/ADN2818 have an integrated PRBS generator/ detector for system testing purposes. The devices are configurable as either a PRBS detector or a PRBS generator. The two functions cannot be used at the same time. The following steps configure the PRBS detector (PRBS 7 only): 1. 2. Set CTRLE[2:0] = 0x5. Set CTRLD[2:0] = 0x4 to enable the PRBS detector. The PRBS error signal outputs on the DATAOUTP/DATAOUTN pins. Every time the PRBS detector detects an error, the DATAOUTP/DATAOUTN outputs pulse twice to a Logic 1, that is, DATAOUTP = 1, DATAOUTN = 0. The following steps configure the PRBS generator (PRBS 7 only): 1. 2. 3. Set CTRLE[2:0] = 0x5. Set CTRLD[2:0] = 0x1 to enable the PRBS generator. Write a 1-to-0 transition into CTRLD[3] to initiate a PRBS 7 pattern. Note that the PRBS generator is clocked by the VCO; therefore, the user needs to feed in a clock at half the desired frequency. For example, for an OC-48 PRBS pattern, input a 1.244 GHz clock to PIN/NIN. This appears as a 2.488 Gbps NRZ data pattern to the ADN2817/ADN2818. The recovered clock is 2.488 GHz, which clocks the PRBS generator to produce an OC-48 PRBS pattern on the outputs. Rev. E | Page 28 of 40 Data Sheet ADN2817/ADN2818 CLK Holdover Mode CDR Bypass Mode This mode of operation is available in LTD mode. In CLK holdover mode, the output clock frequency remains within ±5% if the input data is removed or changed. To operate in this mode, the user writes to the I2C to put the part into CLK holdover mode by setting SEL_MODE[1] = 1. The user must then initiate a frequency acquisition by writing a 1-to-0 transition into CTRLB[5], at which time the device locks onto the input data rate. At this point, the output frequency remains within ±5% of the initial acquired value regardless of whether the input data is removed or the data rate changes. The CDR on the ADN2817/ADN2818 can be bypassed by setting Bit CTRLD[7] = 1. In this mode, the ADN2817/ADN2818 feed the input directly through the input amplifiers to the output buffer, completely bypassing the CDR. It is important to note that all frequency acquisitions in this mode must be initiated by writing a 1-to-0 transition into CTRLB[5]. In this mode, the device does not automatically initiate a new frequency acquisition when the input is momentarily interrupted or if the input data rate changes. Disable Output Buffers The ADN2817/ADN2818 provide the option of disabling the output buffers for power savings. The clock output buffers can be disabled by setting Bit CTRLD[5] = 1. This reduces the total power consumption of the device by ~100 mW. For an additional 100 mW power savings, such as in low power standby mode, the data output buffers can also be disabled by setting Bit CTRLD[6] = 1. Rev. E | Page 29 of 40 ADN2817/ADN2818 Data Sheet APPLICATIONS INFORMATION If connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance, especially on Pin 24, which supplies power to the high speed CLKOUTP/CLKOUTN and DATAOUTP/DATAOUTN output buffers. See the schematic in Figure 36 for recommended connections. PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance. Power Supply Connections and Ground Planes For best practice, the use of one low impedance ground plane is recommended. To reduce series inductance, solder the VEE pins directly to the ground plane. If the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance, especially on Pin 23, which is the ground return for the output buffers. Connect the exposed pad to the ground plane using plugged vias so that solder does not leak through the vias during reflow. By using adjacent power supply and ground planes, excellent high frequency decoupling can be realized by using close spacing between the planes. This capacitance is given by CPLANE = 0.88εr A/d (pF) where: εr is the dielectric constant of the PCB material. A is the area of the overlap of power and ground planes (cm2). d is the separation between planes (mm). Use of a 10 µF electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they should be placed between the IC power supply (VCC and VEE), as close as possible to the ADN2817/ADN2818 VCC pins. For FR-4, εr = 4.4 and 0.25 mm spacing, C ≈ 15 pF/cm2. VCC 50Ω TRANSMISSION LINES 4 × 100Ω VCC + DATAOUTP 10µF DATAOUTN 0.1µF 1nF CLKOUTP CLKOUTN 32 PIN SLICEP 50Ω SLICEN VEE CLKOUTN SQUELCH DATAOUTP CLKOUTP 23 ADN2817/ ADN2818 3 22 TOP VIEW (Not to Scale) 4 21 5 20 EXPOSED PAD TIED OFF TO VEE PLANE WITH VIAS. 6 19 7 18 8 17 9 THRADJ CIN TIA 2 10 11 12 13 14 15 VCC VCC 0.1µF 1nF VEE LOS µC SDA SCK I2C CONTROLLER SADDR5 VCC VEE VCC 1nF 0.1µF 16 µC RTH 0.47µF +20% >300MΩ INSULATION RESISTANCE VCC 0.1µF 1nF Figure 36. Typical ADN2817/ADN2818 Applications Circuit Rev. E | Page 30 of 40 06001-025 50Ω 25 LOL VCC 26 24 CF2 NIN 27 1 REFCLKP 0.1µF 28 CF1 VREF 29 VEE 1nF 30 VCC VCC 0.1µF 31 REFCLKN BERMODE VEE VBER VCC 10kΩ DATAOUTN 10kΩ Data Sheet ADN2817/ADN2818 Transmission Lines Soldering Guidelines for Lead Frame Chip Scale Package Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also REFCLKP, REFCLKN, if using a high frequency reference clock, such as 155 MHz). It is also necessary for the PIN/NIN input traces to be matched in length, and the CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN output traces to be matched in length to avoid skew between the differential traces. The lands on the 32-lead LFCSP are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width. Center the land on the pad to ensure that the solder joint size is maximized. The bottom of the lead frame chip scale package has a central exposed pad. The pad on the printed circuit board should be at least as large as this exposed pad. The user must connect the exposed pad to VEE using plugged vias to prevent solder from leaking through the vias during reflow. This ensures a solid connection from the exposed pad to VEE. All high speed CML outputs (CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN) require 100 Ω back termination chip resistors connected between the output pin and VCC. Place these resistors as close as possible to the output pins. These 100 Ω resistors are in parallel with on-chip 100 Ω termination resistors to create a 50 Ω back termination (see Figure 37). The high speed inputs (PIN and NIN) are internally terminated with 50 Ω to an internal reference voltage (see Figure 38). A 0.1 μF capacitor is recommended between VREF, Pin 3, and GND to provide an ac ground for the inputs. As with any high speed mixed-signal design, take care to keep all high speed digital traces away from sensitive analog nodes. 100Ω 100Ω 100Ω VTERM 100Ω 0.1µF 50Ω For example, assuming that 2% droop can be tolerated, the maximum differential droop is 4%. Normalizing to peak-topeak voltage, 50Ω VTERM ADN2817/ADN2818 06001-026 50Ω 0.1µF Droop = Δ V = 0.04 V = 0.5 V p-p (1 − e–t/τ) ; therefore, τ = 12t Figure 37. Typical ADN2817/ADN2818 Applications Circuit where: τ is the RC time constant (C is the ac coupling capacitor, and R = 100 Ω seen by C). t is the total discharge time, which is equal to n. n is the number of CIDs. T is the bit period. ADN2817/ADN2818 VCC CIN TIA TIA PIN 50Ω NIN CIN 50Ω Calculate the capacitor value by combining the equations for τ and t. 50Ω 2.5V VREF 3kΩ C = 12nT/R 06001-027 0.1µF Figure 38. ADN2817/ADN2818 AC-Coupled Input Configuration AC coupling capacitors at the input (PIN, NIN) and output (DATAOUTP, DATAOUTN) of the ADN2817/ADN2818 must be chosen such that the device works properly over the full range of data rates used in the application. When choosing the capacitors, the time constant formed with the two 50 Ω resistors in the signal path must be considered. When a large number of consecutive identical digits (CIDs) are applied, the capacitor voltage can droop due to baseline wander (see Figure 39), causing pattern dependent jitter (PDJ). The user must determine how much droop is tolerable and choose an ac coupling capacitor based on that amount of droop. The amount of PDJ can then be approximated based on the capacitor selection. The actual capacitor value selection may require some trade-offs between droop and PDJ. VCC VCC Choosing AC Coupling Capacitors When the capacitor value is selected, the PDJ can be approximated as PDJps p-p = 0.5tr(1 − e(−nT/RC))/0.6 where: PDJps p-p is the amount of pattern-dependent jitter allowed; <0.01 UI p-p typical. tr is the rise time, which is equal to 0.22/BW, where BW ≈ 0.7 (bit rate). Note that this expression for tr is accurate only for the inputs. The output rise time for the ADN2817/ADN2818 is ~100 ps regardless of data rate. Rev. E | Page 31 of 40 ADN2817/ADN2818 Data Sheet VCC V1 V2 TIA 50Ω VREF 50Ω CIN V1b V2b 1 ADN2817 PIN DATAOUTP COUT CDR LIMAMP DATAOUTN NIN 2 3 4 V1 V1b V2 VREF V2b VDIFF VTH NOTES 1. DURING THE DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO. 2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE VREF LEVEL WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS. 3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER DOES NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2817. THE QUANTIZER RECOGNIZES BOTH HIGH AND LOW STATES AT THIS POINT. 06001-028 VDIFF = V2 – V2b VTH = ADN2817 QUANTIZER THRESHOLD Figure 39. Example of Baseline Wander PIN V p-p = PIN – NIN = 2 × VSE = 10mV AT SENSITIVITY VSE = 5mV MIN NIN VCM = 2.3V MIN (DC-COUPLED) 06001-030 The inputs to the ADN2817/ADN2818 can also be dc-coupled. This can be necessary in burst mode applications with long periods of CIDs and where baseline wander cannot be tolerated. If the inputs to the ADN2817/ADN2818 are dc-coupled, care must be taken not to violate the input range and common-mode level requirements of the ADN2817/ADN2818 (see Figure 40 through Figure 42). If dc coupling is required, and the output levels of the TIA do not adhere to the levels shown in Figure 41, level shifting and/or attenuation must occur between the TIA outputs and the ADN2817/ADN2818 inputs. INPUT (V) DC-COUPLED APPLICATION Figure 41. Minimum Allowed DC-Coupled Input Levels ADN2817/ADN2818 VCC PIN V p-p = PIN – NIN = 2 × VSE = 2.0V MAX PIN 50Ω VSE = 1.0V MAX 50Ω 0.1µF INPUT (V) NIN 50Ω VREF 3kΩ 2.5V VCM = 2.3V (DC-COUPLED) NIN 06001-031 06001-029 TIA TIA Figure 40. DC-Coupled Application Figure 42. Maximum Allowed DC-Coupled Input Levels Rev. E | Page 32 of 40 Data Sheet ADN2817/ADN2818 COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 19. Coarse Data Rate Readback Look-Up Table Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 fMID (Hz) 5.3205 × 106 5.3202 × 106 5.4294 × 106 5.5473 × 106 5.6735 × 106 5.8086 × 106 5.9533 × 106 6.1087 × 106 6.2771 × 106 6.4716 × 106 6.6702 × 106 6.8884 × 106 7.1269 × 106 7.3889 × 106 7.6789 × 106 7.9990 × 106 7.6264 × 106 7.6263 × 106 7.7893 × 106 7.9650 × 106 8.1539 × 106 8.3566 × 106 8.5749 × 106 8.8103 × 106 9.0650 × 106 9.3584 × 106 9.6606 × 106 9.9906 × 106 10.3514 × 106 10.7475 × 106 11.1821 × 106 11.6571 × 106 10.6409 × 106 10.6403 × 106 10.8588 × 106 11.0945 × 106 11.3469 × 106 11.6173 × 106 11.9065 × 106 12.2174 × 106 12.5543 × 106 12.9432 × 106 13.3403 × 106 13.7767 × 106 14.2539 × 106 14.7778 × 106 15.3577 × 106 15.9980 × 106 15.2529 × 106 Code 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 fMID (Hz) 15.2526 × 106 15.5785 × 106 15.9300 × 106 16.3078 × 106 16.7133 × 106 17.1498 × 106 17.6205 × 106 18.1300 × 106 18.7169 × 106 19.3212 × 106 19.9811 × 106 20.7027 × 106 21.4950 × 106 22.3642 × 106 23.3143 × 106 21.2818 × 106 21.2806 × 106 21.7177 × 106 22.1891 × 106 22.6939 × 106 23.2346 × 106 23.8130 × 106 24.4348 × 106 25.1085 × 106 25.8864 × 106 26.6807 × 106 27.5535 × 106 28.5078 × 106 29.5555 × 106 30.7155 × 106 31.9959 × 106 30.5057 × 106 30.5052 × 106 31.1570 × 106 31.8599 × 106 32.6155 × 106 33.4265 × 106 34.2996 × 106 35.2411 × 106 36.2600 × 106 37.4338 × 106 38.6424 × 106 39.9623 × 106 41.4055 × 106 42.9900 × 106 44.7284 × 106 46.6285 × 106 42.5637 × 106 42.5613 × 106 Code 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 Rev. E | Page 33 of 40 fMID (Hz) 43.4353 × 106 44.3782 × 106 45.3877 × 106 46.4691 × 106 47.6260 × 106 48.8696 × 106 50.2170 × 106 51.7728 × 106 53.3614 × 106 55.1069 × 106 57.0156 × 106 59.1111 × 106 61.4309 × 106 63.9919 × 106 61.0114 × 106 61.0103 × 106 62.3141 × 106 63.7198 × 106 65.2310 × 106 66.8530 × 106 68.5992 × 106 70.4821 × 106 72.5199 × 106 74.8675 × 106 77.2849 × 106 79.9245 × 106 82.8109 × 106 85.9801 × 106 89.4567 × 106 93.2571 × 106 85.1274 × 106 85.1226 × 106 86.8707 × 106 88.7564 × 106 90.7755 × 106 92.9383 × 106 95.2521 × 106 97.7392 × 106 100.4340 × 106 103.5457 × 106 106.7228 × 106 110.2139 × 106 114.0312 × 106 118.2222 × 106 122.8619 × 106 127.9838 × 106 122.0229 × 106 122.0206 × 106 124.6282 × 106 Code 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 fMID (Hz) 127.4396 × 106 130.4620 × 106 133.7061 × 106 137.1983 × 106 140.9643 × 106 145.0399 × 106 149.7350 × 106 154.5698 × 106 159.8491 × 106 165.6218 × 106 171.9601 × 106 178.9134 × 106 186.5142 × 106 170.2547 × 106 170.2451 × 106 173.7413 × 106 177.5128 × 106 181.5509 × 106 185.8765 × 106 190.5041 × 106 195.4784 × 106 200.8681 × 106 207.0913 × 106 213.4455 × 106 220.4277 × 106 228.0624 × 106 236.4443 × 106 245.7237 × 106 255.9676 × 106 244.0458 × 106 244.0412 × 106 249.2563 × 106 254.8792 × 106 260.9240 × 106 267.4122 × 106 274.3966 × 106 281.9286 × 106 290.0798 × 106 299.4700 × 106 309.1396 × 106 319.6981 × 106 331.2437 × 106 343.9202 × 106 357.8269 × 106 373.0284 × 106 340.5094 × 106 340.4903 × 106 347.4826 × 106 355.0256 × 106 ADN2817/ADN2818 Code 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 fMID (Hz) 363.1019 × 106 371.7531 × 106 381.0083 × 106 390.9568 × 106 401.7362 × 106 414.1826 × 106 426.8911 × 106 440.8554 × 106 456.1247 × 106 472.8887 × 106 491.4474 × 106 511.9351 × 106 488.0916 × 106 488.0824 × 106 498.5126 × 106 509.7584 × 106 521.8480 × 106 534.8244 × 106 548.7933 × 106 563.8571 × 106 580.1596 × 106 598.9401 × 106 618.2792 × 106 Data Sheet Code 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 fMID (Hz) 639.3962 × 106 662.4874 × 106 687.8404 × 106 715.6537 × 106 746.0568 × 106 681.0188 × 106 680.9806 × 106 694.9652 × 106 710.0511 × 106 726.2037 × 106 743.5062 × 106 762.0166 × 106 781.9136 × 106 803.4724 × 106 828.3653 × 106 853.7822 × 106 881.7109 × 106 912.2494 × 106 945.7774 × 106 982.8948 × 106 1.0239 × 109 976.1832 × 106 976.1648 × 106 Code 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 Rev. E | Page 34 of 40 fMID (Hz) 997.0253 × 106 1.0195 × 109 1.0437 × 109 1.0696 × 109 1.0976 × 109 1.1277 × 109 1.1603 × 109 1.1979 × 109 1.2366 × 109 1.2788 × 109 1.3250 × 109 1.3757 × 109 1.4313 × 109 1.4921 × 109 1.3620 × 109 1.3620 × 109 1.3899 × 109 1.4201 × 109 1.4524 × 109 1.4870 × 109 1.5240 × 109 1.5638 × 109 1.6069 × 109 Code 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 fMID (Hz) 1.6567 × 109 1.7076 × 109 1.7634 × 109 1.8245 × 109 1.8916 × 109 1.9658 × 109 2.0477 × 109 1.9524 × 109 1.9523 × 109 1.9941 × 109 2.0390 × 109 2.0874 × 109 2.1393 × 109 2.1952 × 109 2.2554 × 109 2.3206 × 109 2.3958 × 109 2.4731 × 109 2.5576 × 109 2.6499 × 109 2.7514 × 109 2.8626 × 109 2.9842 × 109 Data Sheet ADN2817/ADN2818 HI_CODE AND LO_CODE LOOK-UP TABLE Code is the 9-bit value to be written into HI_CODE[8:0] and LO_CODE[8:0]. Use the high limit code for HI_CODE and the low limit code for LO_CODE. Table 20. Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Low Limit 5.7633 × 106 5.7631 × 106 5.8777 × 106 6.0011 × 106 6.1328 × 106 6.2738 × 106 6.4245 × 106 6.5859 × 106 6.7593 × 106 6.9599 × 106 7.1641 × 106 7.3860 × 106 7.6292 × 106 7.8947 × 106 8.1855 × 106 8.5061 × 106 8.2705 × 106 8.2701 × 106 8.4414 × 106 8.6260 × 106 8.8239 × 106 9.0356 × 106 9.2629 × 106 9.5073 × 106 9.7707 × 106 10.0733 × 106 10.3832 × 106 10.7202 × 106 11.0869 × 106 11.4873 × 106 11.9244 × 106 12.3996 × 106 11.5265 × 106 11.5261 × 106 11.7554 × 106 12.0022 × 106 12.2655 × 106 12.5475 × 106 12.8490 × 106 13.1718 × 106 13.5186 × 106 13.9198 × 106 14.3282 × 106 14.7719 × 106 15.2584 × 106 15.7894 × 106 16.3711 × 106 17.0122 × 106 High Limit 4.8677 × 106 4.8674 × 106 4.9708 × 106 5.0827 × 106 5.2027 × 106 5.3312 × 106 5.4692 × 106 5.6188 × 106 5.7807 × 106 5.9680 × 106 6.1614 × 106 6.3740 × 106 6.6070 × 106 6.8660 × 106 7.1541 × 106 7.4742 × 106 6.9705 × 106 6.9703 × 106 7.1241 × 106 7.2904 × 106 7.4696 × 106 7.6624 × 106 7.8705 × 106 8.0958 × 106 8.3404 × 106 8.6236 × 106 8.9165 × 106 9.2377 × 106 9.5915 × 106 9.9825 × 106 10.4145 × 106 10.8902 × 106 9.7355 × 106 9.7347 × 106 9.9415 × 106 10.1654 × 106 10.4053 × 106 10.6624 × 106 10.9384 × 106 11.2376 × 106 11.5615 × 106 11.9360 × 106 12.3228 × 106 12.7480 × 106 13.2140 × 106 13.7321 × 106 14.3081 × 106 14.9484 × 106 Code 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Rev. E | Page 35 of 40 Low Limit 16.5410 × 106 16.5402 × 106 16.8827 × 106 17.2521 × 106 17.6479 × 106 18.0712 × 106 18.5258 × 106 19.0145 × 106 19.5415 × 106 20.1465 × 106 20.7665 × 106 21.4403 × 106 22.1738 × 106 22.9747 × 106 23.8487 × 106 24.7993 × 106 23.0530 × 106 23.0523 × 106 23.5108 × 106 24.0044 × 106 24.5310 × 106 25.0951 × 106 25.6980 × 106 26.3436 × 106 27.0373 × 106 27.8396 × 106 28.6564 × 106 29.5438 × 106 30.5167 × 106 31.5787 × 106 32.7422 × 106 34.0244 × 106 33.0819 × 106 33.0805 × 106 33.7655 × 106 34.5041 × 106 35.2957 × 106 36.1424 × 106 37.0517 × 106 38.0290 × 106 39.0830 × 106 40.2930 × 106 41.5329 × 106 42.8807 × 106 44.3477 × 106 45.9493 × 106 47.6975 × 106 49.5986 × 106 High Limit 13.9411 × 106 13.9407 × 106 14.2483 × 106 14.5807 × 106 14.9392 × 106 15.3247 × 106 15.7411 × 106 16.1915 × 106 16.6807 × 106 17.2471 × 106 17.8330 × 106 18.4754 × 106 19.1829 × 106 19.9651 × 106 20.8291 × 106 21.7805 × 106 19.4710 × 106 19.4695 × 106 19.8831 × 106 20.3308 × 106 20.8107 × 106 21.3248 × 106 21.8768 × 106 22.4751 × 106 23.1230 × 106 23.8720 × 106 24.6457 × 106 25.4960 × 106 26.4281 × 106 27.4641 × 106 28.6162 × 106 29.8968 × 106 27.8821 × 106 27.8813 × 106 28.4965 × 106 29.1615 × 106 29.8783 × 106 30.6494 × 106 31.4822 × 106 32.3831 × 106 33.3615 × 106 34.4942 × 106 35.6659 × 106 36.9508 × 106 38.3658 × 106 39.9301 × 106 41.6582 × 106 43.5610 × 106 ADN2817/ADN2818 Code 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 Low Limit 46.1061 × 106 46.1045 × 106 47.0217 × 106 48.0087 × 106 49.0620 × 106 50.1902 × 106 51.3960 × 106 52.6872 × 106 54.0746 × 106 55.6792 × 106 57.3128 × 106 59.0876 × 106 61.0334 × 106 63.1575 × 106 65.4843 × 106 68.0487 × 106 66.1639 × 106 66.1609 × 106 67.5309 × 106 69.0082 × 106 70.5914 × 106 72.2848 × 106 74.1034 × 106 76.0580 × 106 78.1660 × 106 80.5861 × 106 83.0658 × 106 85.7613 × 106 88.6953 × 106 91.8987 × 106 95.3950 × 106 99.1972 × 106 92.2121 × 106 92.2090 × 106 94.0434 × 106 96.0174 × 106 98.1240 × 106 100.3804 × 106 102.7920 × 106 105.3744 × 106 108.1491 × 106 111.3583 × 106 114.6257 × 106 118.1753 × 106 122.0668 × 106 126.3150 × 106 130.9686 × 106 136.0974 × 106 132.3278 × 106 132.3218 × 106 135.0619 × 106 138.0164 × 106 141.1829 × 106 Data Sheet High Limit 38.9419 × 106 38.9390 × 106 39.7661 × 106 40.6617 × 106 41.6214 × 106 42.6496 × 106 43.7535 × 106 44.9502 × 106 46.2459 × 106 47.7440 × 106 49.2913 × 106 50.9920 × 106 52.8561 × 106 54.9282 × 106 57.2324 × 106 59.7936 × 106 55.7643 × 106 55.7626 × 106 56.9931 × 106 58.3229 × 106 59.7566 × 106 61.2989 × 106 62.9643 × 106 64.7662 × 106 66.7230 × 106 68.9885 × 106 71.3318 × 106 73.9016 × 106 76.7317 × 106 79.8603 × 106 83.3164 × 106 87.1220 × 106 77.8839 × 106 77.8780 × 106 79.5323 × 106 81.3234 × 106 83.2427 × 106 85.2993 × 106 87.5071 × 106 89.9004 × 106 92.4919 × 106 95.4879 × 106 98.5827 × 106 101.9841 × 106 105.7122 × 106 109.8565 × 106 114.4648 × 106 119.5872 × 106 111.5286 × 106 111.5252 × 106 113.9862 × 106 116.6459 × 106 119.5132 × 106 Code 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 Rev. E | Page 36 of 40 Low Limit 144.5697 × 106 148.2068 × 106 152.1160 × 106 156.3320 × 106 161.1721 × 106 166.1317 × 106 171.5227 × 106 177.3906 × 106 183.7974 × 106 190.7899 × 106 198.3944 × 106 184.4242 × 106 184.4181 × 106 188.0868 × 106 192.0348 × 106 196.2480 × 106 200.7608 × 106 205.5841 × 106 210.7488 × 106 216.2983 × 106 222.7166 × 106 229.2514 × 106 236.3506 × 106 244.1336 × 106 252.6300 × 106 261.9373 × 106 272.1948 × 106 264.6556 × 106 264.6437 × 106 270.1237 × 106 276.0329 × 106 282.3657 × 106 289.1393 × 106 296.4136 × 106 304.2321 × 106 312.6640 × 106 322.3443 × 106 332.2633 × 106 343.0453 × 106 354.7812 × 106 367.5947 × 106 381.5798 × 106 396.7887 × 106 368.8485 × 106 368.8362 × 106 376.1735 × 106 384.0696 × 106 392.4961 × 106 401.5216 × 106 411.1681 × 106 421.4977 × 106 432.5966 × 106 445.4332 × 106 High Limit 122.5977 × 106 125.9286 × 106 129.5324 × 106 133.4459 × 106 137.9770 × 106 142.6637 × 106 147.8032 × 106 153.4634 × 106 159.7205 × 106 166.6328 × 106 174.2440 × 106 155.7678 × 106 155.7560 × 106 159.0645 × 106 162.6467 × 106 166.4855 × 106 170.5985 × 106 175.0142 × 106 179.8008 × 106 184.9838 × 106 190.9759 × 106 197.1654 × 106 203.9681 × 106 211.4245 × 106 219.7129 × 106 228.9296 × 106 239.1744 × 106 223.0571 × 106 223.0505 × 106 227.9723 × 106 233.2917 × 106 239.0265 × 106 245.1954 × 106 251.8572 × 106 259.0647 × 106 266.8919 × 106 275.9539 × 106 285.3273 × 106 295.6065 × 106 306.9268 × 106 319.4411 × 106 333.2656 × 106 348.4879 × 106 311.5355 × 106 311.5120 × 106 318.1291 × 106 325.2934 × 106 332.9710 × 106 341.1971 × 106 350.0283 × 106 359.6016 × 106 369.9675 × 106 381.9518 × 106 Data Sheet Code 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 Low Limit 458.5027 × 106 472.7012 × 106 488.2673 × 106 505.2599 × 106 523.8745 × 106 544.3897 × 106 529.3112 × 106 529.2874 × 106 540.2475 × 106 552.0658 × 106 564.7314 × 106 578.2786 × 106 592.8272 × 106 608.4642 × 106 625.3279 × 106 644.6885 × 106 664.5266 × 106 686.0907 × 106 709.5624 × 106 735.1895 × 106 763.1596 × 106 793.5774 × 106 737.6969 × 106 737.6724 × 106 752.3471 × 106 768.1392 × 106 784.9921 × 106 803.0432 × 106 822.3363 × 106 842.9953 × 106 865.1931 × 106 890.8664 × 106 917.0055 × 106 945.4024 × 106 976.5346 × 106 1.0105 × 109 1.0477 × 109 1.0888 × 109 1.0586 × 109 1.0586 × 109 1.0805 × 109 1.1041 × 109 1.1295 × 109 1.1566 × 109 1.1857 × 109 ADN2817/ADN2818 High Limit 394.3307 × 106 407.9363 × 106 422.8489 × 106 439.4259 × 106 457.8593 × 106 478.3487 × 106 446.1142 × 106 446.1009 × 106 455.9446 × 106 466.5834 × 106 478.0529 × 106 490.3908 × 106 503.7145 × 106 518.1295 × 106 533.7838 × 106 551.9079 × 106 570.6547 × 106 591.2129 × 106 613.8536 × 106 638.8822 × 106 666.5311 × 106 696.9759 × 106 623.0711 × 106 623.0240 × 106 636.2582 × 106 650.5869 × 106 665.9419 × 106 682.3941 × 106 700.0567 × 106 719.2032 × 106 739.9350 × 106 763.9035 × 106 788.6615 × 106 815.8726 × 106 845.6979 × 106 878.8518 × 106 915.7186 × 106 956.6975 × 106 892.2284 × 106 892.2018 × 106 911.8893 × 106 933.1668 × 106 956.1059 × 106 980.7817 × 106 1.0074 × 109 Code 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 Rev. E | Page 37 of 40 Low Limit 1.2169 × 109 1.2507 × 109 1.2894 × 109 1.3291 × 109 1.3722 × 109 1.4191 × 109 1.4704 × 109 1.5263 × 109 1.5872 × 109 1.4754 × 109 1.4753 × 109 1.5047 × 109 1.5363 × 109 1.5700 × 109 1.6061 × 109 1.6447 × 109v 1.6860 × 109 1.7304 × 109 1.7817 × 109 1.8340 × 109 1.8908 × 109 1.9531 × 109 2.0210 × 109 2.0955 × 109 2.1776 × 109 2.1172 × 109 2.1171 × 109 2.1610 × 109 2.2083 × 109 2.2589 × 109 2.3131 × 109 2.3713 × 109 2.4339 × 109 2.5013 × 109 2.5788 × 109 2.6581 × 109 2.7444 × 109 2.8382 × 109 2.9408 × 109 3.0526 × 109 3.1743 × 109 High Limit 1.0363 × 109 1.0676 × 109 1.1038 × 109 1.1413 × 109 1.1824 × 109 1.2277 × 109 1.2778 × 109 1.3331 × 109 1.3940 × 109 1.2461 × 109 1.2460 × 109 1.2725 × 109 1.3012 × 109 1.3319 × 109 1.3648 × 109 1.4001 × 109 1.4384 × 109 1.4799 × 109 1.5278 × 109 1.5773 × 109 1.6317 × 109 1.6914 × 109 1.7577 × 109 1.8314 × 109 1.9134 × 109 1.7845 × 109 1.7844 × 109 1.8238 × 109 1.8663 × 109 1.9122 × 109 1.9616 × 109 2.0149 × 109 2.0725 × 109 2.1351 × 109 2.2076 × 109 2.2826 × 109 2.3649 × 109 2.4554 × 109 2.5555 × 109 2.6661 × 109 2.7879 × 109 ADN2817/ADN2818 Data Sheet OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 0.50 BSC 3.65 3.50 SQ 3.35 EXPOSED PAD 17 8 16 TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE 0.80 MAX 0.65 TYP 0.30 0.25 0.18 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 9 0.25 MIN BOTTOM VIEW 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 04-13-2012-A 4.75 BSC SQ PIN 1 INDICATOR PIN 1 INDICATOR 32 1 25 24 Figure 43. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADN2817ACPZ ADN2817ACPZ-RL ADN2817ACPZ-RL7 ADN2818ACPZ ADN2818ACPZ-RL ADN2818ACPZ-RL7 EVAL-ADN2817EBZ EVAL-ADN2818EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ, 13” Tape and Reel 32-Lead LFCSP_VQ, 7” Tape and Reel 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ, 13” Tape and Reel 32-Lead LFCSP_VQ, 7” Tape and Reel Evaluation Board for ADN2817 Evaluation Board for ADN2818 Z = RoHS Compliant Part. Rev. E | Page 38 of 40 Package Option CP-32-4 CP-32-4 CP-32-4 CP-32-4 CP-32-4 CP-32-4 Ordering Quantity 490 5,000 1,500 490 5,000 1,500 Data Sheet ADN2817/ADN2818 NOTES Rev. E | Page 39 of 40 ADN2817/ADN2818 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06001-0-1/13(E) Rev. E | Page 40 of 40