1997-1/21 MITSUBISHI LSIs M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL, -70VLL,-10VLL,-12VLL,-15VLL 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) ADDRESS INPUTS FEATURES Type name M5M51008BFP,VP,RV,KV,KR-70VL M5M51008BFP,VP,RV,KV,KR-10VL M5M51008BFP,VP,RV,KV,KR-12VL M5M51008BFP,VP,RV,KV,KR-15VL M5M51008BFP,VP,RV,KV,KR-70VLL M5M51008BFP,VP,RV,KV,KR-10VLL M5M51008BFP,VP,RV,KV,KR-12VLL M5M51008BFP,VP,RV,KV,KR-15VLL Access time (max) 70ns 100ns 120ns 150ns 70ns 100ns 120ns 150ns Power supply current VCC Active stand-by (1MHz) (max) (max) 3.3±0.3V 10mA 60µA 3.0±0.3V 10mA 55µA 3.3±0.3V 10mA 3.0±0.3V 10mA DATA INPUTS/ OUTPUTS 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC ADDRESS A15 INPUT SELECT S2 CHIP INPUT CONTROL W WRITE INPUT A13 A8 ADDRESS INPUTS A9 A11 ENABLE OE OUTPUT INPUT ADDRESS A10 INPUT SELECT S1 CHIP INPUT DQ8 DQ7 DQ6 DATA INPUTS/ DQ5 OUTPUTS DQ4 Outline 32P2M-A 12µA 11µA Low stand-by current 0.3µA (typ.) Directly TTL compatible : All inputs and outputs Easy memory expansion and power down by S1,S2 Data hold on +2V power supply Three-state outputs : OR - tie capability OE prevents data contention in the I/O bus Common data I/O Package M5M51008BFP ············ 32pin 525mil SOP M5M51008BVP,RV ············ 32pin 8 X 20 mm 2 TSOP M5M51008BKV,KR ············ 32pin 8 X 13.4 mm 2 TSOP A11 A9 A8 A13 W 1 32 2 31 3 30 OE A10 S1 4 29 DQ8 5 28 DQ7 S2 A15 VCC NC A16 A14 A12 A7 A6 6 27 7 26 DQ6 DQ5 DQ4 GND DQ3 DQ2 A5 A4 8 M5M51008BVP,KV 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 DQ1 A0 A1 A2 A3 Outline 32P3H-E(VP), 32P3K-B(KV) APPLICATION Small capacity memory units NC 1 A16 2 A14 3 A12 4 5 A7 6 A6 7 A5 8 A4 9 A3 A2 10 A1 11 A0 12 DQ1 13 DQ2 14 DQ3 15 GND 16 M5M51008BFP The M5M51008BFP,VP,RV,KV,KR are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using high-performance triple polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery result in a high density and low power static RAM. They are low standby current and low operation current and ideal for the battery back-up application. The M5M51008BVP,RV,KV,KR are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(SMD).Two types of devices are available. VP,KV(normal lead bend type package),RV,KR(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board. A4 A5 A6 16 17 15 18 14 19 A7 A12 A14 A16 NC VCC 13 20 12 21 11 22 10 23 8 25 A15 S2 7 26 6 27 W A13 A8 5 28 4 29 3 30 A9 A11 2 31 1 32 9 M5M51008BRV,KR 24 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 DQ8 S1 A10 OE Outline 32P3H-F(RV), 32P3K-C(KR) NC : NO CONNECTION 1 MITSUBISHI ELECTRIC 1997-1/21 MITSUBISHI LSIs M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL, -70VLL,-10VLL,-12VLL,-15VLL 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM FUNCTION The operation mode of the M5M51008B series are determined by a combination of the device control inputs S1,S2,W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S 1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W,S1 or S2,whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while S1 and S2 are in an active state(S1=L,S2=H). When setting S1 at a high level or S2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high- impedance state, allowing OR-tie with other chips and memory expansion by S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as ICC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. FUNCTION TABLE S1 X H L L L S2 L X H H H Mode DQ OE X Non selection High-impedance X Non selection High-impedance Din X Write Dout L Read High-impedance H W X X L H H ICC Stand-by Stand-by Active Active Active BLOCK DIAGRAM * * 21 13 DQ1 A5 7 15 22 14 DQ2 A6 6 14 23 15 DQ3 A7 5 13 25 17 DQ4 A12 4 12 26 18 DQ5 A14 3 11 27 19 DQ6 A16 2 10 28 20 DQ7 A15 31 7 29 21 DQ8 A13 28 4 A8 27 3 A0 12 20 A2 10 18 A3 17 A1 11 19 A11 25 1 A9 26 2 COLUMN DECODER 31 CLOCK GENERATOR OUTPUT BUFFER BLOCK DECODER A10 23 ADDRESS INPUT BUFFER 9 ADDRESS INPUT BUFFER ADDRESS INPUTS * Pin numbers inside dotted line show those of TSOP 2 DATA INPUTS/ OUTPUTS DATA INPUT BUFFER 131072 WORDS X 8 BITS (1024 ROWS X128 COLUMNS X 8BLOCKS) SENSE AMP. 16 ROW DECODER 8 ADDRESS INPUT BUFFER A4 MITSUBISHI ELECTRIC 5 WRITE 29 W CONTROL INPUT 30 22 S1 6 30 S2 32 OUTPUT 24 OE ENABLE INPUT 8 32 VCC 24 GND 16 (0V) CHIP SELECT INPUTS 1997-1/21 MITSUBISHI LSIs M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL, -70VLL,-10VLL,-12VLL,-15VLL 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc Supply voltage VI Input voltage VO Pd Topr Tstg Output voltage Power dissipation Operating temperature Storage temperature Parameter Ratings – 0.3*~4.6 – 0.3*~Vcc + 0.3 (Max 4.6) Conditions With respect to GND Unit V V V 0~Vcc 700 Ta=25°C 0~70 – 65~150 mW °C °C -12VL, -12VLL -15VL, -15VLL Unit * –3.0V in case of AC ( Pulse width ≤ 30ns ) DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, unless otherwise noted) Limits Symbol Parameter -70VL, -70VLL -10VL, -10VLL Test conditions VCC=3.3±0.3V Min Typ Max Vcc +0.3V VCC=3.0±0.3V Min Typ Max Vcc +0.3V V 0.6 VIH High-level input voltage VIL VOH1 Low-level input voltage High-level output voltage 1 IOH= –0.5mA VOH2 High-level output voltage 2 IOH= –0.05mA VOL II Low-level output voltage Input current IOL=2mA VI=0~Vcc 0.4 ±1 0.4 ±1 V µA IO Output current in off-state S1=VIH or S2=VIL or OE=VIH VI/O=0~VCC ±1 ±1 µA ICC1 Active supply current (Min cycle ) ICC2 Active supply current (1MHz) ICC3 ICC4 2.0 Stand-by current 2.4 2.4 V V Vcc -0.5V Vcc -0.5V V –0.3 S1=VIL,S2=VIH, other inputs=VIH or VIL Output-open(duty 100%) 1) S2 ≤ 0.2V 2) S1 ≥ VCC–0.2V, S2 ≥ VCC–0.2V other inputs=0~VCC 0.6 –0.3 20 35 15 30 3 10 3 10 mA -L 60 55 -LL 12 11 0.33 0.33 µA S1=VIH or S2=VIL, other inputs=0~VCC Stand-by current 2.0 mA * –3.0V in case of AC ( Pulse width ≤ 30ns ) CAPACITANCE (Ta=0~70°C, unless otherwise noted) Symbol CI CO Parameter Input capacitance Output capacitance Test conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is Vcc = 3V, Ta = 25°C 3 MITSUBISHI ELECTRIC Min Limits Typ Max 6 8 Unit pF pF 1997-1/21 MITSUBISHI LSIs M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL, -70VLL,-10VLL,-12VLL,-15VLL 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, unless otherwise noted ) (1) MEASUREMENT CONDITIONS 1TTL VCC ................................. 3.3±0.3V(-70VL,-70VLL,-10VL,-10VLL) 3.0±0.3V(-12VL,-12VLL,-15VL,-15VLL) Input pulse level ............. VIH=2.2V,VIL=0.4V Input rise and fall time ..... 5ns Reference level ............... VOH=VOL=1.5V Output loads ................... Fig.1,CL=100pF (-15VL,-15VLL,) CL=30pF (-70VL,-10VL,12VL,-70VLL,-10VLL,12VLL) CL=5pF (for ten,tdis) Transition is measured ± 500mV from steady state voltage. (for ten,tdis) DQ CL including scope and JIG Fig.1 Output load (2) READ CYCLE Limits Symbol tCR ta(A) ta(S1) ta(S2) ta(OE) tdis(S1) tdis(S2) tdis(OE) ten(S1) ten(S2) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select 1 access time Chip select 2 access time Output enable access time Output disable time after S1 high Output disable time after S2 low Output disable time after OE high Output enable time after S1 low Output enable time after S2 high Output enable time after OE low Data valid time after address -70VL,VLL Min Max 70 70 -10VL,VLL Min Max 100 100 100 100 50 35 70 70 35 25 25 25 10 -12VL,VLL Min Max 120 120 120 120 60 40 35 35 10 150 150 75 50 50 50 40 40 10 10 10 5 10 10 5 -15VL,VLL Min Max 150 150 10 10 5 10 10 5 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol tCW tw(W) tsu(A) tsu(A-WH) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) 4 Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to W Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recovery time Output disable time from W low Output disable time from OE high Output enable time from W high Output enable time from OE low -70VL,VLL Min Max 70 55 0 65 65 65 30 0 0 -10VL,VLL Min Max 100 75 0 85 85 85 40 0 0 25 25 5 5 -12VL,VLL Min Max 120 85 0 100 100 100 45 0 0 35 35 5 5 MITSUBISHI ELECTRIC -15VL,VLL Min Max 150 100 0 120 120 120 50 0 0 40 40 5 5 50 50 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 1997-1/21 MITSUBISHI LSIs M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL, -70VLL,-10VLL,-12VLL,-15VLL 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM (4) TIMING DIAGRAMS Read cycle tCR A0~16 ta(A) tv (A) ta (S1) S1 (Note 3) tdis (S1) S2 (Note 3) ta (S2) (Note 3) tdis (S2) ta (OE) (Note 3) ten (OE) OE (Note 3) tdis (OE) (Note 3) ten (S1) ten (S2) DQ1~8 DATA VALID W = "H" level Write cycle (W control mode) tCW A0~16 tsu (S1) S1 (Note 3) (Note 3) S2 tsu (S2) (Note 3) (Note 3) tsu (A-WH) OE tsu (A) tw (W) trec (W) W tdis (W) ten(OE) ten (W) tdis (OE) DQ1~8 DATA IN STABLE tsu (D) 5 th (D) MITSUBISHI ELECTRIC 1997-1/21 MITSUBISHI LSIs M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL, -70VLL,-10VLL,-12VLL,-15VLL 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM Write cycle ( S1 control mode) tCW A0~16 tsu (A) tsu (S1) trec (W) S1 S2 (Note 3) (Note 3) (Note 5) W (Note 4) (Note 3) (Note 3) tsu (D) th (D) DATA IN STABLE DQ1~8 Write cycle (S2 control mode) tCW A0~16 S1 (Note 3) (Note 3) tsu (A) tsu (S2) trec (W) S2 (Note 5) W (Note 4) (Note 3) (Note 3) tsu (D) DQ1~8 th (D) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". 4: Writing is executed while S2 high overlaps S1 and W low. 5: When the falling edge of W is simultaneously or prior to the falling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. 6: Don't apply inverted phase signal externally when DQ pin is output mode. 6 MITSUBISHI ELECTRIC 1997-1/21 MITSUBISHI LSIs M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL, -70VLL,-10VLL,-12VLL,-15VLL 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, unless otherwise noted) Symbol Parameter VCC (PD) VI (S1) Power down supply voltage Chip select input S1 VI (S2) Chip select input S2 ICC (PD) Test conditions Min 2 2.0 Limits Typ Max V V 0.2 VCC = 3V -L 1) S2 ≤ 0.2V, other inputs = 0~3V 2) S1 ≥ VCC - 0.2V,S2 ≥ VCC - 0.2V -LL other inputs = 0~3V Power down supply current Unit V 50 µA 0.3 10 (Note 7) Note7: ICC (PD) = 1µA in case of Ta = 25°C (2) TIMING REQUIREMENTS (Ta = 0~70°C, unless otherwise noted ) Symbol tsu (PD) trec (PD) Parameter Test conditions Power down set up time Power down recovery time Min 0 5 Limits Typ Max Unit ns ms (3) POWER DOWN CHARACTERISTICS S1 control mode VCC t su (PD) 3.0V* 3.0V* t rec (PD) 2.2V 2.2V S1 ≥ VCC - 0.2V S1 S2 control mode VCC S2 t su (PD) 3.0V* 3.0V* t rec (PD) 0.2V 0.2V S2 ≤ 0.2V *Note 2.7V(-12VL,-12VLL,-15VL,-15VLL) 7 MITSUBISHI ELECTRIC