Order Now Product Folder Support & Community Tools & Software Technical Documents CSD95492QVM SLPS672 – JUNE 2017 CSD95492QVM Synchronous Buck NexFET™ Smart Power Stage 1 Features 2 Applications • • • • • • 1 • • • • • • • • • • • 20-A Continuous Operating Current Capability Over 94% System Efficiency at 12 A High-Frequency Operation (up to 1.25 MHz) Diode Emulation Function Temperature Compensated Bi-Directional Current Sense Analog Temperature Output Fault Monitoring 3.3-V and 5-V PWM Signal Compatible Tri-State PWM Input Integrated Bootstrap Switch Optimized Dead Time for Shoot-Through Protection High-Density VSON 4-mm × 5-mm Footprint Ultra-Low-Inductance Package System Optimized PCB Footprint RoHS Compliant – Lead-Free Terminal Plating Halogen Free Multiphase Synchronous Buck Converters – High-Frequency Applications – High-Current, Low-Duty Cycle Applications POL DC-DC Converters Memory and Graphic Cards Desktop and Server VR12.x / VR13.x VRM Synchronous Buck Converters • • • 3 Description The CSD95492QVM NexFET™ power stage is a highly optimized design for use in a high-power, highdensity synchronous buck converter. This product integrates the driver IC and power MOSFETs to complete the power stage switching function. This combination produces high-current, high-efficiency, and high-speed switching capability in a small 4-mm × 5-mm outline package. It also integrates the accurate current sensing and temperature sensing functionality to simplify system design and improve accuracy. In addition, the PCB footprint has been optimized to help reduce design time and simplify the completion of the overall system design. Device Information(1) Application Diagram P12V AVSP AVSN TPS53679 BOOT VIN ASKIP# P5V EN/FCCM VOS QTY PACKAGE SHIP 2500 CSD95492QVMT 7-Inch Reel 250 VSON 4.00-mm × 5.00-mm Package Tape and Reel VSW VDD TAO LSET MEDIA 13-Inch Reel BOOT_R CSD95490Q5M PWM PWM1 DEVICE CSD95492QVM PGND LOAD IOUT REFIN (1) For all available packages, see the orderable addendum at the end of the data sheet. ACSP1 Typical Power Stage Efficiency and Power Loss TSEN 100 P12V BOOT P5V VREF ADDR EN/FCCM VOS TAO PGND Efficiency (%) V3P3 ACSP6 VREF VIN_CSNIN CSPIN VCCIO BEN_VCCIO SCLK SDIO SALERT# PIN_ALT# VR_HOT# SMB_CLK SMB_ALERT# SMB_DIO AVR_RDY BVR_RDY AVR_EN VR_FAULT# RESET# BVSN BVSP P12V BOOT VIN PWM BPWM1 BSKIP# P5V 1.6 85 1.4 80 1.2 75 1 CSD95492QVM VOS VDD = 5 V VIN = 12 V VOUT = 1.2 V LOUT = 220 nH fSW = 500 kHz TA = 25qC 60 VSW VDD TAO PGND 70 65 BOOT_R EN/FCCM LSET 1.8 90 IOUT REFIN 3.3V P12V 95 VSW VDD LSET 2 BOOT_R CSD95490Q5M LOAD IOUT REFIN 55 50 0 BCSP1 AGND 4 8 12 Output Current (A) 16 0.8 0.6 Power Loss (W) VIN PWM APWM6 0.4 0.2 0 20 D000 Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD95492QVM SLPS672 – JUNE 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 8 8.1 8.2 8.3 8.4 8.5 9 6.1 Absolute Maximum Ratings ...................................... 4 6.2 ESD Ratings.............................................................. 4 6.3 Recommended Operating Conditions....................... 4 7 Device and Documentation Support.................... 6 Receiving Notification of Documentation Updates.... Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 6 6 6 6 6 Mechanical, Packaging, and Orderable Information ............................................................. 7 9.1 Mechanical Drawing.................................................. 7 9.2 Recommended PCB Land Pattern............................ 8 9.3 Recommended Stencil Opening ............................... 9 Application Schematic .......................................... 5 4 Revision History 2 DATE REVISION NOTES June 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95492QVM CSD95492QVM www.ti.com SLPS672 – JUNE 2017 5 Pin Configuration and Functions Top View Pin Functions PIN DESCRIPTION NAME NO. REFIN 1 External reference voltage input for current sensing amplifier. IOUT 2 Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current. LSET 3 A resistor from this pin to PGND pin sets the inductor value for the internal current sensing circuitry. VDD 4 Supply voltage for gate drivers and internal circuitry. VOS 5 Output voltage sensing pin for the internal current sensing circuitry. SW 6-9 VIN 10-13 Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor. Input voltage pin. Connect input capacitors close to this pin. BOOTR 14 Return path for HS gate driver. It is connected to VSW internally. BOOT 15 Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic cap from BOOT to BOOTR pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated. PWM 16 Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high sets control FET gate high and sync FET gate low. Both MOSFET gates are set low if PWM stays in Hi-Z for greater than the tri-state shutdown holdoff time (t3HT). EN/FCCM 17 This dual function pin either enables the diode emulation function or can be used as a simple enable for the device. When this pin is driven into the tri-state window and held there for more than the tri-state holdoff time, Diode Emulation Mode is enabled for sync FET. When the pin is high, device operates in Forced Continuous Conduction Mode. When the pin is low, both FETs are held off. An internal resistor pulls this pin low if left floating. TAO/FAULT 18 Temperature Amplifier Output. Reports a voltage proportional to the IC temperature. An ORing diode is integrated in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown, LSOC, or HSS detection circuit is tripped. PGND 19 Power ground. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95492QVM 3 CSD95492QVM SLPS672 – JUNE 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings TA = 25°C (unless otherwise stated) (1) MIN MAX UNIT VIN to PGND –0.3 20 V VIN to VSW –0.3 20 V 23 V –0.3 20 V VIN to VSW (10 ns) VSW to PGND VSW to PGND (10 ns) –7 23 V VDD to PGND –0.3 7 V EN/FCCM, TAO/FLT, LSET to PGND (2) –0.3 VDD + 0.3 V IOUT, VOS, PWM to PGND –0.3 7 V REFIN –0.3 3.6 V BOOT to BOOTR (2) –0.3 VDD + 0.3 V BOOT to PGND –0.3 30 V TJ Operating junction temperature –55 150 °C Tstg Storage temperature –55 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Should not exceed 7 V. 6.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human-body model (HBM) ±2000 Charged-device model (CDM) ±500 UNIT V 6.3 Recommended Operating Conditions TA = 25°C (unless otherwise stated) VDD Driver supply voltage (1) MIN MAX 4.5 5.5 V 4.5 UNIT VIN Input supply voltage 16 V VOUT Output voltage 5.5 V PWM PWM to PGND VDD V IOUT Continuous output current A Peak output current (3) VIN = 12 V, VDD = 5 V, VOUT = 1.2 V, ƒSW = 500 kHz (2) 20 IOUT-PK ƒSW Switching frequency CBST = 0.1 µF (min), VOUT = 2.5 V (max) On-time duty cycle ƒSW = 1 MHz Minimum PWM on-time (2) (3) 4 1250 A kHz 85% 20 Operating junction temperature (1) 30 –40 ns 125 °C Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings. Measurement made with six 10-µF (TDK C3216X7R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins. System conditions as defined in Note 2. Peak output current is applied for tp = 50 µs. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95492QVM CSD95492QVM www.ti.com SLPS672 – JUNE 2017 7 Application Schematic P12V AVSP TPS53679 AVSN BOOT VIN PWM ASKIP# EN/FCCM P5V BOOT_R CSD95490Q5M PWM1 VOS VSW VDD LOAD TAO LSET PGND IOUT REFIN ACSP1 TSEN P12V BOOT VIN P5V VREF ADDR BOOT_R CSD95490Q5M PWM APWM6 EN/FCCM VOS VSW VDD TAO LSET PGND IOUT REFIN 3.3V V3P3 ACSP6 VREF P12V VIN_CSNIN CSPIN VCCIO BEN_VCCIO SCLK SDIO SALERT# PIN_ALT# VR_HOT# SMB_CLK SMB_ALERT# SMB_DIO AVR_RDY BVR_RDY AVR_EN VR_FAULT# RESET# BVSN BVSP P12V BOOT VIN PWM BPWM1 BSKIP# P5V BOOT_R CSD95492QVM EN/FCCM VOS VSW VDD TAO LSET PGND LOAD IOUT REFIN BCSP1 AGND Copyright © 2016, Texas Instruments Incorporated Figure 1. Application Schematic Note: The schematic in Figure 1 is a conceptual drawing only. Actual designs may require additional components not shown. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95492QVM 5 CSD95492QVM SLPS672 – JUNE 2017 www.ti.com 8 Device and Documentation Support 8.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 8.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 8.3 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 8.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 8.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 6 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95492QVM CSD95492QVM www.ti.com SLPS672 – JUNE 2017 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 9.1 Mechanical Drawing 4.1 3.9 A B PIN 1 INDEX AREA 5.1 4.9 1.05 MAX C SEATING PLANE 0.08 C 0.05 0.00 2X 2.4 0.1 EXPOSED THERMAL PAD 0.6 0.4 (0.2) TYP 2X (0.31) 9 10 2X 4 4.4 0.1 1 18 16X 0.5 PIN 1 ID (OPTIONAL) 18X 0.6 10X 0.4 0.3 0.2 0.1 0.05 C A B C 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95492QVM 7 CSD95492QVM SLPS672 – JUNE 2017 www.ti.com 9.2 Recommended PCB Land Pattern (2.5) SYMM 10X (0.7) 1 18 2X (1.275) 10X (0.25) 8X (0.5) SYMM 2X (0.725) 5 14 6 (R0.05) TYP (4.5) 13 2X (1.85) METAL UNDER SOLDER MASK 10 9 SOLDER MASK OPENING 2X (0.31) 2X (0.8) 2X (1) ( 0.2) VIA TYP (3.7) 0.05 MIN ALL AROUND 0.05 MAX ALL AROUND SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB Attachment (SLUA271). 8 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95492QVM CSD95492QVM www.ti.com SLPS672 – JUNE 2017 9.3 Recommended Stencil Opening METAL TYP SYMM 10X (0.7) (0.655) (R0.05) TYP 1 18 10X (0.25) 8X (0.5) SYMM (1.45) TYP 5 14 6 13 2X (1.75) 6X (1.25) 10 9 2X (0.31) 2X (0.7) 6X (1.11) (3.7) 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: CSD95492QVM 9 PACKAGE OPTION ADDENDUM www.ti.com 22-Sep-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD95492QVM ACTIVE VSON-CLIP DMH 18 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -55 to 150 95492QM CSD95492QVMT ACTIVE VSON-CLIP DMH 18 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -55 to 150 95492QM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 22-Sep-2017 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CSD95492QVM VSONCLIP DMH 18 2500 330.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1 CSD95492QVMT VSONCLIP DMH 18 250 180.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD95492QVM VSON-CLIP DMH 18 2500 370.0 355.0 55.0 CSD95492QVMT VSON-CLIP DMH 18 250 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2017, Texas Instruments Incorporated