MITSUBISHI MICROCOMPUTERS A IMIN RY e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L DESCRIPTION The 7480/7481 group is the single-chip microcomputer adopting the silicon gate CMOS process. In addition to its simple instruction set, the ROM, RAM, and I/O addresses are placed in the same memory space. Having built-in serial I/O, A-D converter, and watchdog timer, this single-chip microcomputer is useful for control of automobiles, office automation equipment and home electric appliances. The 7480/7481 group includes multiple types which differ in the memory type, size, and package. APPLICATIONS Automobiles, office automation equipment, home electric appliances, etc. PIN CONFIGURATION P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS 1 32 2 31 3 30 4 29 5 28 6 7 8 9 10 11 12 27 26 25 24 23 22 21 13 20 14 19 15 18 16 17 P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR 1 P40/CNTR 0 P33 P32 P31/INT1 P30/INT0 RESET V CC Outline 32P4B P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN X OUT V SS 1 32 2 31 3 30 4 29 5 28 6 7 8 9 10 11 12 M37480MX-XXXFP M37480MXT-XXXFP M37480E8-XXXFP M37480E8T-XXXFP ●Number of basic machine language instructions ..................... 71 ●Minimum instruction execution time ................................... 0.5 µs (at 8 MHz clock input oscillation frequency) ●Memory size ROM ........................................... 4 K to 16 K bytes RAM ............................................ 128 to 448 bytes ●Programmable I/O ports .................................... 18 (7480 group) (P0, P1, P4, P5) 24 (7481 group) ●Input ports ............................................................ 8 (7480 group) (P2, P3) 12 (7481 group) ●Built-in programmable pull-up transistors (P0, P1) ●Built-in clamp diodes ............................................ 2 (7480 group) (P4, P5) 8 (7481 group) ●Interrupt ................................................... 14 sources, 13 vectors ●Timer X, Y ..................................................................... 16-bit ✕ 2 ●Timer 1, 2 ....................................................................... 8-bit ✕ 2 ●Serial I/O ....................... 8-bit x 1 (UART or clock-synchronized) ●A-D converter ............................ 8-bit x 4 channels (7480 group) 8-bit x 8 channels (7481 group) ●Built-in watchdog timer ●Power source voltage ................................................ 2.7 to 4.5 V (at [2.2 VCC-2] MHz clock input oscillation frequency) 4.5 to 5.5 V (at 8 MHz clock input oscillation frequency) ●Power dissipation .............................................................. 35 mW (at 8 MHz clock input oscillation frequency and 5 V power source voltage) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37480MX-XXXSP M37480MXT-XXXSP M37480E8-XXXSP M37480E8T-XXXSP FEATURES 7480/7481 GROUP 27 26 25 24 23 22 21 13 20 14 19 15 18 16 17 Outline 32P2W-A Fig. 1 Pin configuration (top view) P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1 P30/INT0 RESET VCC MITSUBISHI MICROCOMPUTERS RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som 13 14 15 31 30 29 28 16 27 17 26 18 25 19 24 20 23 21 22 Outline 42P4B 42S1B-A Fig. 2 Pin configuration (top view) 2 32 23 25 24 27 26 29 28 P53 P17/SRDY P16/SCLK 40 P15/TXD P14/RXD 19 M37481MX-XXXFP M37481MXT-XXXFP M37481E8-XXXFP M37481E8T-XXXFP 38 39 18 17 16 41 15 42 14 43 13 44 12 11 12 33 20 37 9 11 34 36 10 10 35 21 8 9 36 22 35 7 8 34 P05 P06 P07 P52 VSS 6 7 P04 5 37 31 38 6 30 39 5 4 40 4 3 3 P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1 P30/INT0 RESET P51 P50 VCC P03 P02 P01 P00 P43 P42 P41/CNTR1 P40/CNTR2 P33 P32 P31/INT1 41 32 42 2 33 1 M37481MX-XXXSP M37481MXT-XXXSP M37481E8-XXXSP M37481E8T-XXXSP M37481E8SS P53 P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 1 L 2 PRE P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 A IMIN Outline 44P6N-A P30/INT0 RESET P51 P50 VCC VSS AVSS XOUT XIN VREF P20/IN0 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 7480/7481 GROUP PRODUCT LIST Table 1. 7480/7481 group product list Product model name M37480M2T-XXXSP ROM (bytes) RAM (bytes) 4096 128 I/O port Package 32P4B M37480M2T-XXXFP 32P2W-A M37480M4-XXXSP 32P4B M37480M4-XXXFP 8192 M37480M4T-XXXSP 32P4B M37480M4T-XXXFP 32P2W-A 18 I/O ports M37480M8-XXXFP 8 input ports (including 4 analog input ports) M37480M8T-XXXFP 32P4B 16384 32P4B 32P4B 448 32P2W-A M37480E8-XXXSP 32P4B M37480E8-XXXFP 32P2W-A M37480E8T-XXXSP 32P4B M37480E8T-XXXFP 32P2W-A 4096 42P4B 128 M37481M2T-XXXFP 44P6N-A M37481M4-XXXSP 42P4B M37481M4-XXXFP 8192 44P6N-A 256 M37481M4T-XXXSP 42P4B M37481M4T-XXXFP 44P6N-A M37481M8-XXXSP 42P4B 24 I/O ports M37481M8-XXXFP 12 input ports (including 8 analog input ports) M37481M8T-XXXSP M37481M8T-XXXFP M37481E8SP Mask ROM version* Mask ROM version 16384 448 Mask ROM version* 32P2W-A M37480E8FP M37481M2T-XXXSP Mask ROM version 32P2W-A M37480M8T-XXXSP M37480E8SP Mask ROM version* 32P2W-A 256 M37480M8-XXXSP Remarks 44P6N-A 42P4B 44P6N-A 42P4B M37481E8FP 44P6N-A M37481E8-XXXSP 42P4B M37481E8-XXXFP 44P6N-A M37481E8T-XXXSP 42P4B M37481E8T-XXXFP 44P6N-A M37481E8SS 42S1B-A One time PROM version (shipped in blank) One time PROM version One time PROM version* Mask ROM version* Mask ROM version Mask ROM version* Mask ROM version Mask ROM version* One time PROM version (shipped in blank) One time PROM version One time PROM version* Built-in EPROM version *: Extended operating temperature range version 3 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 7480/7481 GROUP ROM/RAM DEVELOPMENT SCHEDULE ROM size (bytes) M37481E8SS M37480M8T/E8T-XXXSP/FP M37481M8T/E8T-XXXSP/FP 16K M37480M8/E8-XXXSP/FP M37481M8/E8-XXXSP/FP 12K M37480M4-XXXSP/FP M37480M4T-XXXSP/FP M37481M4-XXXSP/FP M37481M4T-XXXSP/FP 8K M37480M2T-XXXSP/FP M37481M2T-XXXSP/FP 4K : Being developed : Being planned 0 128 256 384 448 RAM size (bytes) Note: Regarding the models being developed and planned, the development schedule may be reviewed. In case of the models being planned, the development of them may be stopped. Fig. 3 ROM/RAM development schedule 4 INT1 INT0 P1 (8) Timer Y (16) Timer X (16) Timer 2 (8) Timer 1 (8) I/O port P1 1 2 3 4 5 6 7 8 Serial I/O (8) Input port P2 9 10 11 12 P2 (4) Stack pointer S (8) ROM 16384 bytes (Note 1) I/O port P0 32 31 30 29 28 27 26 25 P0 (8) Control signal Instruction decoder Instruction register (8) Notes 1: 8192 bytes for M37480M4-XXXSP/FP, M37480M4T-XXXSP/FP and 4096 bytes for M37480M2T-XXXSP/FP 2: 256 bytes for M37480M4-XXXSP/FP, M37480M4T-XXXSP/FP and 128 bytes for M37480M2T-XXXSP/FP I/O port P4 13 4 VREF Input port P3 Reference voltage input 22 21 20 19 24 23 INT1 INT0 P3 (4) Index register Y (8) Program counter PCL (8) Data bus A-D converter Index register X (8) Program counter PCH (8) 16 VSS RY P4 (2) CNTR1 Processor status register PS (8) CNTR0 Accumulator A (8) RAM 448 bytes (Note 2) 17 VCC A IMIN 8-bit arithmetic and logical unit Clock generating circuit 18 . . tion hange c ifica pec ject to s l fina sub ot a its are is n his tric lim T : me ice Not e para Som L 15 Reset input RESET PRE 14 Clock Clock input output XOUT XIN M37480M8/E8-XXXSP/FP, M37480M8T/E8T-XXXSP/FP FUNCTION BLOCK DIAGRAM MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL BLOCK DIAGRAM Fig. 4 Function block diagram (1) 5 6 20 19 Fig. 5 Function block diagram (2) 33 32 31 30 I/O port P4 1 42 24 23 I/O port P5 18 VREF Input port P3 Reference voltage input 29 28 27 26 P3 (4) INT1 INT0 P 2 (8) Input port P2 10 11 12 13 14 15 16 17 8 Stack pointer S (8) P1 (8) Timer Y (16) Timer X (16) I/O port P1 2 3 4 5 6 7 8 9 Serial I/O (8) INT1 INT0 Timer 2 (8) Timer 1 (8) Notes 1: 8192 bytes for M37481M4-XXXSP, M37481M4T-XXXSP and 4096 bytes for M37481M2T-XXXSP 2: 256 bytes for M37481M4-XXXSP, M37481M4T-XXXSP and 128 bytes for M37481M2T-XXXSP P4 (4) P5 (4) CNTR1 Index register Y (8) A-D converter Index register X (8) ROM 16384 bytes (Note 1) I/O port P0 41 40 39 38 37 36 35 34 P0 (8) Control signal Instruction decoder Instruction register (8) . CNTR0 Processor status register PS (8) Program counter PCL (8) Data bus RY Accumulator A (8) Program counter PCH (8) 21 VSS A IMIN 8-bit arithmetic and logical unit RAM 448 bytes (Note 2) 22 VC C . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som L 25 Reset input RESET PRE Clock generating circuit Clock output XOUT Clock input XIN M37481M8/E8-XXXSP, M37481M8T/E8T-XXXSP, M37481E8SS FUNCTION BLOCK DIAGRAM MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 29 28 27 26 I/O port P4 40 38 20 19 I/O port P5 13 VREF 8 (Note 1) Input port P2 5 6 7 8 9 10 11 12 P2 (8) Stack pointer S (8) ROM 16384 bytes P1 (8) Timer Y (16) Timer X (16) I/O port P1 41 42 43 44 1 2 3 4 Serial I/O (8) INT1 INT0 Timer 2 (8) Timer 1 (8) Notes 1: 8192 bytes for M37481M4-XXXFP, M37481M4T-XXXFP and 4096 bytes for M37481M2T-XXXFP 2: 256 bytes for M37481M4-XXXFP, M37481M4T-XXXFP and 128 bytes for M37481M2T-XXXFP Input port P3 Reference voltage input 25 24 23 22 P4 (4) INT1 INT0 P5 (4) Index register Y (8) Program counter PCL (8) A-D converter Index register X (8) Program counter PCH (8) I/O port P0 37 36 35 34 33 32 31 30 P0 (8) Control signal Instruction decoder Instruction register (8) . P3 (4) CNTR0 CNTR1 Processor status register PS (8) (Note 2) 16 Data bus AVSS VSS 17 39 RY Accumulator A (8) RAM 448 bytes 18 VCC A IMIN 8-bit arithmetic and logical unit Clock generating circuit 21 . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som L 15 Reset input RESET PRE 14 Clock Clock input output XOUT XIN M37481M8/E8-XXXFP, M37481M8T/E8T-XXXFP FUNCTION BLOCK DIAGRAM MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 6 Function block diagram (3) 7 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONS OF 7480/7481 GROUP Table 2. Functions of 7480/7481 group Functions Parameter Number of basic instructions M37480M4/M8/E8-XXXSP/FP M37481M4/M8/E8-XXXSP/FP M37480M2T/M4T/M8T/E8T-XXXSP/FP M37481M2T/M4T/M8T/E8T-XXXSP/FP 71 (740 family 69 basic instructions + 2 multiplication/division instructions) 0.5µs (Minimum instructions, at 8 MHz clock input oscillation frequency) Instruction execution time Clock input oscillation frequency ROM Memory size RAM I/O port I/O characteristics 8 MHz (max.) M8/E8 16384 bytes M4 8192 bytes M2 4096 bytes M8/E8 448 bytes M4 256 bytes M2 128 bytes 8 bits ✕ 2 P0, P1 I/O P2 Input P3 Input P4 I/O 2 bits ✕ 1 P5 I/O ————— 4 bits ✕ 1 8 bits ✕ 1 4 bits ✕ 1 4 bits ✕ 1 4 bits ✕ 1 5V I/O withstand voltage Output current –5 to 10 mA (P0, P1: CMOS tri-states), 10 mA (P4, P5: N channel) 8 bits ✕ 1 Serial I/O Timers Subroutine nesting 16-bit timer x 2, 8-bit timer x 2 M8/E8 192 max. M4 96 max. M2 64 max. Interrupt A-D converter (successive comparison method) Clock generating circuit 5 external interrupts, 8 internal interrupts, 1 software interrupt 8 bits ✕ 4 analog inputs 8 bits ✕ 8 analog inputs (in common with P2) (in common with P2) Built-in circuit with feedback resistor (with external ceramic oscillator) Built-in circuit Watchdog timer Power source voltage Power dissipation Operating temperature range Device structure Package 8 2.7 to 4.5 V (at f(XIN) = (2.2VCC – 2) MHz) 4.5 to 5.5 V (at f(XIN)=8 MHz) 35 mW (standard, at 8 MHz clock input oscillation frequency) –20 to 85 °C (–40 to 85 °C for extended operating temperature range version) CMOS silicon gate 32-pin SDIP/32-pin SOP 42-pin SDIP/44-pin OFP MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Table 3. Pin description Input/ output Pin Name Functions VCC, VSS Power source Apply a voltage of 2.7 to 5.5 V to VCC and 0 V to VSS. AVSS Analog power source input Ground level input pin for A-D converter. Apply the same voltage as Vss. (This pin is for 44P6N-A package only.) VREF Reference voltage input Input Reference voltage input pin for A-D converter. (When the A-D converter is not used, connect it to VCC.) RESET Reset input Input Reset input pin active “L”. XIN Clock input Input XOUT Clock output P00 – P07 I/O port P0 _____ Output These are I/O pins for the internal clock generating circuit of the main clock. To control the generating frequency, an external ceramic is connected between the XIN and XOUT pins. If an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. The feedback resistor is connected between XIN and XOUT. I/O 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistors can be connected in units of 1 bit, and a key-on wake-up function is provided. I/O 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistors can be connected in units of 4 bits. P1 2 and P1 3 are in common with timer output pins T0 and T1. P14, P15, P16 and P17 are in common with serial I/O pins RXD, TXD, SCLK and ____ SRDY, respectively. Input 8-bit input port. (Only 4 bits of P20 to P23 for the 7480 group) or analog input pins IN0 to IN7 (IN0 to IN3 for the 7480 group). Input 4-bit input port. P30 and P31 can be configured to serve as external interrupt input pins INT0 and INT1. P10 – P17 I/O port P1 P20 – P27 Input port P2 P30 – P33 Input port P3 P40 – P43 I/O port P4 I/O 4-bit I/O port. (2 bits of P40 and P41 for the 7480 group). The output structure is N-channel open drain output, having a built-in clamp diode. P40 and P41 can be configured to serve as timer I/O pins CNTR0 and CNTR1. P50 – P53 I/O port P5 I/O 4-bit I/O port. (This port is not included in the 7480 group.) The output structure is N-channel open drain output, having built-in clamp diodes. 9 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) CPU Mode Register The 7480/7481 group uses the standard 740 family CPU. Refer to the table of 740 family addressing modes and machine instructions or the MELPS 740 programming manual for details on the instruction set. Machine-resident 740 family instructions are as follows: 1. The FST and SLW instructions are not available. 2. The MUL and DIV instructions are available. 3. The WIT instruction is available. (Note) 4. The STP instruction is available. (Note) Note: When using these instructions, refer to the corresponding chapter “STP and WIT instruction control” below. b7 The stack page selection bit is assigned to the CPU mode register. This register is allocated at address 00FB16. b0 CPU mode register (CPUM: address 00FB16) Not used. These bits must always be set to “0”. Stack page selection bit (Note) 0 : Page 0 1 : Page 1 Watchdog timer L count source selection bit 0 : f(XIN)/8 1 : f(XIN)/16 Not used (undefined at read) System clock division proportion selection bit 0 : f = f(XIN)/2 (high-speed mode) 1 : f = f(XIN)/8 (medium-speed mode) Not used (undefined at read) Note : In the models of RAM size under 192 bytes, set this bit to “0”. Fig. 7 Structure of CPU mode register 10 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Memory • SFR Area This SFR area is provided in the zero page and contains the registers for controlling I/O ports and timers. • RAM RAM is used for data storage and for calling subroutines, as well as for a stack area for interrupts. • ROM ROM is used for storing user programs and interrupt vectors. • Interrupt Vector Area The interrupt vector area is used for storing vector addresses when an interrupt is generated or at reset. • Zero Page This area can be accessed with 2 words when the zero page addressing mode is used. • Special Page This area can be accessed with 2 words when the special page addressing mode is used. 000016 RAM (192 bytes) for M37480M4, M37480M8/E8, M37481M4, M37481M8/E8 RAM (256 bytes) for M37480M8/E8, M37481M8/E8 RAM (128 bytes) for M37480M2, M37481M2 007F16 008016 00BF 16 00C0 16 00FF16 010016 RAM (64 bytes) for M37480M4, M37481M4 Zero page SFR area 013F16 01FF16 Not used C000 16 E00016 ROM (16384 bytes) for M37480M8/E8, M37481M8/E8 F00016 ROM (8192 bytes) for M37480M4, M37481M4 ROM (4096 bytes) for M37480M2, M37481M2 FF0016 Special page FFE4 16 Interrupt vector area FFFF 16 Fig. 8 Memory map 11 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L 00C016 Port P0 (P0) 00E016 Transmit/receive buffer register (TB/RB) 00C116 Port P0 direction register (P0D) 00E116 Serial I/O status register (SIOSTS) 00C216 Port P1 (P1) 00E216 Serial I/O control register (SIOCON) 00C316 Port P1 direction register (P1D) 00E316 UART control register (UARTCON) 00C416 Port P2 (P2) 00E416 Baud rate generator (BRG) 00E516 Bus collision detection control register (BUSARBCON) 00C516 00C616 Port P3 (P3) 00E616 00E716 00C716 00C916 Port P4 (P4) 00E816 00C916 Port P4 direction register (P4D) 00E916 00CA16 Port P5 (P5) (Note) 00EA16 00CB16 Port P5 direction register (P5D) (Note) 00EB16 00CC16 00EC16 00CD16 00ED16 00CE16 00EE16 00EF16 Watchdog timer H (WDTH) 00D016 Port P0 pull-up control register (P0PCON) 00F016 Timer X low-order (TXL) 00D116 Port P1 pull-up control register (P1PCON) 00F116 Timer X high-order (TXH) 00D216 Port P4P5 input control register (P4P5CON) 00F216 Timer Y low-order (TYL) 00F316 Timer Y high-order (TYH) 00CF16 00D316 00D416 00F416 Timer 1 (T1) 00D516 00F516 Timer 2 (T2) 00D616 00F616 Timer X mode register (TXM) 00D716 00F716 Timer Y mode register (TYM) 00D816 00F816 Timer XY control register (TXYCON) 00D916 00F916 Timer 1 mode register (T1M) 00DA16 A-D conversion register (AD) 00FA16 Timer 2 mode register (T2M) 00DB16 00FB16 CPU mode register (CPUM) 00DC16 00FC16 Interrupt request register 1 (IREQ1) 00DD16 00FD16 Interrupt request register 2 (IREQ2) 00DE16 STP instruction operation control register (STPCON) 00FE16 Interrupt control register 1 (ICON1) 00DF16 00FF16 Interrupt control register 2 (ICON2) Edge polarity selection register (EG) A-D control register (ADCON) Fig. 9 SFR (Special Function Register) memory map Note: This port is not allocated in the 7480 group. 12 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L I/O Ports [Direction Registers] The I/O ports have direction registers which determine the input/ output direction of each pin in units of bit. When a bit of the direction register is set to “1”, the corresponding pin becomes an output port. When the bit is cleared to “0”, it becomes an input port. If data is read from a pin configured as output, the value of the port latch is read rather than the value of this pin. A pin configured as input becomes floating and its value can be read. If data is written to a pin, it is written to the port latch, but the pin remains floating. b7 b0 Port P0 pull-up control register (P0PCON : address 00D016) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Pull-up Control Registers] Ports P0 and P1 are provided with a programmable pull-up transistor. When “1” is written to the pull-up control register and the direction register is in the input mode, the pull-up transistor turns on, and the port is pulled up. ■ Notes on Use for STP Instruction When the 7480/7481 group is executing an STP instruction, apply 0 V or the same voltage as Vcc to the following pins. If an intermediate voltage is applied to these pins, a through-current flows to the input gates and the power current increases. P4, P5, P3, P16, P14 [Port P4P5 Input Control Register] When ports P42, P43 and P5 of the 7481 group are selected for input, clear the corresponding direction register to “0” and set “1” to the corresponding bit of the port P4P5 input control register. Ports P4 2, P43 and P5 are not included in the 7480 group. Fix each bit of the port P4P5 input control register to “0”. P00 pull-up control bit P01 pull-up control bit P02 pull-up control bit P03 pull-up control bit P04 pull-up control bit b0 Port P4P5 input control register (P4P5CON : address 00D216) P05 pull-up control bit P42, P43 input control bit P06 pull-up control bit P5 input control bit (For the 7480 group) Set this bit to “0”. (For the 7481 group) Set this bit to “1”. P07 pull-up control bit 0 : Pull-up transistor OFF 1 : Pull-up transistor ON b7 b7 b0 Port P1 pull-up control register (P1PCON : address 00D116) Not used (“0” at read) Fig. 11 Structure of port P4P5 input control register P13 – P10 pull-up control bit P17 – P14 pull-up control bit Not used (undefined at read) 0 : Pull-up transistor OFF 1 : Pull-up transistor ON Fig. 10 Structure of pull-up control register 13 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P0 Pull-up control register Tr1 Direction register Data bus Port latch Port P0 Interrupt control circuit Ports P10 – P13 Data bus Pull-up control register Tr2 T2M1 Direction register Data bus Port latch Port P13 T1 Tr3 T1M 1 Direction register Data bus Port latch Port P12 T0 Tr4 Direction register Data bus Port latch Port P11 Tr5 Direction register Data bus Port latch Port P10 Tr1 to Tr5 are pull-up transistors. Fig. 12 Block diagram of ports (1) 14 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Ports P14 – P17 SIOE SIOM SRDY Tr6 Direction register Data bus Port latch Port P17 SRDY SCS SIOE SIOM SIOE Tr7 Direction register Data bus Port latch Port P16 SCLK output SCLK input SIOE TE Tr8 Direction register Data bus Port latch Port P15 TXD SIOE RE Tr9 Direction register Data bus Port latch Port P14 RXD Data bus Pull-up control register Tr6 to Tr9 are pull-up transistors. Fig. 13 Block diagram of ports (2) 15 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P2 Data bus Port P2 A-D conversion circuit Multiplexer Port P3 Data bus Port P3 INT0, INT1 Port P40, P41 Timer X,Y operating mode bits “001” “100” “101” “110” Direction register Data bus Port latch Timer output Port P40, P41 CNTR0, CNTR1 input Port P42, P43, P50, P51, P52, P53 Direction register Data bus Port latch Port P42, P43, P50, P51, P52, P53 Port P4 P5 input control register (For the 7480 group) Set this bit to “0”. (For the 7481 group) Set this bit to “1”. Fig. 14 Block diagram of ports (3) 16 MITSUBISHI MICROCOMPUTERS A IMIN RY . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L Interrupts Interrupts are vectored interrupts, and they can be caused by 14 different sources: 5 external sources, 8 internal sources, and 1 software source. (1) Interrupt Control All interrupts, except the BRK instruction interrupt, have an interrupt request bit and an interrupt enable bit. Additionally, a global interrupt disable flag affects them. When the interrupt enable bit and the interrupt request bit are set to "1" and the interrupt disable flag is set to "0", an interrupt is accepted. The interrupt request bits can be cleared by the program but cannot be set. The interrupt enable bit can be set and cleared by the program. The reset and BRK instruction interrupt can never be disabled. Other interrupts are disabled when the interrupt disable flag is set. 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Interrupt Operation When an interrupt request is accepted: 1. The contents of the program counter and the processor status register are automatically pushed into the stack. 2. The interrupt disable flag is set and the interrupt request bit is cleared. 3. The interrupt jump destination address is read into the program counter. ■ Notes • When the active edge of an external interrupt (INT0 , INT 1 , CNTR0, CNTR1) is set, the interrupt request bit may also be set. Therefore, disable the external interrupt and set the edge polarity selection register. Then clear the interrupt request bit and accept the external interrupt. • Input a trigger width over 250 ns to the INT0/INT1 pin. 17 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 4. Interrupt vector addresses and priority Interrupt source Priority Vector address (Note 1) High-order Low-order Interrupt request generating conditions Remarks RESET (Note 2) 1 FFFF16 FFFE16 At reset Non-maskable INT0 2 FFFD16 FFFC16 At detection of either rising edge or falling edge of INT0 input External interrupt (active edge programmable) At detection of either rising edge or falling edge of INT1 input External interrupt (active edge programmable) At input “L” to port P0 in key-on wake-up mode Validity after execution of STP/WIT instruction INT1 3 FFFB16 FFFA16 CNTR0 4 FFF916 FFF816 At detection of either rising edge or falling edge of CNTR0 input External interrupt (active edge programmable) CNTR1 5 FFF716 FFF616 At detection of either rising edge or falling edge of CNTR1 input External interrupt (active edge programmable) Timer X 6 FFF516 FFF416 At timer X underflow Timer Y 7 FFF316 FFF216 At timer Y underflow Timer 1 8 FFF116 FFF016 At timer 1 underflow Key-on wake-up Timer 2 9 FFEF16 FFEE16 At timer 2 underflow Serial I/O reception 10 FFED16 FFEC16 At completion of serial I/O data reception Serial I/O transmission 11 FFEB16 FFEA16 At completion of serial I/O transfer shift or when transmission buffer is empty Bus arbitration 12 FFE916 FFE816 At detection of bus collision A-D conversion 13 FFE716 FFE616 At completion of A-D conversion BRK instruction 14 FFE516 FFE416 At execution of BRK instruction Non-maskable software interrupt Notes 1 : Vector addresses contain interrupt jump destination addresses. 2 : RESET is mentioned in the table because its operation is the same as an interrupt. Interrupt request bit Interrupt enable bit Interrupt disable flag BRK instruction Reset Fig. 15 Interrupt control diagram 18 Interrupt request MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L b7 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b0 Edge polarity selection register (EG : address 00D4 16) INT0 selection bit 0 : Falling edge 1 : Rising edge INT1 selection bit 0 : Falling edge 1 : Rising edge CNTR0 edge selection bit 0 : In event count mode, count rising edge. : In pulse output mode, start at “H” level output. : In pulse cycle measurement mode, measure a period from falling edge to falling edge. : In pulse width measurement mode, measure an “H” period. : In programmable one-shot output mode, generate one-shot “H” pulse after start at “L” output. : Interrupt, falling edge active. 1 : In event count mode, count falling edge. : In pulse output mode, start at “L” level output. : In pulse cycle measurement mode, measure a period from rising edge to rising edge. : In pulse width measurement mode, measure an “L” period. : In programmable one-shot output mode, generate one-shot “L” pulse after start at “H” level output. : Interrupt, rising edge active. CNTR1 edge selection bit 0 : In event count mode, count rising edge. : In pulse output mode, start at “H” level output. : In pulse cycle measurement mode, measure a period from falling edge to falling edge. : In pulse width measurement mode, measure an “H” period. : In programmable one-shot output mode, generate one-shot “H” pulse after start at “L” level output. : Interrupt, falling edge active. 1 : In event count mode, count falling edge. : In pulse output mode, start at “L” output. : In pulse cycle measurement mode, measure a period from rising edge to rising edge. : In pulse width measurement mode, measure an “L” period. : In programmable one-shot output mode, generate one-shot “L” pulse after start at “H” output. : Interrupt rising edge active. Not used (undefined at read) INT1 source selection bit at STP or WIT 0 : P31/INT1 1 : P00 – P07 “L” level (for key-on wake-up) Not used (undefined at read) b7 b0 b7 b0 Interrupt request register 1 (IREQ1: address 00FC 16) Interrupt control register 1 (ICON1: address 00FE 16) b7 Timer X interrupt enable bit Timer X interrupt request bit Timer Y interrupt enable bit Timer Y interrupt request bit Timer 1 interrupt enable bit Timer 1 interrupt request bit Timer 2 interrupt enable bit Timer 2 interrupt request bit Serial I/O receive interrupt enable bit Serial I/O receive interrupt request bit Serial I/O transmit interrupt enable bit Serial I/O transmit interrupt request bit Bus arbitration interrupt enable bit Bus arbitration interrupt request bit A-D conversion completion interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled A-D conversion completion interrupt request bit 0 : No interrupt request 1 : Interrupt requested b0 b7 Interrupt control register 2 (ICON2: address 00FF 16) b0 Interrupt request register 2 (IREQ2: address 00FD 16) INT0 interrupt enable bit INT0 interrupt request bit INT1 interrupt enable bit INT1 interrupt request bit CNTR0 interrupt enable bit CNTR0 interrupt request bit CNTR1 interrupt enable bit 0 : Interrupt disable 1 : Interrupt enable CNTR1 interrupt request bit 0 : No interrupt request 1 : Interrupt request Not used (undefined at read) 0 : Interrupt disabled 1 : Interrupt enabled Not used (undefined at read) 0 : No interrupt request 1 : Interrupt requested Fig. 16 Structure of registers related to interrupts 19 MITSUBISHI MICROCOMPUTERS A IMIN RY . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L Timers The 7480/7481 group has two 16-bit timers (timer X and timer Y), and two 8-bit timers (timer 1 and timer 2). All the timers are of a count-down type. When the timer reaches “FF 16” or “000016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to this timer is set to “1”. At reading and setting the timer value to a 16-bit timer, be sure to read and set both high-order byte and low-order byte. At reading the count value from a 16-bit timer, read the high-order byte and the low-order byte in this order. At setting the count value in a 16-bit timer, set the low-order byte and the high-order byte in this order. The 16-bit timer cannot operate normally at reading during set operation or at setting during read operation. ● Timer X, Timer Y Both timer X and timer Y are 16-bit timers independent from each other. They can select 7 operating modes by setting the mode registers. The registers related to timer X and timer Y are shown below. In the following, abbreviations will be used as register names. • Timer XY control register (TXYCON: address 00F816) • Port P4 direction register (P4D: address 00C916) • Timer X low-order (TXL: address 00F016) • Timer X high-order (TXH: address 00F116) • Timer Y low-order (TYL: address 00F216) • Timer Y high-order (TYH: address 00F316) • Timer X mode register (TXM: address 00F616) • Timer Y mode register (TYM: address 00F716) • Edge polarity selection register (EG: address 00D416) • Interrupt request register 1 (IREQ1: address 00FC16) • Interrupt request register 2 (IREQ2: address 00FD16) • Interrupt control register 1 (ICON1: address 00FE16) • Interrupt control register 2 (ICON2: address 00FF16) For register structures, refer to each register structural diagram. In the following, each mode will be described. (1) Timer Mode/Event Count Mode ➀ Timer Mode ● Mode Selection This mode is selected by setting “000” in the timer X operating mode bits (b2b1b0) of TXM and the timer Y operating mode bits (b2b1b0) of TYM. ● Count Source Selection The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16. ● Interrupt When a timer underflows, the timer X interrupt request bit (b0) or timer Y interrupt request bit (b1) of IREQ1 is set to “1”. ● Explanation of Operation After reset release, the timer X stop control bit (b0) or timer Y stop control bit (b1) of TXYCON is “1”, and the timer stops. In the timer stop status, usually the timer value is set by writing the latch and timer at the same time. Timer operation is started by setting “0” in b0 or b1 of TXYCON. When the timer reaches “000016”, an underflow occurs at the next count pulse, the corresponding timer latch is reloaded into the timer, and the count is continued. To change the timer value during count operation, the latch value is changed by writing to 20 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER the latch only. At the next underflow reloading, the timer value is changed. ➁ Event Count Mode ● Mode Selection Select the timer event count mode. This mode is selected by inputting from the CNTR0 pin for timer X or from the CNTR1 pin for timer Y (setting “11” in b7 and b6 of TXM or “11” in b7 and b6 of TYM). The count operation active edge is selected by setting in the CNTR0 edge selection bit (b2) or the CNTR1 edge selection bit (b3) of EG. At “0”, the rising edge is counted. At “1”, the falling edge is counted. ● Interrupt The underflow interrupt is the same as the timer mode. ● Explanation of Operation This operation is the same as that of the timer mode. In this mode, set the port in common with the CNTR0/CNTR1 pin as an input port. Figure 19 shows a timing diagram in the timer event count mode. (2) Pulse Output Mode ● Mode Selection This mode is selected by setting b2, b1 and b0 of TXM or TYM to “001”. ● Count Source Selection The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16. MITSUBISHI MICROCOMPUTERS A IMIN RY . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L ● Interrupt The timer underflow interrupt is the same as the timer event count mode. ● Explanation of Operation This operation is the same as the timer event count mode except that a timer outputs a pulse from the CNTR0/CNTR1 pin in which the polarity of output level is inverted at each timer underflow. When the CNTR0 edge selection bit (b2) or CNTR1 edge selection bit (b3) of EG is “0”, the output of the CNTR0/ CNTR1 pin is started with an “H” level output. When b2 or b3 of EG is “1”, the output of this pin is started with an “L” level. In this mode, set the port in common with the CNTR0/CNTR1 pin as an output port. ■ Note While a timer operation stops The output level of the CNTR0/CNTR1 pin is initialized to the value set in the CNTR0 edge selection bit or CNTR1 edge selection bit by writing to the timer. While a timer operation is enabled The output level of the CNTR0/CNTR1 pin is inverted by changing the CNTR0 edge selection bit or CNTR1 edge selection bit. Figure 20 shows a timing diagram in the pulse output mode. (3) Pulse Cycle Measurement Mode ● Mode Selection This mode is selected by setting b2, b1 and b0 of TXM or TYM to “010”. ● Count Source Selection The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16. ● Interrupt The underflow interrupt is the same as the timer event count mode. Set b2 or b3 of IREQ2 to “1” as soon as the pulse cycle measurement is completed. ● Explanation of Operation While a timer operation stops Select a timer count source. Next, select a pulse cycle to be measured. When b2 or b3 of EG is “0”, a timer counts a period from a falling edge to a falling edge of the CNTR0/CNTR1 pin input. When b2 or b3 of EG is “1”, a timer counts a period from a rising edge to a rising edge of the CNRT0/CNTR1 pin input. While a timer operation is enabled At setting b0 and b1 of TXYCON to “0”, a timer starts to measure the pulse cycle, and starts to count down from the count value provided before measurement. When an active edge is detected at measurement completion or measurement start, 1's complement of the timer value is set to the timer latch and “FFFF16” is set in the timer. When a timer underflows, a timer X or timer Y interrupt occurs, and “FFFF 16” is set in the timer. A measurement value is held until the next measurement is completed. In this mode, set the port in common with the CNTR0/CNTR1 pin as an input port. ■ Note The timer value cannot be read in this mode. A timer value can be set while a timer operation stops (no measurement). Since the timer latch of this mode becomes read only, do not perform a write operation during measurement. The timer is set to “FFFF16” only when the timer underflows or the active edge of pulse cycle measurement is detected. Accordingly, the timer value at a start of measurement depends on 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER the timer value provided before the start of measurement. Figure 21 shows a timing diagram in the pulse cycle measurement mode. (4) Pulse Width Measurement Mode ● Mode Selection This mode is selected by setting b2, b1 and b0 of TXM or TYM to “011”. ● Count Source Selection The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16. ● Interrupt The underflow interrupt is the same as the timer event count mode. Set b2 or b3 of IREQ2 to “1” as soon as pulse width measurement is completed. ● Explanation of Operation While a timer operation stops Select a timer count source. Next, select a pulse width to be measured. A timer counts a period from a falling edge to a rising edge of the CNTR0/CNTR1 pin input (“L” period) when b2 or b3 of EG is “1”. A timer counts a period from a rising edge to a falling edge of the CNTR0/CNTR1 pin input (“H” period) when b2 or b3 of EG is set to “0”. While a timer operation is enabled At setting b0 and b1 of TXYCON to “0”, a timer starts to measure a pulse width, and starts to count down from the count value provided before measurement. When the active edge is detected at measurement completion, 1’s complement of the timer value is set in the timer latch. When the active edge is detected at measurement completion or measurement start, “FFFF16” is set in the timer. When a timer underflows, a timer X or timer Y interrupt occurs, and “FFFF16” is set in the timer. A measurement value is held until the next measurement is completed. In this mode, set the port in common with the CNTR0/CNTR1 pin as an input port. 21 MITSUBISHI MICROCOMPUTERS A IMIN RY . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L ■ Note The timer value cannot be read in this mode. A timer value can be set while a timer operation stops (not under pulse width measurement). Since the timer latch of this mode becomes read only, do not perform a write operation during measurement. The timer is set to “FFFF16” only when a timer underflows or when the active edge of pulse width measurement is detected. Accordingly, the timer value at a start of measurement depends on the timer value provided before the start of measurement. Figure 22 shows a timing diagram in the pulse width measurement mode. (5) Programmable Waveform Generation Mode ● Mode Selection This mode is selected by setting b2, b1 and b0 of TXM or TYM to “100”. ● Count Source Selection The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16. ● Interrupt The underflow interrupt is the same as the timer event count mode. The INT0 interrupt request bit (b0) or INT 1 interrupt request bit (b1) of IREQ2 is set to “1” by detecting an active edge of the INT pin. ● Explanation of Operation This operation is the same as that of the timer event count mode, except that a timer outputs the level of the value set in the output level latch (b4) of TXM or TYM from the CNTR 0 / CNTR 1 pin each time the timer underflows. After the timer underflows, if the values of the output level latch and timer latch are changed, the timer can output an optional waveform from the CNTR0/CNTR 1 pin. In this mode, set the port in common with the CNTR0/CNTR1 pin as an output port. In this mode, if the trigger selection bit of TXM or TYM is set to “1” and the count stop control bit of TXYCON is set to “0” (count operation), a timer can be started concurrently with the occurrence of a trigger (input signal of INT0/INT1 pin). A timer starting trigger is set in the INT0 edge selection bit (b0) or INT1 edge selection bit (b1) of EG. At “0”, the falling edge is active. At “1”, the rising edge is active. When the count stop control bit is “1” (count status), a timer is not started at the occurrence of a trigger. Figure 23 shows a timing diagram in the programmable waveform generation mode. (6) Programmable One-Shot Output Mode ● Mode Selection This mode is selected by setting b2, b1 and b0 of TXM or TYM to “101”. ● Count Source Selection The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16. ● Interrupt The underflow interrupt is the same as the timer event count mode. One-shot output trigger is set in the INT0 edge selection bit (b0) or INT1 edge selection bit (b1) of EG. At “0”, the falling edge is active. At “1”, the rising edge is active. The INT0 interrupt request bit (b0) or INT1 interrupt request bit (b1) of IREQ2 is set to “1” by detecting an active edge of the INT pin. ● Explanation of Operation ➀ In case of One-shot Output “H” 22 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (b2, b3 of EG = “0”) While a timer operation stops The output level of the CNTR0/CNTR1 pin is initialized to “L” at mode selection. Set the one-shot width in TXH, TXL, TYH and TYL. While a timer operation stops, a trigger (input signal of INT0/INT1 pin) cannot occur. While a timer operation is enabled At detecting a trigger, a timer outputs “H” from the CNTR 0 / CNTR1 pin, and outputs “L” at a timer underflow. ➁ In Case of One-shot Output “L” (b2, b3 of EG = “1”) While a timer operation stops The output level of the CNTR0/CNTR1 pin is initialized to “H” at mode selection. Set the one-shot width in TXH, TXL, TYH and TYL. While a timer operation stops, a trigger (input signal of the INT0/INT1 pin) cannot occur. While a timer operation is enabled At the detection of a trigger, a timer outputs “L” from the CNTR0/ CNTR1 pin and outputs “H” at a timer underflow. In this mode, set the port in common with the CNTR 0/CNTR1 pin as an output port. ■ Note ● Input a trigger width over 250 ns to the INT0/INT1 pin. ● If the value of the CNTR0 edge selection bit or CNTR1 edge selection bit is changed while one-shot output is enabled or one-shot output occurs, the output level from the CNTR 0 / CNTR1 pin changes. Figure 24 shows a timing diagram in the programmable oneshot output mode. MITSUBISHI MICROCOMPUTERS A IMIN RY . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L (7) PWM Mode ● Mode Selection This mode is selected by setting b2, b1 and b0 of TXM or TYM to “110”. ● Count Source Selection The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16. ● Interrupt At the rising edge of the CNTR0/CNTR1 output, set the timer X interrupt request bit (b0) or timer Y interrupt request bit (b1) of IREQ1 to “1”. ● Explanation of Operation In the case of timer X, the PWM waveform is output from the CNTR0 pin. In the case of timer Y, the PWM waveform is output from the CNTR1 pin. The PWM waveform “H” period is determined by the setting value n (n=0 to 255) of TXH or TYH. The “L” period is determined by the setting value m (m=0 to 255) of TXL or TYL. The PWM cycle is as follows: 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER same time. At writing only to the timer latch, when the write timing for the timer latch is almost equal to the underflow timing, the value that is set in the timer may not be constant. ● Read Control for Timer X/Timer Y When the pulse cycle measurement mode or pulse width measurement mode is selected, the timer value cannot be read out. In the other modes, the timer value can be read regardless of count operation and count stop. However, the timer latch value cannot be read out. ● Note on CNTR0, CNTR1, INT0, INT1 Interrupt Polarity Selection When the CNTR0/CNTR1 edge selection bit or INT0/INT1 interrupt edge selection bit is set, this affects the respective interrupt polarity. PWM cycle = (n + m) ✕ ts PWM output duty = n (n + m) ts: Timer X/timer Y count source cycle While a timer operation stops The timer value is set in TXL, TXH, TYL and TYH by writing to the timer and timer latch at the same time. The output of the CNTR0/CNTR1 pin is initialized to “H” by setting this timer value. While a timer operation is enabled When b1 and b0 of TXYCON are set to “0”, “H” is output during the period of the setting value of TXH or TYH. After that, “L” is output during the period of the setting value of TXL or TYL. Then, these operations will be repeated. The PWM output subsequent to an underflow can be changed by setting the timer value in TXL, TXH, TYL, TYH by writing only to the timer latch. In this mode, set the port in common with the CNTR 0/CNTR1 pin as an output port. ■ Note ● When the PWM “H” period is set to “0016”, the PWM output is always “L” level. ● When the PWM “L” period is set to “0016”, the PWM output is always “H” level. ● When the PWM “H” period is set to “0016” and the “L” period is set to “0016”, the PWM output is always “L” level. ● When at least one of the PWM “H” period and “L” period is set to “0016”, a timer X interrupt request/timer Y interrupt request does not occur. ● When the timer latch is set at “0016”, the timer counts down, so its value is not constant. Figure 25 shows a timing diagram in the PWM mode. ■ Note on All Modes ● Write Control for Timer X, Timer Y Timer X and timer Y can select either writing to both timer latch and timer or writing only to the timer latch by b3 of TXM or TYM. At writing only to the timer latch, a value is set in the timer latch by writing the value in the timer X/timer Y address, so the timer is updated at the next underflow. After reset release, writing to both the timer latch and timer is selected. At this status, when a value is written in the timer X/timer Y address, the value is set in both the timer and timer latch at the 23 MITSUBISHI MICROCOMPUTERS RY A N IMI 7480/7481 GROUP ge. ion. icat to chan ecif l sp ubject a in f s are ot a is n limits his e: T ametric ic t No e par Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CNTR0 edge selection bit “1” “1” P30/INT0 Programmable one-shot output mode Data bus Programmable one-shot output circuit “0” INT0 edge selection bit Programmable one-shot output mode PWM mode PWM mode “0” PWM generating circuit INT0 interrupt request Programmable waveform generation mode Output level latch D Q Pulse output mode T S “001” “100” “101” “110” T Q Q P40 latch Timer X operating mode bits P40 direction register CNTR0 edge selection bit “0” Pulse output mode “1” Timer X (low-order) latch Timer X (high-order) latch Timer X (low-order) Timer X interrupt request Timer X (high-order) Pulse width measurement mode Pulse cycle measurement mode CNTR0 edge selection bit Edge detecting circuit “1” P40/CNTR0 “0” f(XIN )/2 f(XIN )/8 f(XIN )/16 Programmable waveform generation mode Timer X trigger selection bit “0” Timer X stop control bit D Q “1” T CNTR1 edge selection bit “1” “1” P31/INT1 CNTR0 interrupt request Timer X count source selection bit Programmable one-shot output circuit “0” INT1 edge selection bit Programmable one-shot output mode PWM mode Programmable one-shot output mode “0” PWM generating circuit INT1 interrupt request PWM mode Programmable waveform generation mode Output level latch D Q T Pulse output mode S “001” “100” “101” “110” T P41 latch Timer Y operating mode bits P41 direction register Q Q CNTR1 edge selection bit “0” “1” Pulse output mode Timer Y (low-order) latch Timer Y (high-order) latch Timer Y (low-order) Timer Y (high-order) Timer Y interrupt request Pulse width measurement mode Pulse cycle measurement mode CNTR1 edge selection bit Edge detecting circuit P41/CNTR1 “0” Timer Y count source selection bit f(XIN )/2 f(XIN )/8 f(XIN )/16 Programmable waveform generation mode “0” Timer Y trigger selection bit Timer Y stop control bit D T Fig. 17 Block diagram of timer X and timer Y 24 interrupt request CNTR 1 “1” Q “1” MI ELI MITSUBISHI MICROCOMPUTERS Y NAR 7480/7481 GROUP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR b7 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Timer X mode register (TXM : address 00F6 16) b7 b0 Timer Y mode register (TYM : address 00F7 16) Timer X operating mode bits b2 b1 b0 0 0 0 : Timer event count mode 0 0 1 : Pulse output mode 0 1 0 : Pulse cycle measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generation mode 1 0 1 : Programmable one-shot output mode 1 1 0 : PWM mode 1 1 1 : Not used Timer Y operating mode bits b2 b1 b0 0 0 0 : Timer event count mode 0 0 1 : Pulse output mode 0 1 0 : Pulse cycle measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generation mode 1 0 1 : Programmable one-shot output mode 1 1 0 : PWM mode 1 1 1 : Not used Timer X write control bit 0 : Writing to both latch and timer 1 : Writing to latch only Timer Y write control bit 0 : Writing to both latch and timer 1 : Writing to latch only Output level latch 0 : “L” output 1 : “H” output Output level latch 0 : “L” output 1 : “H” output Timer X trigger selection bit 0 : Timer X free run in programmable waveform generation mode 1 : Trigger occurrence (input signal of INT 0 pin) and timer X start in programmable waveform generation mode. Timer Y trigger selection bit 0 : Timer Y free run in programmable waveform generation mode 1 : Trigger occurrence (input signal of INT 1 pin) and timer Y start in programmable waveform generation mode. Timer X count source selection bits b7 b6 0 0 : f(XIN)/2 0 1 : f(XIN)/8 1 0 : f(XIN)/16 1 1 : Input from CNTR 0 pin Timer Y count source selection bits b7 b6 0 0 : f(XIN)/2 0 1 : f(XIN)/8 1 0 : f(XIN)/16 1 1 : Input from CNTR1 pin b0 Timer XY control register (TXYCON : address 00F8 16) Timer X stop control bit 0 : Count operation 1 : Count stop Timer Y stop control bit 0 : Count operation 1 : Count stop Not used (all “0” at read) Fig. 18 Structure of timer X/timer Y mode register and timer XY control register 25 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FFFF 16 TL 000016 TR TR TR TL : Value set in timer latch TR : Timer interrupt request Fig. 19 Timing diagram in timer mode/event count mode FFFF 16 TL 000016 TR TR TR Output waveform from CNTR 0/CNTR 1 pin CNTR CNTR TL : Value set in timer latch TR : Timer interrupt request CNTR : CNTR 0/CNTR1 interrupt request (CNTR polarity selection bit “0” : falling edge active) Fig. 20 Timing diagram in pulse output mode 26 TR MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 0000 16 T3 T2 T1 FFFF 16 TR TR FFFF16+T1 T2 T3 FFFF 16 Input signal from CNTR 0/CNTR 1 pin CNTR CNTR CNTR CNTR CNTR 0/CNTR1 interrupt polarity is active at rising edge. TR : Timer interrupt request CNTR: CNTR 0/CNTR1 interrupt request Fig. 21 Timing diagram in pulse cycle measurement mode (at “rising edge interval” measurement) 0000 16 T3 T2 T1 FFFF 16 TR FFFF16+T2 T3 T1 Input signal from CNTR 0/CNTR 1 pin CNTR CNTR CNTR CNTR 0/CNTR 1 interrupt polarity is active at rising edge, and pulse L width is measured. TR : Timer interrupt request CNTR : CNTR 0/CNTR1 interrupt request Fig. 22 Timing diagram in pulse width measurement mode (at “L section” measurement) 27 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FFFF16 T3 L T2 T1 000016 TR L TR TR T3 T1 TR T2 Input signal from INT 0/INT1 pin Output waveform from CNTR 0/CNTR 1 pin CNTR CNTR L : Initial value of TL H, TLL TR : Timer interrupt request CNTR : CNTR 0/CNTR1 interrupt request (CNTR polarity selection bit “0” : falling edge active) Fig. 23 Timing diagram in programmable waveform generation mode (when trigger selection bit = “1”) FFFF16 L 0000 16 TR TR TR Input signal from INT0/INT1 pin L Output waveform from CNTR 0/ CNTR 1 pin L L CNTR CNTR L : One-shot pulse width TR : Timer interrupt request CNTR : CNTR 0/CNTR1 interrupt request (CNTR polarity selection bit “0” : falling edge active) Fig. 24 Timing diagram in programmable one-shot output mode 28 CNTR MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ts Timer X/timer Y count source Timer X/timer Y PWM output n✕t s m ✕t s (n+m) ✕t s TR CNTR TR CNTR : CNTR 0/CNTR 1 interrupt request (CNTR polarity selection bit “0” : falling edge active) TR : Timer interrupt Note : A PWM waveform with duty n/(n+m) and cycle (n+m) ✕ ts is output. • TXH/TYH setting value: n= 0 – 255 • TXL/TYL setting value: m = 0 – 255 • Timer X/timer Y count source cycle: ts • n+m = 0 – 510 Fig. 25 Timing diagram in PWM mode 29 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ● Timers 1 and 2 Timer 1 and timer 2 are the 8-bit timers. They can select the following 2 modes by setting timer 1 mode register and timer 2 mode register. • Timer mode • Programmable waveform generation mode When the count source is changed, set it again as the timer value may go wrong. (1) Timer Mode The frequency of f(X IN)/8, f(X IN)/64, f(X IN)/128 or f(X IN)/256 is counted. (2) Programmable Waveform Generation Mode This operation is the same as the timer mode, except that a timer outputs the level of the value set in the output level latch of the timer 1 mode register/timer 2 mode register from the T 0 or T1 pin each time a timer underflows. After the timer underflows, the timer can output an optional waveform from the T0 or T1 pin if the values of the output level latch and timer latch are changed. In this mode, set the port in common with the T0/T1 pin as an output port. Data bus 8 Timer count source selection bits 8 Count stop control bit “00” “01” “10” “11” f(XIN)/8 f(XIN)/64 f(XIN)/128 f(XIN)/256 TL Timer interrupt request bit T T T0, T1 output Q D 8 Output level latch Timer mode register 8 Data bus Fig. 26 Block diagram of timer 1, timer 2 b7 b0 Timer 1 mode register (T1M : address 00F9 16) Timer 2 mode register (T2M : address 00FA 16) Timer stop control bit 0 : Count operation 1 : Count stop Timer operation mode bit 0 : Timer mode 1 : Programmable waveform generation mode Not used (“0” at read) Output level latch 0 : “L” output 1 : “H” output Not used (“0” at read) Timer count source selection bits b7 b6 0 0 : f(XIN)/8 0 1 : f(XIN)/64 1 0 : f(XIN)/128 1 1 : f(XIN)/256 Fig. 27 Structure of timer 1/timer 2 mode register 30 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O the serial I/O mode selection bit of the serial I/O control register (address 00E216) to “1”. In the clock synchronous serial I/O, the transmitter-side microcomputer and the receiver-side microcomputer must use the same clock for serial I/O operation. If an internal clock is used as operating clock, a transfer is started by a write signal to the transmit/ receive buffer register. Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation when serial I/O is in operation. (1) Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode can be selected by setting Data bus P16 Address 00E016 Receive buffer register P14 RXD Receive enable bit (RE) Address 00E216 Serial I/O control register Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register Shift clock Clock control circuit SCLK Serial I/O enable bit (SIOE) XIN Serial I/O synchronous BRG count source Frequency division clock selection selection bit (CSS) ratio 1/(n+1) bit (SCS) Baud rate generator 1/4 1/4 1/4 SRDY output enable bit (SRDY) SRDY Falling edge detection F/F Transmit enable bit (TE) TXD Address 00E416 Clock control circuit Transmit shift register shift completion flag (TSC) Transmit shift register Transmit interrupt source selection bit (TIC) P17 P15 Transmit interrupt request (TI) Transmit buffer register Transmit buffer empty flag (TBE) Serial I/O status register Address 00E116 Address 00E016 Data bus Fig. 28 Block diagram of clock synchronous serial I/O Transmit/receive shift clock, 1/8 – 1/8192 of internal clock, or external clock Serial output TxD Serial input RxD D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal S RDY Write signal to receive/ transmit buffer register (address 00E016 ) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1 : The transmit interrupt (TI) can be selected to be generated either when the transmit buffer is empty (TBE = 1) or after the transmit shift operation is completed (TSC = 1) by using the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2 : If data is written to the transmit buffer register when TSC = 0, the transmit clock is generated continuously, and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”. Fig. 29 Operation of clock synchronous serial I/O function 31 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Asynchronous Serial I/O (UART) Mode The UART mode can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats to be used by a transmitter and a receiver must be identical. Each of the transmit and receive registers has a buffer register (the same address on memory). Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register and receive data is read from the receive buffer register. These buffer registers can also hold the next data to be transmitted and receive 2-byte receive data in succession. Data bus Address 00E2 16 P14 RXD Receive enable bit (RE) ST detection Address 00E0 16 Serial I/O control register Receive buffer register OE 7-bit Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register Character length selection bit (CHAS) 8-bit PE SP detection FE UART control register 1/16 Address 00E3 16 Clock control circuit Serial I/O enable bit (SIOE) Serial I/O synchronous clock selection bit (SCS) SCLK XIN BRG count source selection bit (CSS) Serial I/O synchronous clock selection bit (SCS) Frequency division ratio 1/(n+1) 1/4 Baud rate generator Address 00E4 16 1/4 ST/SP/PA generation Transmit enable bit (TE) T XD Transmit shift register Character length selection bit Transmit (CHAS) P16 P15 1/16 Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit (TIC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) buffer register Address 00E1 16 Serial I/O status register Address 00E0 16 Data bus Fig. 30 Block diagram of UART serial I/O Transmit or receive clock Transmit buffer register write signal TBE=0 TSC=0 TBE=1 Serial output TxD ST TBE=0 TSC=1 * TBE=1 D0 D1 SP ST D0 D1 1 start bit 7/8 data bit 1/0 parity bit 1/2 stop bit Receive buffer register read signal SP ✽Generated at 2nd bit in 2 stop bit mode RBF=0 RBF=1 RBF=1 Serial input RxD ST D0 D1 SP ST D0 D1 SP Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit during reception). 2 : The transmit interrupt (TI) can be selected to be generated when either TBE=1 or TSC=1, depending on the setting of the transmit interrupt source selection bit of the serial I/O control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes “1”. Fig. 31 Operation of UART serial I/O function 32 MI ELI MITSUBISHI MICROCOMPUTERS Y NAR 7480/7481 GROUP . ion. hange icat ecif ct to c p s al bje a fin are su not s is is ric limit h T t me ice: Not e para Som PR [Serial I/O Control Register] SIOCON The serial I/O control register consists of 8 control bits for control of the serial I/O. SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Transmit buffer empty flag (TBE) 0 : Buffer full 1 : Buffer empty Receive buffer full flag (RBF) 0 : Buffer empty 1 : Buffer full Transmit shift register shift completion flag (TSC) 0 : Transmit shift in progress 1 : Transmit shift completed Overrun error flag (OE) 0 : No error 1 : Overrun error Parity error flag (PE) 0 : No error 1 : Parity error Framing error flag (FE) 0 : No error 1 : Framing error Summing error flag (SE) 0 : (OE)U(PE)U(FE)=0 1 : (OE)U(PE)U(FE)=1 Not used (“1” at read) [UART Control Register] UARTCON The UART control register is a 4-bit control register which is valid when UART is selected. This 4-bit control register sets a data format for serial data transfer. [Serial I/O Status Register] SIOSTS This is a 7-bit read-only register consisting of flags that indicate the serial I/O operating status and different error flags. The 3 bits of bit 4 to bit 6 are valid only in the UART mode. The receive buffer full flag is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. Writing to the serial I/O status register clears all the error flags (OE, PE, FE, SE). All the bits of this register are initialized to “0” at reset. However, if the transmit enable bit of the serial I/O control register is set to “1”, bit 2 and bit 0 become “1”. Serial I/O status register SIOSTS (address 00E116) b7 b0 Serial I/O control register SIOCON (address 00E216) BRG count source selection bit (CSS) 0 : f(X IN)/4 1 : f(X IN)/16 Serial I/O synchronous clock selection bit (SCS) 0 : BRG output/4 (when clock synchronous serial I/O is selected) BRG output/16 (when UART is selected) 1 : External clock input (when clock synchronous serial I/O is selected) External clock input/16 (when UART is selected) SRDY output enable bit (SRDY) 0 : P1 7 pin operates as ordinary I/O pin. 1 : P1 7 pin operates as SRDY output pin. Transmit interrupt source selection bit (TIC) 0 : Interrupt when transmit buffer is empty. 1 : Interrupt when transmit shift operation is completed. Transmit enable bit (TE) 0 : Transmit disabled 1 : Transmit enabled Receive enable bit (RE) 0 : Receive disabled 1 : Receive enabled Serial I/O mode selection bit (SIOM) 0 : Asynchronous serial I/O (UART) 1 : Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0 : Serial I/O disabled (P14 to P17: ordinary I/O ports) 1 : Serial I/O enabled (P14 to P17: serial I/O function pins) [Transmit Buffer Register/Receive Buffer Register] TB/RG The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is a write-only type and the receive buffer register is a read-only type. If a character bit length is 7 bits, the MSB of the receive data stored in the receive buffer is “0”. [Baud Rate Generator] BRG The baud rate generator determines a baud rate for serial transfer. The baud rate generator, being an 8-bit counter with a reload register, divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator. b7 b0 UART control register UARTCON (address 00E316) Character length selection bit (CHAS) 0 : 8-bit 1 : 7-bit Parity enable bit (PARE) 0 : Parity disabled 1 : Parity enabled Parity selection bit (PARS) 0 : Even parity 1 : Odd parity Stop bit length selection bit (STPS) 0 : 1 stop bit 1 : 2 stop bits Not used (“1” at read) Fig. 32 Structure of serial I/O related registers (SIOSTS, UARTCON, SIOCON) 33 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Bus Arbitration Interrupt The 7480/7481 group is provided with a built-in bus arbitration interrupt as a function for bus conflict system communication. At such bus conflict system communication, as shown in Figure 33, if transmit data cannot be transmitted to the LAN data bus due to a transmit data collision, the data collision can be detected by the bus arbitration interrupt. LAN data bus 7480/7481 group serial I/O TxD RxD Fig. 33 Example of bus conflict system communication 34 Interface driver/ receiver MITSUBISHI MICROCOMPUTERS RY A N IMI 7480/7481 GROUP ge. ion. icat to chan ecif l sp ubject a in f s are ot a is n limits his e: T ametric ic t No e par Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Bus Collision Detection The 7480/7481 group can detect a bus collision by setting the bus collision detection enable bit to “1”. When transmission is started in the clock synchronous or asynchronous (UART) serial I/O mode, the transmit pin TxD is compared with the receive pin RxD in synchronization with a rising edge of transmit shift clock. If they do not coincide with each other, a bus arbitration interrupt request occurs (bus collision detection). TXD RXD A transmit data collision is detected between LSB and MSB of transmit data in the clock synchronous serial I/O mode or between the start bit and stop bit of transmit data in the UART mode. Bus collision detection can be performed by both the internal clock and the external clock. A block diagram is shown in Figure 34. A timing diagram is shown in Figure 35. A bus collision detection control register is shown in Figure 36. D Q Bus arbitration interrupt request Shift clock Bus collision detection enable bit TE Fig. 34 Block diagram of bus arbitration interrupt circuit Transmit shift clock Bus arbitration interrupt generation Transmit pin TxD Receive pin RxD Data collision Fig. 35 Timing diagram of bus arbitration interrupt b7 b0 Bus collision detection control register (BUSARBCON address 00E5 16) Bus collision detection enable bit 0 : Collision detection disabled 1 : Collision detection enabled Not used (“0” at read) Fig. 36 Structure of bus collision detection control register 35 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Application Example Priority Control at Simplified SAEJ1850 At simplified SAEJ1850 communication, when multiple units start to transmit data at the same time, priority control is exerted. On the LAN data bus, the “H” level has priority over the “L” level. When an “H” level collides with an “L” level, the LAN data bus status goes to the “H” level. For example, when unit A outputs “H” and unit B outputs “L” at the same time in Figure 37, the LAN data bus goes to “H”. Accordingly, unit A takes priority of control and continues its transmission, and unit B stops its transmission immediately. In this way, the 7480/7481 group exerts priority control for each bit and finally allows only the highest-priority unit to transmit data. BU S+ LAN data bus BU S- Unit A Unit B Continue to transmit Unit A Unit B Stop transmitting LAN data bus Data collision Fig. 37 Priority control at simplified SAEJ1850 36 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D Converter Next, the procedure for executing A-D conversion will be explained below. First, set values in bit 2 to bit 0 of the A-D control register and select pins to be A-D converted. Next, clear the A-D conversion completion bit to “0”. With this write operation, A-D conversion is started. The A-D conversion is completed after the lapse of 50 machine cycles (12.5 µs at f(X IN)= 8 MHz), and the A-D conversion completion bit is set to “1”. The A-D conversion interrupt request bit is also set to “1”. Conversion results are stored in the A-D conversion register. For A-D conversion, the 8-bit successive comparison method is used. Figure 38 shows a block diagram of A-D conversion. Conversion is automatically performed once started by the program. There are 8 analog input pins that are in common with P27 to P20 of port P2 (4 pins of P23 to P20 in the 7480 group). Pin inputs to be A-D converted are selected by bit 2 to bit 0 of the A-D control register (address 00D916). Bit 3 of the A-D control register is an A-D conversion completion bit. This bit is “0” during A-D conversion and “1” after completion of it. Accordingly, it is possible by checking this bit to know whether A-D conversion is completed or not. Figure 39 shows the relationship between the contents of the A-D control register and input pins to be selected. The A-D conversion register (address 00DA16) stores conversion results, so it is possible to know them by reading the contents of this register. Data bus b0 b4 A-D control register (address 00D9 16) P20/IN0 A-D control circuit P22/IN2 P23/IN3 P24/IN4 P25/IN5 Channel selector P21/IN1 Comparator A-D conversion completion interrupt request A-D conversion register (address 00DA 16) Switch tree Ladder resistor P26/IN6 P27/IN7 VSS (Note 1) VREF Notes 1 : AV SS for the 44P6N package of the 7481 group. 2 : The 7480 group is not provided with P2 4/IN4 to P2 7/IN7. Fig. 38 Block diagram of A-D converter circuit 37 MITSUBISHI MICROCOMPUTERS A IMIN RY e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE b7 L b0 A-D control register ADCON (address 00D916) Analog input pin selection bits 000 : P20/IN0 001 : P21/IN1 010 : P22/IN2 011 : P23/IN3 100 : P24/IN4 101 : P25/IN5 (Note) 110 : P26/IN6 111 : P27/IN7 A-D conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF connection selection bit 0: Disconnect between V REF pin and ladder resistor 1: Connect between V REF pin and ladder resistor Not used (undefined at read) Note : Do not perform setting in the 7480 group. Fig. 39 Structure of A-D control register 38 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of a 7-bit watchdog timer L and an 8bit watchdog timer H. ● Initial Value of Watchdog Timer By a reset or writing to the watchdog timer H, the watchdog timer H is set to “FF16” and the watchdog timer L is set to “7F16”. Any instruction that permits generating a write signal can be used; for example, STA, LDM, CLB, etc. Write data has no significance, so the above values are set regardless of that data. ● Operation of Watchdog Timer The watchdog timer stops at reset, and writing a value in the watchdog timer H causes it to start to count down. When bit 7 of the watchdog timer H becomes “0”, an internal reset occurs. The reset status is released as soon as the release reset time is up. After that, the 7480/7481 group runs the program from the reset vector address. It is programmed that the watchdog timer H can be set before bit 7 of the watchdog timer H is cleared to “0”. If the watchdog timer H is never written, the watchdog timer does not function. When the STP instruction is executed, the clock stops and the watchdog timer also stops. The count is restarted as soon as the stop mode is released. (Note) On the other hand, the watchdog timer does not stop after execution of the WIT instruction. The timing from writing to the watchdog timer H to clearing bit 7 of the watchdog timer H to “0” is shown below. (f(XIN)=8 MHz) • When bit 3 of the CPU mode register is “0” ............. 16.384 ms • When bit 3 of the CPU mode register is “1” ............ 32.768 ms Note: Since the watchdog timer still counts for the stop release waiting time (about 2048 cycles of X IN), bit 7 of the watchdog timer H should not be cleared to “0” in this period. Data bus Write “7F16” to the watchdog timer register 1/8 Write “FF16” to the watchdog timer register “0” Watchdog timer L (7) f(XIN) Watchdog timer H (8) 1/16 “1” Watchdog timer L count source selection bit bit7 Reset circuit Internal reset RESET Fig. 40 Block diagram of watchdog timer 39 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER STP/WIT Instruction Control The STP instruction and the WIT instruction can be enabled or disabled selectively by using the STP instruction operation control register. To cope with a program runaway after reset, the STP instruction and the WIT instruction are disabled in the initial status. b7 The STP and WIT instructions can be set as enable/disable only by writing to the STP instruction operation control register twice successively so as not to stop the oscillation clock even if a write data error is caused by program runaway. Figure 41 shows a structure of the STP instruction operation control register. b0 STP instruction operation control register (STPCON: address 00DE 16) STP instruction and WIT instruction enable/disable selection bit (Note) 0 : STP/WIT instruction enabled 1 : STP/WIT instruction disabled Not used (“0” at read) Note : The STP instruction and the WIT instruction are disabled in the initial status. When using these instructions, set bit 0 of the STP instruction operation control register to “1”, then set this bit to “0”. (Writing twice successively) When not using the STP and WIT instructions, set this bit to “1” either once or twice. Fig. 41 Structure of STP instruction operation control register Explanation of STP Instruction Operation Control Register The STP instruction operation control register will be enabled by writing data to the same address twice successively. If data is not written in continuous form, the written data is not valid but the previous value is held. ●STP/WIT instruction enable ●STP/WIT instruction disable • • • • • • SEI LDM #01H, 0DEH LDM #00H, 0DEH CLI • • • Interrupt disable in this period Use only in interrupt enable status Fig. 42 Reference example of data rewriting 40 If an interrupt is received while the same data is written twice, there is a possibility that the write instruction in the interrupt routine may be executed. For this reason, rewriting is required after interrupt disable. Figure 42 shows a reference example of data rewriting. SEI LDM #01H, 0DEH LDM #01H, 0DEH CLI • • • Interrupt disable in this period Use only in interrupt enable status MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Recovery From Power-down Status By Key Input Interrupt (Key-on wake-up) “Key-on wake-up” is one way of recovery from a power-down status by using the STP or WIT instruction. If an “L” level voltage is input to any pin of port P0 when bit 5 of the edge polarity selection register is “1”, an interrupt occurs, and a recovery can be made to the normal operating state. If a key matrix of active “L” with port P0 as an input port is constructed, a recovery can be made to the normal operating status by pressing a key. The key input interrupt is in common with the INT1 interrupt. When bit 5 of the edge polarity selection register is set to “1”, the key input interrupt function is selected. If this bit is set to “1” except in the power-down status, both INT1 and key-on wake-up are invalidated. P41/CNTR 1 Port P4 1 data read circuit CNTR 1 interrupt request signal EG3 P40/CNTR 0 Port P40 data read circuit CNTR 0 interrupt request signal EG2 P30/INT0 Port P30 data read circuit INT0 interrupt request signal EG 0 P31/INT1 Port P31 data read circuit EG1 EG 5 INT1 interrupt request signal CPU stop status signal Pull-up control register P07 Direction register Pull-up control register P01 Direction register Port P0 data read circuit Pull-up control register P00 Direction register Fig. 43 Block diagram of interrupt input/key-on wake-up circuit 41 MITSUBISHI MICROCOMPUTERS A IMIN RY . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Clock Generating Circuit The 7480/7481 group is provided with a built-in oscillation circuit. An oscillation circuit can be formed by connecting a resonator between X IN and X OUT . Use the manufacturer's recommended values for constants such as capacitance, which will differ depending on each resonator. The 7480/7481 group has a built-in feedback resistor between the XIN and XOUT pins, so an external resistor can be omitted. XIN XOUT Rd ● Frequency Control (1) High-speed Mode The frequency applied to the clock input pin XIN divided by 2 is used as the internal clock φ. This mode is set after reset release. (2) Medium-speed Mode The frequency applied to the clock input pin XIN divided by 8 is used as the internal clock φ. ● Oscillation Frequency (1) Stop Mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and the oscillator stops. At this time, timer 1 is set to “FF 16,” and f(XIN)/8 is forcibly connected to the count source of timer 1. Accordingly, set the timer 1 interrupt enable bit to the disable status (“0”) before execution of the STP instruction. When a reset or an external interrupt is accepted, oscillation is restarted, but the internal clock φ is supplied to the CPU after timer 1 underflows. This is because when an external resonator is used, some time is required until a start of oscillation. (2) Wait Mode If the WIT instruction is executed, the internal clock φ stops at an “H” level. But, the oscillator does not stop. When a reset or interrupt is accepted, the stop status is released. The microcomputer can execute any instruction immediately, because the oscillator does not stop. CIN Fig. 44 External circuit of ceramic resonator XIN XOUT Open VCC External oscillation circuit Fig. 45 External clock input circuit 42 COUT VSS Duty ratio 50% MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L XIN SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XOUT 1/2 Timer 1 1/4 1/4 CM6 “1” Internal clock “0” Q S R S Q STP instruction WIT instruction R Q S Q R R Reset STP instruction Reset Interrupt disable flag Interrupt request Fig. 46 Block diagram of clock generating circuit 43 MITSUBISHI MICROCOMPUTERS RY A N IMI 7480/7481 GROUP ge. ion. icat to chan ecif l sp ubject a in f s are ot a is n limits his e: T ametric ic t No e par Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset Circuit The microcomputer is put into a reset status by holding the _____ RESET pin at the “L” level for 2µs or more when the power source voltage is 2.7 to 5.5 V and XIN is in stable oscillation. _____ After that, this reset status is released by returning the RESET pin to the “H” level. The program starts from the address having the contents of address FFFF16 as high-order address and the contents of address FFFE16 as low-order address. Note that the reset input voltage should be 0.32 V or less when the power source voltage passes 2.7 V. Power ON RESET VCC Power source voltage 0V Reset input voltage 0V (Note) 0.12VCC Note : Reset release voltage V CC = 2.7 V RESET Power source voltage detecting circuit VCC Fig. 47 Reset circuit diagram XIN φ RESET Internal reset Address ? Data ? ? ? ? ? ? FFFE16 FFFF16 ? ADL ADH,L ADH Reset address from the vector table SYNC X IN 2048 clock cycle Fig. 48 Reset sequence 44 Notes 1 : The frequency relation between f(X IN) and φ is f(XIN)=2·f(φ). 2 : The mark “?” means that the address is changeable depending on the previous state. MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Port P0 direction register (P0D) Address b7 (C1 16) • • • 0016 b0 (2) Port P1 direction register (P1D) (C3 16) • • • 0016 (3) Port P4 direction register (P4D) (C9 16) • • • 0 0 0 0 (4) Port P5 direction register (P5D) (CB16) • • • 0 0 0 0 (5) Port P0 pull-up control register (P0PCON) (D0 16) • • • (6) Port P1 pull-up control register (P1PCON) (D1 16) • • • 0016 0 0 00 16 ( 7 ) Port P4P5 input control register (P4P5CON) (D216) • • • ( 8 ) Edge polarity selection register (EG) (D416) • • • (9) A-D control register (ADCON) (D9 16) • • • (10) STP instruction operation control register (STPCON) (DE16) • • • 0 0 0 0 0 0 0 1 (11) Serial I/O status register (SIOSTS) (E116) • • • 1 0 0 0 0 0 0 0 (12) Serial I/O control register (SIOCON) (E2 16) • • • (13) UART control register (UARTCON) (E3 16) • • • 1 1 1 1 0 0 0 0 (14) Bus collision detection control register (BUSARBCON) (E516) • • • 0016 (15) Watchdog timer H (WDTH) (EF 16) • • • FF16 (16) Timer X low-order (TXL) (F0 16) • • • FF16 (17) Timer X high-order (TXH) (F1 16) • • • FF16 (18) Timer Y low-order (TYL) (F2 16) • • • FF16 (19) Timer Y high-order (TYH) (F3 16) • • • FF16 (20) Timer 1 (T1) (F4 16) • • • FF16 (21) Timer X mode register (TXM) (F6 16) • • • 0016 (22) Timer Y mode register (TYM) (F7 16) • • • 0016 (23) Timer XY control register (TXYCON) (F816) • • • 0 0 0 0 0 0 1 1 (24) Timer 1 mode register (T1M) (F9 16) • • • 0016 (25) Timer 2 mode register (T2M) (FA 16) • • • 0016 (26) CPU mode register (CPUM) (FB 16) • • • (27) Interrupt request register 1 (IREQ1) (FC 16) • • • (28) Interrupt request register 2 (IREQ2) (FD 16) • • • (29) Interrupt control register 1 (ICON1) (FE 16) • • • (30) Interrupt control register 2 (ICON2) (FF 16) • • • (31) Program counter (PC H) Contents of address FFFF 16 (PCL) Contents of address FFFE 16 (32) 0 0 0 0 0 0 1 0 0 0 0016 0 0 0 0 0 0016 0 0 0 0 0016 0 0 0 0 Processor status register (PS) 1 : At reset release, the read value is undefined. Note : Some kinds of microcomputers do not use some of these bits. Refer to the structure of each register. Fig. 49 Internal state of microcomputer at reset 45 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER BUILT-IN PROGRAMMABLE ROM VERSIONS M37480E8-XXXSP/FP, M37480E8T-XXXSP/FP, M37481E8-XXXSP/FP, M37481E8T-XXXSP/FP, M37481E8SS PIN DESCRIPTION Table 5. Pin description Pin VCC, VSS AVSS (Note 1) Mode Name Input/ output Function Single-chip/ EPROM Power source Single-chip Reference power input Input Reference voltage input pin for A-D converter. EPROM Mode input Input Used as CE input pin. Single-chip Reset input Input Reset input pin. EPROM Reset input Input Connect to VSS. XIN Single-chip/ EPROM Clock input Input XOUT Single-chip/ EPROM Clock output Single-chip I/O port P0 I/O 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, a pull-up transistor can be connected in units of 1 bit, and a key-on wake-up function is provided. EPROM Data I/O D0 – D7 I/O Data 8-bit (D0 to D7) I/O pins I/O 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, a pull-up transistor can be connected in units of 4 bits. P1 2 and P1 3 are in common with timer output pins T0 and T1. P14, P15, P1 6 and P17 are in common with ____ serial I/O pins RxD, TxD, SCLK and SRDY. VREF _____ RESET Apply a voltage of 2.7 to 5.5 V to VCC and 0 V to VSS and AVSS. __ P00 – P07 Output Single-chip I/O port P1 EPROM Address input A4 – A10 Input P11 to P17 are address (A4 to A10) input pins. Leave P10 open. Single-chip Input port P2 Input 8-bit input port. This port is in common with analog input pins IN0 to IN7 (IN0 to IN3 for the 7480 group). EPROM Address input A0 – A3 Input P2 0 to P23 are address (A 0 to A 3) input pins. Leave P24 to P27 open. Single-chip Input port P3 Input 4-bit input port. P30 and P31 are in common with external interrupt input pins INT0 and INT1. EPROM Address input A11, A12, mode input, VPP input Input P30 and P31 are address (A11, A12) input pins. P32 is used for OE input. P3 3 is V PP input. Apply V PP in the program and program verify modes. Single-chip I/O port P4 I/O 4-bit I/O port. The output structure is N-channel open drain output, having built-in clamp diode. P40 and P41 are in common with timer input pins CNTR0 and CNTR1. EPROM Address input A13, A14 Input P40 and P41 are address (A13, A14) input pins. Leave P42 and P43 open. Single-chip I/O port P5 I/O 4-bit I/O port. The output structure is N-channel open drain output, having a built-in clamp diode. EPROM Input port P5 P10 – P17 P20 – P27 (Note 2) __ P30 – P33 P40 – P43 (Note 3) P50 – P53 (Note 4) These are I/O pins of internal clock generating circuit for the main clock. To control generating frequency, an external ceramic resonator is connected between XIN and XOUT pins. If an external clock is used, the clock oscillation source should be connected to the XIN pin, and the XOUT pin should be left open. Feedback resistor is connected between XIN and XOUT. Input Leave these pins open. Notes 1 : This is a dedicated pin for the 44P6N-A package in the 7481 group. 2 : Only 4 bits of P20 to P23 (IN0 to IN3) for the 7480 group. 3 : Only 2 bits of P40 and P41 for the 7480 group. 4 : This is a dedicated pin for the 7481 group. 46 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER EPROM MODE Table 6. Correspondence between pins in EPROM mode The built-in programmable ROM has the EPROM mode in addition _____ to its normal operation modes. When the RESET level becomes “L”, the chip automatically enters the EPROM mode. Table 6 shows a list of correspondence between pins and Figure 50 to Figure 52 show pin connection diagrams. In this status, each of ports P0, P11 to P17, P2 0 to P23, P3, P4 0, P4 1 and VREF are used for the PROM (equivalent to M5M27C256K). In this mode, the built-in PROM can be written to or read from using these pins in the same way as with the M5M27C256K. The clock should be connected to XIN and XOUT pins. A10 A9 A8 A7 A6 A4 A3 A2 A1 A0 CE VSS 42 41 3 40 4 39 5 38 6 37 7 36 10 11 12 13 14 VPP P33 VPP VSS VSS VSS Data I/O __ CE __ OE 2 9 VCC Ports 1 8 M5M27C256K VCC Address input M37481E8-XXXSP M37481E8T-XXXSP M37481E8SS A5 P53 P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS M37480E8, M37481E8 VCC 35 34 33 32 31 30 29 15 28 16 27 17 26 18 25 19 24 20 23 21 22 P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41/CNTR 1 P40/CNTR 0 P33 P32 P31/INT1 P30/INT0 RESET P51 P50 VCC P11 – P17, P20 – P23, P30, P31, P40, P41 A0 – A14 Port P0 D0 – D7 __ CE __ OE VREF P32 D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 VPP OE A12 A11 VSS VCC Outline 42P4B 42S1B-A (M37481E8SS) : PROM pin (equivalent to M5M27C256K) Fig. 50 Pin connection in EPROM mode (1) 47 MITSUBISHI MICROCOMPUTERS RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som OE A13 A14 VPP 24 23 25 26 28 27 29 30 31 19 38 18 M37481E8-XXXFP M37481E8T-XXXFP 39 17 41 15 42 14 43 44 P30/INT0 RESET P51 P50 A11 VCC VSS AVSS VCC VSS VSS CE 12 P20/IN0 A0 11 13 XOUT XIN VREF A2 A1 A3 A4 A6 A5 P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 10 16 1 40 9 A8 A7 20 8 A9 36 37 7 A10 21 6 VSS 22 5 D7 34 35 4 D6 P04 P05 P06 P07 P52 VSS P53 P17/SRDY P16/SCLK P15/TXD P14/RXD 3 D5 2 D4 32 33 P03 P02 P01 P00 P43 P42 P41/CNTR1 P40/CNTR 0 P33 P32 P31/INT1 D0 D1 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D2 L D3 PRE A12 A IMIN Outline 44P6N-A : PROM pin (equivalent to M5M27C256K) Fig. 51 Pin connection in EPROM mode (2) A10 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS 1 32 2 31 3 30 4 29 5 6 7 8 9 10 11 12 M37480E8-XXXSP/FP M37480E8T-XXXSP/FP P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS A9 28 27 26 25 24 23 22 21 13 20 14 19 15 18 16 17 Outline 32P4B 32P2W-A : PROM pin (equivalent to M5M27C256K) Fig. 52 Pin connection in EPROM mode (3) 48 P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR 1 P40/CNTR 0 P33 P32 P31/INT1 P30/INT0 RESET V CC D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 VPP OE A12 A11 VCC VSS MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l fina sub ot a its are n is m This etric li m ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION OF PROM VERSION Reading __ __ To read the PROM, set the CE and OE pins to “L” level, and set the address signal (A0 to A14). The __ stored contents will appear to __ data I/O pins (D0 to D7). When the CE and OE pins are set to “H” level, the data I/O pins will be put into a floating status. Writing __ To write to the PROM, apply “H” to the OE pin and VPP to the VPP pin to set the program mode. Select addresses to be written to with address input pins (A0 to A14) and give write data to the data input pins (D0 to D7) in 8-bit parallel form. In this status, when the __ CE pin becomes “L”, writing will be started. Notes on Writing When using a PROM programmer, specify the address range to address 400016 to address 7FFF16. When data is written between address 0000 16 and address 7FFF16, fill addresses 000016 to 3FFF16 with “FF16”. NOTES ON HANDLING (1) Sunlight and fluorescent light contain wavelengths capable of erasing data. For use in the read mode, be sure to cover the transparent window with a seal. (Ceramic package type) (2) We can supply the seal with which the transparent window is covered. Be careful not to allow the seal to contact the microcomputer lead pins. (Ceramic package type) (3) Before erasing, clean the transparent glass. If the glass is smeared with greasy hands or paste, ultraviolet light transmission will be prevented, having a negative effect on erasing characteristics. (Ceramic package type) (4) Since a high voltage is used for writing data, care should be taken not to apply an overvoltage when turning on the power source. (5) For the programmable microcomputers (one-time programmable version, version shipped in blank), Mitsubishi does not perform PROM write testing and screening in the assembly process and subsequent processes. To improve reliability after writing, perform writing and testing according to the following operation flow before use. Erasing Data can be erased only on the ceramic package with window M37481E8SS. To erase data on this chip, use an ultraviolet light source with a 2537 Angstrom wave length. The minimum radiation power required for erasing is 15W·s/cm2. Writing with PROM programmer Screening (Leave at 150°C for 40 hours.) (Note) Verify test with PROM programmer Function check in target device Note : The screening temperature is up to 150°C. Never expose to 150°C exceeding 100 hours. The M37480E8SP/FP, M37481E8SP/FP and M37481E8SS are not T versions (mountable on vehicles), so it is impossible to mount them on vehicles. The M37481E8SS is for user program evaluation, so it is impossible to mount it on vehicles or on user’s mass-production real machines. Fig. 53 Writing and testing for one-time programmable version 49 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O SIGNALS IN EACH MODE Table 7. I/O signals in each mode Pin __ __ CE OE VPP VCC Data I/O Read-out VIL VIL VCC VCC Output Output disable VIL VIH VCC VCC Floating Programming VIL VIH VPP VCC Input Programming verify VIH VIL VPP VCC Output Program disable VIH VIH VPP VCC Floating Mode Note : VIL and VIH denote an “L” input voltage and an “H” input voltage, respectively. 50 MITSUBISHI MICROCOMPUTERS A IMIN RY . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ADDRESSING MODES DATA REQUIRED FOR MASK ORDERING The 7480/7481 group has strong accessability, because it has 17 kinds of addressing modes. For details, refer to the 740 family addressing modes. Please submit the following data when placing mask orders. (1) Mask ROM confirmation form (2) Mark specification form (3) ROM data .......................................................... EPROM 3 sets MACHINE-LANGUAGE INSTRUCTIONS The 7480/7481 group has 71 machine-language instructions. For details, refer to the 740 family machine-language instruction list. NOTES ON PROGRAMMING (1) The frequency division ratio of the timer is 1/(n+1). n: Timer setting value However, n = 0 – 255 (for timer 1, timer 2) n = 0 – 65535 (timer X, timer Y) (2) The contents of the interrupt request bits can be changed by software, but the values will not change immediately after being overwritten. After changing the value of the interrupt request bits, execute at least one instruction before executing a the BBC or BBS instruction. (3) To calculate in decimal notation, set the decimal mode flag (D) to “1”. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. (4) A NOP instruction should be executed after every PLP instruction. (5) Do not execute the STP instruction during A-D conversion. (6) Multiplication and Division Instructions The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instructions. The execution of these instructions does not change the contents of the processor status register. DATA R E QU I R E D F O R RO M W R I T I N G ORDERING Please submit the following data when placing ROM writing orders. (1) ROM writing confirmation form (2) Mark specification form (3) ROM data .......................................................... EPROM 3 sets 51 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37480M4/M8/E8-XXXSP/FP, M37480M2T/M4T/M8T/E8T-XXXSP/FP ABSOLUTE MAXIMUM RATINGS (7480 Group) Table 8. Absolute maximum ratings Symbol Parameter Condition Rated value Unit –0.3 to 7 V –0.3 to VCC + 0.3 V VCC Power source voltage All voltages are measured on the basis VI Input voltage of the VSS pin. VO Output voltage Output transistors are cut off. –0.3 to VCC + 0.3 V Pd Power dissipation Ta = 25 °C 1000 (Note 1) mW Topr Operating temperature range –20 to 85 (Note 2) °C Tstg Storage temperature –40 to 150 (Note 3) °C Notes 1 : 500 mW for 32P2W-A package type. 2 : –40 to 85 °C for extended operating temperature range version. 3 : –65 to 150 °C for extended operating temperature range version. RECOMMENDED OPERATING CONDITIONS (7480 Group) (VCC = 2.7 to 5.5 V, V SS = 0 V, Ta = –20 to 85°C (Note 1) unless otherwise specified) Table 9. Recommended operating conditions Symbol VCC Power source voltage VSS Power source voltage VIH “H” input voltage P00 – P07, P10 – P17 VIH “H” input voltage P20 – P23 VIH Standard values Parameter Typ. Max. f(XIN) = (2.2VCC – 2) MHz 2.7 3 4.5 V f(XIN) = 8 MHz 4.5 5 5.5 V 0 “H” input voltage P30 – P33 Unit Min. V 0.8 VCC VCC V 0.7 VCC VCC V VCC = 4.5 to 5.5 V 0.8 VCC VCC V VCC = 2.7 to 4.5 V 0.9 VCC VCC V VCC = 4.5 to 5.5 V 0.8 VCC VCC V VCC = 2.7 to 4.5 V 0.9 VCC VCC V 0.8 VCC VCC V VIH “H” input voltage P40 – P41 (Note 4) VIH “H” input voltage XIN, RESET VIL “L” input voltage P00 – P07, P10 – P17 0 0.2 VCC V VIL “L” input voltage P20 – P23 0 0.25 VCC V VIL “L” input voltage P30 – P33 VCC = 4.5 to 5.5 V 0 0.4 VCC V VCC = 2.7 to 4.5 V 0 0.3 VCC V VCC = 4.5 to 5.5 V 0 0.4 VCC V VCC = 2.7 to 4.5 V 0 0.3 VCC V 0 0.16 VCC V 0 0.12 VCC V _____ VIL “L” input voltage P40 – P41 VIL “L” input voltage XIN VIL “L” input voltage RESET II Input current P40 – P41 (Note 4) VI > VCC 1 mA IOH(sum) “H” sum output current P00 – P07 – 30 mA IOH(sum) “H” sum output current P10 – P17 – 30 mA IOL(sum) “L” sum output current P00 – P07, P40 – P41 60 mA IOL(sum) “L” sum output current P10 – P17 IOH(peak) “H” peak output current P00 – P07, P10 – P17 IOL(peak) IOH(avg) IOL(avg) _____ 52 60 mA – 10 mA “L” peak output current P00 – P07, P10 – P17, P40 – P41 20 mA “H” average output current P00 – P07, P10 – P17 (Note 2) –5 mA “L” average output current P00 – P07, P10 – P17, P40 – P41 (Note 2) 10 mA MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 9. Recommended operating conditions (cont.) Symbol f(CNTR) Typ. Max. f(XIN) = 4 MHz 1 CNTR1 (P41) (Note 3) f(XIN) = 8 MHz 2 Clock synchronous f(XIN) = 4 MHz 250 serial I/O mode f(XIN) = 8 MHz 500 f(XIN) = 4 MHz 1 f(XIN) = 8 MHz 2 UART mode Clock input oscillation frequency (Note 3) f(XIN) Min. Timer input frequency CNTR0 (P40), Serial I/O clock input frequency SCLK (P16) (Note 3) f(SCLK) Standard values Parameter VCC = 2.7 to 4.5 V 2.2VCC – 2 VCC = 4.5 to 5.5 V 8 Unit MHz kHz MHz MHz Notes 1 : –40 to 85 °C for extended operating temperature range version. 2 : The average output currents IOH(avg) and IOL(avg) are the average values during 100 ms. 3 : The clock input oscillation frequency is at 50 % duty ratio. 4 : When applying a voltage through a resistor as shown in the figure 54, VI > VCC may be accepted if the current is 1 mA or less. VI Notes on Countermeasures for Noise and Latch-up (7480 Group) I Port P4 Fig. 54 Note on use of port P4 Notes on Clamp Diode (7480 Group) (1) Total input current The current of port P4 through the clamp diode can be drawn up to 1.0 mA per port. When a current that cannot be consumed by microcomputer is sent to the clamp diode, this may raise the power source pin voltage of the microcomputer. The system power circuit must be designed so that the power source voltage of the microcomputer may be stabilized within standard values. (2) Maximum input voltage If the input voltage of a signal connected to port P4 is beyond VCC + 0.3 V, the input waveform should have a delay exceeding 2 µs/V from the moment that this waveform goes over the voltage. For using a CR circuit for delay, calculate a proper delay value by the following expression: dt = dv t 0.6 ✕ VIN The clamp diode of the 7480/7481 group is designed for a level shift of DC signal unlike ordinary switching diodes. Do not apply sudden stress, such as rush current, directly to the diode. (1) Connect a bypass capacitor (0.1 µF) across the V CC pin and the VSS pin with the shortest possible wiring, using a relatively thick wire. (2) Connect a bypass capacitor (0.01 µF) across the VREF pin and the VSS pin with the shortest possible wiring, using a relatively thick wire. (3) In the oscillation circuit, connect across the XIN and XOUT pins with the shortest possible wiring. Connect the GND and V SS pins of the oscillation circuit with the shortest possible wiring, using a relatively thick wire. (4) In the case of the P33/V PP pin of the built-in programmable ROM version, connect an approximately 5 kΩ resistor to the P33/VPP pin the shortest possible in series. ≥ 2 ✕ 10–6 (s/V) where VIN = Maximum input voltage amplitude margin and t = C ✕ R. 53 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37480M4/M8/E8-XXXSP/FP, M37480M2T/M4T/M8T/E8T-XXXSP/FP ELECTRICAL CHARACTERISTICS (7480 Group) (VCC = 2.7 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C (Note 1) unless otherwise specified) Table 10. Electrical characteristics Symbol VOH VOL VT + – VT– VT + – VT– IIH IIH 3 VCC = 3 V, IOH = –1.5 mA 2 “L” output voltage VCC = 5 V, IOL = 10 mA 2 P00 – P07, P10 – P17, P40 – P41 VCC = 3 V, IOL = 3 mA 1 Hysteresis P00 – P07, VCC = 5 V 0.5 P30 – P33, P40 – P41 (Note 2) VCC = 3 V 0.3 Hysteresis P16/SCLK, P14/RXD Hysteresis RESET When used as SCLK, RxD VCC = 5 V 0.5 input VCC = 3 V 0.3 VCC = 5 V 0.5 VCC = 3 V 0.3 V V VI = VCC without pull-up VCC = 5 V 5 transistor VCC = 3 V 3 “H” input current VI = VCC = 5 V 5 P30 – P33, P40 – P41 VI = VCC = 3 V 3 _____ VI = VCC when analog VCC = 5 V 5 input is not selected VCC = 3 V 3 VI = VCC VCC = 5 V 5 (XIN at stop) VCC = 3 V 3 VI = 0 V without pull-up VCC = 5 V –5 “L” input current transistor VCC = 3 V –3 P00 – P07, P10 – P17 VI = 0 V with pull-up VCC = 5 V –0.25 transistor (Note 3) VCC = 3 V –0.08 “L” input current P30 – P33, P40 – P41 IIL “L” input current P20 – P23 IIL “L” input current RESET, XIN _____ –0.5 –1.0 –0.18 –0.35 VCC = 5 V –5 VCC = 3 V –3 VI = 0 V when analog input VCC = 5 V –5 is not selected VCC = 3 V –3 VI = 0 V VCC = 5 V –5 (XIN at stop) VCC = 3 V –3 VI = 0 V Notes 1 : –40 to 85 °C for extended operating temperature range version. 2 : At using P0 for key-on wake-up function. 3 : Can be indicated in resistance value as shown below: When VCC = 5 V: 5 kΩ (min.), 10 kΩ (typ.), 20 kΩ (max.). When VCC = 3 V: 8.6 kΩ (min.), 16.7 kΩ (typ.), 37.5 kΩ (max.). V V P00 – P07, P10 – P17 “H” input current RESET, X IN Unit V “H” input current IIH 54 Max. VCC = 5 V, IOH = –5 mA “H” input current P20 – P23 IIL Typ. P00 – P07, P10 – P17 IIH IIL Min. “H” output voltage _____ VT + – VT– Standard values Test conditions Parameter µA µA µA µA µA mA µA µA µA MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37480M4/M8/E8-XXXSP/FP, M37480M2T/M4T/M8T/E8T-XXXSP/FP Table 10. Electrical characteristics (cont.) Symbol VRAM Parameter RAM retention voltage Test conditions At clock stop mode In high-speed mode, f(XIN) = 4 MHz, VCC = 5 V In operating mode In high-speed mode, f(XIN) = 4 MHz, VCC = 3 V In high-speed mode, f(XIN) = 8 MHz, VCC = 5 V In medium-speed mode, f(XIN) = 4 MHz, VCC = 5 V In medium-speed mode, f(XIN) = 4 MHz, VCC = 3 V Power source current In medium-speed mode, f(XIN) = 8 MHz, VCC = 5 V In wait mode In high-speed mode, f(XIN) = 4 MHz In high-speed mode, f(XIN) = 8 MHz In medium-speed mode, f(XIN) = 4 MHz In medium-speed mode, f(XIN) = 8 MHz In stop mode ICC f(XIN) = 0 VCC = 5 V Standard values Min. Typ. Max. 2 Unit V A-D conversion not executed 3.5 7 mA A-D conversion in progress 4 8 mA A-D conversion not executed 1.8 3.6 mA A-D conversion in progress 2 4 mA A-D conversion not executed 7 14 mA A-D conversion in progress 7.5 15 mA A-D conversion not executed 1.75 3.5 mA A-D conversion in progress 2 4 mA A-D conversion not executed 0.9 1.8 mA A-D conversion in progress 1 2 mA A-D conversion not executed 3.5 7 mA A-D conversion in progress 3.75 7.5 mA VCC = 5 V 1 2 VCC = 3 V 0.5 1 VCC = 5 V 2 4 VCC = 5 V 0.9 1.8 VCC = 3 V 0.45 0.9 VCC = 5 V 1.8 3.6 Ta = 25 °C 0.1 1 µA Ta = 85 °C 1 10 µA mA mA 55 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37480M4/M8/E8-XXXSP/FP, M37480M2T/M4T/M8T/E8T-XXXSP/FP A-D CONVERSION CHARACTERISTICS (7480 Group) (VCC = 2.7 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C (Note) unless otherwise specified) Table 11. A-D conversion characteristics Symbol Parameter —— Resolution —— Absolute accuracy (except quantization error) TCONV Conversion time VVREF Reference voltage RLADDER Ladder resistance VIA Analog input voltage IVREF Reference input current Test conditions Min. Typ. VCC = VREF = 5.0 V Max. bits ±2 LSB 25 VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz 12.5 VCC = 2.7 to 4.0 V 2 VCC VCC = 4.0 to 5.5 V 0.5 VCC VCC 12 35 0 VREF = 5.0 V 50 143 Unit 8 VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz Note: –40 to 85 °C for extended operating temperature range version. 56 Standard values µs V 100 kΩ VREF V 416 µA MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37481M4/M8/E8-XXXSP/FP, M37481M2T/M4T/M8T/E8T-XXXSP/FP, M37481E8SS ABSOLUTE MAXIMUM RATINGS (7481 Group) Table 12. Absolute maximum ratings Symbol Parameter Condition Rated value Unit –0.3 to 7 V –0.3 to VCC + 0.3 V VCC Power source voltage All voltages are measured on the basis VI Input voltage of the VSS pin. VO Output voltage Output transistors are cut off. –0.3 to VCC + 0.3 V Pd Power dissipation Ta = 25 °C 1000 (Note 1) mW Topr Operating temperature range –20 to 85 (Note 2) °C Tstg Storage temperature –40 to 150 (Note 3) °C Notes 1 : 500 mW for 44P6N-A package type. 2 : –40 to 85 °C for extended operating temperature range version. 3 : –65 to 150 °C for extended operating temperature range version. RECOMMENDED OPERATING CONDITIONS (7481 Group) (VCC = 2.7 to 5.5 V, V SS = 0 V, Ta = –20 to 85°C (Note 1) unless otherwise specified) Table 13. Recommended operating conditions Symbol VCC Power source voltage VSS Power source voltage VIH “H” input voltage P00 – P07, P10 – P17 VIH “H” input voltage P20 – P27 VIH Standard values Parameter Typ. Max. f(XIN) = (2.2VCC – 2) MHz 2.7 3 4.5 V f(XIN) = 8 MHz 4.5 5 5.5 V 0 “H” input voltage P30 – P33 Unit Min. V 0.8 VCC VCC V 0.7 VCC VCC V VCC = 4.5 to 5.5 V 0.8 VCC VCC V VCC = 2.7 to 4.5 V 0.9 VCC VCC V VCC = 4.5 to 5.5 V 0.8 VCC VCC V VCC = 2.7 to 4.5 V 0.9 VCC VCC V 0.8 VCC VCC V VIH “H” input voltage P40 – P43, P50 – P53 (Note 4) VIH “H” input voltage XIN, RESET VIL “L” input voltage P00 – P07, P10 – P17 0 0.2 VCC V VIL “L” input voltage P20 – P27 0 0.25 VCC V VIL “L” input voltage P30 – P33 VCC = 4.5 to 5.5 V 0 0.4 VCC V VCC = 2.7 to 4.5 V 0 0.3 VCC V VCC = 4.5 to 5.5 V 0 0.4 VCC V VCC = 2.7 to 4.5 V 0 0.3 VCC V 0 0.16 VCC V 0 0.12 VCC V _____ VIL “L” input voltage P40 – P43, P50 – P53 VIL “L” input voltage XIN VIL “L” input voltage RESET II Input current P40 – P43, P50 – P53 (Note 4) VI > VCC 1 mA IOH(sum) “H” sum output current P00 – P07 –30 mA IOH(sum) “H” sum output current P10 – P17 –30 mA IOL(sum) “L" sum output current P00 – P07, P40 – P43, P50 – P52 60 mA IOL(sum) “L” sum output current P10 – P17, P53 IOH(peak) “H” peak output current P00 – P07, P10 – P17 IOL(peak) IOH(avg) IOL(avg) _____ 60 mA –10 mA “L” peak output current P00 – P07, P10 – P17, P40 – P43, P50 – P53 20 mA “H” average output current P00 – P07, P10 – P17 (Note 2) –5 mA “L” average output current P00 – P07, P10 – P17, P40 – P43, P50 – P53 (Note 2) 10 mA 57 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 13. Recommended operating conditions (cont.) Symbol f(CNTR) Typ. Max. f(XIN) = 4 MHz 1 CNTR1 (P41) (Note 3) f(XIN) = 8 MHz 2 Clock synchronous f(XIN) = 4 MHz 250 serial I/O mode f(XIN) = 8 MHz 500 f(XIN) = 4 MHz 1 f(XIN) = 8 MHz 2 UART mode Clock input oscillation frequency (Note 3) f(XIN) Min. Timer input frequency CNTR0 (P40), Serial I/O clock input frequency SCLK (P16) (Note 3) f(SCLK) Standard values Parameter VCC = 2.7 to 4.5 V 2.2VCC – 2 VCC = 4.5 to 5.5 V 8 Unit MHz kHz MHz MHz Notes 1 : –40 to 85 °C for extended operating temperature range version. 2 : The average output currents IOH(avg) and IOL(avg) are the average values during 100 ms. 3 : The clock input oscillation frequency is at 50 % duty ratio. 4 : When applying a voltage through a resistor as shown in the figure 55, VI > VCC may be accepted if the current is 1 mA or less. VI Notes on Countermeasures for Noise and Latch-up (7481 Group) I Port P4, P5 Fig. 55 Notes on use of ports P4 and P5 Notes on Clamp Diode (7481 Group) (1) Total input current The current of ports P4 and P5 through the clamp diode can be drawn up to 1.0 mA per port. When a current that cannot be consumed by microcomputer is sent flow to the clamp diode, this may raise the power source pin voltage of the microcomputer. The system power circuit must be designed so that the power source voltage of the microcomputer may be stabilized within the standard values. (2) Maximum input voltage If the input voltage of a signal connected to ports P4 and P5 is beyond VCC + 0.3 V, the input waveform should have a delay exceeding 2 µs/V from the moment that this waveform goes over the voltage. For using a CR circuit for delay, calculate a proper delay value by the following expression: dt = dv t 0.6 ✕ VIN ≥ 2 ✕ 10–6 (s/V) where VIN = Maximum input voltage amplitude margin and t = C ✕ R. 58 The clamp diode of the 7480/7481 group is designed for a level shift of DC signal unlike ordinary switching diodes. Do not apply sudden stress, such as rush current, directly to the diode. (1) Connect a bypass capacitor (0.1 µF) across the V CC pin and the VSS pin with the shortest possible wiring, using a relatively thick wire. (2) Connect a bypass capacitor (0.01 µF) across the VREF pin and the VSS pin with the shortest possible wiring, using a relatively thick wire. (3) In the oscillation circuit, connect across the XIN and XOUT pins with the shortest possible wiring. Connect the GND and V SS pins of the oscillation circuit with the shortest possible wiring, using a relatively thick wire. (4) In the case of the P33/V PP pin of the built-in programmable ROM version, connect an approximately 5 kΩ resistor to the P33/VPP pin the shortest possible in series. MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37481M4/M8/E8-XXXSP/FP, M37481M2T/M4T/M8T/E8T-XXXSP/FP, M37481E8SS ELECTRICAL CHARACTERISTICS (7481 Group) (VCC = 2.7 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C (Note 1) unless otherwise specified) Table 14. Electrical characteristics Symbol VOH VOL VT + – VT– VT + – VT– IIH IIH Max. VCC = 5 V, IOH = –5 mA 3 VCC = 3 V, IOH = –1.5 mA 2 “L” output voltage P00 – P07, VCC = 5 V, IOL = 10 mA 2 P10 – P17, P40 – P43, P50 – P53 VCC = 3 V, IOL = 3 mA 1 Hysteresis P00 – P07, (Note 2) VCC = 5 V 0.5 P30 – P33, P40 – P43, P50 – P53 VCC = 3 V 0.3 Hysteresis P16/SCLK, P14/RXD Hysteresis RESET When used as SCLK, RxD VCC = 5 V 0.5 input VCC = 3 V 0.3 VCC = 5 V 0.5 VCC = 3 V 0.3 V V VI = VCC without pull-up VCC = 5 V 5 transistor VCC = 3 V 3 “H” input current VI = VCC = 5 V 5 P30 – P33, P40 – P43, P50 – P53 VI = VCC = 3 V 3 “H” input current RESET, X IN _____ VI = VCC when analog VCC = 5 V 5 input is not selected VCC = 3 V 3 VI = VCC VCC = 5 V 5 (XIN at stop) VCC = 3 V 3 VI = 0 V without pull-up VCC = 5 V –5 “L” input current P00 – P07, transistor VCC = 3 V –3 P10 – P17 VI = 0 V with pull-up VCC = 5 V –0.25 transistor (Note 3) VCC = 3 V –0.08 “L” input current P30 – P33, P40 – P43, P50 – P53 IIL “L” input current P20 – P27 IIL “L” input current RESET, XIN _____ –0.5 –1.0 –0.18 –0.35 VCC = 5 V –5 VCC = 3 V –3 VI = 0 V when analog input VCC = 5 V –5 is not selected VCC = 3 V –3 VI = 0 V VCC = 5 V –5 (XIN at stop) VCC = 3 V –3 VI = 0 V V V P00 – P07, P10 – P17 IIH Unit V “H” input current “H” input current P20 – P27 IIL Typ. P00 – P07, P10 – P17 IIH IIL Min. “H” output voltage _____ VT + – VT– Standard values Test conditions Parameter µA µA µA µA µA mA µA µA µA Notes 1 : –40 to 85 °C for extended operating temperature range version. 2 : Using P0 for key-on wake-up function. 3 : Can be indicated in resistance value as shown below: When VCC = 5 V: 5 kΩ (min.), 10 kΩ (typ.), 20 kΩ (max.). When VCC = 3 V: 8.6 kΩ (min.), 16.7 kΩ (typ.), 37.5 kΩ (max.). 59 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37481M4/M8/E8-XXXSP/FP, M37481M2T/M4T/M8T/E8T-XXXSP/FP, M37481E8SS Table 14. Electrical characteristics (cont.) Symbol VRAM Parameter RAM retention voltage Test conditions At clock stop mode In high-speed mode, f(XIN) = 4 MHz, VCC = 5 V In operating mode In high-speed mode, f(XIN) = 4 MHz, VCC = 3 V In high-speed mode, f(XIN) = 8 MHz, VCC = 5 V In medium-speed mode, f(XIN) = 4 MHz, VCC = 5 V In medium-speed mode, f(XIN) = 4 MHz, VCC = 3 V ICC Power source current In medium-speed mode, f(XIN) = 8 MHz, VCC = 5 V In wait mode In high-speed mode, f(XIN) = 4 MHz In high-speed mode, f(XIN) = 8 MHz In medium-speed mode, f(XIN) = 4 MHz In stop mode In medium-speed mode, f(XIN) = 8 MHz 60 f(XIN) = 0 VCC = 5 V Standard values Min. Typ. Max. 2 Unit V A-D conversion not executed 3.5 7 mA A-D conversion in progress 4 8 mA A-D conversion not executed 1.8 3.6 mA A-D conversion in progress 2 4 mA A-D conversion not executed 7 14 mA A-D conversion in progress 7.5 15 mA A-D conversion not executed 1.75 3.5 mA A-D conversion in progress 2 4 mA A-D conversion not executed 0.9 1.8 mA A-D conversion in progress 1 2 mA A-D conversion not executed 3.5 7 mA A-D conversion in progress 3.75 7.5 mA VCC = 5 V 1 2 VCC = 3 V 0.5 1 VCC = 5 V 2 4 VCC = 5 V 0.9 1.8 VCC = 3 V 0.45 0.9 VCC = 5 V 1.8 3.6 Ta = 25 °C 0.1 1 µA Ta = 85 °C 1 10 µA mA mA MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37481M4/M8/E8-XXXSP/FP, M37481M2T/M4T/M8T/E8T-XXXSP/FP, M37481E8SS A-D CONVERSION CHARACTERISTICS (7481 Group) (VCC = 2.7 to 5.5 V, V SS = 0 V, Ta = –20 to 85°C (Note) unless otherwise specified) Table 15. A-D conversion characteristics Symbol Parameter —— Resolution —— Absolute accuracy (except quantization error) TCONV Conversion time VVREF Reference voltage RLADDER Ladder resistance VIA Analog input voltage IVREF Reference input current Test conditions Standard values Min. Typ. VCC = VREF = 5.0 V Max. 8 bits ±2 LSB VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz 25 VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz 12.5 VCC = 2.7 to 4.0 V 2 VCC VCC = 4.0 to 5.5 V 0.5 VCC VCC 12 35 0 VREF = 5.0 V 50 143 Unit µs V 100 kΩ VREF V 416 µA Note: –40 to 85 °C for extended operating temperature range version. 61 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MASK ROM CONFIRMATION FORM Mask ROM number GZZ-SH09-84B<56A0> 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37480M2T-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued ) Date: Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37480M2T-XXXSP Microcomputer name : M37480M2T-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27128 27256 27512 EPROM address 000016 Area for ASCII EPROM address 000016 Area for ASCII EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37480M2T–’ 2FFF16 300016 000F16 001016 6FFF16 700016 ROM (4K) 3FFF16 codes of the name of the product ‘M37480M2T-’ EFFF16 F00016 ROM (4K) 7FFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480M2T–’ to addresses 000016 to 000F16. ASCII codes ‘M37480M2T–’ are listed on the right. The addresses and data are in hexadecimal notation. 62 000F16 001016 codes of the name of the product ‘M37480M2T–’ ROM (4K) FFFF16 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘M’ = 4D16 ‘2’ = 3216 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Mask ROM number GZZ-SH09-84B<56A0> 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480M2T-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27128 ✽= .BYTE $C000 ‘M37480M2T–’ 27256 ✽= $8000 .BYTE ‘M37480M2T–’ 27512 ✽= $0000 .BYTE ‘M37480M2T–’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M2T-XXXSP, 32P2W-A for M37480M2T-XXXFP) and attach to the mask ROM confirmation form. ❈ 3. Comments 63 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-85B<56A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37480M4-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued ) Date: Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37480M4-XXXSP Microcomputer name : M37480M4-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27128 27256 27512 EPROM address 000016 Area for ASCII EPROM address 000016 Area for ASCII EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37480M4–’ 1FFF16 200016 000F16 001016 5FFF16 600016 ROM (8K) 3FFF16 codes of the name of the product ‘M37480M4-’ DFFF16 E00016 ROM (8K) 7FFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480M4–’ to addresses 000016 to 000F16. ASCII codes ‘M37480M4–’ are listed on the right. The addresses and data are in hexadecimal notation. 64 000F16 001016 codes of the name of the product ‘M37480M4–’ ROM (8K) FFFF16 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-85B<56A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480M4-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type 27128 27256 27512 The pseudo-command ✽= $C000 .BYTE ‘M37480M4–’ ✽= $8000 .BYTE ‘M37480M4–’ ✽= $0000 .BYTE ‘M37480M4–’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M4-XXXSP, 32P2W-A for M37480M4-XXXFP) and attach to the mask ROM confirmation form. ❈ 3. Comments 65 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-86B<56A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37480M4T-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued ) Date: Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37480M4T-XXXSP Microcomputer name : M37480M4T-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27128 27256 27512 EPROM address 000016 Area for ASCII EPROM address 000016 Area for ASCII EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37480M4T–’ 1FFF16 200016 000F16 001016 5FFF16 600016 ROM (8K) 3FFF16 codes of the name of the product ‘M37480M4T-’ DFFF16 E00016 ROM (8K) 7FFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480M4T–’ to addresses 000016 to 000F16. ASCII codes ‘M37480M4T–’ are listed on the right. The addresses and data are in hexadecimal notation. 66 000F16 001016 codes of the name of the product ‘M37480M4T–’ ROM (8K) FFFF16 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-86B<56A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480M4T-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27128 ✽= .BYTE $C000 ‘M37480M4T–’ 27256 ✽= .BYTE $8000 ‘M37480M4T–’ 27512 ✽= .BYTE $0000 ‘M37480M4T–’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M4T-XXXSP, 32P2W-A for M37480M4T-XXXFP) and attach to the mask ROM confirmation form. ❈ 3. Comments 67 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-87B<56A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37480M8-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37480M8-XXXSP Microcomputer name : M37480M8-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27256 EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37480M8–’ 3FFF16 400016 27512 EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016 ROM (16K) 7FFF16 codes of the name of the product ‘M37480M8–’ ROM (16K) FFFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480M8–’ to addresses 000016 to 000F16. ASCII codes ‘M37480M8–’ are listed on the right. The addresses and data are in hexadecimal notation. 68 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-87B<56A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480M8-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the assembler source file : EPROM type 27256 27512 The pseudo-command ✽= $8000 .BYTE ‘M37480M8-’ ✽= $0000 .BYTE ‘M37480M8-’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M8-XXXSP, 32P2W-A for M37480M8-XXXFP) and attach to the mask ROM confirmation form. ❈ 3. Comments 69 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-88B<56A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37480M8T-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37480M8T-XXXSP Microcomputer name : M37480M8T-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27256 EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37480M8T–’ 3FFF16 400016 27512 EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016 ROM (16K) 7FFF16 codes of the name of the product ‘M37480M8T–’ ROM (16K) FFFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480M8T–’ to addresses 000016 to 000F16. ASCII codes ‘M37480M8T–’ are listed on the right. The addresses and data are in hexadecimal notation. 70 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-88B<56A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480M8T-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the assembler source file : EPROM type The pseudo-command 27256 ✽= .BYTE $8000 ‘M37480M8T-’ 27512 ✽= .BYTE $0000 ‘M37480M8T-’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M8T-XXXSP, 32P2W-A for M37480M8T-XXXFP) and attach to the mask ROM confirmation form. ❈ 3. Comments 71 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Mask ROM number GZZ-SH09-78B<56A0> 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37481M2T-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued ) Date: Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37481M2T-XXXSP Microcomputer name : M37481M2T-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27128 27256 27512 EPROM address 000016 Area for ASCII EPROM address 000016 Area for ASCII EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37481M2T–’ 2FFF16 300016 000F16 001016 6FFF16 700016 ROM (4K) 3FFF16 codes of the name of the product ‘M37481M2T-’ EFFF16 F00016 ROM (4K) 7FFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481M2T–’ to addresses 000016 to 000F16. ASCII codes ‘M37481M2T–’ are listed on the right. The addresses and data are in hexadecimal notation. 72 000F16 001016 codes of the name of the product ‘M37481M2T–’ ROM (4K) FFFF16 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘M’ = 4D16 ‘2’ = 3216 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Mask ROM number GZZ-SH09-78B<56A0> 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481M2T-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27128 ✽= .BYTE $C000 ‘M37481M2T–’ 27256 ✽= .BYTE $8000 ‘M37481M2T–’ 27512 ✽= .BYTE $0000 ‘M37481M2T–’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M2T-XXXSP, 44P6N-A for M37481M2T-XXXFP) and attach to the mask ROM confirmation form. ❈ 3. Comments 73 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Mask ROM number GZZ-SH09-79B<56A0> 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37481M4-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued ) Date: Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37481M4-XXXSP Microcomputer name : M37481M4-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27128 27256 27512 EPROM address 000016 Area for ASCII EPROM address 000016 Area for ASCII EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37481M4–’ 1FFF16 200016 000F16 001016 5FFF16 600016 ROM (8K) 3FFF16 codes of the name of the product ‘M37481M4-’ DFFF16 E00016 ROM (8K) 7FFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481M4–’ to addresses 000016 to 000F16. ASCII codes ‘M37481M4–’ are listed on the right. The addresses and data are in hexadecimal notation. 74 000F16 001016 codes of the name of the product ‘M37481M4–’ ROM (8K) FFFF16 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Mask ROM number GZZ-SH09-79B<56A0> 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481M4-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type 27128 27256 27512 The pseudo-command ✽= $C000 .BYTE ‘M37481M4–’ ✽= $8000 .BYTE ‘M37481M4–’ ✽= $0000 .BYTE ‘M37481M4–’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M4-XXXSP, 44P6N-A for M37481M4-XXXFP) and attach to the mask ROM confirmation form. ❈ 3. Comments 75 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Mask ROM number GZZ-SH09-80B<56A0> 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37481M4T-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued ) Date: Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37481M4T-XXXSP Microcomputer name : M37481M4T-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27128 27256 27512 EPROM address 000016 Area for ASCII EPROM address 000016 Area for ASCII EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37481M4T–’ 1FFF16 200016 000F16 001016 5FFF16 600016 ROM (8K) 3FFF16 codes of the name of the product ‘M37481M4T-’ DFFF16 E00016 ROM (8K) 7FFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481M4T–’ to addresses 000016 to 000F16. ASCII codes ‘M37481M4T–’ are listed on the right. The addresses and data are in hexadecimal notation. 76 000F16 001016 codes of the name of the product ‘M37481M4T–’ ROM (8K) FFFF16 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘M’ = 4D16 ‘4’ = 3416 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Mask ROM number GZZ-SH09-80B<56A0> 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481M4T-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27128 ✽= .BYTE $C000 ‘M37481M4T–’ 27256 ✽= .BYTE $8000 ‘M37481M4T–’ 27512 ✽= .BYTE $0000 ‘M37481M4T–’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M4T-XXXSP, 44P6N-A for M37481M4T-XXXFP) and attach to the mask ROM confirmation form. ❈ 3. Comments 77 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-81B<56A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37481M8-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37481M8-XXXSP Microcomputer name : M37481M8-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27256 EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37481M8–’ 3FFF16 400016 27512 EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016 ROM (16K) 7FFF16 codes of the name of the product ‘M37481M8–’ ROM (16K) FFFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481M8–’ to addresses 000016 to 000F16. ASCII codes ‘M37481M8–’ are listed on the right. The addresses and data are in hexadecimal notation. 78 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-81B<56A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481M8-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the assembler source file : EPROM type 27256 27512 The pseudo-command ✽= $8000 .BYTE ‘M37481M8-’ ✽= $0000 .BYTE ‘M37481M8-’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M8-XXXSP, 44P6N-A for M37481M8-XXXFP) and attach to the mask ROM confirmation form. ❈ 3. Comments 79 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-82B<56A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37481M8T-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37481M8T-XXXSP Microcomputer name : M37481M8T-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27256 EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37481M8T–’ 3FFF16 400016 27512 EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016 ROM (16K) 7FFF16 codes of the name of the product ‘M37481M8T–’ ROM (16K) FFFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481M8T–’ to addresses 000016 to 000F16. ASCII codes ‘M37481M8T–’ are listed on the right. The addresses and data are in hexadecimal notation. 80 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘M’ = 4D16 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-82B<56A0> Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481M8T-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the assembler source file : EPROM type 27256 27512 The pseudo-command ✽= $8000 .BYTE ‘M37481M8T-’ ✽= $0000 .BYTE ‘M37481M8T-’ Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M8T-XXXSP, 44P6N-A for M37481M8T-XXXFP) and attach to the mask ROM confirmation form. ❈ 3. Comments 81 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP e. n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ROM PROGRAMMING CONFIRMATION FORM GZZ-SH09-91B<56A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37480E8-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37480E8-XXXSP Microcomputer name : M37480E8-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27256 EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37480E8–’ 3FFF16 400016 27512 EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016 ROM (16K) 7FFF16 codes of the name of the product ‘M37480E8–’ ROM (16K) FFFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480E8–’ to addresses 000016 to 000F16. ASCII codes ‘M37480E8–’ are listed on the right. The addresses and data are in hexadecimal notation. 82 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘E’ = 4516 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-91B<56A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480E8-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the assembler source file : EPROM type 27256 27512 The pseudo-command ✽= $8000 .BYTE ‘M37480E8-’ ✽= $0000 .BYTE ‘M37480E8-’ Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37480E8-XXXSP or the 32P2W-A Mark Specification Form for the M37480E8-XXXFP. ❈ 3. Comments 83 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-92B<56A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37480E8T-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37480E8T-XXXSP Microcomputer name : M37480E8T-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27256 EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37480E8T–’ 3FFF16 400016 27512 EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016 ROM (16K) 7FFF16 codes of the name of the product ‘M37480E8T–’ ROM (16K) FFFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37480E8T–’ to addresses 000016 to 000F16. ASCII codes ‘M37480E8T–’ are listed on the right. The addresses and data are in hexadecimal notation. 84 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘0’ = 3016 ‘E’ = 4516 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-92B<56A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480E8T-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the assembler source file : EPROM type The pseudo-command 27256 ✽= .BYTE $8000 ‘M37480E8T-’ 27512 ✽= .BYTE $0000 ‘M37480E8T-’ Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37480E8T-XXXSP or the 32P2W-A Mark Specification Form for the M37480E8T-XXXFP. ❈ 3. Comments 85 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-89B<56A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37481E8-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37481E8-XXXSP Microcomputer name : M37481E8-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27256 EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37481E8–’ 3FFF16 400016 27512 EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016 ROM (16K) 7FFF16 codes of the name of the product ‘M37481E8–’ ROM (16K) FFFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481E8–’ to addresses 000016 to 000F16. ASCII codes ‘M37481E8–’ are listed on the right. The addresses and data are in hexadecimal notation. 86 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘E’ = 4516 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-89B<56A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481E8-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the assembler source file : EPROM type 27256 27512 The pseudo-command ✽= $8000 .BYTE ‘M37481E8-’ ✽= $0000 .BYTE ‘M37481E8-’ Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37481E8-XXXSP or the 44P6N-A Mark Specification Form for the M37481E8-XXXFP. ❈ 3. Comments 87 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-90B<56A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM Receipt SINGLE-CHIP MICROCOMPUTER M37481E8T-XXXSP/FP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature ❈ Customer TEL ( Company name Date issued Date: ) Issuance signature Note : Please fill in all items marked ❈. Submitted by Supervisor ❈ 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. M37481E8T-XXXSP Microcomputer name : M37481E8T-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27256 EPROM address 000016 Area for ASCII 000F16 001016 codes of the name of the product ‘M37481E8T–’ 3FFF16 400016 27512 EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016 ROM (16K) 7FFF16 codes of the name of the product ‘M37481E8T–’ ROM (16K) FFFF16 (1) Set “FF16” in the shaded area. (2) Write the ASCII codes that indicates the name of the product ‘M37481E8T–’ to addresses 000016 to 000F16. ASCII codes ‘M37481E8T–’ are listed on the right. The addresses and data are in hexadecimal notation. 88 Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = 4D16 ‘3’ = 3316 ‘7’ = 3716 ‘4’ = 3416 ‘8’ = 3816 ‘1’ = 3116 ‘E’ = 4516 ‘8’ = 3816 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘ T ’ = 5416 ‘ – ’ = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GZZ-SH09-90B<56A0> ROM number 740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481E8T-XXXSP/FP MITSUBISHI ELECTRIC Recommend to writing the following pseudo-command to the assembler source file : EPROM type 27256 27512 The pseudo-command ✽= $8000 .BYTE ‘M37481E8T-’ ✽= $0000 .BYTE ‘M37481E8T-’ Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM processing is disabled. Write the data correctly. ❈ 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37481E8T-XXXSP or the 44P6N-A Mark Specification Form for the M37481E8T-XXXFP. ❈ 3. Comments 89 MITSUBISHI MICROCOMPUTERS A IMIN RY . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L PACKAGE OUTLINE 32P2W–A 32P4B 90 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS A IMIN RY . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 42P4B 44P6N–A 91 MITSUBISHI MICROCOMPUTERS A IMIN RY . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MARK SPECIFICATION FORM 32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM 92 MITSUBISHI MICROCOMPUTERS A IMIN RY . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 32P2W (32-PIN SOP) MARK SPECIFICATION FORM 93 MITSUBISHI MICROCOMPUTERS A IMIN RY . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 42P4B (42-PIN SHRINK DIP) MARK SPECIFICATION FORM 94 MITSUBISHI MICROCOMPUTERS A IMIN RY 7480/7481 GROUP . . tion hange c ifica pec ject to s l a b a fin are su not s is is ric limit h T t me ice: Not e para Som PRE L SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 44P6N (44-PIN QFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark #3 @3 #4 @2 Mitsubishi lot number (6-digit) $4 Mitsubishi IC catalog name !2 q !1 B. Customer’s Parts Number + Mitsubishi Catalog Name #3 @3 #4 @2 Customer’s parts number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name and Mitsubishi lot number $4 !2 q Note4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required. !1 Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s parts number can be up to 7 characters : Only 0 ~ 9, A ~ Z,+,–, ⁄ , (, ), &, ©, • (period), and (comma) are usable. , C. Special Mark Required #3 @3 #4 @2 $4 !2 q Note1 : If the special mark is to be printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit ) and mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the special mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required !1 3 : The standard Mitsubishi font is used for all characters except for a logo. 95 MITSUBISHI MICROCOMPUTERS A IMIN RY . e n. atio chang cific o spe bject t l a fin su ot a its are is n m This etric li : e m ic Not e para Som PRE L 7480/7481 GROUP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Notes regarding these materials • • • • • • © 1997 MITSUBISHI ELECTRIC CORP. KI-9711 Printed in Japan (ROD) II New publication, effective Nov. 1997. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 7480/7481 GROUP DATA SHEET Revision Description First Edition Rev. date 971130 (1/1)