LINER LT1506IS8-3.3 4.5a, 500khz step-down switching regulator Datasheet

LT1506
4.5A, 500kHz Step-Down
Switching Regulator
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DESCRIPTION
FEATURES
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■
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■
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The LT ®1506 is a 500kHz monolithic buck mode switching
regulator functionally identical to the LT1374 but optimized
for lower input voltage applications. It will operate over a
4V to 15V input range compared with 5.5V to 25V for the
LT1374. A 4.5A switch is included on the die along with all
the necessary oscillator, control and logic circuitry. High
switching frequency allows a considerable reduction in the
size of external components. The topology is current mode
for fast transient response and good loop stability. Both
fixed output voltage and adjustable parts are available.
Constant 500kHz Switching Frequency
Easily Synchronizable
Operates with Input as Low as 4V
Uses All Surface Mount Components
Inductor Size Reduced to 1.8µH
Saturating Switch Design: 0.07Ω
Shutdown Current: 20µA
Cycle-by-Cycle Current Limiting
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APPLICATIONS
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A special high speed bipolar process and new design techniques achieve high efficiency at high switching frequency.
Efficiency is maintained over a wide output current range
by keeping quiescent supply current to 4mA and by utilizing a supply boost capacitor to saturate the power switch.
Portable Computers
Battery-Powered Systems
Battery Charger
Distributed Power
The LT1506 fits into standard 7-pin DD and fused lead
SO-8 packages. Full cycle-by-cycle short-circuit protection
and thermal shutdown are provided. Standard surface
mount external parts are used, including the inductor and
capacitors. There is the optional function of shutdown or
synchronization. A shutdown signal reduces supply current
to 20µA. Synchronization allows an external logic level signal to increase the internal oscillator from 580kHz to 1MHz.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
Efficiency vs Load Current
90
5V to 3.3V Down Converter
VOUT = 3.3V
VIN = 5V
L = 10µH
D2
1N914
C2
0.68µF
INPUT
5V
C3
10µF TO
50µF
CERAMIC
L1
5µH
BOOST
VIN
+
OPEN
OR
HIGH
= ON
OUTPUT
3.3V
4A
VSW
LT1506-3.3
SHDN
GND
EFFICIENCY (%)
85
80
75
SENSE
VC
+
CC
1.5nF
D1
MBRS330T3
C1
100µF, 10V
SOLID
TANTALUM
1506 TA01
70
0
0.5
1.0
1.5 2.0 2.5 3.0
LOAD CURRENT (A)
3.5
4.0
1506 TA02
1
LT1506
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ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Voltage .......................................................... 16V
BOOST Pin Above Input Voltage ............................. 15V
SHDN Pin Voltage ..................................................... 7V
FB Pin Voltage (Adjustable Part) ............................ 3.5V
FB Pin Current (Adjustable Part) ............................ 1mA
Sense Voltage (Fixed 3.3V Part) ............................... 5V
SYNC Pin Voltage ..................................................... 7V
Operating Junction Temperature Range
LT1506C ............................................... 0°C to 125° C
LT1506I ........................................... – 40°C to 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER INFORMATION
FRONT VIEW
TAB
IS
GND
7
6
5
4
3
2
1
FB OR SENSE*
BOOST
VIN
GND
VSW
SYNC OR SHDN*
VC
R PACKAGE
7-LEAD PLASTIC DD PAK
TJMAX = 125°C, θJA = 30°C/W
WITH PACKAGE SOLDERED TO 0.5 SQUARE INCH
COPPER AREA OVER BACKSIDE GROUND PLANE OR
INTERNAL POWER PLANE. θJA CAN VARY FROM 20°C/W
TO > 40°C/W DEPENDING ON MOUNTING TECHNIQUES
ORDER PART
NUMBER
LT1506CR
LT1506CR-3.3
LT1506CR-SYNC
LT1506CR-3.3 SYNC
LT1506IR
LT1506IR-3.3
LT1506IR-SYNC
LT1506IR-3.3 SYNC
ORDER PART
NUMBER
TOP VIEW
VIN 1
BOOST 2
FB OR
3
SENSE*
GND** 4
8 VSW
LT1506CS8
LT1506CS8-3.3
LT1506IS8
LT1506IS8-3.3
7 SYNC
6 SHDN
5 VC
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PART MARKING
θJA = 80°C/ W
**WITH FUSED (GND) GROUND PIN
CONNECTED TO GROUND PLANE OR
LARGE LANDS
1506
150633
1506I
506I33
*Default is the adjustable output voltage device with FB pin and shutdown function. Option -3.3 replaces FB with SENSE pin for fixed 3.3V output
applications. -SYNC replaces SHDN with SYNC pin for applications requiring synchronization. Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
TJ = 25°C, VIN = 5V, VC = 1.5V, Boost = VIN + 5V, switch open, unless otherwise noted.
PARAMETER
Feedback Voltage (Adjustable)
CONDITIONS
All Conditions
●
All Conditions
●
Sense Voltage (Fixed 3.3V)
SENSE Pin Resistance
Reference Voltage Line Regulation
Feedback Input Bias Current
Error Amplifier Voltage Gain
Error Amplifier Transconductance
4.3V ≤ VIN ≤ 15V
●
(Notes 2, 8)
∆I (VC) = ±10µA (Note 8)
●
VC Pin to Switch Current Transconductance
Error Amplifier Source Current
Error Amplifier Sink Current
VC Pin Switching Threshold
VC Pin High Clamp
Switch Current Limit
Slope Compensation
2
MIN
2.39
2.36
3.25
3.23
4
200
1500
1000
VFB = 2.1V or VSENSE = 2.9V
VFB = 2.7V or VSENSE = 3.7V
Duty Cycle = 0
●
●
140
140
VC Open, VFB = 2.1V or VSENSE = 2.9V, DC ≤ 50%
DC = 80%
●
4.5
TYP
2.42
3.3
6.6
0.01
0.5
400
2000
5.3
225
225
0.9
2.1
6
0.8
MAX
2.45
2.48
3.35
3.37
9.5
0.03
2
UNITS
V
V
V
V
kΩ
%/ V
µA
2700
3100
µMho
µMho
A/ V
µA
µA
V
V
A
A
320
320
8.5
LT1506
ELECTRICAL CHARACTERISTICS
TJ = 25°C, VIN = 5V, VC = 1.5V, Boost = VIN + 5V, switch open, unless otherwise noted.
PARAMETER
Switch On Resistance (Note 7)
CONDITIONS
ISW = 4.5A
Maximum Switch Duty Cycle
VFB = 2.1V or VSENSE = 2.9V
MIN
TYP
0.07
90
86
460
440
93
93
500
●
●
Switch Frequency
VC Set to Give 50% Duty Cycle
●
Switch Frequency Line Regulation
Frequency Shifting Threshold on FB Pin
Minimum Input Voltage (Note 3)
Minimum Boost Voltage (Note 4)
Boost Current (Note 5)
Input Supply Current (Note 6)
Shutdown Supply Current
4.3V ≤ VIN ≤ 15V
∆f = 10kHz
●
●
0.8
●
ISW ≤ 4.5A
ISW = 1A
ISW = 4.5A
●
●
●
●
VSHDN = 0V, VSW = 0V, VC Open
0
1.0
4.0
2.3
20
90
3.8
15
●
Lockout Threshold
Shutdown Thresholds
VC Open
VC Open Device Shutting Down
Device Starting Up
Synchronization Threshold
Synchronizing Range
SYNC Pin Input Resistance
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Gain is measured with a VC swing equal to 200mV above the
switching threshold level to 200mV below the upper clamp level.
Note 3: Minimum input voltage is not measured directly, but is guaranteed
by other tests. It is defined as the voltage where internal bias lines are still
regulated so that the reference voltage and oscillator frequency remain
constant. Actual minimum input voltage to maintain a regulated output will
depend on output voltage and load current. See Applications Information.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
●
●
●
2.3
0.13
0.25
●
2.38
0.37
0.45
1.5
580
40
MAX
0.1
0.13
540
560
0.15
1.3
4.3
3.0
35
140
5.4
50
75
2.46
0.60
0.7
2.2
1000
UNITS
Ω
Ω
%
%
kHz
kHz
%/ V
V
V
V
mA
mA
mA
µA
µA
V
V
V
V
kHz
kΩ
Note 5: Boost current is the current flowing into the boost pin with the pin
held 5V above input voltage. It flows only during switch on time.
Note 6: Input supply current is the bias current drawn by the input pin
with switching disabled.
Note 7: Switch on resistance is calculated by dividing VIN to VSW voltage
by the forced current (4.5A). See Typical Performance Characteristics for
the graph of switch voltage at other currents.
Note 8: Transconductance and voltage gain refer to the internal amplifier
exclusive of the voltage divider. To calculate gain and transconductance
refer to SENSE pin on fixed voltage parts. Divide values shown by the ratio
VOUT/2.42.
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LT1506
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TYPICAL PERFORMANCE CHARACTERISTICS
Feedback Pin Voltage
Switch Peak Current Limit
4.7
6.5
4.5
6.0
4.3
4.1
3.9
3.7
3.5
2.430
TYPICAL
5.5
5.0
MINIMUM
4.5
4.0
3.0
10
100
LOAD CURRENT (mA)
1
1000
0
20
60
40
DUTY CYCLE (%)
80
2.420
2.415
2.410
– 50
100
0
25
50
75
1506 G03
Lockout and Shutdown
Thresholds
–500
125
100
1506 G02
Shutdown Pin Bias Current
Shutdown Supply Current
25
2.40
VSHDN = 0V
AT 0.37V SHUTDOWN THRESHOLD.
AFTER SHUTDOWN, CURRENT
DROPS TO A FEW µA
LOCKOUT
– 300
– 200
–8
AT 2.38V LOCKOUT THRESHOLD
–4
20
INPUT SUPPLY CURRENT (µA)
SHUTDOWN PIN VOLTAGE (V)
– 400
–25
TEMPERATURE (°C)
1506 G12
CURRENT (µA)
2.425
3.5
3.3
2.36
2.32
0.8
START-UP
0.4
15
10
5
SHUTDOWN
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
0
125
Error Amplifier Transconductance
2500
3000
2000
2500
VIN = 10V
30
20
PHASE
GAIN (µMho)
40
200
1500
1000
500
150
GAIN
2000
100
VC
(
)
ROUT
200k
COUT
12pF
1500
VFB 2 × 10–3
1000
ERROR AMPLIFIER EQUIVALENT CIRCUIT
50
0
10
RLOAD = 50Ω
0
0
0.1
0.2
0.3
SHUTDOWN VOLTAGE (V)
0.4
1506 G07
4
0
50
0
75 100
25
–50 –25
JUNCTION TEMPERATURE (°C)
125
1506 G08
500
100
1k
10k
100k
FREQUENCY (Hz)
1M
–50
10M
1506 G09
PHASE (DEG)
TRANSCONDUCTANCE (µMho)
50
15
1506 G06
Error Amplifier Transconductance
60
5
10
INPUT VOLTAGE (V)
1506 G05
Shutdown Supply Current
70
0
0
50
100
25
75
–50 –25
0
JUNCTION TEMPERATURE (°C)
125
1506 G04
INPUT SUPPLY CURRENT (µA)
FEEDBACK VOLTAGE (V)
SWITCH PEAK CURRENT (A)
INPUT VOLTAGE (V)
Minimum Input Voltage
with 3.3V Output
LT1506
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TYPICAL PERFORMANCE CHARACTERISTICS
Inductor Core Loss for 3.3V Output
Switching Frequency
550
500
1.0
540
530
SWITCHING
FREQUENCY
300
200
520
CORE LOSS (W)
400
FREQUENCY (kHz)
510
500
490
480
FEEDBACK PIN
CURRENT
Kool Mµ®
0.01
450
– 50
0
0
0.5
1.5
2.0
1.0
FEEDBACK PIN VOLTAGE (V)
2.5
–25
0
25
50
75
100
125
0.001
0
L= 10µH
L= 5µH
LOAD CURRENT (A)
3.4
3.2
4.0
L= 3µH
3.8
3.6
3.4
L= 1.8µH
L= 1.8µH
3.2
2.8
5
7
11
9
INPUT VOLTAGE (V)
8
10
20
0
1
MOS LOAD
500
SHUTDOWN
450
1.2
125°C
400
SWITCH VOLTAGE (mV)
2
5
Switch Voltage Drop
1.4
THRESHOLD VOLTAGE (V)
3
3
2
4
SWITCH CURRENT (A)
1506 G14
VC Pin Shutdown Threshold
POSSIBLE UNDESIRED
CURRENT
STABLE POINT FOR
SOURCE
CURRENT SOURCE
LOAD
LOAD*
RESISTOR
LOAD
4
30
1506 G13
FOLDBACK
CHARACTERISTICS
5
40
INPUT VOLTAGE (V)
Current Limit Foldback
6
50
14
12
1506 G17
7
70
60
0
6
4
15
13
80
10
3.0
2.6
DUTY CYCLE = 100%
90
4.2
L= 5µH
L= 3µH
10
BOOST Pin Current
100
L= 10µH
4.2
3.6
8
1506 G01
4.4
3.8
4
6
INDUCTANCE (µH)
1506 G11
4.4
4.0
2
TEMPERATURE (°C)
Maximum Load Current
at VOUT = 3.3V
3.0
Metglas®
460
Maximum Load Current
at VOUT = 5V
LOAD CURRENT (A)
TYPE 52
PERMALLOY
µ = 125
1506 G10
OUTPUT CURRENT (A)
0.1
470
100
BOOST PIN CURRENT (mA)
SWITCHING FREQUENCY (kHz) OR CURRENT (µA)
Frequency Foldback
1.0
0.8
0.6
350
25°C
300
250
– 40°C
200
150
100
1
50
0
0
20
40
60
80
100
0.4
–50
OUTPUT VOLTAGE (%)
1506 G18
0
–25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
125
1506 G15
0
1
2
4
3
SWITCH CURRENT (A)
5
1506 G16
Kool Mµ is a registered trademark of Magnetics, Inc.
Metglas is a registered trademark of AlliedSignal Inc.
*See “More Than Just Voltage Feedback” in the Applications Information section.
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LT1506
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PIN FUNCTIONS
FB/SENSE: The feedback pin is used to set output voltage
using an external voltage divider that generates 2.42V at
the pin with the desired output voltage. The fixed voltage
(-3.3) parts have the divider included on the chip and the
FB pin is used as a SENSE pin, connected directly to the
3.3V output. Three additional functions are performed by
the FB pin. When the pin voltage drops below 1.7V, switch
current limit is reduced. Below 1.5V the external sync
function is disabled. Below 1V, switching frequency is also
reduced. See Feedback Pin Function section in Applications Information for details.
BOOST: The BOOST pin is used to provide a drive voltage,
higher than the input voltage, to the internal bipolar NPN
power switch. Without this added voltage, the typical
switch voltage loss would be about 1.5V. The additional
boost voltage allows the switch to saturate and voltage
loss approximates that of a 0.07Ω FET structure, but with
much smaller die area. Efficiency improves from 75% for
conventional bipolar designs to > 89% for these new parts.
VIN: This is the collector of the on-chip power NPN switch.
This pin powers the internal circuitry and internal regulator. At NPN switch on and off, high dI/dt edges occur on
this pin. Keep the external bypass and catch diode close to
this pin. All trace inductance on this path will create a
voltage spike at switch off, adding to the VCE voltage
across the internal NPN.
GND: The GND pin connection needs consideration for
two reasons. First, it acts as the reference for the regulated
output, so load regulation will suffer if the “ground” end of
the load is not at the same voltage as the GND pin of the
IC. This condition will occur when load current or other
currents flow through metal paths between the GND pin
and the load ground point. Keep the ground path short
between the GND pin and the load and use a ground plane
when possible. The second consideration is EMI caused
by GND pin current spikes. Internal capacitance between
the VSW pin and the GND pin creates very narrow (<10ns)
6
current spikes in the GND pin. If the GND pin is connected
to system ground with a long metal trace, this trace may
radiate excess EMI. Keep the path between the input
bypass and the GND pin short. The GND pin of the SO-8
package is directly attached to the internal tab. This pin
should be attached to a large copper area to improve
thermal resistance.
VSW: The switch pin is the emitter of the on-chip power
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the switch
pin negative during switch off time. Negative voltage is
clamped with the external catch diode. Maximum negative
switch voltage allowed is – 0.8V.
SYNC: The sync pin is used to synchronize the internal
oscillator to an external signal. It is directly logic compatible and can be driven with any signal between 10% and
90% duty cycle. The synchronizing range is equal to initial
operating frequency, up to 1MHz. This pin replaces SHDN
on -SYNC option parts. See Synchronizing section in
Applications Information for details. When not in use, this
pin should be grounded.
SHDN: The shutdown pin is used to turn off the regulator
and to reduce input drain current to a few microamperes.
Actually, this pin has two separate thresholds, one at
2.38V to disable switching, and a second at 0.4V to force
complete micropower shutdown. The 2.38V threshold
functions as an accurate undervoltage lockout (UVLO).
This is sometimes used to prevent the regulator from
operating until the input votlage has reached a predetermined level.
VC: The VC pin is the output of the error amplifier and the
input of the peak switch current comparator. It is normally
used for frequency compensation, but can do double duty
as a current clamp or control loop override. This pin sits
at about 1V for very light loads and 2V at maximum load.
It can be driven to ground to shut off the regulator, but if
driven high, current must be limited to 4mA.
LT1506
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BLOCK DIAGRAM
The LT1506 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
two feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS flip-flop to turn the switch on.
When switch current reaches a level set by the inverting
input of the comparator, the flip-flop is reset and the
switch turns off. Output voltage control is obtained by
using the output of the error amplifier to set the switch
current trip point. This technique means that the error
amplifier commands current to be delivered to the output
rather than voltage. A voltage fed system will have low
phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180° shift will occur.
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes
it much easier to frequency compensate the feedback loop
and also gives much quicker transient response.
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external capacitor and diode. Two comparators are connected to the
shutdown pin. One has a 2.38V threshold for undervoltage
lockout and the second has a 0.4V threshold for complete
shutdown.
0.01Ω
INPUT
+
2.9V BIAS
REGULATOR
–
CURRENT
SENSE
AMPLIFIER
VOLTAGE GAIN = 20
INTERNAL
VCC
SLOPE COMP
Σ
BOOST
0.9V
500kHz
OSCILLATOR
SYNC
S
CURRENT
COMPARATOR
SHUTDOWN
COMPARATOR
+
DRIVER
CIRCUITRY
RS
FLIP-FLOP
R
–
Q1
POWER
SWITCH
VSW
0.4V
PARASITIC DIODES
DO NOT FORWARD BIAS
FREQUENCY
SHIFT CIRCUIT
SHDN
3.5µA
FOLDBACK
CURRENT
LIMIT
CLAMP
Q2
–
2.38V
VC
ERROR
AMPLIFIER
gm = 2000µMho
+
LOCKOUT
COMPARATOR
FB
2.42V
GND
1506 BD
Figure 1. Block Diagram
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LT1506
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APPLICATIONS INFORMATION
FEEDBACK PIN FUNCTIONS
More Than Just Voltage Feedback
The feedback (FB) pin on the LT1506 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a final
design. The fixed 3.3V LT1506-3.3 has internal divider
resistors and the FB pin is renamed SENSE, connected
directly to the output.
The feedback pin is used for more than just output voltage
sensing. It also reduces switching frequency and current
limit when output voltage is very low (see the Frequency
Foldback graph in Typical Performance Characteristics).
This is done to control power dissipation in both the IC and
in the external diode and inductor during short-circuit
conditions. A shorted output requires the switching regulator to operate at very low duty cycles, and the average
current through the diode and inductor is equal to the
short-circuit current limit of the switch (typically 6A for the
LT1506, folding back to less than 3A). Minimum switch on
time limitations would prevent the switcher from attaining
a sufficiently low duty cycle if switching frequency were
maintained at 500kHz, so frequency is reduced by about
5:1 when the feedback pin voltage drops below 1V (see
Frequency Foldback graph). This does not affect operation
with normal load conditions; one simply sees a gear shift
in switching frequency during start-up as the output
voltage rises.
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. Please read the following
if divider resistors are increased above the suggested
values.
R1 =
LT1506
(
)
R2 VOUT − 2.42
2.42
VSW
TO FREQUENCY
SHIFTING
1.6V
OUTPUT
5V
Q1
ERROR
AMPLIFIER
+
R1
2.4V
–
R3
1k
R4
1k
FB
+
R5
5k
Q2
R2
5k
TO SYNC CIRCUIT
1506 F02
VC
GND
Figure 2. Frequency and Current Limit Foldback
8
In addition to lower switching frequency, the LT1506 also
operates at lower switch current limit when the feedback
pin voltage drops below 1.7V. Q2 in Figure 2 performs this
function by clamping the VC pin to a voltage less than its
normal 2.1V upper clamp level. This foldback current limit
greatly reduces power dissipation in the IC, diode and
inductor during short-circuit conditions. External synchronization is also disabled to prevent interference with
foldback operation. Again, it is nearly transparent to the
user under normal load conditions. The only loads that may
be affected are current source loads which maintain full
load current with output voltage less than 50% of final value.
In these rare situations the feedback pin can be clamped
above 1.5V with an external diode to defeat foldback current limit. Caution: clamping the feedback pin means that
frequency shifting will also be defeated, so a combination
of high input voltage and dead shorted output may cause
the LT1506 to lose control of current limit.
LT1506
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APPLICATIONS INFORMATION
The internal circuitry which forces reduced switching
frequency also causes current to flow out of the feedback
pin when output voltage is low. The equivalent circuitry is
shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 1V, Q1 begins to
conduct current and reduces frequency at the rate of
approximately 5kHz/µA. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance must be low enough
to pull 150µA out of the FB pin with 0.6V on the pin (RDIV
≤ 4k). The net result is that reductions in frequency and
current limit are affected by output voltage divider impedance. Although divider impedance is not critical, caution
should be used if resistors are increased beyond the
suggested values and short-circuit conditions will occur
with high input voltage. High frequency pickup will
increase and the protection accorded by frequency and
current foldback will decrease.
MAXIMUM OUTPUT LOAD CURRENT
Maximum load current for a buck converter is limited by
the maximum switch current rating (IP) of the LT1506.
This current rating is 4.5A up to 50% duty cycle (DC),
decreasing to 3.7A at 80% duty cycle. This is shown
graphically in Typical Performance Characteristics and as
shown in the formula below:
IP = 4.5A for DC ≤ 50%
IP = 3.21 + 5.95(DC) – 6.75(DC)2 for 50% < DC < 90%
DC = Duty cycle = VOUT/VIN
Example: with VOUT = 5V, VIN = 8V; DC = 5/8 = 0.625, and;
ISW(MAX) = 3.21 + 5.95(0.625) – 6.75(0.625)2 = 4.3A
Current rating decreases with duty cycle because the
LT1506 has internal slope compensation to prevent current mode subharmonic switching. For more details, read
Application Note 19. The LT1506 is a little unusual in this
regard because it has nonlinear slope compensation which
gives better compensation with less reduction in current
limit.
finite inductor size, maximum load current is reduced by
one-half peak-to-peak inductor current. The following
formula assumes continuous mode operation, implying
that the term on the right is less than one-half of IP.
IOUT(MAX) =
IP −
Continuous Mode
(V )(V − V )
2(L)(f)(V )
OUT
IN
OUT
IN
For the conditions above and L = 3.3µH,
IOUT (MAX ) = 4.3 −
(5)(8 − 5)
()
2 3.3 • 10 − 6  500 • 10 3  8
= 4.3 − 0.57 = 3.73 A
At VIN = 15V, duty cycle is 33%, so IP is just equal to a fixed
4.5A, and IOUT(MAX) is equal to:
4.5 −
(5)(15 − 5)
( )
2 3.3 • 10 − 6  500 • 10 3  15
= 4.5 − 1.01 = 3.49 A
Note that there is less load current available at the higher
input voltage because inductor ripple current increases.
This is not always the case. Certain combinations of
inductor value and input voltage range may yield lower
available load current at the lowest input voltage due to
reduced peak switch current at high duty cycles. If load
current is close to the maximum available, please check
maximum available current at both input voltage extremes. To calculate actual peak switch current with a
given set of conditions, use:
ISW(PEAK ) = IOUT +
(
)
2(L)(f)(V )
VOUT VIN − VOUT
IN
Maximum load current would be equal to maximum
switch current for an infinitely large inductor, but with
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CHOOSING THE INDUCTOR AND OUTPUT CAPACITOR
For most applications the output inductor will fall in the
range of 3µH to 20µH. Lower values are chosen to reduce
physical size of the inductor. Higher values allow more
output current because they reduce peak current seen by
the LT1506 switch, which has a 4.5A limit. Higher values
also reduce output ripple voltage, and reduce core loss.
Graphs in the Typical Performance Characteristics section
show maximum output load current versus inductor size
and input voltage. A second graph shows core loss versus
inductor size for various core materials.
When choosing an inductor you might have to consider
maximum load current, core and copper losses, allowable
component height, output voltage ripple, EMI, fault current in the inductor, saturation, and of course, cost. The
following procedure is suggested as a way of handling
these somewhat complicated and conflicting requirements.
1. Choose a value in microhenries from the graphs of
maximum load current and core loss. Choosing a small
inductor with lighter loads may result in discontinuous
mode of operation, but the LT1506 is designed to work
well in either mode. Keep in mind that lower core loss
means higher cost, at least for closed core geometries
like toroids. The core loss graphs show absolute loss
for a 3.3V output, so actual percent losses must be
calculated for each situation.
Assume that the average inductor current is equal to
load current and decide whether or not the inductor
must withstand continuous fault conditions. If maximum load current is 0.5A, for instance, a 0.5A inductor
may not survive a continuous 4.5A overload condition.
Dead shorts will actually be more gentle on the inductor because the LT1506 has foldback current limiting.
2. Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
can be significantly higher than output current, especially with smaller inductors and lighter loads, so don’t
omit this step. Powdered iron cores are forgiving
10
because they saturate softly, whereas ferrite cores
saturate abruptly. Other core materials fall in between
somewhere. The following formula assumes continuous mode of operation, but it errs only slightly on the
high side for discontinuous mode, so it can be used for
all conditions.
IPEAK = IOUT +
(
)
2(f)(L)(V )
VOUT VIN − VOUT
IN
VIN = Maximum input voltage
f = Switching frequency, 500kHz
3. Decide if the design can tolerate an “open” core geometry like a rod or barrel, which have high magnetic field
radiation, or whether it needs a closed core like a toroid
to prevent EMI problems. One would not want an open
core next to a magnetic storage media, for instance!
This is a tough decision because the rods or barrels are
temptingly cheap and small and there are no helpful
guidelines to calculate when the magnetic field radiation will be a problem.
4. Start shopping for an inductor (see representative
surface mount units in Table 2) which meets the
requirements of core shape, peak current (to avoid
saturation), average current (to limit heating), and fault
current (if the inductor gets too hot, wire insulation will
melt and cause turn-to-turn shorts). Keep in mind that
all good things like high efficiency, low profile, and high
temperature operation will increase cost, sometimes
dramatically. Get a quote on the cheapest unit first to
calibrate yourself on price, then ask for what you really
want.
5. After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc.
Use the experts in the Linear Technology’s applications department if you feel uncertain about the final
choice. They have experience with a wide range of
inductor types and can tell you about the latest developments in low profile, surface mounting, etc.
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Table 2
VENDOR/
PART NO.
VALUE
DC
(µH) (Amps)
CORE
TYPE
SERIES
CORE
RESIS- MATER- HEIGHT
TANCE(Ω)
IAL
(mm)
Coiltronics
range for typical LT1506 applications is 0.05Ω to 0.2Ω. A
typical output capacitor is an AVX type TPS, 100µF at 10V,
with a guaranteed ESR less than 0.1Ω. This is a “D” size
surface mount solid tantalum capacitor. TPS capacitors
are specially constructed and tested for low ESR, so they
give the lowest ESR for a given volume. The value in
microfarads is not particularly critical, and values from
22µF to greater than 500µF work well, but you cannot
cheat mother nature on ESR. If you find a tiny 22µF solid
tantalum capacitor, it will have high ESR, and output ripple
voltage will be terrible. Table 3 shows some typical solid
tantalum surface mount capacitors.
CTX2-1
2
4.1
Tor
0.011
KMµ
4.2
CTX5-4
5
4.4
Tor
0.019
KMµ
6.4
CTX8-4
8
3.5
Tor
0.020
KMµ
6.4
CTX2-1P
2
3.4
Tor
0.014
52
4.2
CTX2-3P
2
4.6
Tor
0.012
52
4.8
CTX5-4P
5
3.3
Tor
0.027
52
6.4
CDRH125
10
4.0
SC
0.025
Fer
6
CDRH125
12
3.5
SC
0.027
Fer
6
CDRH125
15
3.3
SC
0.030
Fer
6
Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E Case Size
ESR (Max., Ω )
Ripple Current (A)
CDRH125
18
3.0
SC
0.034
Fer
6
AVX TPS, Sprague 593D
0.1 to 0.3
0.7 to 1.1
AVX TAJ
0.7 to 0.9
0.4
DT3316-222
2.2
5
SC
0.035
Fer
5.1
D Case Size
DT3316-332
3.3
5
SC
0.040
Fer
5.1
AVX TPS, Sprague 593D
0.1 to 0.3
0.7 to 1.1
DT3316-472
4.7
3
SC
0.045
Fer
5.1
C Case Size
0.2 (typ)
0.5 (typ)
Sumida
Coilcraft
Pulse
AVX TPS
PE-53650
4
4.8
Tor
0.017
Fer
9.1
PE-53651
5
5.4
Tor
0.018
Fer
9.1
PE-53652
9
5.5
Tor
0.022
Fer
10
PE-53653
16
5.1
Tor
0.032
Fer
10
IHSM-4825
2.7
5.1
Open
0.034
Fer
5.6
IHSM-4825
4.7
4.0
Open
0.047
Fer
5.6
IHSM-5832
10
4.3
Open
0.053
Fer
7.1
IHSM-5832
15
3.5
Open
0.078
Fer
7.1
IHSM-7832
22
3.8
Open
0.054
Fer
7.1
Dale
Tor = Toroid
SC = Semiclosed geometry
Fer = Ferrite core material
52 = Type 52 powdered iron core material
KMµ = Kool Mµ
Output Capacitor
The output capacitor is normally chosen by its Effective
Series Resistance (ESR), because this is what determines
output ripple voltage. At 500kHz, any polarized capacitor
is essentially resistive. To get low ESR takes volume, so
physically smaller capacitors have high ESR. The ESR
Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents.
This is historically true, and type TPS capacitors are
specially tested for surge capability, but surge ruggedness
is not a critical issue with the output capacitor. Solid
tantalum capacitors fail during very high turn-on surges,
which do not occur at the output of regulators. High
discharge surges, such as when the regulator output is
dead shorted, do not harm the capacitors.
Unlike the input capacitor, RMS ripple current in the
output capacitor is normally low enough that ripple current rating is not an issue. The current waveform is
triangular with a typical value of 200mARMS. The formula
to calculate this is:
Output Capacitor Ripple Current (RMS):
IRIPPLE(RMS) =
( )(
(L)(f)(V )
0.29 VOUT VIN − VOUT
)
IN
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(5)(10 − 5)
Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
available in smaller case sizes. These are ideal for input
bypassing because of their high ripple rating and tolerance
to turn-on surges. As output capacitors, caution must be
used. Solid tantalum capacitor’s ESR generates a loop
“zero” at 5kHz to 50kHz that is beneficial in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually resonate with their
ESL before ESR becomes effective. When using ceramic
output capacitors, the loop compensation pole frequency
must be reduced by a typical factor of 10.
IP-P =
= 0.5A
10  10 • 10 − 6  500 • 103 
10
dI
= 10 6
Σ =
dt 10 • 10 − 6
VRIPPLE = 0.5A 0.1 +  10 • 10 − 9   10 6 
= 0.05 + 0.01 = 60mVP-P
( )
( )( )
VOUT AT IOUT = 1A
20mV/DIV
OUTPUT RIPPLE VOLTAGE
VOUT AT IOUT = 50mA
Figure 3 shows a typical output ripple voltage waveform
for the LT1506. Ripple voltage is determined by the high
frequency impedance of the output capacitor, and ripple
current through the inductor. Peak-to-peak ripple current
through the inductor into the output capacitor is:
IP-P
(V )(V − V )
=
(V )(L)(f)
OUT
IN
dI VIN
=
dt L
Peak-to-peak output ripple voltage is the sum of a triwave
created by peak-to-peak ripple current times ESR, and a
square wave created by parasitic inductance (ESL) and
ripple current slew rate. Capacitive reactance is assumed
to be small compared to ESR or ESL.
( )( ) ( )
dI
dt
Example: with VIN =10V, VOUT = 5V, L = 10µH, ESR = 0.1Ω,
ESL = 10nH:
12
INDUCTOR CURRENT
AT IOUT = 50mA
0.5µs/DIV
1374 F03
CATCH DIODE
For high frequency switchers, the sum of ripple current
slew rates may also be relevant and can be calculated
from:
VRIPPLE = IP-P ESR + ESL Σ
0.5A/DIV
Figure 3. LT1506 Ripple Voltage Waveform
OUT
IN
Σ
INDUCTOR CURRENT
AT IOUT = 1A
The suggested catch diode (D1) is a 1N5821 Schottky, or
its Motorola equivalent, MBR330. It is rated at 3A average
forward current and 30V reverse voltage. Typical forward
voltage is 0.5V at 3A. The diode conducts current only
during switch off time. Peak reverse voltage is equal to
regulator input voltage. Average forward current in normal
operation can be calculated from:
ID(AVG) =
(
IOUT VIN − VOUT
)
VIN
This formula will not yield values higher than 3A with
maximum load current of 4.25A unless the ratio of input to
output voltage exceeds 3.4:1. The only reason to consider
a larger diode is the worst-case condition of a high input
voltage and overloaded (not shorted) output. Under shortcircuit conditions, foldback current limit will reduce diode
current to less than 2.6A, but if the output is overloaded
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and does not fall to less than 1/3 of nominal output voltage,
foldback will not take effect. With the overloaded condition, output current will increase to a typical value of 5.7A,
determined by peak switch current limit of 6A. With
VIN = 15V, VOUT = 4V (5V overloaded) and IOUT = 5.7A:
ID(AVG) =
(
) = 4.18A
5.7 15 − 4
15
This is safe for short periods of time, but it would be
prudent to check with the diode manufacturer if continuous operation under these conditions must be tolerated.
BOOST PIN CONSIDERATIONS
For most applications, the boost components are a 0.27µF
capacitor and a 1N914 or 1N4148 diode. The anode is
connected to the regulated output voltage and this generates a voltage across the boost capacitor nearly identical
to the regulated output. In certain applications, the anode
may instead be connected to the unregulated input voltage. This could be necessary if the regulated output
voltage is very low (< 3V) or if the input voltage is less than
5V. Efficiency is not affected by the capacitor value, but the
capacitor should have an ESR of less than 1Ω to ensure
that it can be recharged fully under the worst-case condition of minimum input voltage. Almost any type of film or
ceramic capacitor will work fine.
For nearly all applications, a 0.27µF boost capacitor works
just fine, but for the curious, more details are provided
here. The size of the boost capacitor is determined by
switch drive current requirements. During switch on time,
drain current on the capacitor is approximately IOUT/ 50. At
peak load current of 4.25A, this gives a total drain of 85mA.
Capacitor ripple voltage is equal to the product of on time
and drain current divided by capacitor value;
∆V = (tON)(85mA/C). To keep capacitor ripple voltage to
less than 0.6V (a slightly arbitrary number) at the worstcase condition of tON = 1.8µs, the capacitor needs to be
0.27µF. Boost capacitor ripple voltage is not a critical
parameter, but if the minimum voltage across the capacitor drops to less than 3V, the power switch may not
saturate fully and efficiency will drop. An approximate
formula for absolute minimum capacitor value is:
C MIN =
(IOUT / 50)(VOUT / VIN)
(f)(VOUT − 2.8 V)
f = Switching frequency
VOUT = Regulated output voltage
VIN = Minimum input voltage
This formula can yield capacitor values substantially less
than 0.27µF, but it should be used with caution since it
does not take into account secondary factors such as
capacitor series resistance, capacitance shift with temperature and output overload.
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1506. Typically, ULVO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions. ULVO
prevents the regulator from operating at source voltages
where these problems might occur.
Threshold voltage for lockout is about 2.38V, slightly less
than the internal 2.42V reference voltage. A 3.5µA bias
current flows out of the pin at threshold. This internally
generated current is used to force a default high state on
the shutdown pin if the pin is left open. When low shutdown current is not an issue, the error due to this current
can be minimized by making RLO 10k or less. If shutdown
current is an issue, RLO can be raised to 100k, but the error
due to initial bias current and changes with temperature
should be considered.
(
)
RLO = 10k to 100k 25k suggested
RHI =
(
RLO VIN − 2.38V
(
)
)
2.38V − RLO 3.5 µA
VIN = Minimum input voltage
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RFB
LT1506
OUTPUT
VSW
IN
INPUT
2.38V
LOCKOUT
RHI
3.5µA
+
SHDN
TOTAL
SHUTDOWN
RLO
C1
0.4V
GND
1506 F04
Figure 4. Undervoltage Lockout
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capacitance to the switching nodes are minimized. If high
resistor values are used, the shutdown pin should be
bypassed with a 1000pF capacitor to prevent coupling
problems from the switch node. If hysteresis is desired in
the undervoltage lockout point, a resistor RFB can be
added to the output node. Resistor values can be calculated from:
RHI =
[
(
)
RLO VIN − 2.38 ∆V / VOUT + 1 + ∆V
( )(
(
2.38 − R2 3.5µA
RFB = RHI VOUT / ∆V
)
)
]
25k suggested for RLO
VIN = Input voltage at which switching stops as input
voltage descends to trip level
∆V = Hysteresis in input voltage level
Example: output voltage is 5V, switching is to stop if input
voltage drops below 6V and should not restart unless
input rises back to 7.5V. ∆V is therefore 1.5V and VIN = 6V.
Let RLO = 25k.
14
R HI =
=
[
(
)
25k 6 − 2.38 1.5 / 5 + 1 + 1.5
(
2.38 − 25k 3.5µA
( ) = 48k
)
]
25k 5.2
2.29
R FB = 48k 5 / 1.5 = 160 k
(
)
SWITCH NODE CONSIDERATIONS
For maximum efficiency, switch rise and fall times are
made as short as possible. To prevent radiation and high
frequency resonance problems, proper layout of the components connected to the switch node is essential. B field
(magnetic) radiation is minimized by keeping catch diode,
switch pin, and input bypass capacitor leads as short as
possible. E field radiation is kept low by minimizing the
length and area of all traces connected to the switch pin
and BOOST pin. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling. A suggested layout for the critical components is
shown in Figure 5. Note that the feedback resistors and
compensation components are kept as far as possible
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from the switch node. Also note that the high current
ground path of the catch diode and input capacitor are kept
very short and separate from the analog ground line.
The high speed switching current path is shown schematically in Figure 6. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, catch diode, and input capacitor is
the only one containing nanosecond rise and fall times. If
you follow this path on the PC layout, you will see that it is
irreducibly short. If you move the diode or input capacitor
away from the LT1506, get your resumé in order. The
other paths contain only some combination of DC and
500kHz triwave, so are much less critical.
CONNECT TO
GROUND PLANE
MINIMIZE LT1506 C3, D1 LOOP
VIN
C3
D1
C5
GND
C6
VOUT
1
GND
C1
CONNECT TO
GROUND PLANE
R3
TAKE OUTPUT
DIRECTLY FROM
END OF OUTPUT
CAPACITOR
L1
U1
D2
PLACE FEEDTHROUGHS
AROUND GND PIN FOR GOOD
THERMAL CONDUCTIVITY
R2
KEEP FB AND VC COMPONENTS
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
C4
KELVIN SENSE
VOUT
1506 F05
Figure 5. Suggested Layout (Topside Only Shown)
SWITCH NODE
L1
5V
VIN
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
1506 F06
Figure 6. High Speed Switching Path
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PARASITIC RESONANCE
Resonance or “ringing” may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schottky diodes have very high “Q” junction capacitance that
can ring for many cycles when excited at high frequency.
If total lead length for the input capacitor, diode and switch
path is 1 inch, the inductance will be approximately 25nH.
At switch off, this will produce a spike across the NPN
output device in addition to the input voltage. At higher
currents this spike can be in the order of 10V to 20V or
higher with a poor layout, potentially exceeding the absolute max switch voltage. The path around switch, catch
diode and input capacitor must be kept as short as
possible to ensure reliable operation. When looking at this,
a >100MHz oscilloscope must be used, and waveforms
should be observed on the leads of the package. This
switch off spike will also cause the SW node to go below
ground. The LT1506 has special circuitry inside which
RISE AND FALL
WAVEFORMS ARE
SUPERIMPOSED
(PULSE WIDTH IS
NOT 120ns)
5V/DIV
20ns/DIV
1375/76 F07
Figure 7. Switch Node Resonance
5V/DIV
SWITCH NODE
VOLTAGE
INDUCTOR
CURRENT
100mA/DIV
20ns/DIV
1375/76 F11
0.5µs/DIV
1375/76 F08
Figure 8. Discontinuous Mode Ringing
16
mitigates this problem, but negative voltages over 1V
lasting longer than 10ns should be avoided. Note that
100MHz oscilloscopes are barely fast enough to see the
details of the falling edge overshoot in Figure 7.
A second, much lower frequency ringing is seen during
switch off time if load current is low enough to allow the
inductor current to fall to zero during part of the switch off
time (see Figure 8). Switch and diode capacitance resonate with the inductor to form damped ringing at 1MHz to
10 MHz. This ringing is not harmful to the regulator and it
has not been shown to contribute significantly to EMI. Any
attempt to damp it with a resistive snubber will degrade
efficiency.
INPUT BYPASSING AND VOLTAGE RANGE
Input Bypass Capacitor
Step-down converters draw current from the input supply
in pulses. The average height of these pulses is equal to
load current, and the duty cycle is equal to VOUT/ VIN. Rise
and fall time of the current is very fast. A local bypass
capacitor across the input supply is necessary to ensure
proper operation of the regulator and minimize the ripple
current fed back into the input supply. The capacitor also
forces switching current to flow in a tight local loop,
minimizing EMI.
Do not cheat on the ripple current rating of the Input
bypass capacitor, but also don’t get hung up on the value
in microfarads. The input capacitor is intended to absorb
all the switching current ripple, which can have an RMS
value as high as one half of load current. Ripple current
ratings on the capacitor must be observed to ensure
reliable operation. In many cases it is necessary to parallel
two capacitors to obtain the required ripple rating. Both
capacitors must be of the same value and manufacturer to
guarantee power sharing. The actual value of the capacitor
in microfarads is not particularly important because at
500kHz, any value above 5µF is essentially resistive. RMS
ripple current rating is the critical parameter. Actual RMS
current can be calculated from:
(
)
IRIPPLE(RMS) = IOUT VOUT VIN − VOUT / VIN
2
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The term inside the radical has a maximum value of 0.5
when input voltage is twice output, and stays near 0.5 for
a relatively wide range of input voltages. It is common
practice therefore to simply use the worst-case value and
assume that RMS ripple current is one half of load current.
At maximum output current of 4.5A for the LT1506, the
input bypass capacitor should be rated at 2.25A ripple
current. Note however, that there are many secondary
considerations in choosing the final ripple current rating.
These include ambient temperature, average versus peak
load current, equipment operating schedule, and required
product lifetime. For more details, see Application Notes
19 and 46, and Design Note 95.
Input Capacitor Type
Some caution must be used when selecting the type of
capacitor used at the input to regulators. Aluminum
electrolytics are lowest cost, but are physically large to
achieve adequate ripple current rating, and size constraints (especially height), may preclude their use.
Ceramic capacitors are now available in larger values, and
their high ripple current and voltage rating make them
ideal for input bypassing. Cost is fairly high and footprint
may also be somewhat large. Solid tantalum capacitors
would be a good choice, except that they have a history of
occasional spectacular failures when they are subjected to
large current surges during power-up. The capacitors can
short and then burn with a brilliant white light and lots of
nasty smoke. This phenomenon occurs in only a small
percentage of units, but it has led some OEM companies
to forbid their use in high surge applications. The input
bypass capacitor of regulators can see these high surges
when a battery or high capacitance source is connected.
Several manufacturers have developed a line of solid
tantalum capacitors specially tested for surge capability
(AVX TPS series for instance, see Table 3), but even these
units may fail if the input voltage surge approaches the
maximum voltage rating of the capacitor. AVX recommends derating capacitor voltage by 2:1 for high surge
applications.
Larger capacitors may be necessary when the input voltage is very close to the minimum specified on the data
sheet. Small voltage dips during switch on time are not
normally a problem, but at very low input voltage they may
cause erratic operation because the input voltage drops
below the minimum specification. Problems can also
occur if the input-to-output voltage differential is near
minimum. The amplitude of these dips is normally a
function of capacitor ESR and ESL because the capacitive
reactance is small compared to these terms. ESR tends to
be the dominate term and is inversely related to physical
capacitor size within a given capacitor type.
SYNCHRONIZING (-SYNC Option for DD Package)
The SYNC pin, is used to synchronize the internal oscillator to an external signal. The SYNC input must pass from
a logic level low, through the maximum synchronization
threshold with a duty cycle between 10% and 90%. The
input can be driven directly from a logic level output. The
synchronizing range is equal to initial operating frequency
up to 1MHz. This means that minimum practical sync
frequency is equal to the worst-case high self-oscillating
frequency (560kHz), not the typical operating frequency of
500kHz. Caution should be used when synchronizing
above 700kHz because at higher sync frequencies the
amplitude of the internal slope compensation used to
prevent subharmonic switching is reduced. This type of
subharmonic switching only occurs at input voltages less
than twice output voltage. Higher inductor values will tend
to eliminate this problem. See Frequency Compensation
section for a discussion of an entirely different cause of
subharmonic switching before assuming that the cause is
insufficient slope compensation. Application Note 19 has
more details on the theory of slope compensation.
At power-up, when VC is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows the
frequency foldback to operate in the shorted output condition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
1.5V, after which the SYNC pin becomes operational.
THERMAL CALCULATIONS
Power dissipation in the LT1506 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following
17
LT1506
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formulas show how to calculate each of these losses.
These formulas assume continuous mode operation, so
they should not be used for calculating efficiency at light
load currents.
Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations.
( ) (VOUT ) + 24ns(I )(V )(f)
OUT IN
VIN
RSW IOUT
2
Boost current loss:
FREQUENCY COMPENSATION
(
VOUT IOUT / 50
)
VIN
Quiescent current loss:
(
)
PQ = VIN 0.001 + VOUT
(
)
2

 VOUT  0.002


0.005 +
VIN
(
)
RSW = Switch resistance (≈0.07)
24ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Example: with VIN = 10V, VOUT = 5V and IOUT = 3A:
(0.07)(3) (5) +  24 • 10  (3)(10) 500 • 10 
=




10
2
PSW
−9
3
= 0.32 + 0.36 = 0.68W
(5) (3 / 50) = 0.15W
=
2
PBOOST
10
(
) (
Loop frequency compensation of switching regulators
can be a rather complicated problem because the reactive
components used to achieve high efficiency also
introduce multiple poles into the feedback loop. The
inductor and output capacitor on a conventional stepdown converter actually form a resonant tank circuit that
can exhibit peaking and a rapid 180° phase shift at the
resonant frequency. By contrast, the LT1506 uses a “current mode” architecture to help alleviate phase shift created by the inductor. The basic connections are shown in
Figure 9. Figure 10 shows a Bode plot of the phase and gain
of the power section of the LT1506, measured from the VC
pin to the output. Gain is set by the 5.3A/V transconductance of the LT1506 power section and the effective
complex impedance from output to ground. Gain rolls off
smoothly above the 600Hz pole frequency set by the
100µF output capacitor. Phase drop is limited to about
70°. Phase recovers and gain levels off at the zero frequency (≈16kHz) set by capacitor ESR (0.1Ω).
LT1506
CURRENT MODE
POWER STAGE
gm = 5.3A/V
) ( ) (10 ) = 0.04W
PQ = 10 0.001 + 5 0.005 +
5
2
0.002
Total power dissipation is 0.68 + 0.15 + 0.04 = 0.87W.
18
+
Thermal resistance for LT1506 package is influenced by
the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
about 80°C/W. No plane will increase resistance to about
120°C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:
VSW
ERROR
AMPLIFIER
–
2
PBOOST =
With the SO-8 package (θJA = 80°C/W), at an ambient
temperature of 50°C,
TJ = 50 + 80 (0.87) = 120°C
Switch loss:
PSW =
TJ = TA + θJA (PTOT)
OUTPUT
R1
FB
ESR
2.42V
+
VC
GND
CF
RC
C1
R2
CC
1506 F09
Figure 9. Model for Loop Response
LT1506
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40
0
20
PHASE
–80
–20
PHASE
2500
150
GAIN
2000
1500
100
(
VC
)
1000
COUT
12pF
ROUT
200k
VFB 2 × 10–3
50
ERROR AMPLIFIER EQUIVALENT CIRCUIT
PHASE (DEG)
–40
0
200
3000
GAIN (µMho)
GAIN
VIN = 10V
VOUT = 5V
IOUT = 2A
PHASE: VC PIN TO OUTPUT (DEG)
GAIN: VC PIN TO OUTPUT (dB)
40
0
RLOAD = 50Ω
–40
10
100
1k
10k
FREQUENCY (Hz)
100k
500
100
–120
1M
10k
100k
FREQUENCY (Hz)
1k
1505 F10
1506 F11
Figure 10. Response from VC Pin to Output
Figure 11. Error Amplifier Gain and Phase
Analog experts will note that around 4.4kHz, phase dips
very close to the zero phase margin line. This is typical of
switching regulators, especially those that operate over a
wide range of loads. This region of low phase is not a
problem as long as it does not occur near unity-gain. In
practice, the variability of output capacitor ESR tends to
dominate all other effects with respect to loop response.
Variations in ESR will cause unity-gain to move around,
but at the same time phase moves with it so that adequate
phase margin is maintained over a very wide range of ESR
(≥ ±3:1).
200
80
GAIN
LOOP GAIN (dB)
60
150
40
100
PHASE
20
50
VIN = 10V
VOUT = 5V, IOUT = 2A
COUT = 100µF, 10V, AVX TPS
CC = 1.5nF, RC = 0, L = 10µH
0
–20
10
100
LOOP PHASE (DEG)
Error amplifier transconductance phase and gain are shown
in Figure 11. The error amplifier can be modeled as a
transconductance of 2000µMho, with an output impedance of 200kΩ in parallel with 12pF. In all practical
applications, the compensation network from VC pin to
ground has a much lower impedance than the output
impedance of the amplifier at frequencies above 500Hz.
This means that the error amplifier characteristics themselves do not contribute excess phase shift to the loop, and
the phase/gain characteristics of the error amplifier section are completely controlled by the external compensation network.
In Figure 12, full loop phase/gain characteristics are
shown with a compensation capacitor of 1.5nF, giving the
error amplifier a pole at 530Hz, with phase rolling off to 90°
and staying there. The overall loop has a gain of 74dB at
low frequency, rolling off to unity-gain at 100kHz. Phase
shows a two-pole characteristic until the ESR of the output
capacitor brings it back above 10kHz. Phase margin is
about 60° at unity-gain.
–50
10M
1M
0
1k
10k
FREQUENCY (Hz)
100k
–50
1M
1505 F12
Figure 12. Overall Loop Characteristics
What About a Resistor in the Compensation Network?
It is common practice in switching regulator design to add
a “zero” to the error amplifier compensation to increase
loop phase margin. This zero is created in the external
network in the form of a resistor (RC) in series with the
compensation capacitor. Increasing the size of this resistor generally creates better and better loop stability, but
there are two limitations on its value. First, the combination of output capacitor ESR and a large value for RC may
cause loop gain to stop rolling off altogether, creating a
gain margin problem. An approximate formula for RC
where gain margin falls to zero is:
(
) (G )(G V)(ESR)(2.42)
R C Loop Gain = 1 =
OUT
MP
MA
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LT1506
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GMP = Transconductance of power stage = 5.3A/V
GMA = Error amplifier transconductance = 2(10–3)
ESR = Output capacitor ESR
2.42 = Reference voltage
With VOUT = 5V and ESR = 0.03Ω, a value of 6.5k for RC
would yield zero gain margin, so this represents an upper
limit. There is a second limitation however which has
nothing to do with theoretical small signal dynamics. This
resistor sets high frequency gain of the error amplifier,
including the gain at the switching frequency. If switching
frequency gain is high enough, output ripple voltage will
appear at the VC pin with enough amplitude to muck up
proper operation of the regulator. In the marginal case,
subharmonic switching occurs, as evidenced by alternating pulse widths seen at the switch node. In more severe
cases, the regulator squeals or hisses audibly even though
the output voltage is still roughly correct. None of this will
show on a theoretical Bode plot because Bode is an
amplitude insensitive analysis. Tests have shown that if
ripple voltage on the VC is held to less than 100mVP-P, the
LT1506 will be well behaved. The formula below will give
an estimate of VC ripple voltage when RC is added to the
loop, assuming that RC is large compared to the reactance
of CC at 500kHz.
VC(RIPPLE ) =
(R )(G )(V − V )(ESR)(2.4)
(V )(L)(f)
C
MA
IN
OUT
IN
GMA = Error amplifier transconductance (2000µMho)
If a computer simulation of the LT1506 showed that a
series compensation resistor of 3k gave best overall loop
response, with adequate gain margin, the resulting VC pin
ripple voltage with VIN = 10V, VOUT = 5V, ESR = 0.1Ω,
L = 10µH, would be:
3k ) 2 • 10  (10 − 5)(0.1)(2.4)
(
= 0.144V
)=
 10 • 10   500 • 10 
10
( )


−3
VC (RIPPLE
−6
3
This ripple voltage is high enough to possibly create
subharmonic switching. In most situations a compromise
value (< 2k in this case) for the resistor gives acceptable
phase margin and no subharmonic problems. In other
20
cases, the resistor may have to be larger to get acceptable
phase response, and some means must be used to control
ripple voltage at the VC pin. The suggested way to do this
is to add a capacitor (CF) in parallel with the RC /CC network
on the VC pin. Pole frequency for this capacitor is typically
set at one-fifth of switching frequency so that it provides
significant attenuation of switching ripple, but does not
add unacceptable phase shift at loop unity-gain frequency.
With RC = 3k,
CF =
5
(2π)(f)(R )
C
=
5
( )
2π  500 • 103  3k
= 531pF
How Do I Test Loop Stability?
The “standard” compensation for LT1506 is a 1.5nF
capacitor for CC, with RC = 0. While this compensation will
work for most applications, the “optimum” value for loop
compensation components depends, to various extent, on
parameters which are not well controlled. These include
inductor value (±30% due to production tolerance, load
current and ripple current variations), output capacitance
(±20% to ±50% due to production tolerance, temperature, aging and changes at the load), output capacitor ESR
(±200% due to production tolerance, temperature and
aging), and finally, DC input voltage and output load
current . This makes it important for the designer to check
out the final design to ensure that it is “robust” and tolerant
of all these variations.
I check switching regulator loop stability by pulse loading
the regulator output while observing transient response at
the output, using the circuit shown in Figure 13. The
regulator loop is “hit” with a small transient AC load
current at a relatively low frequency, 50Hz to 1kHz. This
causes the output to jump a few millivolts, then settle back
to the original value, as shown in Figure 14. A well behaved
loop will settle back cleanly, whereas a loop with poor
phase or gain margin will “ring” as it settles. The number
of rings indicates the degree of stability, and the frequency
of the ringing shows the approximate unity-gain frequency of the loop. Amplitude of the signal is not particularly important, as long as the amplitude is not so high that
the loop behaves nonlinearly.
LT1506
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RIPPLE FILTER
470Ω
SWITCHING
REGULATOR
ADJUSTABLE
INPUT SUPPLY
+
ADJUSTABLE
DC LOAD
100µF TO
1000µF
3300pF
TO X1
OSCILLOSCOPE
PROBE
4.7k
330pF
50Ω
TO
OSCILLOSCOPE
SYNC
100Hz TO 1kHz
100mV TO 1VP-P
1506 F13
Figure 13. Loop Stability Test Circuit
VOUT AT IOUT =
500mA
BEFORE FILTER
VOUT AT IOUT =
500mA
AFTER FILTER
10mV/DIV
VOUT AT IOUT = 50mA
AFTER FILTER
LOAD PULSE
THROUGH 50Ω
f ≈ 780Hz
5A/DIV
0.2ms/DIV
1375/76 F14
Figure 14. Loop Stability Check
The output of the regulator contains both the desired low
frequency transient information and a reasonable amount
of high frequency (500kHz) ripple. The ripple makes it
difficult to observe the small transient, so a two-pole,
100kHz filter has been added. This filter is not particularly
critical; even if it attenuated the transient signal slightly,
this wouldn’t matter because amplitude is not critical.
After verifying that the setup is working correctly, I start
varying load current and input voltage to see if I can find
any combination that makes the transient response look
suspiciously “ringy.” This procedure may lead to an
adjustment for best loop stability or faster loop transient
response. Nearly always you will find that loop response
looks better if you add in several kΩ for RC. Do this only
if necessary, because as explained before, RC above 1k
may require the addition of CF to control VC pin ripple. If
everything looks OK, I use a heat gun and cold spray on the
circuit (especially the output capacitor) to bring out any
temperature-dependent characteristics.
Keep in mind that this procedure does not take initial
component tolerance into account. You should see fairly
clean response under all load and line conditions to ensure
that component variations will not cause problems. One
note here: according to Murphy, the component most
likely to be changed in production is the output capacitor,
because that is the component most likely to have manufacturer variations (in ESR) large enough to cause problems. It would be a wise move to lock down the sources of
the output capacitor in production.
A possible exception to the “clean response” rule is at very
light loads, as evidenced in Figure 14 with ILOAD = 50mA.
Switching regulators tend to have dramatic shifts in loop
response at very light loads, mostly because the inductor
current becomes discontinuous. One common result is very
slow but stable characteristics. A second possibility is low
phase margin, as evidenced by ringing at the output with
transients. The good news is that the low phase margin at
light loads is not particularly sensitive to component variation, so if it looks reasonable under a transient test, it will
probably not be a problem in production. Note that frequency of the light load ringing may vary with component
tolerance but phase margin generally hangs in there.
CURRENT SHARING MULTIPHASE SUPPLY
The circuit in Figure 15 uses multiple LT1506s to produce
a 5V, 12A power supply. There are several advantages to
using a multiple switcher approach compared to a single
larger switcher. The inductor size is considerably reduced.
Three 4A inductors store less energy (LI2/2) than one 12A
coil so are far smaller. In addition, synchronizing three
21
LT1506
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converters 120° out of phase with each other reduces
input and output ripple currents. This reduces the ripple
rating, size and cost of filter capacitors.
Synchronized Ripple Currents
A ring counter generates three synchronization signals at
600kHz, 33% duty cycle phased 120° apart. The sync
input will operate over a wide range of duty cycles, so no
further pulse conditioning is needed. Each device’s maximum input ripple current is a 4A square wave at 600kHz.
When synchronously added together, the ripple remains
at 4A but frequency increases to 1.8MHz. Likewise, the
output ripple current is a 1.8MHz triangular waveform,
with maximum amplitude of 350mA at 10V VIN. Interestingly, at 7.6V and 15V VIN, the theoretical summed output
ripple current cancels completely. To reduce board space
and ripple voltage, C1 and C3 are ceramic capacitors. Loop
compensation C4 must be adjusted when using ceramic
output capacitors due to the lack of effective series resistance. The typical tantalum compensation of 1.5nF is
increased to 22nF (× 3) for the ceramic output capacitor.
If synchronization is not used and the internal oscillators
free run, the circuit will operate correctly, but ripple
cancellation will not occur. Input and output capacitors
must be ripple rated for the total output current.
Current Sharing/Split Input Supplies
Current sharing is accomplished by joining the VC pins to
a common compensation capacitor. The output of the
error amplifier is a gm stage, so any number of devices can
be connected together. The effective gm of the composite
error amplifier is the multiple of the individual devices. In
Figure 15, the compensation capacitor C4 has been
increased by ×3. Tolerances in the reference voltages
result in small offset currents to flow between the VC pins.
The overall effect is that the loop regulates the output at a
voltage between the minimum and maximum reference of
the devices used. Switch current matching between
devices will be typically better than 300mA. The negative
temperature coefficient of the VC to switch current transconductance prevents current hogging.
A common VC voltage forces each LT1506 to operate at the
same switch current, not duty cycle. Each device operates
at the duty cycle defined by its respective input voltage. In
Figure 15, the input could be split and each device operated at a different voltage. The common VC ensures
loading is shared between inputs.
C1, C3: MARCON THCS50E1E106Z
D1: ROHM RB051L-40
D2: 1N914
L1: DO3316P-682
3-BIT RING
COUNTER
1.8MHz
INPUT
6V TO 15V
LT1506-SYNC
LT1506-SYNC
LT1506-SYNC
VC SYNC SW GND VIN BOOST FB
VC SYNC SW GND VIN BOOST FB
VC SYNC SW GND VIN BOOST FB
R1
5.36k
1% +
+
+
C3A
10µF
25V
D1A
C4
68nF
25V
+
D1B
D1C
D2A
L1B
6.8µH
C2B
330nF
10V
+
C2A
330nF
10V
C3C
10µF
25V
+
+
L1A
6.8µH
+
C3B
10µF
25V
R2
4.99k
1%
D2B
L1C
6.8µH
C2C
330nF
10V
D2C
1506 F15
Figure 15. Current Sharing 12A Supply
22
5V
12A
C1
10µF
25V
LT1506
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Redundant Operation
The circuit shown in Figure 15 is fault tolerant when
operating at less than 8A of output current. If one device
fails, the output will remain in regulation. The feedback
loop will compensate by raising the voltage on the VC pin,
increasing switch current of the two remaining devices.
BUCK CONVERTER WITH ADJUSTABLE SOFT START
Large capacitive loads can cause high input currents at
start-up. Figure 16 shows a circuit that limits the dv/dt of
the output at start-up, controlling the capacitor charge
rate. The buck converter is a typical configuration with the
addition of R3, R4, CSS and Q1. As the output starts to rise,
Q1 turns on, regulating switch current via the VC pin to
maintain a constant dv/dt at the output. Output rise time is
controlled by the current through CSS defined by R4 and
Q1’s VBE. Once the output is in regulation, Q1 turns off and
the circuit operates normally. R3 is transient protection for
the base of Q1.
RiseTime =
(R4)(CSS )(VOUT )
(VBE )
Using the values shown in Figure 16,
RiseTime =
(47 • 103 )(15 • 10 –9 )(5)
= 5ms
0.7
output current is unchanged. Variants of this circuit can be
used for sequencing multiple regulator outputs.
Dual Output SEPIC Converter
The circuit in Figure 17 generates both positive and
negative 5V outputs with a single piece of magnetics. The
two inductors shown are actually just two windings on a
standard B H Electronics inductor. The topology for the 5V
output is a standard buck converter. The – 5V topology
would be a simple flyback winding coupled to the buck
converter if C4 were not present. C4 creates a SEPIC
(Single-Ended Primary Inductance Converter) topology
whicn improves regulation and reduces ripple current in
L1. Without C4, the voltage swing on L1B compared to
L1A would vary due to relative loading and coupling
losses. C4 provides a low impedance path to maintain an
equal voltage swing in L1B, improving regulation. In a
flyback converter, during switch on time, all the converter’s
energy is stroed in L1A only, since no current flows in L1B.
At switch off, energy is transferred by magnetic coupling
into L1B, powering the – 5V rail. C4 pulls L1B positive
during switch on time, causing current to flow, and energy
to build in L1B and C4. At switch off, the energy stored in
both L1B and C4 supply the –5V rail. This reduces the
current in L1A and changes L1B current waveform from
square to triangular. For details on this circuit see Design
Note 100.
D2
1N914
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
C2
0.27µF
VIN
SHDN
GND
C2
0.33µF
INPUT
12V
+
C3
10µF
VIN
+
L1
5µH
VSW
SHDN
GND
C1
100µF
D1
LT1506
FB
R1
5.36k
VC
CC
1.5nF
Q1
CSS
R3 15nF
2k
OUTPUT
5V
VSW
LT1506
D2
1N914
BOOST
L1*
6.8µH
BOOST
INPUT
6V TO 15V
R2
4.99k
1506 F16
R4
47k
Figure 16. Buck Converter with Adjustable Soft Start
OUTPUT
5V
4A
C3
10µF
25V
CERAMIC
FB
R1
5.36k
VC
CC
1.5nF
+
C1**
100µF
10V TANT
R2
4.99k
D1
GND
C4**
4.7µF
* L1 IS A SINGLE CORE WITH TWO WINDINGS
BH ELECTRONICS #501-0726
** TOKIN IE475ZY5U-C304
† IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: MBRD340
+
L1*
C5**
100µF
10V TANT
+
OUTPUT
–5V†
D3
1506 F17
Figure 17. Dual Output SEPIC Converter
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT1506
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
R Package
7-Lead Plastic DD Pak
(LTC DWG # 05-08-1462)
0.256
(6.502)
0.060
(1.524)
TYP
0.060
(1.524)
0.390 – 0.415
(9.906 – 10.541)
0.165 – 0.180
(4.191 – 4.572)
0.045 – 0.055
(1.143 – 1.397)
15° TYP
0.060
(1.524)
0.183
(4.648)
0.059
(1.499)
TYP
0.330 – 0.370
(8.382 – 9.398)
(
+0.008
0.004 –0.004
+0.203
0.102 –0.102
)
0.095 – 0.115
(2.413 – 2.921)
0.075
(1.905)
0.300
(7.620)
(
+0.012
0.143 –0.020
+0.305
3.632 –0.508
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAT SINK
)
0.040 – 0.060
(1.016 – 1.524)
0.026 – 0.036
(0.660 – 0.914)
0.050 ± 0.012
(1.270 ± 0.305)
0.013 – 0.023
(0.330 – 0.584)
R (DD7) 0396
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
8
7
6
5
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
0.050
(1.270)
TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
1
3
2
4
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Burst Mode is a trademark of Linear Technology Corporation.
24
Linear Technology Corporation
1506f LT/TP 1198 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1998