LT3050
100mA, Low Noise
Linear Regulator With Precision Current
Limit And Diagnostic Functions
DESCRIPTION
FEATURES
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Output Current: 100mA
Dropout Voltage: 340mV
Input Voltage Range: 1.6V to 45V
Programmable Precision Current Limit: ±5%
Programmable Minimum IOUT Monitor
Output Current Monitor: 1/100th of IOUT
Fault Indicator: Current Limit, Minimum IOUT or
Thermal Limit
Low Noise: 30μVRMS (10Hz to 100kHz)
Adjustable Output (VREF = VOUT(MIN) = 0.6V)
Output Tolerance: ±2% Over Line, Load and Temperature
Stable with Low ESR, Ceramic Output Capacitors
(2.2μF minimum)
Shutdown Current: <1μA
Reverse-Battery, Reverse-Output and
Reverse-Current Protection
Thermal Limit Protection
12-Lead 3mm × 2mm DFN and MSOP Packages
APPLICATIONS
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Protected Antenna Supplies
Automotive Telematics
Industrial Applications (Trucks, Forklifts, etc.)
High Reliability Applications
The LT®3050 is a micro-power, low noise, low dropout
voltage (LDO) linear regulator. The device supplies 100mA
of output current with a dropout voltage of 340mV. A 10nF
bypass capacitor reduces output noise to 30μVRMS in a
10Hz to 100kHz bandwidth and soft-starts the reference.
The LT3050’s ±45V input voltage rating combined with its
precision current limit and diagnostic functions make the IC
an ideal choice for robust, high reliability applications.
A single resistor programs the LT3050’s current limit, accurate
to ±5% over a wide input voltage and temperature range.
A single resistor programs the LT3050’s minimum output
current monitor, useful for detecting open-circuit conditions.
The current monitor function sources a current equal to
1/100th of output current. A logic FAULT pin asserts low if
the LT3050 is in current limit, operating below its minimum
output current (open-circuit) or is in thermal shutdown.
The LT3050 optimizes stability and transient response
with low ESR ceramic capacitors, requiring a minimum
of 2.2μF. The LT3050 is available as an adjustable device
with an output voltage range down to the 0.6V reference.
The LT3050 is available in the thermally-enhanced 12-Lead
3mm × 2mm DFN and MSOP packages.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
External Current Limit
RIMAX = 1.15k
IN
12V
VIN
1μF
120k
OUT
5V
1%
442k
SHDN
2.2μF
ADJ
FAULT
1%
60.4k
LT3050
IMAX
10nF
0.1μF
IMON
1.15k
(THRESHOLD = 100mA)
11.3k
(THRESHOLD = 10mA)
TO μP ADC
3k
(ADC FULL SCALE = 3V)
IMIN
REF/BYP
GND
0.1μF
CURRENT LIMIT FAULT THRESHOLD (mA)
105
5V Supply with 100mA Precision Current Limit, 10mA IMIN
104
VOUT = 5V
103
102
VIN = 15V
101
100
VIN = 12V
99
98
VIN = 5.6V
97
96
95
–75 –50 –25 0 –25 50 75 100 125 150 175
TEMPERATURE (°C)
10nF
3050 TA01
3050 TA01a
3050f
1
LT3050
ABSOLUTE MAXIMUM RATINGS
(Note 1)
IN Pin Voltage ........................................................ ±50V
OUT Pin Voltage ..................................................... ±50V
Input-to-Output Differential Voltage ....................... ±50V
ADJ Pin Voltage ..................................................... ±50V
REF/BYP Pin Voltage ........................................–0.3V, 1V
SHDN Pin Voltage ...................................................±50V
IMON Pin Voltage ..............................................–0.3V, 7V
IMIN Pin Voltage ...............................................–0.3V, 7V
IMAX Pin Voltage...............................................–0.3V, 7V
FAULT Pin Voltage ..........................................–0.3V, 50V
Output Short-Circuit Duration .......................... Indefinite
Operating Junction Temperature Range (Notes 2, 3)
E, I Grades .........................................–40°C to 125°C
MP Grade...........................................–55°C to 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature: Soldering, 10 sec .................... 300°C
(MSOP Package Only)
PIN CONFIGURATION
TOP VIEW
TOP VIEW
REF/BYP
IMIN
FAULT
SHDN
IN
IN
1
2
3
4
5
6
13
GND
12
11
10
9
8
7
REF/BYP 1
IMON
IMAX
GND
ADJ
OUT
OUT
FAULT 3
SHDN 4
MSE PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 45°C/W, θJC = 5°C/W TO 10°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
12 IMON
11 IMAX
IMIN 2
13
GND
10 GND
9 ADJ
IN 5
8 OUT
IN 6
7 OUT
DDB PACKAGE
12-LEAD (3mm s 2mm) PLASTIC DFN
TJMAX = 125°C, θJA = 49°C/W, θJC = 13.5°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3050EMSE#PBF
LT3050EMSE#TRPBF
3050
12-Lead Plastic MSOP
–40°C to 125°C
LT3050IMSE#PBF
LT3050IMSE#TRPBF
3050
12-Lead Plastic MSOP
–40°C to 125°C
LT3050MPMSE#PBF
LT3050MPMSE#TRPBF
3050
12-Lead Plastic MSOP
–55°C to 125°C
LT3050EDDB#PBF
LT3050EDDB#TRPBF
LFGC
12-Lead (3mm × 2mm) Plastic DFN
–40°C to 125°C
LT3050IDDB#PBF
LT3050IDDB#TRPBF
LFGC
12-Lead (3mm × 2mm) Plastic DFN
–40°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3050EMSE
LT3050EMSE#TR
3050
12-Lead Plastic MSOP
–40°C to 125°C
LT3050IMSE
LT3050IMSE#TR
3050
12-Lead Plastic MSOP
–40°C to 125°C
LT3050MPMSE
LT3050MPMSE#TR
3050
12-Lead Plastic MSOP
–55°C to 125°C
LT3050EDDB
LT3050EDDB#TR
LFGC
12-Lead (3mm × 2mm) Plastic DFN
–40°C to 125°C
LT3050IDDB
LT3050IDDB#TR
LFGC
12-Lead (3mm × 2mm) Plastic DFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3050f
2
LT3050
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
Minimum Input Voltage (Notes 3, 11)
ILOAD = 100mA
l
ADJ Pin Voltage (Notes 3, 4)
VIN = 2.2V, ILOAD = 1mA
2.2V < VIN < 15V, 1mA < ILOAD < 100mA (Note 15)
l
Line Regulation (Note 3)
ΔVIN = 2.2V to 45V, ILOAD = 1mA
l
Load Regulation (Note 3)
VIN = 2.2V, ILOAD = 1mA to 100mA
l
Dropout Voltage
VIN = VOUT(NOMINAL) (Notes 5, 6)
ILOAD = 1mA
ILOAD = 1mA
l
ILOAD = 10mA
ILOAD = 10mA
l
ILOAD = 50mA
ILOAD = 50mA
l
ILOAD = 100mA
ILOAD = 100mA
l
GND Pin Current
VIN = VOUT(NOMINAL) + 0.6V (Notes 6, 7, 11)
ILOAD = 0mA
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 50mA
ILOAD = 100mA
l
l
l
l
l
Quiescent Current in Shutdown
VIN = 12V, VSHDN = 0V
ADJ Pin Bias Current (Notes 3, 12)
VIN = 12V
Output Voltage Noise
COUT = 10μF, ILOAD = 100mA, VOUT = 600mV,
BW = 10Hz to 100kHz
90
μVRMS
Output Voltage Noise
COUT = 10μF, CBYP = 0.01μF, ILOAD = 100mA, VOUT = 600mV
BW = 10Hz to 100kHz
30
μVRMS
Shutdown Threshold
VOUT = Off to On
VOUT = On to Off
l
l
VSHDN = 0V
VSHDN = 45V
l
l
SHDN Pin Current (Note 13)
MIN
594
588
l
0.3
TYP
MAX
1.6
2.2
V
600
606
612
mV
mV
0.25
3
mV
0.2
4
mV
110
150
220
mV
mV
195
240
340
mV
mV
280
330
450
mV
mV
340
400
550
mV
mV
45
60
175
0.85
2.2
90
160
370
2
5.2
μA
μA
μA
mA
mA
0.17
1
μA
12.5
60
nA
0.7
0.6
0.9
1.5
V
V
1
3
μA
μA
Ripple Rejection (Note 3)
VIN –VOUT = 2V (AVG), VRIPPLE = 0.5VP-P,
fRIPPLE = 120Hz, ILOAD = 100mA
FAULT Pin Logic Low Voltage
VIN = 2.2V, FAULT Asserted, IFAULT = 100μA
FAULT Pin Leakage Current
FAULT = 5V, FAULT Not Asserted
Input Reverse Leakage Current
VIN = –45V, VOUT = 0
Reverse Output Current (Note 14)
VOUT = 1.2V, VIN = 0
Internal Current Limit (Note 3)
VIN = 2.2V, VOUT = 0, IMAX Pin Grounded
ΔVOUT = –5%
l
110
5.6V < VIN < 15V, VOUT = 5V, RIMAX = 2.26K
FAULT Pin Threshold
l
47.8
50.4
52.9
mA
5.6V < VIN < 15V, VOUT = 5V, RIMAX = 1.5K
FAULT Pin Threshold
l
72.1
75.9
79.7
mA
5.6V < VIN < 15V, VOUT = 5V, RIMAX = 1.15K
FAULT Pin Threshold
l
94.4
99.3
104.3
mA
External Programmed Current Limit (Note 8)
70
UNITS
l
85
140
0.01
l
0.2
dB
250
mV
1
μA
300
μA
10
μA
240
mA
3050f
3
LT3050
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
Minimum IMIN Threshold Accuracy (Note 9)
5.6V < VIN < 15V, VOUT = 5V, RIMIN = 110K
l
IMIN Threshold Accuracy (Note 9)
5.6V < VIN < 15V, VOUT = 5V, RIMIN = 11.3K
l
9
Current Monitor Ratio (Note10)
Ratio = IOUT/IMON
VIMON = VOUT = 5V, 5.6V < VIN < 15V
ILOAD = 5mA, 25mA, 50mA, 75mA, 100mA
l
95
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Absolute maximum input-to-output differential
voltage is not achievable with all combinations of rated IN pin and OUT pin
voltages. With the IN pin at 50V, the OUT pin may not be pulled below 0V.
The total differential voltage from IN to OUT must not exceed ±50V.
Note 2: The LT3050 is tested and specified under pulse load conditions
such that TJ ~ TA. The LT3050E is 100% production tested at TA = 25°C.
Performance at –40°C and 125°C is assured by design, characterization
and correlation with statistical process controls. The LT3050I is
guaranteed over the full –40°C to 125°C operating junction temperature
range. The LT3050MP is 100% tested over the –55°C to 125°C operating
junction temperature range.
Note 3: The LT3050 is tested and specified for these conditions with ADJ
pin connected to the OUT pin.
Note 4: Maximum junction temperature limits operating conditions.
Regulated output voltage specifications do not apply for all possible
combinations of input voltage and output current. If operating at the
maximum input voltage, limit the output current range. If operating at the
maximum output current, limit the input voltage range.
Note 5: Dropout voltage is the minimum differential IN-to-OUT voltage
needed to maintain regulation at a specified output current. In dropout,
the output voltage equals (VIN - VDROPOUT). For some output voltages,
minimum input voltage requirements limit dropout voltage.
Note 6: To satisfy minimum input voltage requirements, the LT3050 is
tested and specified for these conditions with an external resistor divider
(60k bottom, 440k top) which sets VOUT to 5V. The external resistor
divider adds 10μA of DC load on the output. This external current is not
factored into GND pin current.
MIN
TYP
MAX
UNITS
0.9
1
1.1
mA
10
11
mA
100
105
Note 7: GND pin current is tested with VIN = VOUT(NOMINAL) + 0.5V and a
current source load. GND pin current increases in dropout. See GND pin
current curves in the Typical Performance Characteristics section.
Note 8: Current limit varies inversely with the external resistor value tied
from the IMAX pin to GND. For detailed information on how to set the
IMAX pin resistor value, please see the Operation section. If a programmed
current limit is not needed, the IMAX pin must be tied to GND and internal
protection circuitry implements short-circuit protection as specified.
Note 9: The IMIN fault condition asserts if the output current falls below the
IMIN threshold defined by an external resistor from the IMIN pin to GND.
For detailed information on how to set the IMIN pin resistor value, please
see the Operation section. IMIN settings below the Minimum IMIN Accuracy
specification in the Electrical Characteristics section are not guaranteed
to ± 10% tolerance. If the IMIN fault condition is not needed, the IMIN pin
must be left floating (unconnected).
Note 10: The current monitor ratio varies slightly when VIMON ≠ VOUT. For
detailed information on how to calculate the output current from the IMON
pin, please see the Operation section. If the current monitor function is not
needed, the IMON pin must be tied to GND.
Note 11: To satisfy requirements for minimum input voltage, current limit
is tested at VIN = VOUT(NOMINAL) +1V or VIN = 2.2V, whichever is greater.
Note 12: ADJ pin bias current flows out of the ADJ pin:
Note 13: SHDN pin current flows into the SHDN pin.
Note 14: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the specified voltage. This current flows into the OUT pin
and out of the GND pin.
Note 15: 100mA of output current does not apply to the full range of input
voltage due to the internal current limit foldback.
3050f
4
LT3050
TYPICAL PERFORMANCE CHARACTERISTICS
Guaranteed Dropout Voltage
550
550
500
500
TJ ≤ 125°C
400
350
300
250
TJ ≤ 25°C
200
150
Dropout Voltage
600
=TEST POINTS
550
TJ = 125°C
400
350
TJ = 25°C
300
250
200
150
450
350
250
200
100
50
50
0
0
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
3050 G01
IL = 1mA
150
100
0
IL = 10mA
300
50
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
IL = 50mA
400
100
0
IL = 100mA
500
450
DROPOUT VOLTAGE (mV)
600
DROPOUT VOLTAGE (mV)
DROPOUT VOLTAGE (mV)
Typical Dropout Voltage
600
450
TJ = 25°C, unless otherwise noted.
3050 G02
3050 G03
Quiescent Current
ADJ Pin Voltage
80
100
610
90
60
VIN = VSHDN = 12V
VOUT = 5V
IL = 5μA
50
40
30
20
10
QUIESCENT CURRENT (μA)
608
ADJ PIN VOLTAGE (mV)
QUIESCENT CURRENT (μA)
70
5V Quiescent Current
612
606
604
602
600
598
596
594
592
VIN = 12V
ALL OTHER PINS = 0V
70
60
VSHDN = VIN, RL = 500k
50
40
30
20
10
590
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
80
588
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0
VSHDN = 0V, RL = 0
0
5
10
15
20 25
VIN (V)
30
35
40
45
3050 G06
3050 G04
3050 G05
GND Pin Current
4.0
GND PIN CURRENT (mA)
RL = 50, IL = 100mA
1.75
1.50
1.25
RL = 100, IL = 50mA
1.00
0.75
RL = 5k, IL = 1mA
0.50
3.5
3.0
2.5
2.0
1.5
1.0
RL = 500, IL = 10mA
0.25
0.5
0
0
1 2
SHDN PIN THRESHOLD (V)
2.00
GND PIN CURRENT (mA)
VIN = 5.6V
4.5 VOUT = 5V
VOUT = 5V
2.25
0
SHDN Pin Threshold
GND Pin Current vs ILOAD
5.0
2.50
3 4 5 6 7 8 9 10 11
INPUT VOLTAGE (V)
12
3050 G07
0 10 20 30 40 50 60 70 80 90 100
ILOAD (mA)
3050 G08
1.5
1.4 IL = 1mA
1.3
1.2
1.1
1.0
0.9
0.8
0.7
OFF TO ON
0.6
ON
TO
OFF
0.5
0.4
0.3
0.2
0.1
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3050 G09
3050f
5
LT3050
TYPICAL PERFORMANCE CHARACTERISTICS
SHDN Pin Input Current
SHDN Pin Input Current
2.5
2.0
1.5
1.0
0.5
ADJ Pin Bias Current
2.0
50
1.8
45
1.6
40
ADJ PIN BIAS CURRENT (nA)
VSHDN = 45V
SHDN PIN INPUT CURRENT (μA)
SHDN PIN INPUT CURRENT (μA)
3.0
TJ = 25°C, unless otherwise noted.
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0
0
10
20
30
40
SHDN PIN VOLTAGE (V)
200
150
100
50
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
200
200
175
175
150
125
100
75
0
TJ = 125°C
TJ = 25°C
TJ = –40°C
TJ = –55°C
0
5
150
125
100
75
10 15 20 25 30 35 40
INPUT/OUTPUT DIFFERENTIAL (V)
25
0
45
VOUT = VADJ = 1.2V
45 VIN = 0
0.8
40
0.7
35
CURRENT(μA)
ALL PINS GROUNDED EXCEPT FOR OUT
25
20
15
0.2
10
0.1
5
50
3050 G16
80
30
0.3
40
5
10
15 20 25 30 35
OUTPUT VOLTAGE (V)
40
45
Input Ripple Rejection
90
RIPPLE REJECTION (dB)
0.9
0.4
0
CURRENT LIMIT
AT FAULT
THRESHOLD
3050 G15
Reverse Output Current
0.5
TJ = 125°C
TJ = 25°C
TJ = –40°C
TJ = –55°C
50
CURRENT LIMIT
AT FAULT
THRESHOLD
50
0.6
VIN – VOUT(NOMINAL) = 1V
3050 G14
Reverse Output Current
IOUT (μA)
Internal Current Limit
vs Output Voltage
225
3050 G13
20
30
VOUT (V)
3050 G12
225
25
10
10
250
50
0
15
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
50
CURRENT LIMIT (mA)
CURRENT LIMIT (mA)
CURRENT LIMIT (mA)
250
0
20
Internal Current Limit
VIN = 12V
VOUT = 0V
1.0
25
3050 G11
Internal Current Limit
300
30
5
3050 G10
350
35
IADJ
IOUT
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3050 G17
70
CREF/BYP = 10nF
CREF/BYP = 100pF
CREF/BYP = 0
60
50
40
30
20 IL = 100mA
COUT = 10μF
10 VOUT = 5V
VIN = 5.8V + 50mVRMS RIPPLE
0
10
100
1K
10K 100K
FREQUENCY (Hz)
1M
10M
3050 G18
3050f
6
LT3050
TYPICAL PERFORMANCE CHARACTERISTICS
COUT = 10μF
COUT = 2.2μF
COUT = 10μF
CREF/BYP = 10nF
90
80
RIPPLE REJECTION (dB)
70
60
50
40
30
20 IL = 100mA
CREF/BYP = 100pF
10 VOUT = 5V
VIN = 5.8V + 50mVRMS RIPPLE
0
10
100
1K
10K 100K
FREQUENCY (Hz)
70
60
50
40
30
20
10
1M
IL = 100mA
VOUT = 5V
VIN = 5.8V + 0.5VP-P RIPPLE AT f = 120Hz
10M
IL =100mA
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
0
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3050 G19a
3050 G19
3050 G20
Output Noise Spectral Density
CREF/BYP = 0
4
ΔIL = 1mA TO 100mA
3 VOUT = 0.6V
VIN = 2.2V
2
1
0
–1
–2
–3
–4
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
OUTPUT NOISE SPECTRAL DENSITY (μV/√Hz)
Load Regulation
LOAD REGULATION (mV)
Minimum Input Voltage
2.2
Output Noise Spectral Density
vs CREF/BYP
10
1
VOUT = 5V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 0.6V
0.1
0.01
10
100
COUT = 10μF
IL = 100mA
1K
10K
FREQUENCY (Hz)
OUTPUT NOISE SPECTRAL DENSITY (μV/√Hz)
80
INPUT RIPPLE REJECTION (dB)
Ripple Rejection vs Temperature
100
MINIMUM INPUT VOLTAGE (V)
Input Ripple Rejection
90
TJ = 25°C, unless otherwise noted.
10
CREF/BYP = 100pF
VOUT = 5V
1
VOUT = 0.6V
0.1
CREF/BYP = 10nF
COUT = 10μF
IL = 100mA
0.01
10
100k
100
CREF/BYP = 1nF
1k
10k
FREQUENCY (Hz)
100k
3050 G22
3050 G21
3050 G23
RMS Output Noise vs Load Current
vs CREF/BYP
RMS Output Noise vs Load Current
CREF/BYP = 10nF
80
CREF/BYP = 0
CREF/BYP = 10pF
70
60
CREF/BYP = 100pF
50
40
30
CREF/BYP = 1nF
20
CREF/BYP = 10nF
10
0
0.01
CREF/BYP = 100nF
0.1
1
10
LOAD CURRENT (mA)
100
170
160 fOUT = 10Hz TO 100kHz
VOUT = 5V
150 COUT = 10μF
140
VOUT = 2.5V
130
VOUT = 3.3V
120
V
OUT = 1.8V
110
100
VOUT = 1.5V
90
80
70
60
50
40
VOUT = 1.2V
30
20
VOUT = 0.6V
10
0
0.01
0.1
1
10
100
LOAD CURRENT (mA)
60
50
STARTUP TIME (ms)
VOUT = 0.6V
100 COUT = 10μF
90
OUTPUT NOISE VOLTAGE (μVRMS)
OUTPUT NOISE VOLTAGE (μVRMS)
110
Startup Time
vs REF/BYP Capacitor
40
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100
REF/BYP CAPACITOR (nF)
3050 G33
3050 G24
3050 G25
3050f
7
LT3050
TYPICAL PERFORMANCE CHARACTERISTICS
5V 10Hz to 100kHz Output Noise
CREF/BYP = 0
TJ = 25°C, unless otherwise noted.
5V 10Hz to 100kHz Output Noise
CREF/BYP = 10nF
Transient Response
VOUT
100mV/DIV
VOUT
500μV/DIV
VOUT
500μV/DIV
IOUT = 10mA TO 100mA
VIN = 6V
VOUT = 5V
COUT = CIN = 10μF
IOUT
50mA/DIV
COUT = 10μF
IL = 100mA
1ms/DIV
3050 G27
COUT = 10μF
IL = 100mA
1ms/DIV
3050 G26
200μs/DIV
SHDN Transient Response
CREF/BYP = 10nF
SHDN Transient Response
CREF/BYP =0
Transient Response (Load Dump)
VOUT
20mV/DIV
3050 G28
OUT
5V/DIV
IL=100mA
OUT
5V/DIV
IL = 100mA
REF/BYP
500mV/DIV
REF/BYP
500mV/DIV
SHDN
1V/DIV
SHDN
1V/DIV
45V
VOUT = 5V
IOUT = 50mA
COUT = 2.2μF
1ms/DIV
12V
2ms/DIV
3050 G29
External Current Limit
RIMAX = 2.26k
52.3
79.50
VOUT = 5V
51.8
51.3
VIN = 15V
50.8
50.3
49.8
49.3
2ms/DIV
External Current Limit
RIMAX = 1.5k
CURRENT LIMIT FAULT THRESHOLD (mA)
CURRENT LIMIT FAULT THRESHOLD (mA)
52.8
3050 G30
VIN = 12V
VIN = 5.6V
48.8
48.3
47.8
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3050 G34
78.75
105
VOUT = 5V
78.00
77.25
VIN = 15V
76.50
75.75
75.00
74.25
3050 G31
External Current Limit
RIMAX = 1.5k
CURRENT LIMIT FAULT THRESHOLD (mA)
VIN
10V/DIV
VIN = 12V
VIN = 5.6V
73.50
72.75
72.00
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3050 G35
104
VOUT = 5V
103
102
VIN = 15V
101
100
VIN = 12V
99
98
VIN = 5.6V
97
96
95
–75 –50 –25 0 –25 50 75 100 125 150 175
TEMPERATURE (°C)
3050 G36
3050f
8
LT3050
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = 25°C, unless otherwise noted.
11.00
Minimum Output Current
Threshold RIMIN = 110k
MINIMUM OUTPUT CURRENT THRESHOLD (mA)
MINIMUM OUTPUT CURRENT THRESHOLD (mA)
Minimum Output Current
Threshold RIMIN = 11.3k
VOUT = 5V
10.75
10.50
10.25
VIN = 15V
10.00
VIN = 12V
9.75
VIN = 5.6V
9.50
9.25
9.00
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1.100
VOUT = 5V
1.075
1.050
1.025
VIN = 15V
1.000
VIN = 12V
VIN = 5.6V
0.975
0.950
0.925
0.900
–75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3050 G38
IOUT/IMON Current Ratio
VOUT = 5, VIN = 5.6V
101
100
100
99
98
97
96
VIMON = 5V
VIMON = 4V
VIMON = 3V
VIMON = 2V
VIMON = 1V
VIMON = 0V
95
94
93
0
25
50
75
IOUT (mA)
100
102
100
VIMON = 5V
99
98
VIMON = 4V
97
VIMON = 3V
96
VIMON = 2V
95
VIMON = 1V
94
VIMON = 0V
93
92
125
0
3050 G39
25
50
75
IOUT (mA)
100
98
97
125°C
25°C
–55°C
96
95
94
VIMON = 0V
93
91
125
0
25
50
75
IOUT (mA)
3050 G40
IOUT/IMON Current Ratio
VOUT = 5V, VIN = 12V
100
125
3050 G41
IOUT Calculated From IMON
VOUT = 5V
103
5
102
VIMON = 5V
101
100
125°C
25°C
–55°C
9
98
97
VIMON = 0V
96
95
94
93
VIMON = 5V
99
92
%ERROR OF CALCULATION
92
IOUT/IMON Current Ratio
VOUT = 5V, VIN = 5.6V
IOUT/IMON CURRENT RATIO
102
101
IOUT/IMON CURRENT RATIO
102
IOUT/IMON CURRENT RATIO
IOUT/IMON CURRENT RATIO
IOUT/IMON Current Ratio
VOUT = 5V, VIN = 12V
3050 G37
4 IOUT = IMONR • VIMON • 70 + VIN – VOUT
RIMON
70 + VIN – VOUT
3
(SEE PAGE 12 FOR DETAILS)
2
1
0
–1
VIN=5.6V, RIMON=1k
VIN=5.6V, RIMON=2k
VIN=5.6V, RIMON=3k
VIN=12V, RIMON=1k
VIN=12V, RIMON=2k
VIN=12V, RIMON=3k
–2
–3
–4
0
25
50
75
IOUT (mA)
100
125
3050 G42
–5
0
25
50
75
IOUT (mA)
100
125
3050 G43
3050f
9
LT3050
PIN FUNCTIONS
REF/BYP (Pin 1): Bypass/Soft-Start. Connecting a single
capacitor from this pin to GND bypasses the LT3050’s
reference noise and soft-starts the reference. A 10nF
bypass capacitor typically reduces output voltage noise to
30μVRMS in a 10Hz to 100kHz bandwidth. Soft-start time
is directly proportional to the REF/BYP capacitor value.
If the LT3050 is placed in shutdown, REF/BYP is actively
pulled low by an internal device to reset soft-start. If low
noise or soft-start performance is not required, this pin
must be left floating (unconnected). Do not drive this pin
with any active circuitry. Because the REF/BYP pin is the
reference input to the error amplifier, stray capacitance at
this point should be minimized. Special attention should
be given to any stray capacitances that can couple external
signals onto the REF/BYP pin producing undesirable output
transients or ripple. A minimum REF/BYP capacitance of
100pF is recommended.
IMIN (Pin 2): Minimum Output Current Programming
Pin. This pin is the collector of a PNP current mirror that
outputs 1/200th of the power PNP load current. This pin
is also the input to the minimum output current fault
comparator. Connecting a resistor between IMIN and GND
sets the minimum output current fault threshold. For
detailed information on how to set the IMIN pin resistor
value, please see the Operation section.
A small external decoupling capacitor (10nF minimum)
is required to improve IMIN PSRR. If minimum output
current programming is not required, the IMIN pin must
be left floating (unconnected).
FAULT (Pin 3): Fault Pin. This is an open collector logic
pin which asserts during current limit, thermal limit or
a minimum current fault condition. The maximum low
logic output level is defined for sinking 100μA of current.
Off state logic may be as high as 45V without damaging
internal circuitry regardless of the VIN used.
SHDN (Pin 4): Shutdown. Pulling the SHDN pin low puts the
LT3050 into a low power state and turns the output off. Drive
the SHDN pin with either logic or an open collector/drain
with a pull-up resistor. The resistor supplies the pull-up
current to the open collector/drain logic, normally several
microamperes, and the SHDN pin current, typically less than
2μA. If unused, connect the SHDN pin to IN. The LT3050
does not function if the SHDN pin is not connected. The
SHDN pin cannot be driven below GND unless tied to the
IN pin. If the SHDN pin is driven below GND while IN is
powered, the output may turn on. SHDN pin logic cannot
be referenced to a negative rail.
IN (Pin 5,6): Input. These pins supply power to the
device. The LT3050 requires a local IN bypass capacitor
if it is located more than six inches from the main input
filter capacitor. In general, battery output impedance rises
with frequency, so adding a bypass capacitor in battery
powered circuits is advisable. A minimum input of 1μF
generally suffices.
OUT (Pin 7,8): Output. These pins supply power to the
load. Stability requirements demand a minimum 2.2μF
ceramic output capacitor to prevent oscillations. Large
load transient applications require larger output capacitors
to limit peak voltage transients. See the Applications
Information section for details on transient response and
reverse output characteristics. Permissible output voltage
range is 600mV to 44.5V.
ADJ (Pin 9): Adjust. This pin is the error amplifier’s inverting
terminal. Its typical bias of 16nA current flows out of the
pin (see curve of ADJ Pin Bias Current vs. Temperature
in the Typical Performance Characteristics section). The
typical ADJ pin voltage is 600mV referenced to GND.
GND (PIN 10, Exposed Pad Pin 13): Ground. The exposed
pad of the DFN and MSOP packages is an electrical
connection to GND. To ensure proper electrical and
thermal performance, solder Pin 13 to the PCB ground
and tie directly to Pin 10. Connect the bottom of the output
voltage setting resistor divider directly to GND (Pin 10)
for optimum load regulation performance.
IMAX (Pin 11): Precision Current Limit Programming
Pin. This pin is the collector of a current mirror PNP that
is 1/200th the size of the output power PNP. This pin is
also the input to the current limit amplifier. Current limit
threshold is set by connecting a resistor between the IMAX
pin and GND.
3050f
10
LT3050
PIN FUNCTIONS
For detailed information on how to set the IMIN pin resistor
value, please see the Operation section.
The IMAX pin requires a 10nF decoupling capacitor to
ground. If not used, tie IMAX to GND.
IMON (Pin 12): Output Current Monitor. This pin is the
collector of a PNP current mirror that outputs 1/100th
of the power PNP current. When OUT = IMON, the pin
current exactly equals 1/100th that of the output current.
For detailed information on how to calculate the output
current from the IMON pin, please see the Operation section.
The IMON pin requires a small (22nF minimum) external
decoupling capacitor. If the IMON pin is not used, it must
be tied to GND.
BLOCK DIAGRAM
IN
5, 6
R1
D1
QIMIN
1/200
9
ADJ
30k
R4
–
+
Q2
IDEAL DIODE
D3
QIMON
1/100
QIMAX
1/200
THERMAL/
CURRENT LIMITS
Q3
ERROR
AMPLIFIER
CURRENT
LIMIT
AMPLIFIER
+
–
D2
QPOWER
1
OUT
7, 8
100k
R3
IMAX
IMON
11
12
IMIN
COMPARATOR
4
SHDN
+
–
+
–
600mV
REFERENCE
100k
R2
IMIN
FAULT
2
3
U1
QFAULT
1
REF/BYP
GND
10, 13
3050 BD01
3050f
11
LT3050
OPERATION
IMON Pin Operation (Current Monitor)
The IMON pin is the collector of a PNP which mirrors the
LT3050 output PNP at a ratio of 1:100 (see block diagram
on page 11). The current sourced by the IMON pin is
~1/100th of the current sourced by the OUT pin when the
IMON and OUT pin voltages are equal and the device is not
operating in dropout. If the IMON and OUT pin voltages
are not the same, the ratio deviates from 1/100 due to
the Early voltages of the IMON and OUT PNPs according
to the equation:
IIMON
IOUT
1
IMONR
¥ 70 VIN VIMON ´
v ¦
µ
§ 70 VIN VOUT ¶
14442444
3
Early Voltage Compensation
where the Early voltage of the PNPs is 70V and IMONR is
a variable which represents the IOUT to IMON current ratio.
IMONR varies with VIN to VOUT voltage according to the
empirically derived equation:
IMONR = 97 + 5 • log10 (1+VIN – VOUT) for (VIN – VOUT)
≥0.5
IMONR = 96 + 2 • (VIN – VOUT) for (VIN – VOUT) < 0.5
The IMON pin current can be converted into a voltage for
use by monitoring circuitry simply by connecting the IMON
pin to a resistor.
Connecting a resistor from IMON to GND converts the
IMON pin current into a voltage that can be monitored by
circuitry such as an ADC.
For example, a 1.2k resistor results in a IMON pin voltage
of 1.2V for an output current of 100mA and an output
voltage of 1.2V.
A small decoupling capacitor (22nF minimum) from IMON
to GND is required to improve IMON pin power supply
rejection. If the current monitor is not needed, it must be
tied to GND.
Open Circuit Detection (IMIN Pin)
The IMIN pin is the collector of a PNP which mirrors the
LT3050 output at a ratio of approximately 1:200 (see block
diagram on page 11). The IMIN fault comparator asserts
the FAULT pin if the IMIN pin voltage is below 0.6V. This
low output current fault threshold voltage (IOPEN) is set
by attaching a resistor from IMIN to GND.
RIMIN =
119.85 – (1.68 – 36.8 • IOPEN ) • VOUT
IOPEN
This equation is empirically derived and partially
compensates for early voltage effects in the IMIN current
mirror. It is valid for an input voltage range from 0.6V
above the output to 10V above the output. It is valid for
output voltages up to 12V. The accuracy of this equation
for setting the resistor value is approximately ±2%. Unit
values are Amps, Volts, and Ohms.
If the open circuit detection function is not needed, the IMIN
pin must be left floating (unconnected). A small decoupling
capacitor (10nF minimum) from IMIN to GND is required
to improve IMIN pin power supply rejection and to prevent
FAULT pin glitches.
See the Typical Performance Characteristics section for
additional information.
The output current of the device can be calculated from
the IMON pin voltage by the following equation:
V
IOUT IMONR v IMON v
{ RIMON
123
IOUT
IMON
Ratio
IIMON
¥ 70 VIN VOUT ´
¦
µ
§ 70 VIN VIMON ¶
14442444
3
Early VoltageCompensation
3050f
12
LT3050
OPERATION
External Programmable Current Limit (IMAX Pin)
requires a 10nF decoupling capacitor.
The IMAX pin is the collector of a PNP which mirrors the
LT3050 output at a ratio of approximately 1:200 (see Block
Diagram). The IMAX pin is also the input to the precision
current limit amplifier. If the output load increases to the
point where it causes the IMAX pin voltage to reach 0.6V,
the current limit amplifier takes control of output regulation
so that the IMAX pin clamps at 0.6V, regardless of the
output voltage. The current limit threshold (ILIMIT) is set
by attaching a resistor (RIMAX) from IMAX to GND:
See the Typical Performance Characteristics section for
additional information.
RIMAX =
119.22 − 0.894 • VOUT
ILIMIT
This equation is empirically derived and partially
compensates for early voltage effects in the IMAX current
mirror. It is valid for an input voltage range from 0.6V
above the output to 10V above the output. It is valid for
output voltages up to 12V. The accuracy of this equation
for setting the resistor value is approximately ±1%. Unit
values are Amps, Volts, and Ohms.
In cases where the IN to OUT voltage exceeds 10V, foldback current limit will lower the internal current level limit,
possibly causing it to preempt the external programmable
current limit. See the Internal Current Limit vs VIN – VOUT
graph in the Typical Performance Characteristics section.
If the external programmable current limit is not needed,
the IMAX pin must be connected to GND. The IMAX pin
FAULT Pin Operation
The FAULT pin is an open collector logic pin which asserts
during internal current limit, precision current limit, thermal
limit, or a minimum current fault. There is no internal
pull-up on the FAULT pin; an external pull-up resistor is
required. The FAULT pin provides drive for up to 100μA
of pull-down current. Off state logic may be as high as
45V, regardless of the input voltage used. When asserted,
the FAULT pin drive circuitry adds 50μA (nominal) of GND
pin current.
Depending on the IMIN capacitance, BYP capacitance,
and OUT capacitance, the FAULT pin may assert during
startup. Consideration should be given to masking the
FAULT signal during startup. The FAULT pin circuitry is
inactive (not asserted) during shutdown and when the
OUT pin is pulled above the IN pin.
Operation in Dropout
The LT3050 contains circuitry which prevents the PNP
output power device from saturating in dropout. This also
keeps the IMON, IMIN, and IMAX current mirrors functioning
accurately, even in dropout. However, this anti-saturation
circuitry becomes less active at lower output currents, so
there is some degradation of current mirror function for
output currents less than 10mA.
3050f
13
LT3050
APPLICATIONS INFORMATION
The LT3050 is a micropower, low noise and low dropout
voltage, 100mA linear regulator with micropower shutdown,
programmable current limit, and diagnostic functions. The
device supplies up to 100mA at a typical dropout voltage
of 340mV and operates over a 2.2V to 45V input range.
A single external capacitor can provide low noise reference
performance and output soft-start functionality. For
example, connecting a 10nF capacitor from the REF/BYP pin
to GND lowers output noise to 30μVRMS over a 10Hz to
100kHz bandwidth. This capacitor also soft-starts the
reference and prevents output voltage overshoot at turn-on.
The LT3050’s quiescent current is merely 45μA but
provides fast transient response with a minimum low ESR
2.2μF ceramic output capacitor. In shutdown, quiescent
current is less than 1μA and the reference soft-start
capacitor is reset.
The LT3050 optimizes stability and transient response
with low ESR, ceramic output capacitors. The regulator
does not require the addition of ESR as is common with
other regulators. The LT3050 typically provides 0.1% line
regulation and 0.1% load regulation. Internal protection
circuitry includes reverse-battery protection, reverseoutput protection, reverse-current protection, current limit
with fold-back and thermal shutdown.
This “bullet-proof” protection set makes it ideal for use in
battery-powered, automotive and industrial systems.
In battery backup applications where the output is held
up by a backup battery and the input is pulled to ground,
the LT3050 acts like it has a diode in series with its output
and prevents reverse current flow.
Adjustable Operation
The LT3050 has an output voltage range of 0.6V to 44.5V.
The output voltage is set by the ratio of two external
resistors, as shown in Figure 1. The device servos the
output to maintain the ADJ pin voltage at 0.6V referenced
to ground. The current in R1 is then equal to 0.6V/R1, and
the current in R2 is the current in R1 minus the ADJ pin
bias current.
IN
VIN
VOUT
OUT
LT3050
SHDN
R2
ADJ
GND
R1
3050 F01
⎛ R2 ⎞
VOUT = 0.6 V ⎜1 + ⎟ – (IADJ ) • R2
⎝ R1 ⎠
VADJ = 0.6 V
IADJ = 16nA at 25°C
OUTPUT RANGE = 0.6 V to 44.5V
Figure 1. Adjustable Operation
The ADJ pin bias current, 16nA at 25°C, flows from the
ADJ pin through R1 to GND. Calculate the output voltage
using the formula in Figure 1. The value of R1 should be
no greater than 124k to provide a minimum 5μA load
current so that output voltage errors, caused by the ADJ
pin bias current, are minimized. Note that in shutdown,
the output is turned off and the divider current is zero.
Curves of ADJ Pin Voltage vs Temperature and ADJ Pin Bias
Current vs Temperature appear in the Typical Performance
Characteristics Section.
The LT3050 is tested and specified with the ADJ pin tied
to the OUT pin, yielding VOUT = 0.6V. Specifications for
output voltages greater than 0.6V are proportional to the
ratio of the desired output voltage to 0.6V: VOUT/0.6V. For
example, load regulation for an output current change
of 1mA to 100mA is –0.2mV (typical) at VOUT = 0.6V.
at VOUT = 12V, load regulation is:
12V
• ( –0.2mV ) = – 4mV
0.6 V
3050f
14
LT3050
APPLICATIONS INFORMATION
Table 1 shows 1% resistor divider values for some common
output voltages with a resistor divider current of 5μA.
Table 1. Output Voltage Resistor Divider Valves
VOUT (V)
R1 (kΩ)
R2 (kΩ)
1.2
118
118
1.5
121
182
1.8
124
249
2.5
115
365
3
124
499
3.3
124
562
5
115
845
Bypass Capacitance and Output Voltage Noise
The LT3050 regulator provides low output voltage noise
over the 10Hz to 100kHz bandwidth while operating at
full load with the addition of a bypass capacitor from the
REF/BYP pin to GND. A good quality, low leakage capacitor
is recommended. This capacitor bypasses the reference of
the regulator, providing a low frequency noise pole for the
internal reference. The noise pole provided by this bypass
capacitor decreases the output voltage noise to as low
as 30μVRMS with the addition of a 10nF bypass capacitor
when the output voltage is 0.6V. For higher output voltages
(generated by using a resistor divider), the output voltage
noise increases proportionately.
Higher values of output voltage noise are often measured
if care is not exercised with regard to circuit layout and
testing. Crosstalk from nearby traces induces unwanted
noise onto the LT3050’s output. Power supply ripple
rejection must also be considered. The LT3050 regulator
does not have unlimited power supply rejection and passes
a small portion of the input noise through to the output.
During start-up, the internal reference will soft-start the
reference if a bypass capacitor is present. Regulator startup time is directly proportional to the size of the bypass
capacitor, slowing to 5.5ms with a 10nF bypass capacitor
and 2.2μF output capacitor.
Output Capacitance and Transient Response
The LT3050 regulator is stable with a wide range of output
capacitors. The ESR of the output capacitor affects stability,
most notably with small capacitors. Use a minimum output
capacitor of 2.2μF to prevent oscillations. The LT3050 is a
micropower device and output load transient response is
a function of output capacitance. Larger values of output
capacitance decrease the peak deviations and provide
improved transient response for larger load current
changes. Bypass capacitors, used to decouple individual
components powered by the LT3050, increase the effective
output capacitor value. For applications with large load
current transients, a low ESR ceramic capacitor in parallel
with a bulk tantalum capacitor often provides an optimally
damped response.
Give extra consideration to the use of ceramic capacitors.
Manufacturers make ceramic capacitors with a variety of
dielectrics, each with different behavior across temperature
and applied voltage. The most common dielectrics are
specified with EIA temperature characteristic codes of
Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics
provide high C-V products in a small package at low cost,
but exhibit strong voltage and temperature coefficients, as
shown in Figures 2 and 3. When used with a 5V regulator,
a 16V 10μF Y5V capacitor can exhibit an effective value
as low as 1μF to 2μF for the DC bias voltage applied, and
over the operating temperature range. The X5R and X7R
dielectrics yield much more stable characteristics and are
more suitable for use as the output capacitor.
The X7R type works over a wider temperature range and
has better temperature stability, while the X5R is less
expensive and is available in higher values. Care still must
be exercised when using X5R and X7R capacitors; the X5R
and X7R codes only specify operating temperature range
and maximum capacitance change over temperature.
Capacitance change due to DC bias with X5R and X7R
capacitors is better than Y5V and Z5U capacitors, but can
still be significant enough to drop capacitor values below
appropriate levels. Capacitor DC bias characteristics tend
to improve as component case size increases, but expected
capacitance at operating voltage should be verified.
3050f
15
LT3050
APPLICATIONS INFORMATION
20
VOUT = 5V
COUT = 10μF
CREF/BYP = 10nF
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
CHANGE IN VALUE (%)
0
X5R
VOUT
1mV/DIV
–20
–40
–60
Y5V
3050 F04
10ms/DIV
–80
–100
Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor
0
2
4
14
8
6
10 12
DC BIAS VOLTAGE (V)
16
3050 F02
Figure 2. Ceramic Capacitor DC Bias Characteristics
40
CHANGE IN VALUE (%)
20
X5R
0
–20
–40
Y5V
–60
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
–100
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3050 F03
Figure 3. Ceramic Capacitor Temperature Characteristics
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to technical stress, similar
to the way a piezoelectric accelerometer or microphone
works. For a ceramic capacitor, the stress is induced by
vibrations in the system or thermal transients. The resulting
voltages produced cause appreciable amounts of noise.
A ceramic capacitor produced the trace in Figure 4 in
response to light tapping from a pencil. Similar vibration
induced behavior can masquerade as increased output
voltage noise.
Overload Recovery
Like many IC power regulators, the LT3050 has safe
operating area protection. The safe area protection
decreases current limit as input-to-output voltage
increases, and keeps the power transistor inside a safe
operating region for all values of input-to-output voltage.
The LT3050 provides some output current at all values of
input-to-output voltage up to the device breakdown.
When power is first applied, the input voltage rises and the
output follows the input; allowing the regulator to start-up
into very heavy loads. During start-up, as the input voltage
is rising, the input-to-output voltage differential is small,
allowing the regulator to supply large output currents.
With a high input voltage, a problem can occur wherein
the removal of an output short will not allow the output
to recover. Other regulators, such as the LT1083/LT1084/
LT1085 family and LT1764A also exhibit this phenomenon,
so it is not unique to the LT3050. The problem occurs with
a heavy output load when the input voltage is high and the
output voltage is low. Common situations are: immediately
after the removal of a short-circuit or if the shutdown pin
is pulled high after the input voltage is already turned on.
The load line for such a load intersects the output current
curve at two points. If this happens, there are two stable
output operating points for the regulator. With this double
intersection, the input power supply needs to be cycled
down to zero and brought up again to make the output
recover.
3050f
16
LT3050
APPLICATIONS INFORMATION
Thermal Considerations
The LT3050’s maximum rated junction temperature of
125°C limits its power handling capability. Two components
comprise the power dissipated by the device:
1. Output current multiplied by the input/output
voltage differential: IOUT • (VIN – VOUT), and
2. GND pin current multiplied by the input voltage:
IGND • VIN
Table 1. MSOP Measured Thermal Resistance
COPPER AREA
TOPSIDE
BACKSIDE
THERMAL RESISTANCE
BOARD AREA (JUNCTION-TO-AMBIENT)
2500 sq mm 2500 sq mm 2500 sq mm
40°C/W
1000 sq mm 2500 sq mm 2500 sq mm
41°C/W
225 sq mm 2500 sq mm 2500 sq mm
43°C/W
100 sq mm 2500 sq mm 2500 sq mm
45°C/W
Table 2. DFN Measured Thermal Resistance
GND pin current is determined using the GND Pin Current
curves in the Typical Performance Characteristics section.
Power dissipation equals the sum of the two components
listed above.
COPPER AREA
TOPSIDE
BOARD AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
2500 sq mm
2500 sq mm
44°C/W
1000 sq mm
2500 sq mm
45°C/W
225 sq mm
2500 sq mm
47°C/W
The LT3050 regulator has internal thermal limiting that
protects the device during overload conditions. For
continuous normal conditions, do not exceed the maximum
junction temperature of 125°C. Carefully consider all
sources of thermal resistance from junction-to-ambient
including other heat sources mounted in proximity to the
LT3050.
100 sq mm
2500 sq mm
49°C/W
The undersides of the LT3050 DFN and MSOP packages
have exposed metal from the lead frame to the die
attachment. These packages allow heat to directly transfer
from the die junction to the printed circuit board metal
to control maximum operating junction temperature.
The dual-in-line pin arrangement allows metal to extend
beyond the ends of the package on the topside (component
side) of a PCB. Connect this metal to GND on the PCB.
The multiple IN and OUT pins of the LT3050 also assist
in spreading heat to the PCB.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes also can spread the heat generated by
power devices. The following tables list thermal resistance
as a function of copper area in a fixed board size. All
measurements were taken in still air on a four-layer FR-4
board with one ounce solid internal planes and two ounce
external trace planes with a total board thickness of 1.6mm.
For further information on thermal resistance and using
thermal information, refer to JEDEC standard JESD51,
notably JESD51-12.
Calculating Junction Temperature
Example: Given an output voltage of 5V, an input voltage
range of 12V ±5%, a maximum output current range of
75mA and a maximum ambient temperature of 85°C, what
will the maximum junction temperature be?
The power dissipated by the device equals:
IOUT(MAX) * (VIN(MAX) – VOUT) + IGND * VIN(MAX)
where,
IOUT(MAX) = 75mA
VIN(MAX) = 12.6V
IGND at (IOUT = 75mA, VIN = 12V) = 1.5mA
So,
P = 75mA • (12.6V - 5V) + 1.5mA • 12.6V = 0.589W
Using a DFN package, the thermal resistance ranges from
44°C/W to 49°C/W depending on the copper area. So the
junction temperature rise above ambient approximately
equals:
0.589W • 49°C/W = 28.86°C
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction
temperature rise above ambient or:
TJMAX = 85°C + 28.86°C = 113.86°C
3050f
17
LT3050
APPLICATIONS INFORMATION
The LT3050 incorporates several protection features
that make it ideal for use in battery-powered circuits. In
addition to the normal protection features associated with
monolithic regulators, such as current limiting and thermal
limiting, the device also protects against reverse-input
voltages, reverse-output voltages and reverse output-toinput voltages.
Current limit protection and thermal overload protection
protect the device against current overload conditions at
the output of the device. For normal operation, do not
exceed a junction temperature of 125°C.
The LT3050 IN pin withstands reverse voltages of 50V. The
device limits current flow to less than 300μA (typically less
than 10μA) and no negative voltage appears at OUT. The
device protects both itself and the load against batteries
that are plugged in backwards.
The SHDN pin cannot be driven below GND unless tied
to the IN pin. If the SHDN pin is driven below GND while
IN is powered, the output may turn on. SHDN pin logic
cannot be referenced to a negative rail.
The LT3050 incurs no damage if its output is pulled below
ground. If the input is left open-circuit or grounded, the
output can be pulled below ground by 50V. No current
flows through the pass transistor from the output.
However, current flows in (but is limited by) the resistor
divider that sets the output voltage. Current flows from
the bottom resistor in the divider and from the ADJ pin’s
internal clamp through the top resistor in the divider to
the external circuitry pulling OUT below ground. If the
input is powered by a voltage source, the output sources
current equal to its current limit capability and the LT3050
protects itself by thermal limiting. In this case, grounding
the SHDN pin turns off the device and stops the output
from sourcing current.
1.0
ALL PINS GROUNDED EXCEPT FOR OUT
0.9
0.8
0.7
IOUT (μA)
Protection Features
0.6
0.5
0.4
0.3
0.2
0.1
0
0
10
20
30
VOUT (V)
40
50
3050 F05
Figure 5. Reverse Output Current
3050f
18
LT3050
PACKAGE DESCRIPTION
DDB Package
12-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1723 Rev Ø)
0.64 ±0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
R = 0.05
TYP
R = 0.115
TYP
7
0.40 ± 0.10
12
0.70 ±0.05
2.55 ±0.05
1.15 ±0.05
2.00 ±0.10
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
PACKAGE
OUTLINE
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.45 BSC
0.64 ± 0.10
(2 SIDES)
6
0.23 ± 0.05
1
(DDB12) DFN 0106 REV Ø
0.45 BSC
2.39 ±0.05
(2 SIDES)
0 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1
R = 0.20 OR
0.25 s 45°
CHAMFER
2.39 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAG
MSE Package
12-Lead Plastic MSOP Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev B)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 p 0.102
(.112 p .004)
5.23
(.206)
MIN
2.845 p 0.102
(.112 p .004)
0.889 p 0.127
(.035 p .005)
6
1
1.651 p 0.102 3.20 – 3.45
(.065 p .004) (.126 – .136)
0.12 REF
12
0.65
0.42 p 0.038
(.0256)
(.0165 p .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.35
REF
4.039 p 0.102
(.159 p .004)
(NOTE 3)
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
7
NO MEASUREMENT PURPOSE
12 11 10 9 8 7
0.406 p 0.076
(.016 p .003)
REF
DETAIL “A”
0o – 6o TYP
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
1 2 3 4 5 6
DETAIL “A”
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
0.86
(.034)
REF
0.1016 p 0.0508
(.004 p .002)
MSOP (MSE12) 0608 REV B
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3050f
19
LT3050
TYPICAL APPLICATION
5V Protected Antenna Supply with 100mA Current Limit, 10mA IMIN
IN
12V
VIN
1μF
120k
OUT
5V
1%
442k
SHDN
2.2μF
ADJ
FAULT
1%
60.4k
LT3050
IMAX
10nF
1.15k
(THRESHOLD = 100mA)
IMON
IMIN
0.1μF
TO μP ADC
3k
(ADC FULL SCALE = 3V)
11.3k
(THRESHOLD = 10mA)
0.1μF
REF/BYP
GND
10nF
3050 TA02
RELATED PARTS
PART
NUMBER
DESCRIPTION
COMMENTS
LT1761
100mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS , VIN = 1.8V to 20V, ThinSOT Package
LT1762
150mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS , VIN = 1.8V to 20V, MS8 Package
LT1763
500mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μVRMS , VIN = 1.8V to 20V, SO-8 Package
LT1962
300mA, Low Noise LDO
270mV Dropout Voltage, Low Noise: 20μVRMS , VIN = 1.8V to 20V, MS8 Package
LT1963/A
1.5A Low Noise, Fast Transient
Response LDO
340mV Dropout Voltage, Low Noise: 40μVRMS , VIN = 2.5V to 20V, “A” Version Stable with Ceramic
Capacitors, TO-220, DD-PAK, SOT-223 and SO-8 Packages
LT1965
1.1A, Low Noise, Low Dropout Linear
Regulator
290mV Dropout Voltage, Low Noise: 40μVRMS , VIN : 1.8V to 20V, VOUT: 1.2V to 19.5V, Stable with
Ceramic Capacitors, TO-220, DD-PAK, MSOP and 3 × 3 DFN Packages
LT3008
20mA, 45V, 3uA IQ Micropower LDO
300mV Dropout Voltage, Low IQ: 3μA, VIN = 2.0V to 45V, VOUT = 0.6V to 39.5V; ThinSOT and
2mm × 2mm DFN-6 Packages
LT3009
20mA, 3uA IQ Micropower LDO
280mV Dropout Voltage, Low IQ: 3μA, VIN = 1.6V to 20V, ThinSOT and SC-70 Packages
LT3010
50mA, High Voltage, Micropower LDO
VIN: 3V to 80V, VOUT: 1.275V to 60V, VDO = 0.3V, IQ = 30μA, ISD < 1μA, Low Noise: <100μVRMS,
Stable with 1μF Output Capacitor, Exposed MS8 Package
LT3011
50mA, High Voltage, Micropower LDO
with PWRGD
VIN: 3V to 80V, VOUT: 1.275V to 60V, VDO = 0.3V, IQ = 46μA, ISD < 1μA, Low Noise: <100μVRMS,
Power Good, Stable with 1μF Output Capacitor, 3 × 3 DFN-10 and Exposed MS12E Packages
LT3012
250mA, 4V to 80V, Low Dropout
Micropower Linear Regulator
VIN: 4V to 80V, VOUT : 1.24V to 60V, VDO = 0.4V, IQ = 40μA, ISD < 1μA, TSSOP-16E and
4mm × 3mm DFN-12 Packages
LT3013
250mA, 4V to 80V, Low Dropout
VIN: 4V to 80V, VOUT: 1.24V to 60V, VDO = 0.4V, IQ = 65μA, ISD < 1μA, Power Good feature;
Micropower Linear Regulator with PWRGD TSSOP-16E and 4mm × 3mm DFN-12 Packages
LT3014/HV 20mA, 3V to 80V, Low Dropout
Micropower Linear Regulator
VIN: 3V to 80V (100V for 2ms, “HV” version), VOUT : 1.22V to 60V, VDO = 0.35V, IQ = 7μA, ISD <
1μA, ThinSOT and 3mm × 3mm DFN-8 Packages
LT3060
100mA, Low Noise LDO with Soft Start
300mV Dropout Voltage, Low Noise: 20μVRMS , VIN = 1.8V to 45V, DFN Package
LT3080/-1
1.1A, Parallelable, Low Noise, Low
Dropout Linear Regulator
300mV Dropout Voltage (2-supply operation), Low Noise: 40μVRMS, VIN: 1.2V to 36V, VOUT : 0V
to 35.7V, Current-Based Reference with 1-Resistor VOUT set; Directly Parallelable (no op amp
required), Stable with Ceramic Caps, TO-220, SOT-223, MSOP and 3mm × 3mm DFN Packages;
“–1” Version has Integrated Internal Ballast Resistor
LT3085
500mA, Parallelable. Low Noise, Low
Dropout Linear Regulator
275mV Dropout Voltage (2-supply operation), Low Noise: 40μVRMS , VIN: 1.2V to 36V, VOUT: 0V
to 35.7V, Current-Based Reference with 1-Resistor VOUT set; Directly Parallelable (no op amp
required), Stable with Ceramic Caps, MSOP-8 and 2mm × 3mm DFN Packages
3050f
20 Linear Technology Corporation
LT 1209 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009