TI ADS8319IDGST 16-bit, 500-ksps, serial interface micropower, miniature, sar analog-to-digital converter Datasheet

ADS8319
www.ti.com ........................................................................................................................................................................................................ SLAS600 – MAY 2008
16-BIT, 500-KSPS, SERIAL INTERFACE MICROPOWER, MINIATURE,
SAR ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
•
•
•
•
The ADS8319 is a 16-bit, 500-KSPS analog-to-digital
converter. It operates with a 2.25-V to 5.5-V external
reference. The device includes a capacitor based,
SAR A/D converter with inherent sample and hold.
1
•
•
•
•
•
•
500-kHz Sample Rate
16-Bit Resolution
Zero Latency at Full Speed
Unipolar, Single-Ended Input, Range: 0 V to
Vref
SPI Compatible Serial Interface with Daisy
Chain Option
Excellent Performance:
– 93.6 dB SNR Typ at 10-kHz I/P
– –106 dB THD Typ at 10-kHz I/P
– ±1.5 LSB Max INL
– ±1.0 LSB Max DNL
Low Power Dissipation: 18 mW Typ at 500
KSPS
Power Scales Linearly with Speed: 3.6 mW/100
KSPS
Power Dissipation During Power-Down State:
0.25 µW Typ
10-Pin MSOP and SON Packages
APPLICATIONS
•
•
•
•
•
Battery Powered Equipments
Data Acquisition Systems
Instrumentation and Process Control
Medical Electronics
Optical Networking
The device includes a 50-MHz SPI compatible serial
interface. The interface is designed to support daisy
chaining or cascading of multiple devices. Also a
Busy Indicator makes it easy to synchronize with the
digital host.
The ADS8319 unipolar single-ended input range
supports an input swing of 0 V to +Vref.
Device operation is optimized for very low power
operation, and the power consumption directly scales
with speed. This feature makes it attractive for lower
speed applications.
It is available in 10-pin MSOP and SON packages.
+VA
SAR
O/P
Drive
COMP
I/P
Shift
Reg
IN+
CDAC
+VBD
IN-
REFIN
Conversion and I/O
Control Logic
ADS8319
GND
SDO
SDI
SCLK
CONVST
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
ADS8319
SLAS600 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
DEVICE
ADS8319I
±2.5
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
CODES AT
RESOLUTION
(BIT)
+1.5/–1
PACKAGE
TYPE
PACKAGE
DESIGNATOR
10 Pin MSOP
DGS
16
10 Pin MSOP
±1.5
±1.0
ORDERING
INFORMATION
TRANSPORT
MEDIA
QUANTITY
ADS8319IDGST
250
ADS8319IDGSR
2500
CBC
DRC
ADS8319IDRCT
250
ADS8319IDRCR
2500
CBE
DGS
16
ADS8319IBDGST
250
ADS8319IBDGSR
2500
CBC
–40°C to 85°C
10 Pin SON
(1)
PACKAGE
MARKING
–40°C to 85°C
10 Pin SON
ADS8319IB
TEMPERATURE
RANGE
DRC
ADS8319IBDRCT
250
ADS8319IBDRCR
2500
CBE
For the most current specifications and ordering information, see the Package Option Addendum at the end of this document, or see the
TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
+IN
VALUE
UNIT
–0.3 to +VA + 0.3
V
±130
mA
–0.3 to 0.3
V
±130
mA
+VA to AGND
–0.3 to 7
V
+VBD to BDGND
–0.3 to 7
V
Digital input voltage to GND
–0.3 to +VBD + 0.3
V
Digital output to GND
–0.3 to +VBD + 0.3
V
–IN
TA
Operating free-air temperature range
–40 to 85
°C
Tstg
Storage temperature range
–65 to 150
°C
150
°C
Junction temperature (TJ max)
MSOP package
Maximum MSOP reflow temperature
SON package
Maximum SON Reflow Temperature
(1)
2
Power dissipation
θJA thermal impedance
(TJMax – TA)/θJA
°C
180
°C/W
ADS8319 is rated to MSL2 260C per the
JSTD-020 specification
Power dissipation
θJA thermal impedance
(TJMax – TA)/θJA
70
°C/W
ADS8319 is rated to MSL2 260C per the
JSTD-020 specification
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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www.ti.com ........................................................................................................................................................................................................ SLAS600 – MAY 2008
SPECIFICATIONS
TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, fSAMPLE = 500 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input span
(1)
Operating input range
+IN – (–IN)
0
Vref
+IN
– 0.1
Vref + 0.1
–IN
– 0.1
Input capacitance
Input leakage current
During acquisition
V
0.1
59
pF
1000
pA
16
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
16
Bits
ADS8319I
–2.5
±1.2
2.5
ADS8319IB
–1.5
±1
1.5
–1
±0.65
1.5
–1
±0.5
1
INL
Integral linearity (2)
DNL
Differential linearity
EO
Offset error (4)
EG
Gain error
CMRR
Common-mode rejection ratio
With common mode input signal = 200 mVp-p at 500
kHz
PSRR
Power supply rejection ratio
At FFF0h output code
ADS8319I
ADS8319IB
At 16-bit level
LSB (3)
LSB (3)
–1.5
±0.3
1.5
mV
–0.03
±0.0045
0.03
%FSR
78
Transition noise
dB
80
dB
0.5
LSB
SAMPLING DYNAMICS
tCONV
Conversion time
Acquisition time
+VBD = 5 V
1400
+VBD = 3 V
1400
+VBD = 5 V
600
+VBD = 3 V
600
ns
Maximum throughput rate with or
without latency
0.5
Aperture delay
Aperture jitter, RMS
Step response
Overvoltage recovery
(1)
(2)
(3)
(4)
Settling to 16-bit accuracy
ns
MHz
2.5
ns
6
ps
600
ns
600
ns
Ideal input span, does not include gain or offset error.
This is endpoint INL, not best fit.
LSB means least significant bit
Measured relative to actual measured reference.
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ADS8319
SLAS600 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
SPECIFICATIONS (continued)
TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, fSAMPLE = 500 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion
(5)
ADS8319IB
SNR
Signal-to-noise ratio
SINAD
SFDR
Signal-to-noise + distortion
Spurious free dynamic range
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V
–111
VIN 0.4 dB below FS at 10 kHz, Vref = 5 V
–106
VIN 0.4 dB below FS at 100 kHz, Vref = 5 V
–89
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V
dB
92
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V
93.9
VIN 0.4 dB below FS at 10 kHz, Vref = 5 V
93.6
VIN 0.4 dB below FS at 100 kHz, Vref = 5 V
92.2
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V
93.8
VIN 0.4 dB below FS at 10 kHz, Vref = 5 V
93.4
VIN 0.4 dB below FS at 100 kHz, Vref = 5 V
87.4
VIN 0.4 dB below FS at 1 kHz, Vref = 5 V
113
VIN 0.4 dB below FS at 10 kHz, Vref = 5 V
107
VIN 0.4 dB below FS at 100 kHz, Vref = 5 V
90
–3dB Small signal bandwidth
dB
dB
dB
15
MHz
EXTERNAL REFERENCE INPUT
Vref
Input range
2.25
Reference input current
(6)
During conversion
4.096
VDD+0.1
V
µA
250
POWER SUPPLY REQUIREMENTS
Power supply
voltage
+VBD
Supply current
+VA
2.375
3.3
5.5
4.5
5
5.5
V
500-kHz Sample rate
3.6
4.5
mA
+VA
V
PVA
Power dissipation
+VA = 5 V, 500-kHz Sample rate
18
22.5
mW
IVApd
Device power-down current (7)
+VA = 5 V
50
300
nA
LOGIC FAMILY CMOS
VIH
IIH = 5 µA
+(0.7×VBD)
+VBD+0.3
V
VIL
IIL = 5 µA
–0.3
+(0.3×VBD)
V
IOH = 2 TTL loads
+VBD–0.3
+VBD
V
IOL = 2 TTL loads
0
0.4
V
–40
85
°C
VOH
Logic level
VOL
TEMPERATURE RANGE
TA
(5)
(6)
(7)
4
Operating free-air temperature
Calculated on the first nine harmonics of the input frequency
Can vary ±20%
Device automatically enters power-down state at the end of every conversion, and continues to be in power-down state as long as it is
in acquistion phase.
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TIMING REQUIREMENTS
All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD ≥ 4.5 V
PARAMETER
REF FIGURE
MIN
TYP
MAX
UNIT
SAMPLING AND CONVERSION RELATED
tacq
Acquisition time
tcnv
Conversion time
tcyc
Time between conversions
t1
Pulse duration, CONVST high
t6
Pulse duration, CONVST low
600
Figure 46, Figure 48, Figure 50,
Figure 52
ns
1400
ns
2000
ns
Figure 46, Figure 48
10
ns
Figure 50, Figure 52, Figure 54
20
ns
20
ns
9
ns
9
ns
I/O RELATED
tclk
SCLK Period
tclkl
SCLK Low time
tclkh
SCLK High time
t2
SCLK Falling edge to data remains valid
t3
SCLK Falling edge to next data valid delay
ten
Enable time, CONVST or SDI Low to MSB valid
tdis
Disable time, CONVST or SDI high or last SCLK falling edge
to SDO 3-state (CS mode)
t4
Setup time, SDI valid to CONVST rising edge
t5
Hold time, SDI valid from CONVST rising edge
t7
Setup time, SCLK valid to CONVST rising edge
t8
Hold time, SCLK valid from CONVST rising edge
Figure 46, Figure 48, Figure 50,
Figure 52, Figure 54, Figure 56
5
ns
16
ns
Figure 46, Figure 50
15
ns
Figure 46, Figure 48, Figure 50,
Figure 52
12
ns
Figure 50, Figure 52
Figure 54
5
ns
5
ns
5
ns
5
ns
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ADS8319
SLAS600 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
TIMING REQUIREMENTS
All specifications typical at –40°C to 85°C, +VA = 5 V, +4.5 V > +VBD ≥ 2.375 V
PARAMETER
REF FIGURE
MIN
TYP
MAX
UNIT
SAMPLING AND CONVERSION RELATED
tacq
Acquisition time
tcnv
Conversion time
tcyc
Time between conversions
t1
Pulse width CONVST high
t6
Pulse width CONVST low
600
Figure 46, Figure 48, Figure 50,
Figure 52
ns
1400
ns
2000
ns
Figure 46, Figure 48
10
ns
Figure 50, Figure 52, Figure 54
20
ns
30
ns
13
ns
13
ns
I/O RELATED
tclk
SCLK period
tclkl
SCLK low time
tclkh
SCLK high time
t2
SCLK falling edge to data remains valid
t3
SCLK falling edge to next data valid delay
ten
CONVST or SDI low to MSB valid
tdis
CONVST or SDI high or last SCLK falling edge to SDO
3-state (CS mode)
t4
SDI valid setup time to CONVST rising edge
t5
SDI valid hold time from CONVST rising edge
t7
SCLK valid setup time to CONVST rising edge
t8
SCLK valid hold time from CONVST rising edge
Figure 46, Figure 48, Figure 50,
Figure 52, Figure 54, Figure 56
5
ns
Figure 46, Figure 50
22
ns
Figure 46, Figure 48, Figure 50,
Figure 52
15
ns
Figure 50, Figure 52
Figure 54
500µA
ns
24
5
ns
5
ns
5
ns
5
ns
I ol
From
SDO
1.4V
20pF
500µA
I oh
Figure 1. Load Circuit for Digital Interface Timing
0.7 VBD
0.3 VBD
t DELAY
tDELAY
2V
2V
0.8V
0.8V
Figure 2. Voltage Levels for Timing
6
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PIN ASSIGNMENTS
MSOP PACKAGE
(TOP VIEW)
REFIN
+VA
IN+
INGND
1
10
2
9
3
8
4
7
5
6
SON PACKAGE
(TOP VIEW)
+VBD
SDI
SCLK
SDO
CONVST
REFIN
+VA
IN+
INGND
1
10
2
9
3
8
4
7
5
6
+VBD
SDI
SCLK
SDO
CONVST
Terminal Functions
TERMINAL
NO.
I/O
NAME
DESCRIPTION
ANALOG PINS
1
REFIN
I
Reference (positive) input. Decouple with GND pin using 0.1-µF bypass capacitor and 10-µF storage
capacitor.
3
+IN
I
Noninverting analog signal input
4
–IN
I
Inverting analog signal input. Note this input has a limited range of ±0.1 V, and typically it is grounded at the
input decoupling capacitor.
6
CONVST
I
Convert input. It also functions as the CS input in 3-wire interface mode. Refer to Description and Timing
Diagrams sections for more details.
7
SDO
O
Serial data output.
8
SCLK
I
Serial I/O clock input. Data (on SDO o/p) is synchronized with this clock.
9
SDI
I
Serial data input. The SDI level at the start of a conversion selects the mode of operation such as CS or daisy
chain mode. It also serves as the CS input in 4-wire interface mode. Refer to Description and Timing
Diagrmas sections for more details.
I/O PINS
POWER SUPPLY PINS
2
+VA
–
Analog power supply. Decoupled with GND pin.
5
GND
–
Device ground. Note this is a common ground pin for both analog power supply (+VA) and digital I/O supply
(+VBD).
10
+VBD
–
Digital I/O power supply. Decouple with GND pin.
TYPICAL CHARACTERISTICS
OFFSET ERROR
vs
SUPPLY VOLTAGE
GAIN ERROR
vs
SUPPLY VOLTAGE
OFFSET ERROR
vs
REFERENCE VOLTAGE
0.005
-0.2
0
0.0045
-0.35
-0.4
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
TA = 30°C
-0.45
4.75
5
5.25
-0.1
0.0035
0.003
0.0025
0.002
0.0015
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
TA = 30°C
0.001
0.0005
5.5
Offset Error - mV
Gain Error - %FSR
Offset Error - mV
0.004
-0.3
-0.5
4.5
+VBD = 2.7 V,
+VA = 5 V,
fs = 500 KSPS,
TA = 30°C
-0.05
-0.25
0
4.5
4.75
5
5.25
+VA - Supply Voltage - V
+VA - Supply Voltage - V
Figure 3.
Figure 4.
-0.15
-0.2
-0.25
-0.3
5.5
-0.35
2
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
GAIN ERROR
vs
REFERENCE VOLTAGE
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
0.0045
0
0.004
-0.1
0.003
0.0025
0.002
0.0015
+VBD = 2.7 V,
+VA = 5 V,
fs = 500 KSPS,
TA = 30°C
0.001
0.0005
2
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
5
-0.4
-0.5
-0.6
-0.7
GAIN ERROR DRIFT HISTOGRAM
0.004
0.003
0.002
0.001
5
20
35
50
65
0
-40 -25 -10 5
20
35 50 65
TA - Free-Air Temperature - °C
80
Figure 8.
OFFSET ERROR DRIFT HISTOGRAM
DIFFERENTIAL NONLINEARITY
vs
SUPPLY VOLTAGE
1
20
Number of Devices
8
6
4
3
3
20
15
10
5
5
5
1
2
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0.6
DNLMAX
0.4
0.2
0
-0.2
DNLMIN
-0.4
-0.6
-0.8
-1
4.5
-0.5 -0.4 -0.3-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
ppm/°C
-0.5 -0.4-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
ppm/°C
4.75
5
5.25
+VA - Supply Voltage - V
Figure 9.
Figure 10.
Figure 11.
INTEGRAL NONLINEARITY
vs
SUPPLY VOLTAGE
DIFFERENTIAL NONLINEARITY
vs
REFERENCE VOLTAGE
INTEGRAL NONLINEARITY
vs
REFERENCE VOLTAGE
1.5
DNL - Differential Nonlinearity LSBs
INLMAX
0.5
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
TA = 30°C
0
-0.5
INLMIN
-1
4.75
5
5.25
5.5
+VA - Supply Voltage - V
Figure 12.
5.5
1.5
1
1
-1.5
4.5
0
0
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
TA = 30°C
0.8
0.8
INL - Integral Nonlinearity LSBs
10
+VA = 5 V
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS
12 12
DNL - Differential Nonlinearity - LSBs
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS
80
Figure 7.
25
12
Number of Devices
0.005
-0.9
-25 -10
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS
0.006
TA - Free-Air Temperature - °C
14
INL - Integral Nonlinearity LSBs
0.007
-0.8
Figure 6.
8
0.008
-0.3
-1
-40
0
0.009
Gain Error - %FSR
Offset Error - mV
Gain Error - %FSR
0.01
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS
-0.2
0.0035
GAIN ERROR
vs
FREE-AIR TEMPERATURE
DNLMAX
0.6
0.4
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
TA = 30°C
0.2
0
-0.2
DNLMIN
-0.4
-0.6
INLMAX
1
0.5
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
TA = 30°C
0
-0.5
INLMIN
-1
-0.8
-1.5
-1
2
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
Figure 13.
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2
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
5
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1
0.8
0.6
DNLMAX
0.4
0.2
0
-0.2
DNLMIN
-0.4
+VA = 5 V
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS
-0.6
-0.8
-1
-40
-25 -10 5
20 35 50 65
TA - Free-Air Temperature - °C
+VA = 5 V
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS
0.2
0
-0.2
-0.4
-0.6
-0.8
INLMIN
-25
-10
5
20 35
50 65
TA - Free-Air Temperature - °C
80
15.4
15.3
15.2
15.1
15
4.5
4.75
5
5.25
+VA - Supply Voltage - V
5.5
SPURIOUS FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE
15.2
15
14.8
14.6
14.4
14.2
2.5
3
3.5
4
4.5
15.9
15.8
15.7
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
fi = 1.9 kHz
15.6
15.5
15.4
15.3
15.2
15.1
15
-40 -25
14
2
15.5
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
5
SFDR - Spurious Free Dynamic Range - dB
15.4
15.6
EFFECTIVE NUMBER OF BITS
vs
REFERENCE VOLTAGE
16
15.6
15.7
Figure 17.
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
15.8
15.8
Figure 16.
ENOB - Effective Number Of Bits - LSBs
Vref - Reference Voltage - V
-10
5
20 35
50 65
TA - Free-Air Temperature - °C
80
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
119
117
115
113
111
109
107
105
4.5
4.75
5
5.25
+VA - Supply Voltage - V
5.5
Figure 18.
Figure 19.
Figure 20.
SIGNAL-TO-NOISE + DISTORTION
vs
SUPPLY VOLTAGE
SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE
TOTAL HARMONIC DISTORTION
vs
SUPPLY VOLTAGE
94.5
119
SNR - Signal-to-Noise Ratio - dB
94
94.5
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
93.5
93
92.5
92
4.5
4.75
5
5.25
+VA - Supply Voltage - V
5.5
Figure 21.
THD - Total Harmonic Distortion - dB
ENOB - Effective Number Of Bits - LSBs
0.6
0.4
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
15.9
Figure 15.
16
SINAD - Signal-to-Noise and Distortion - dB
16
INLMAX
-1
-40
80
EFFECTIVE NUMBER OF BITS
vs
SUPPLY VOLTAGE
ENOB - Effective Number Of Bits - LSBs
1
0.8
INL - Integral Nonlinearity - LSBs
INL - Integral Nonlinearity LSBs
DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
94
93.5
93
92.5
92
4.5
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
4.75
5
5.25
+VA - Supply Voltage - V
Figure 22.
5.5
117
115
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
113
111
109
107
105
4.5
4.75
5
5.25
+VA - Supply Voltage - V
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
115
113
111
109
107
105
2
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
SIGNAL-TO-NOISE RATIO
vs
REFERENCE VOLTAGE
95
95
94.5
94.5
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
94
93.5
93
SNR - Signal-to-Noise Ratio - dB
117
SIGNAL-TO-NOISE + DISTORTION
vs
REFERENCE VOLTAGE
SINAD - Signal-to-Noise + Distortion - dB
SFDR - Spurious Free Dynamic Range - dB
SPURIOUS FREE DYNAMIC RANGE
vs
REFERENCE VOLTAGE
92.5
92
91.5
91
93.5
93
92.5
92
91.5
91
90.5
90.5
90
5
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
94
2
2.5
3
3.5
4
4.5
90
2
5
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
5
Vref - Reference Voltage - V
Figure 25.
Figure 26.
TOTAL HARMONIC DISTORTION
vs
REFERENCE VOLTAGE
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE + DISTORTION
vs
FREE-AIR TEMPERATURE
113
111
109
107
105
2
2.5
3
3.5
4
4.5
Vref - Reference Voltage - V
5
113
SFDR
111
109
107
105
103
-40
SINAD
94
93
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
fi = 1.9 kHz
92
91
90
-40
80
-25
-10
5
20
35
50
65
80
TA - Free-Air Temperature - °C
Figure 29.
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE + DISTORTION
vs
SIGNAL INPUT FREQUENCY
117
SNR
94
93
92
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
fi = 1.9 kHz
91
90
-40
-25 -10
5
20 35 50 65
TA - Free-Air Temperature - °C
95
Figure 28.
-25
-10
5
20 35 50 65
TA - Free-Air Temperature - °C
80
Figure 30.
THD - Total Harmonic Distortion
SNR - Signal-to-Noise Ratio - dB
115
115
95
96
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
fi = 1.9 kHz
Figure 27.
96
10
117
SINAD - Signal-to-noise + Distortion - dB
115
+VA = 5 V,
+VBD = 2.7 V,
fs = 500 KSPS,
fi = 1.9 kHz,
TA = 30°C
113
95
SINAD - Signal-To-Noise + Distortion - dB
THD - Total Harmonic Distortion - dB
117
SFDR - Spurious Free Dynamic Range - dB
Figure 24.
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
fi = 1.9 kHz
111
THD
109
107
105
103
-40
-25
-10
5
20 35 50 65
TA - Free-Air Temperature - °C
Figure 31.
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80
94
SINAD @ -10 dB
93
92
91
SINAD @ -0.5 dB
90
89
88
87
1
+VA = 5 V
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
TA = 30°C
10
fi - Signal Input Frequency - kHz
100
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION
vs
SIGNAL INPUT FREQUENCY
300000
125
115
THD @ -0.5 dB
105
150000
100000
95
THD @ -10 dB
85
50000
75
0
1
10
fi - Signal Input Frequency - kHz
100
101
32765
0
32766
Codes
108
104
102
100
0
400
500
SUPPLY CURRENT
vs
SAMPLING FREQUENCY
3.7
3500
+VA = 5 V
+VBD = 2.7 V,
fs = 500 KSPS
3.5
3.4
3.3
3.5
3.2
3.45
3000
4.75
5
5.25
+VA - Supply Voltage - V
3.0
-40
5.5
+VA = 5 V,
+VBD = 2.7 V,
TA = 30°C
2500
2000
1500
1000
500
3.1
3.4
-25 -10 5
20 35 50 65
TA - Free-Air Temperature - °C
0
0
80
100
200
300
400
fs - sampling frequency - kSPS
Figure 36.
Figure 37.
Figure 38.
POWER DISSIPATION
vs
SAMPLING FREQUENCY
POWERDOWN CURRENT
vs
SUPPLY VOLTAGE
POWERDOWN CURRENT
vs
FREE-AIR TEMPERATURE
14
12
10
8
6
4
2
180
160
140
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 0.0 KSPS,
TA = 30°C
450
Iavdd-PD - Powerdown Current - nA
Iavdd-pd - Powerdown Current - nA
+VA = 5 V,
+VBD = 2.7 V,
Vref = 5 V,
TA = 30°C
120
100
80
60
40
20
0
100
200
300
400
fs - sampling frequency - kSPS
500
Figure 39.
0
4.5
500
500
200
20
600
4000
Iavdd - Supply Current - mA
3.8
3.55
0
300
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
3.6
16
200
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
3.65
18
100
Source Resistance - W
3.6
3.35
4.5
+VA = 5V, +VBD = 2.7 V,
Vref = 5 V, fi = 1.9 kHz,
fs = 500 KSPS, TA = 30°C
106
Figure 35.
Iavdd - Supply Current - mA
3.7
680 pF
100 pF
32767
3.9
3.75
110
Figure 34.
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 500 KSPS,
TA = 30°C
3.8
0 pF
112
Figure 33.
3.85
Iavdd - Supply Current - mA
114
262043
THD - Total Harmonic Distortion - dB
+VA = 5 V,
+VBD = 2.7 V,
250000 Vref = 5 V,
fs = 500 KSPS,
T = 30°C
200000 A
+VA = 5 V
+VBD = 2.7 V,
Vref = 5 V,
fs = 500 KSPS,
TA = 30°C
Hits
THD - Total Harmonic Distortion - dB
135
Iavdd*VA - Power Dissipation - mW
TOTAL HARMONIC DISTORTION
vs
SOURCE RESISTANCE
DC HISTORAM OF ADC CLOSE TO
CENTER CODE
5
+VA - Supply Voltage - V
Figure 40.
5.5
400
350
+VA = 5 V
+VBD = 2.7 V,
Vref = 4.096 V,
fs = 0.0 KSPS
300
250
200
150
100
50
0
-40
-25
-10 5
20 35
50 65
TA - Free-Air Temperature - °C
Figure 41.
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TYPICAL CHARACTERISTICS (continued)
DNL - LSB
DNL
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
+VA = 5 V, +VBD = 2.7 V,
Vref = 5 V, fs = 500 KSPS,
TA = 30°C
0
10000
20000
30000
40000
Codes
Figure 42.
50000
60000
INL - LSB
INL
1
0.8
0.6
0.4
0.2
+VA = 5 V, +VBD = 2.7 V,
Vref = 5 V, fs = 500 KSPS,
TA = 30°C
0
-0.2
-0.4
-0.6
-0.8
-1
0
10000
20000
30000
40000
50000
60000
Codes
Figure 43.
Amplitude - dB
FFT
0
-20
-40
-60
-80
+VA = 5 V, +VBD = 2.7 V,
Vref = 5 V, fi = 1.9 kHz,
fs = 500 KSPS, TA = 30°C
-100
-120
-140
-160
-180
-200
0
50000
100000
150000
200000
250000
f - Frequency - Hz
Figure 44.
12
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DETAILED DESCRIPTIONS AND TIMING DIAGRAMS
The ADS8319 is a high-speed, low power, successive approximation register (SAR) analog-to-digital converter
(ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently
includes a sample/hold function.
The ADS8319 is a single channel device. The analog input is provided to two input pins: +IN and -IN where -IN is
a pseudo differential input and it has a limited range of ±0.1 V. When a conversion is initiated, the differential
input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both +IN and
-IN inputs are disconnected from any internal function.
The ADS8319 has an internal clock that is used to run the conversion, and hence the conversion requires a fixed
amount of time. After a conversion is completed, the device reconnects the sampling capacitors to the +IN and
–IN pins, and the device is in the acquisition phase. During this phase the device is powered down and
conversion data can be read.
The device digital output is available in SPI compatible format. It easily interfaces with microprocessors, DSPs, or
FPGAs.
This is a low pin count device; however, it offers six different options for the interface. They can be grossly
classified as CS mode (3- or 4-wire interface) and daisy chain mode. In both modes it can either be with or
without a busy indicator, where the busy indicator is a bit preceeding the 16-bit serial data.
The 3-wire interface CS mode is useful for applications which need galvanic isolation on-board, where as 4-wire
interface CS mode makes it easy to control an individual device while having multiple devices on-board. The
daisy chain mode is provided to hook multiple devices in a chain like a shift register and is useful to reduce
component count and the number of signal traces on the board.
CS MODE
CS Mode is selected if SDI is high at the rising edge of CONVST. As indicated before there are four different
interface options available in this mode, namely 3-wire CS mode without busy indicator, 3-wire CS mode with
busy indicator, 4-wire CS mode without busy indicator, 4-wire CS mode with busy indicator. The following section
discusses these interface options in detail.
3-Wire CS Mode Without Busy Indicator
Digital Host
ADS8319
+VBD
SDI
CONVST
CNV
SCLK
CLK
SDO
SDI
Figure 45. Connection Diagram, 3-Wire CS Mode without Busy Indicator (SDI = 1)
The three wire interface option in CS mode is selected if SDI is tied to +VBD (see Figure 45). In the three wire
interface option, CONVST acts like CS. As shown in Figure 46, the device samples the input signal and enters
the conversion phase on the rising edge of CONVST, at the same time SDO goes to 3-state. Conversion is done
with the internal clock and it continues irrespective of the state of CONVST. As a result it is possible to bring
CONVST (acting as CS) low after the start of the conversion to select other devices on the board. But it is
absolutely necessary that CONVST is high again before the minimum conversion time (tcnv in timing
requirements table) is elapsed. A high level on CONVST at the end of the conversion ensures the device does
not generate a busy indicator.
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When the conversion is over, the device enters the acquisition phase and powers down. On the falling edge of
CONVST, SDO comes out of three state, and the device outputs the MSB of the data. After this, the device
outputs the next lower data bits on every falling edge of SCLK. SDO goes to 3-state after the 16th falling edge of
SCLK or CONVST high, whichever occurs first. It is necessary that the device sees a minimum of 15 falling
edges of SCLK during the low period of CONVST.
tcyc
t1
CONVST
tacq
tcnv
ACQUISITION
CONVERSION
ACQUISITION
tclkl
t2
SCLK
1
2
ten
t3
SDO
D15
16
15
tclkh
tdis
tclk
D14
D1
D0
Figure 46. Interface Timing Diagram, 3 Wire CS Mode Without Busy Indicator (SDI = 1)
3 Wire CS Mode With Busy Indicator
Digital Host
ADS8319
CNV
CONVST
SDI
SCLK
+ VBD
SDO
CLK
SDI
IRQ
Figure 47. Connection Diagram, 3 Wire CS Mode With Busy Indicator
The three wire interface option in CS mode is selected if SDI is tied to +VBD (see Figure 47). In the three wire
interface option, CONVST acts like CS. As shown in Figure 48, the device samples the input signal and enters
the conversion phase on the rising edge of CONVST, at the same time SDO goes to 3 state. Conversion is done
with the internal clock and it continues irrespective of the state of CONVST. As a result it is possible to toggle
CONVST (acting as CS) after the start of the conversion to select other devices on the board. But it is absolutely
necessary that CONVST is low again before the minimum conversion time (tcnv in timing requirements table) is
elapsed and continues to stay low until the end of maximum conversion time. A low level on the CONVST input
at the end of a conversion ensures the device generates a busy indicator.
When the conversion is over, the device enters the acquisition phase and powers down, and the device forces
SDO out of three state and outputs a busy indicator bit (low level). The device outputs the MSB of data on the
first falling edge of SCLK after the conversion is over and continues to output the next lower data bits on every
subsequent falling edge of SCLK. SDO goes to three state after the 17th falling edge of SCLK or CONVST high,
whichever occurs first. It is necessary that the device sees a minimum of 16 falling edges of SCLK during the low
period of CONVST.
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tcyc
t1
CONVST
tacq
tcnv
ACQUISITION
CONVERSION
ACQUISITION
tclkl
t2
1
SCLK
2
3
16
t3
SDO
D15
tclk
D14
D1
17
tclkh
tdis
D0
Figure 48. Interface Timing Diagram, 3 Wire CS Mode With Busy Indicator (SDI = 1)
4 Wire CS Mode Without Busy Indicator
CS1
CS2
CNV
CONVST
SDI
CONVST
SDO
SCLK
SDI
SDO
SDI
SCLK
CLK
ADS8319#1
ADS8319#2
Digital Host
Figure 49. Connection Diagram, 4 Wire CS Mode Without Busy Indicator
As mentioned before for selecting CS mode it is necessary that SDI is high at the time of the CONVST rising
edge. Unlike in three wire interface option, SDI is controlled by digital host and acts like CS. As shown in
Figure 50, SDI goes to a high level before the rising edge of CONVST. The rising edge of CONVST while SDI is
high selects CS mode, forces SDO to three state, samples the input signal, and the device enters the conversion
phase. In the 4 wire interface option CONVST needs to be at a high level from the start of the conversion until all
of the data bits are read. Conversion is done with the internal clock and it continues irrespective of the state of
SDI. As a result it is possible to bring SDI (acting as CS) low to select other devices on the board. But it is
absolutely necessary that SDI is high again before the minimum conversion time (tcnv in timing requirements
table) is elapsed.
When the conversion is over, the device enters the acquisition phase and powers down. SDI falling edge can
occur after the maximum conversion time (tcnv in timing requirements table). Note that it is necessary that SDI is
high at the end of the conversion, so that the device does not generate a busy indicator. The falling edge of SDI
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brings SDO out of 3-state and the device outputs the MSB of the data. Subsequent to this the device outputs the
next lower data bits on every falling edge of SCLK. SDO goes to three state after the 16th falling edge of SCLK or
SDI (CS) high, whichever occurs first. As shown in Figure 49, it is possible to hook multiple devices on the same
data bus. In this case the second device SDI (acting as CS) can go low after the first device data is read and
device 1 SDO is in three state.
Care needs to be taken so that CONVST and SDI are not low together at any time during the cycle.
t6
CONVST
SDI (CS) #1
t4
t5
SDI (CS) #2
tcnv
ACQUISITION
tacq
CONVERSION
ten
ACQUISITION
tclkl
t2
SCLK
1
2
ten
t3
SDO
D15#1
D14#1
17
16
15
tclkh
D0#1
32
tdis
tdis
tclk
D1#1
31
18
D15#2 D14#2
D1#2
D0#2
Figure 50. Interface Timing Diagram, 4 Wire CS Mode Without Busy Indicator
4 Wire CS Mode With Busy Indicator
CS
SDI
CNV
CONVST
+ VBD
SDO
ADS8319
CLK
SDI
IRQ
Digital Host
Figure 51. Connection Diagram, 4 Wire CS Mode With Busy Indicator
As mentioned before for selecting CS mode it is necessary that SDI is high at the time of the CONVST rising
edge. Unlike in the three wire interface option, SDI is controlled by the digital host and acts like CS. As shown in
Figure 52, SDI goes to a high level before the rising edge of CONVST. The rising edge of CONVST while SDI is
high selects CS mode, forces SDO to three state, samples the input signal, and the device enters the conversion
phase. In the 4 wire interface option CONVST needs to be at a high level from the start of the conversion until all
of the data bits are read. Conversion is done with the internal clock and it continues irrespective of the state of
SDI. As a result it is possible to toggle SDI (acting as CS) to select other devices on the board. But it is
absolutely necessary that SDI is low before the minimum conversion time (tcnv in timing requirements table) is
elapsed and continues to stay low until the end of the maximum conversion time. A low level on the SDI input at
the end of a conversion ensures the device generates a busy indicator.
When the conversion is over, the device enters the acquisition phase and powers down, forces SDO out of three
state, and outputs a busy indicator bit (low level). The device outputs the MSB of the data on the first falling edge
of SCLK after the conversion is over and continues to output the next lower data bits on every falling edge of
SCLK. SDO goes to three state after the 17th falling edge of SCLK or SDI (CS) high, whichever occurs first.
16
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Care needs to be taken so that CONVST and SDI are not low together at any time during the cycle.
tcyc
t6
CNVST
t5
SDI (CS) t
4
tacq
tcnv
ACQUISITION
CONVERSION
ACQUISITION
tclkh
t2
1
SCLK
2
3
t3
SDO
D15
17
16
tclkl
tdis
tclk
D14
D1
D0
Figure 52. Interface Timing Diagram, 4 Wire CS Mode With Busy Indicator
Daisy Chain Mode
Daisy chain mode is selected if SDI is low at the time of CONVST rising edge. This mode is useful to reduce
wiring and hardware like digital isolators in the applications where multiple (ADC) devices are used. In this mode
all of the devices are connected in a chain (SDO of one device connected to the SDI of the next device) and data
transfer is analogous to a shift register.
Like CS mode even this mode offers operation with or without a busy indicator. The following section discusses
these interface options in detail.
Daisy Chain Mode Without Busy Indicator
CNV
CONVST
SDI
CONVST
SDO
SCLK
ADS8319#2
SDI
SDO
SDI
SCLK
ADS8319#1
CLK
Digital Host
Figure 53. Connection Diagram, Daisy Chain Mode Without Busy Indicator (SDI = 0)
Refer to Figure 53 for the connection diagram. SDI for device 1 is tied to ground and SDO of device 1 goes to
SDI of device 2 and so on. SDO of the last device in the chain goes to the digital host. CONVST for all of the
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devices in the chain are tied together. In this mode there is no CS signal. The device SDO is driven low when
SDI low selects daisy chain mode and the device samples the analog input and enters the conversion phase. It is
necessary that SCLK is low at the rising edge of CONVST so that the device does not generate a busy indicator
at the end of the conversion. In this mode CONVST continues to be high from the start of the conversion until all
of the data bits are read. Once started, conversion continues irrespective of the state of SCLK.
At the end of the conversion, every device in the chain initiates output of its conversion data starting with the
MSB bit. Further the next lower data bit is output on every falling edge of SCLK. While every device outputs its
data on the SDO pin, it also receives previous device data on the SDI pin (other than device #1) and stores it in
the shift register. The device latches incoming data on every falling edge of SCLK. SDO of the first device in the
chain goes low after the 16th falling edge of SCLK. All subsequent devices in the chain output the stored data
from the previous device in MSB first format immediately following their own data word.
It needs 16 × N clocks to read data for N devices in the chain.
tcyc
t6
CONVST
tacq
tcnv
ACQUISITION
ACQUISITION
CONVERSION
t7
tclkl
t2
SCLK
1
2
16
15
t8
tclk
#1-D15
SDO #1, SDI #2
#1-D14
17
18
31
32
#2-D1
#2-D0
tclkh
#1-D1
#1-D0
#1-D1
#1-D0 #2-D15
t3
SDO #2
#1-D15
#1-D14
#2-D14
Figure 54. Interface Timing Diagram, Daisy Chain Mode Without Busy Indicator
Daisy Chain Mode With Busy Indicator
CNV
CONVST
SDI
CONVST
SDO
SCLK
ADS8319#2
SDI
IRQ
SDO
SDI
SCLK
ADS8319#1
CLK
Digital Host
Figure 55. Connection Diagram, Daisy Chain Mode With Busy Indicator (SDI = 0)
Refer to Figure 55 for the connection diagram. SDI for device 1 is wired to it's CONVST and CONVST for all the
devices in the chain are wired together. SDO of device 1 goes to SDI of device 2 and so on. SDO of the last
device in the chain goes to the digital host. In this mode there is no CS signal. On the rising edge of CONVST,
all of the device in the chain sample the analog input and enter the conversion phase. For the first device, SDI
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ADS8319
www.ti.com ........................................................................................................................................................................................................ SLAS600 – MAY 2008
and CONVST are wired together, and the setup time of SDI to rising edge of CONVST is adjusted so that the
device still enters chain mode even though SDI and CONVST rise together. It is necessary that SCLK is high at
the rising edge of CONVST so that the device generates a busy indicator at the end of the conversion. In this
mode, CONVST continues to be high from the start of the conversion until all of the data bits are read. Once
started, conversion continues irrespective of the state of SCLK.
At the end of the conversion, all the devices in the chain generate busy indicators. On the first falling edge of
SCLK following the busy indicator bit, all of the devices in the chain output their conversion data starting with the
MSB bit. After this the next lower data bit is output on every falling edge of SCLK. While every device outputs its
data on the SDO pin, it also receives the previous device data on the SDI pin (except for device #1) and stores it
in the shift register. Each device latches incoming data on every falling edge of SCLK. SDO of the first device in
the chain goes high after the 17th falling edge of SCLK. All subsequent devices in the chain output the stored
data from the pervious device in MSB first format immediately following their own data word. It needs 16 × N + 1
clock pulses to read data for N devices in the chain.
tcyc
t6
CONVST
tacq
tcnv
ACQUISITION
ACQUISITION
CONVERSION
t7
tclkl
t2
1
SCLK
2
3
16
t8
SDO #1, SDI #2
17
18
19
32
33
#2-D14
#2-D1
#2-D0
tclk
tclkh
#1-D15
#1-D14
#1-D1
#1-D0
#1-D1
#1-D0 #2-D15
t3
SDO #2
#1-D15
#1-D14
Figure 56. Interface Timing Diagram, Daisy Chain Mode With Busy Indicator
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19
ADS8319
SLAS600 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
APPLICATION INFORMATION
ANALOG INPUT
When the converter samples the input, the voltage difference between the +IN and -IN inputs is captured on the
internal capacitor array. The voltage on the +IN is limited between GND –0.1 V and Vref + 0.1 V and on -IN is
limited between GND-0.1 to GND+0.1V; where as the differential signal range is [(+IN) – (–IN)]. This allows the
input to reject small signals which are common to both the +IN and –IN inputs.
The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input
voltage, and source impedance. The current into the ADS8319 charges the internal capacitor array during the
sample period. After this capacitance has been fully charged, there is no further input current. The source of the
analog input voltage must be able to charge the input capacitance (59 pF) to a 18-bit settling level within the
minimum acquisition time. When the converter goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN
and -IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, converter
linearity may not meet specifications.
Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are
matched. If this is not observed, the two inputs could have different settling times. This may result in an offset
error, gain error, and linearity error which change with temperature and input voltage. Typically the -IN input is
grounded at the input decoupling capacitor.
Device in Hold Mode
218 W
+IN
55 pF
4 pF
+VA
AGND
4 pF
218 W
-IN
55 pF
Figure 57. Input Equivalent Circuit
DRIVER AMPLIFIER CHOICE
The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031, OPA211. An
RC filter is recommended at the input pins to low-pass filter the noise from the source. A resistor of 5Ω and a
capacitor of 1nF is recommended. The input to the converter is a unipolar input voltage in the range 0 V to Vref.
The minimum –3dB bandwidth of the driving operational amplifier can be calculated as:
f3db = (ln(2) × (n+2))/(2π × tACQ)
where n is equal to 16, the resolution of the ADC (in the case of the ADS8319). When tACQ = 600 ns (minimum
acquisition time), the minimum bandwidth of the driving circuit is ~3 MHz (including RC following the driver OPA).
The bandwidth can be relaxed if the acquisition time is increased by the application.
Typically a low noise OPA with ten times or higher bandwidth is selected. The driving circuit bandwidth is
adjusted (to the required value) with a RC following the OPA. The OPA211 or THS4031 from Texas Instruments
is recommended for driving high-resolution high-speed ADCs.
DRIVER AMPLIFIER CONFIGURATIONS
It is better to use a unity gain, noninverting buffer configuration. As explained before a RC following the OPA
limits the input circuit bandwidth just enough for 16-bit settling. Note higher bandwidth reduces the settling time
(beyond what is needed) but increases the noise in the ADC sampled signal, and hence the ADC output.
20
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ADS8319
www.ti.com ........................................................................................................................................................................................................ SLAS600 – MAY 2008
0-Vref
+VA
+
THS4031
or OPA211
ADS8319
5W
+IN
1nF
50 W
-IN
5W
Figure 58. Input Drive Configuration
REFERENCE
The ADS8319 can operate with an external reference with a range from 2.25 V to VDD + 0.1 V. A clean, low
noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A
low noise band-gap reference like the REF5040, REF5050 can be used to drive this pin. A ceramic decoupling
capacitor is required between the REF+ and GND pins of the converter (see Figure 59). The capacitor should be
placed as close as possible to the pins of the device.
50 W
REF5050
OUT
+
+
-
47 mF,
1.5 W ESR
(High ESR)
10 mF
OPA365
REFIN
TRIM
+
-
4.7 mF,
Low ESR
IN +
ADS8319
IN -
Figure 59. External Reference Driving Circuit
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ADS8319
SLAS600 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
REF5050
OUT
+
-
22 mF
47 mF,
1.5 W ESR
(High ESR)
REFIN
TRIM
+
-
4.7 mF,
Low ESR
IN +
ADS8319
IN -
Figure 60. Direct External Reference Driving Circuit
POWER SAVING
The ADS8319 has an auto power-down feature. The device powers down at the end of every conversion. The
input signal is acquired on sampling capacitors while the device is in the power-down state, and at the same time
the conversion results are available for reading. The device powers up by itself on the start of the conversion. As
discussed before, the conversion runs on an internal clock and takes a fixed time. As a result, device power
consumption is directly proportional to the speed of operation.
DIGITAL OUTPUT
As discussed before (in the DESCRIPTION and TIMING DIAGRAMS sections) the device digital output is SPI
compatible. The following table lists the output codes corresponding to various analog input voltages.
DESCRIPTION
ANALOG VALUE (V)
DIGITAL OUTPUT STRAIGHT BINARY
Full-scale range
Vref
Least significant bit (LSB)
Vref/65536
Positive full scale
+Vref – 1 LSB
1111 1111 1111 1111
FFFF
Midscale
Vref/2
1000 0000 0000 0000
8000
Midscale – 1 LSB
Vref/2– 1 LSB
0111 1111 1111 1111
7FFF
Zero
0
0000 0000 0000 0000
0000
BINARY CODE
HEX CODE
SCLK INPUT
The device uses SCLK for serial data output. Data is read after the conversion is over and the device is in the
acquisition phase. It is possible to use a free running SCLK for the device, but it is recommended to stop the
clock during a conversion, as the clock edges can couple with the internal analog circuit and can affect
conversion results.
22
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS8319IBDGSR
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8319IBDGST
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8319IBDRCR
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS8319IBDRCT
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS8319IDGSR
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8319IDGST
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS8319IDRCR
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS8319IDRCT
ACTIVE
SON
DRC
10
250
CU NIPDAU
Level-3-260C-168 HR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS8319IBDGSR
MSOP
DGS
10
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS8319IBDGST
MSOP
DGS
10
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS8319IBDRCR
SON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS8319IBDRCT
SON
DRC
10
250
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS8319IDGSR
MSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS8319IDGST
MSOP
DGS
10
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS8319IDRCR
SON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS8319IDRCT
SON
DRC
10
250
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS8319IBDGSR
MSOP
DGS
10
2500
346.0
346.0
29.0
ADS8319IBDGST
MSOP
DGS
10
250
346.0
346.0
29.0
ADS8319IBDRCR
SON
DRC
10
3000
340.5
333.0
20.6
ADS8319IBDRCT
SON
DRC
10
250
340.5
333.0
20.6
ADS8319IDGSR
MSOP
DGS
10
2500
346.0
346.0
29.0
ADS8319IDGST
MSOP
DGS
10
250
346.0
346.0
29.0
ADS8319IDRCR
SON
DRC
10
3000
340.5
333.0
20.6
ADS8319IDRCT
SON
DRC
10
250
340.5
333.0
20.6
Pack Materials-Page 2
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