Maxim MAX1265ACEI 265ksps, 3v, 6-/2-channel, 12-bit adcs with 2.5v reference and parallel interface Datasheet

19-2721; Rev 0; 04/03
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Power consumption is only 5.4mW at the maximum
sampling rate of 265ksps. Two software-selectable
power-down modes enable the MAX1265/MAX1267 to
be shut down between conversions; accessing the parallel interface returns them to normal operation.
Powering down between conversions can reduce supply current below 10µA at lower sampling rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differential operation. In single-ended mode, the MAX1265 has
six input channels and the MAX1267 has two (three
input channels and one input channel, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power, combined with ease of use and small package size, make
these converters ideal for battery-powered and dataacquisition applications or for other circuits with demanding power-consumption and space requirements. The
MAX1265 is offered in a 28-pin QSOP package, while the
MAX1267 comes in a 24-pin QSOP. For pin-compatible
+5V, 12-bit versions, refer to the MAX1266/MAX1268
data sheet.
Applications
Industrial Control Systems
Data Logging
Energy Management
Patient Monitoring
Data-Acquisition Systems
Touch Screens
TEMP RANGE
PIN-PACKAGE
♦ 12-Bit Resolution, ±0.5 LSB Linearity
♦ +3V Single-Supply Operation
♦ Internal +2.5V Reference
♦ Software-Configurable Analog Input Multiplexer
6-Channel Single Ended/
3-Channel Pseudo Differential (MAX1265)
2-Channel Single Ended/
1-Channel Pseudo Differential (MAX1267)
♦ Software-Configurable Unipolar/Bipolar
Analog Inputs
♦ Low Current
1.9mA (265ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)
♦ Internal 3MHz Full-Power Bandwidth Track/Hold
♦ Parallel 12-Bit Interface
♦ Small Footprint
28-Pin QSOP (MAX1265)
24-Pin QSOP (MAX1267)
Pin Configurations
TOP VIEW
D9 1
28 D10
D8 2
27 D11
D7 3
26 VDD
D6 4
25 REF
D5 5
D4 6
Ordering Information
PART
Features
INL
(LSB)
24 REFADJ
MAX1265
23 GND
D3 7
22 COM
D2 8
21 CH0
D1 9
20 CH1
D0 10
19 CH2
INT 11
18 CH3
MAX1265ACEI
0°C to +70°C
28 QSOP
±0.5
MAX1265BCEI
0°C to +70°C
28 QSOP
±1
MAX1265AEEI
-40°C to +85°C
28 QSOP
±0.5
RD 12
17 CH4
MAX1265BEEI
-40°C to +85°C
28 QSOP
±1
WR 13
16 CH5
MAX1267ACEG
0°C to +70°C
24 QSOP
±0.5
CLK 14
15 CS
MAX1267BCEG
0°C to +70°C
24 QSOP
±1
MAX1267AEEG -40°C to +85°C
24 QSOP
±0.5
MAX1267BEEG -40°C to +85°C
24 QSOP
±1
QSOP
Pin Configurations continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1265/MAX1267
General Description
The MAX1265/MAX1267 low-power, 12-bit analog-todigital converters (ADCs) feature a successive-approximation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed 12-bit parallel interface. They operate with
a single +2.7V to +3.6V analog supply.
MAX1265/MAX1267
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
CH0–CH5, COM to GND ............................-0.3V to (VDD + 0.3V)
REF, REFADJ to GND.................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND ...............................................-0.3V to +6V
Digital Outputs (D0–D11, INT) to GND.......-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW
28-Pin QSOP (derate 8.0mW/°C above +70°C)..........667mW
Operating Temperature Ranges
MAX1265_C_ _ /MAX1267_C_ _ ........................0°C to +70°C
MAX1265_E_ _ /MAX1267_E_ _ ......................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle),
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
12
RES
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
Bits
MAX126_A
±0.5
MAX126_B
±1
No missing codes overtemperature
±1
LSB
±4
LSB
Offset Error
Gain Error
±4
(Note 3)
LSB
LSB
Gain Temperature Coefficient
±2.0
ppm/°C
Channel-to-Channel Offset
Matching
±0.2
LSB
DYNAMIC SPECIFICATIONS (fIN(sine-wave) = 50kHz, VIN = 2.5VP-P, 265ksps, external fCLK = 4.8MHz, bipolar input mode)
Signal-to-Noise Plus Distortion
SINAD
Total Harmonic Distortion
(Including 5th-Order Harmonic)
THD
Spurious-Free Dynamic Range
SFDR
Intermodulation Distortion
IMD
67
70
dB
-78
80
dB
76
fIN1 = 49kHz, fIN2 = 52kHz
dB
dB
Channel-to-Channel Crosstalk
fIN = 125kHz (Note 4)
-78
dB
Full-Linear Bandwidth
SINAD > 68dB
250
kHz
Full-Power Bandwidth
-3dB rolloff
3
MHz
CONVERSION RATE
Conversion Time (Note 5)
tCONV
Track/Hold Acquisition Time
tACQ
Aperture Delay
Aperture Jitter
External Clock Frequency
Duty Cycle
2
fCLK
External clock mode
3.3
External acquisition/internal clock mode
2.5
3.0
Internal acquisition/internal clock mode
3.2
3.6
3.5
4.1
625
External acquisition or external clock mode
50
External acquisition or external clock mode
<50
Internal acquisition/internal clock mode
<200
µs
ns
ns
ps
0.1
4.8
MHz
30
70
%
_______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
(VDD = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle),
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION
RATE (continued)
ANALOG
INPUTS
Analog Input Voltage Range
Single Ended and Differential
(Note 6)
VIN
Multiplexer Leakage Current
Unipolar, VCOM = 0
bipolar, VCOM = VREF / 2
0
- VREF/2
±0.01
On-/off-leakage current, VIN = 0 or VDD
Input Capacitance
VREF
+ VREF/2
±1
12
CIN
V
µA
pF
INTERNAL REFERENCE
2.49
REF Output Voltage
REF Short-Circuit Current
REF Temperature Coefficient
TCREF
REFADJ Input Range
For small adjustments
REFADJ High Threshold
To power down the internal reference
Load Regulation (Note 7)
0 to 0.5mA output load
2.5
2.51
15
mA
±20
ppm/°C
±100
mV
VDD - 1
V
0.2
0.01
mV/mA
1
µF
4.7
10
µF
1.0
VDD +
50mV
V
Capacitive Bypass at REFADJ
Capacitive Bypass at REF
V
EXTERNAL REFERENCE AT REF
REF Input Voltage Range
VREF
REF Input Current
IREF
200
VREF = 2.5V, fSAMPLE = 265ksps
300
2
Shutdown mode
µA
DIGITAL INPUTS AND OUTPUTS
Input Voltage High
VIH
Input Voltage Low
VIL
Input Hysteresis
2.0
200
VHYS
Input Leakage Current
IIN
Input Capacitance
CIN
Output Voltage Low
VOL
ISINK = 1.6mA
Output Voltage High
VOH
ISOURCE = 1mA
Tri-State Leakage Current
Tri-State Output Capacitance
V
0.8
±0.1
VIN = 0 or VDD
V
mV
±1
15
µA
pF
0.4
VDD - 0.5
V
V
ILEAKAGE
CS = VDD
±0.1
COUT
CS = VDD
15
±1
µA
pF
POWER REQUIREMENTS
Analog Supply Voltage
2.7
VDD
Operating mode,
fSAMPLE = 265ksps
Positive Supply Current
IDD
Standby mode
2.5
2.8
External reference
1.9
2.3
Internal reference
0.9
1.2
External reference
0.5
0.8
Shutdown mode
Power-Supply Rejection
PSR
3.6
Internal reference
VDD = 2.7V to 3.6V, full-scale input
V
mA
2
10
µA
±0.4
±0.9
mV
_______________________________________________________________________________________
3
MAX1265/MAX1267
ELECTRICAL CHARACTERISTICS (continued)
MAX1265/MAX1267
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle),
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLK Period
tCP
208
ns
CLK Pulse Width High
tCH
40
ns
CLK Pulse Width Low
tCL
40
ns
Data Valid to WR Rise Time
tDS
40
ns
WR Rise to Data Valid Hold Time
tDH
0
ns
WR to CLK Fall Setup Time
tCWS
40
ns
CLK Fall to WR Hold Time
tCWH
40
ns
CS to CLK or WR Setup Time
tCSWS
60
ns
CLK or WR to CS Hold Time
tCSWH
0
ns
CS Pulse Width
tCS
100
ns
WR Pulse Width
tWR
(Note 8)
60
CS Rise to Output Disable
tTC
CLOAD = 20pF, Figure 1
20
100
ns
RD Rise to Output Disable
tTR
CLOAD = 20pF, Figure 1
20
70
ns
RD Fall to Output Data Valid
tDO
CLOAD = 20pF, Figure 1
20
70
ns
RD Fall to INT High Delay
tINT1
CLOAD = 20pF, Figure 1
100
ns
CS Fall to Output Data Valid
tDO2
CLOAD = 20pF, Figure 1
110
ns
ns
Note 1: Tested at VDD = +3V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
VDD
DOUT
3kΩ
6kΩ
CLOAD
20pF
DOUT
CLOAD
20pF
a) HIGH-Z TO VOH AND VOL TO VOH
b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for Enable/Disable Times
4
_______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.4
0.3
0.2
0.1
0.1
DNL (LSB)
0.2
0
-0.1
0
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
-0.5
3000
4000
10
WITH EXTERNAL REFERENCE
0
0
5000
1000
SUPPLY CURRENT vs. SUPPLY VOLTAGE
5000
0.1
IDD (mA)
1.95
RL = ∞
CODE = 101010100000
1.9
1.90
1.8
1.85
1.7
1.80
3.3
3.6
10k 100k
920
900
890
880
-40
-15
10
35
60
2.7
85
3.0
3.3
3.6
VDD (V)
STANDBY CURRENT
vs. TEMPERATURE
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs. TEMPERATURE
1.25
1.00
880
35
TEMPERATURE (°C)
60
85
1.0
0.8
0.50
10
1.1
0.9
0.75
890
1.2
POWER-DOWN IDD (µA)
POWER-DOWN IDD (µA)
900
MAX1265/67 toc07
1.50
MAX1265/67 toc06
910
1M
910
TEMPERATURE (°C)
920
-15
1k
VDD (V)
930
-40
100
930
1.6
3.0
10
STANDBY CURRENT vs. SUPPLY VOLTAGE
2.0
2.7
1
fSAMPLE (Hz)
2.1
2.00
IDD (mA)
4000
STANDBY IDD (µA)
RL = ∞
CODE = 101010100000
2.05
STANDBY IDD (µA)
3000
SUPPLY CURRENT vs. TEMPERATURE
2.2
MAX1265/67 toc03
2.10
2000
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
MAX1265/67 toc05
2000
100
MAX1265/67 toc08
1000
WITH INTERNAL REFERENCE
1000
MAX1265/67 toc04
0
10,000
IDD (µA)
0.3
MAX1265/67 toc02A
0.4
INL (LSB)
0.5
MAX1265/67 toc01
0.5
SUPPLY CURRENT
vs. SAMPLE FREQUENCY
MAX1265/67 toc02B
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
2.7
3.0
3.3
VDD (V)
3.6
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX1265/MAX1267
Typical Operating Characteristics
(VDD = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25°C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.51
2.50
2.50
2.49
2.49
-0.5
OFFSET ERROR (LSB)
2.51
OFFSET ERROR vs. SUPPLY VOLTAGE
0
MAX1265/67 toc10
2.52
VREF (mA)
2.52
3.0
2.7
3.3
-2.5
-40
3.6
-15
10
60
35
85
OFFSET ERROR vs. TEMPERATURE
3.3
-1.0
-1.5
MAX1265/67 toc13
0
-1.0
-2.0
60
85
-0.5
-1.0
-2.0
-3.0
35
0
-1.5
-2.0
-2.5
0.5
GAIN ERROR (LSB)
-0.5
2.7
3.0
TEMPERATURE (°C)
3.3
3.6
-40
-15
10
VDD = 3V
fIN = 50kHz
fSAMPLE = 250ksps
AMPLITUDE (dB)
-20
MAX1265/67 toc15
FFT PLOT
0
-40
-60
-80
-100
-120
-140
0
200
400
35
TEMPERATURE (°C)
VDD (V)
20
600
800
1000
FREQUENCY (kHz)
6
3.6
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR (LSB)
0
10
3.0
VDD (V)
1.0
MAX1265/67 toc12
0.5
-15
2.7
TEMPERATURE (°C)
VDD (V)
-40
-1.5
-2.0
2.48
2.48
-1.0
MAX1265/67 toc14
VREF (V)
2.53
MAX1265/67 toc09
2.53
MAX1265/67 toc11
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
OFFSET ERROR (LSB)
MAX1265/MAX1267
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________
60
85
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
PIN
NAME
FUNCTION
MAX1265
MAX1267
1
1
D9
Tri-State Digital Output (D9)
2
2
D8
Tri-State Digital Output (D8)
3
3
D7
Tri-State Digital I/O Line (D7)
4
4
D6
Tri-State Digital I/O Line (D6)
5
5
D5
Tri-State Digital I/O Line (D5)
6
6
D4
Tri-State Digital I/O Line (D4)
7
7
D3
Tri-State Digital I/O Line (D3)
8
8
D2
Tri-State Digital I/O Line (D2)
9
9
D1
Tri-State Digital I/O Line (D1)
10
10
D0
Tri-State Digital I/O Line (D0)
11
11
INT
INT goes low when the conversion is complete and output data is ready.
12
12
RD
Active-Low Read Select. If CS is low, a falling edge on RD enables the read operation on the data bus.
13
13
WR
Active-Low Write Select. When CS is low in the internal acquisition mode, a rising
edge on WR latches in configuration data and starts an acquisition plus a conversion cycle. When CS is low in external acquisition mode, the first rising edge on WR
ends acquisition and starts a conversion.
14
14
CLK
Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock.
In internal clock mode, connect this pin to either VDD or GND.
15
15
CS
16
—
CH5
Analog Input Channel 5
17
—
CH4
Analog Input Channel 4
18
—
CH3
Analog Input Channel 3
19
—
CH2
Analog Input Channel 2
20
16
CH1
Analog Input Channel 1
21
17
CH0
Analog Input Channel 0
22
18
COM
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode
and must be stable to ±0.5 LSB during conversion.
23
19
GND
Analog and Digital Ground
24
20
REFADJ
Active-Low Chip Select. When CS is high, digital outputs (D11–D0) are high
impedance.
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with
a 0.01µF capacitor. When using an external reference, connect REFADJ to VDD to
disable the internal bandgap reference.
_______________________________________________________________________________________
7
MAX1265/MAX1267
Pin Description
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
MAX1265/MAX1267
Pin Description (continued)
PIN
NAME
FUNCTION
21
REF
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor
to GND when using the internal reference.
26
22
VDD
Analog +2.7V to +3.6V Power Supply. Bypass with a 0.1µF capacitor to GND.
27
23
D11
Tri-State Digital Output (D11)
28
24
D10
Tri-State Digital Output (D10)
MAX1265
MAX1267
25
REF
REFADJ
AV =
2.05
(CH5)
(CH4)
(CH3)
(CH2)
CH1
CH0
1.22V
REFERENCE
T/H
ANALOG
INPUT
MULTIPLEXER
CHARGE REDISTRIBUTION
12-BIT DAC
COMP
12
COM
CLK
17kΩ
SUCCESSIVEAPPROXIMATION
REGISTER
CLOCK
CS
WR
RD
INT
CONTROL LOGIC
AND
LATCHES
MAX1265
MAX1267
VDD
12
TRI-STATE, BIDIRECTIONAL
I/O INTERFACE
GND
D0–D11
12-BIT DATA BUS
( ) ARE FOR MAX1265 ONLY.
Figure 2. Simplified Functional Diagram of 6-/2-Channel MAX1265/MAX1267
________________Detailed Description
Converter Operation
The MAX1265/MAX1267 ADCs use a successiveapproximation (SAR) conversion technique and an input
track/hold (T/H) stage to convert an analog input signal
to a 12-bit digital output. This output format provides an
easy interface to standard microprocessors (µPs). Figure
2 shows the simplified internal architecture of the
MAX1265/MAX1267.
8
Single-Ended and
Pseudo-Differential Operation
The sampling architecture of the ADC’s analog comparator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH5 for the MAX1265
(Figure 3a) and to CH0–CH1 for the MAX1267 (Figure
3b), while IN- is switched to COM (Table 2). In differential mode, IN+ and IN- are selected from analog input
pairs (Table 3) and are internally switched to either of
_______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. At the
12-BIT CAPACITIVE DAC
12-BIT CAPACITIVE DAC
VREF
CH0
VREF
COMPARATOR
INPUT
CHOLD
MUX –
+
ZERO
CH0
12pF
CH2
CSWITCH
CH3
RIN
800Ω
CH1
CSWITCH
HOLD
TRACK
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
CH4
T/H
SWITCH
CH5
ZERO
12pF
RIN
800Ω
CH1
COMPARATOR
INPUT
CHOLD
MUX –
+
COM
T/H
SWITCH
COM
SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1, CH2/CH3, AND CH4/CH5
HOLD
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR
CH0/CH1
Figure 3a. MAX1265 Simplified Input Structure
Figure 3b. MAX1267 Simplified Input Structure
Table 1. Control-Byte Functional Description
BIT
NAME
FUNCTIONAL DESCRIPTION
PD1 and PD0 select the various clock and power-down modes.
D7, D6
D5
D4
D3
D2, D1, D0
PD1, PD0
0
0
Full power-down mode. Clock mode is unaffected.
0
1
Standby power-down mode. Clock mode is unaffected.
1
0
Normal operation mode. Internal clock mode selected.
1
1
Normal operation mode. External clock mode selected.
ACQMOD
ACQMOD = 0: Internal acquisition mode
ACQMOD = 1: External acquisition mode
SGL/DIF
SGL/DIF = 0: Pseudo-differential analog input mode
SGL/DIF = 1: Single-ended analog input mode
In single-ended mode, input signals are referred to COM. In differential mode, the voltage difference
between two channels is measured (Tables 2 and 4).
UNI/BIP
UNI/BIP = 0: Bipolar mode
UNI/BIP = 1: Unipolar mode
In unipolar mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the
signal can range from -VREF/2 to +VREF/2.
A2, A1, A0
Address bits A2, A1, A0 select which of the 6/2 (MAX1265/MAX1267) channels are to be converted
(Tables 2 and 3).
_______________________________________________________________________________________
9
MAX1265/MAX1267
end of the acquisition interval, the T/H switch opens,
retaining charge on CHOLD as a sample of the signal
at IN+.
The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the
negative input (IN-). This unbalances node zero at the
comparator’s positive input. The capacitive digital-toanalog converter (DAC) adjusts during the remainder
the analog inputs. This configuration is pseudo-differential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
MAX1265/MAX1267
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 2. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
A2
A1
A0
CH0
0
0
0
+
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
CH1
CH2*
CH3*
CH4*
CH5*
COM
-
+
+
+
+
+
-
*Channels CH2–CH5 apply to MAX1265 only.
Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
A2
A1
A0
CH0
CH1
0
0
0
+
-
CH2*
CH3*
CH4*
CH5*
0
0
1
-
+
0
1
0
+
-
0
1
1
-
+
1
0
0
+
-
1
0
1
-
+
*Channels CH2–CH5 apply to MAX1265 only.
of the conversion cycle to restore node 0 to 0V within
the limits of 12-bit resolution. This action is equivalent to
transferring a 12pF (VIN+ - VIN-) charge from CHOLD to
the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and GND, allow each input channel to
swing within (GND - 300mV) to (VDD + 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD + 50mV) or be
less than (GND - 50mV).
If an analog input voltage exceeds the supplies by
more than 50mV, limit the forward-bias input current to
4mA.
Track/Hold
The MAX1265/MAX1267 T/H stage enters its tracking
mode on WR’s rising edge. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this is approximately 1µs after writing the control
byte.
10
In single-ended operation, IN- is connected to COM
and the converter samples the positive (+) input. In
pseudo-differential operation, IN- connects to the negative (-) input, and the difference of |(IN+) - (IN-)| is sampled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the following equation:
tACQ = 9(RS + RIN)CIN
where RS is the source impedance of the input signal,
RIN (800Ω) is the input resistance, and CIN (12pF) is
the input capacitance of the ADC. Source impedances
below 3kΩ have no significant impact on the MAX1265/
MAX1267s’ AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
MAX1265/MAX1267
tCS
CS
tACQ
tCSWS
tCSWH
tWR
tCONV
WR
tDH
tDS
CONTROL
BYTE
D11–D0
ACQMOD = 0
tINT1
INT
RD
tTR
tD0
HIGH-Z
VALID DATA
DOUT
HIGH-Z
Figure 4. Conversion Timing Using Internal Acquisition Mode
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
Input Bandwidth
The MAX1265/MAX1267 T/H stage offers a 250kHz fulllinear and a 3MHz full-power bandwidth. This makes it
possible to digitize high-speed transients and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
Starting a Conversion
Initiate a conversion by writing a control byte that selects
the multiplexer channel and configures the MAX1265/
MAX1267 for either unipolar or bipolar operation. A
write pulse (WR + CS) can either start an acquisition
interval or initiate a combined acquisition plus conversion. The sampling interval occurs at the end of the
acquisition interval. The acquisition mode (ACQMOD)
bit in the input control byte (Table 1) offers two options
for acquiring the signal: an internal and an external
acquisition. The conversion period lasts for 13 clock
cycles in either the internal or external clock or acquisition mode. Writing a new control byte during a conversion cycle aborts the conversion and starts a new
acquisition interval.
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval (three external clock
cycles or approximately 1µs in internal clock mode)
ends (Figure 4). Note that, when the internal acquisition
is combined with the internal clock, the aperture jitter
can be as high as 200ps. Internal clock users wishing
to achieve the 50ps jitter specification should always
use external acquisition mode.
______________________________________________________________________________________
11
MAX1265/MAX1267
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
tCS
CS
tCSWS
tWR
tACQ
tCSWH
tCONV
WR
tDH
tDS
CONTROL
BYTE
ACQMOD = 1
D11–D0
CONTROL
BYTE
ACQMOD = 0
tINT1
INT
RD
tD0
HIGH-Z
tTR
HIGH-Z
VALID DATA
DOUT
Figure 5. Conversion Timing Using External Acquisition Mode
External Acquisition
Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisition and conversion times. The user controls acquisition
and start of conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0 (all other bits in
control byte unchanged), terminates acquisition and
starts conversion on WR rising edge (Figure 5).
The address bits for the input multiplexer must have the
same values on the first and second write pulse.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see Power-Down
Modes section). Changing other bits in the control byte
corrupts the conversion.
Reading a Conversion
A standard interrupt signal, INT, is provided to allow the
MAX1265/MAX1267 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
12
when the conversion is complete and the output data is
ready (Figures 4 and 5). It returns high on the first read
cycle or if a new control byte is written.
Selecting Clock Mode
The MAX1265/MAX1267 operate with either an internal
or an external clock. Control bits D6 and D7 select
either internal or external clock mode. The part retains
the last-requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock mode, internal or external acquisition
can be used. At power-up, the MAX1265/MAX1267
enter the default external clock mode.
Internal Clock Mode
Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. Bit D7 of
the control byte must be set to 1 and bit D6 must be set
to zero. The internal clock frequency is then selected,
resulting in a conversion time of 3.6µs. When using the
internal clock mode, tie the CLK pin either high or low
to prevent the pin from floating.
______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
MAX1265/MAX1267
ACQUISITION STARTS
CONVERSION STARTS
ACQUISITION ENDS
tCP
CLK
tCWS
tCH
WR
tCL
WR GOES HIGH WHEN CLK IS HIGH.
ACQMOD = 0
tCWH
ACQUISITION STARTS
CONVERSION STARTS
ACQUISITION ENDS
CLK
WR
ACQMOD = 0
WR GOES HIGH WHEN CLK IS LOW.
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
ACQUISITION ENDS
ACQUISITION STARTS
CONVERSION STARTS
CLK
tCWS
tDH
WR
ACQMOD = 0
ACQMOD = 1
WR GOES HIGH WHEN CLK IS HIGH
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
tCWH
tDH
WR
ACQMOD = 1
WR GOES HIGH WHEN CLK IS LOW
ACQMOD = 0
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
External Clock Mode
To select the external clock mode, bits D6 and D7 of
the control byte must be set to 1. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. For proper operation, a 100kHz to
4.8MHz clock frequency with 30% to 70% duty cycle is
recommended. Operating the MAX1265/MAX1267 with
clock frequencies lower than 100kHz is not recommended, because the resulting voltage droop across the hold
capacitor in the T/H stage degrades performance.
Digital Interface
The input and output data are multiplexed on a tri-state
parallel interface (I/O) that can easily be interfaced with
standard µPs. The signals CS, WR, and RD control the
write and read operations. CS represents the chip-
______________________________________________________________________________________
13
MAX1265/MAX1267
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 4. Control-Byte Format
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
PD1
PD0
ACQMOD
SGL/DIF
UNI/BIP
A2
A1
A0
An internal buffer is designed to provide +2.5V at REF for
both the MAX1265 and MAX1267. The internally trimmed
+1.22V reference is buffered with a +2.05V/V gain.
VDD = +3V
50kΩ
MAX1265
MAX1267
330kΩ
50kΩ
REFADJ
REF
GND
0.01µF
4.7µF
GND
Figure 7. Reference Adjustment with External Potentiometer
select signal, which enables a µP to address the
MAX1265/MAX1267 as an I/O port. When high, CS disables the CLK, WR, and RD inputs and forces the interface into a high-impedance (high-Z) state.
Input Format
The control bit sequence is latched into the device on
pins D7–D0 during a write command. Table 4 shows
the control-byte format.
Output Data Format
The 12-bit-wide output format for both the MAX1265/
MAX1267 is binary in unipolar mode and two’s complement in bipolar mode. CS, RD, WR, INT, and the 12 bits
of output data can interface directly to a 16-bit data bus.
When reading the output data, CS and RD must be low.
__________Applications Information
Internal Reference
The full-scale range with the internal reference is +2.5V
with unipolar inputs and ±1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
(±100mV) in the reference voltage (Figure 7).
Note: The reference buffer must be compensated with
an external capacitor (4.7µF min) connected between
REF and GND to reduce reference noise and switching
spikes from the ADC. To further minimize noise on the
reference, connect a 0.01µF capacitor between REFADJ
and GND.
External Reference
With both the MAX1265 and MAX1267, an external reference can be placed at either the input (REFADJ) or the
output (REF) of the internal reference buffer amplifier.
Using the REFADJ input makes buffering the external
reference unnecessary. The REFADJ input impedance
is typically 17kΩ.
When applying an external reference to REF, disable
the internal reference buffer by connecting REFADJ to
V DD . The DC input resistance at REF is 25kΩ.
Therefore, an external reference at REF must deliver up
to 200µA DC load current during a conversion and
have an output impedance less than 10Ω. If the reference has higher output impedance or is noisy, bypass
it close to the REF pin with a 4.7µF capacitor.
Power-On Reset
Power-Down Modes
When power is first applied, internal power-on reset circuitry activates the MAX1265/MAX1267 in external clock
mode and sets INT high. After the power supplies stabilize, the internal reset time is 10µs; no conversions
should be attempted during this phase. When using the
internal reference, 500µs is required for VREF to stabilize.
To save power, place the converter in a low-current
shutdown state between conversions. Select standby
mode or shutdown mode using bits D6 and D7 of the
control byte (Tables 1 and 4). In both software powerdown modes, the parallel interface remains active, but
the ADC does not convert.
Internal and External Reference
Standby Mode
While in standby mode, the supply current is typically
850µA. The part powers up on the next rising edge of
WR and is ready to perform conversions. This quick
turn-on time allows the user to realize significantly
reduced power consumption for conversion rates
below 265ksps.
The MAX1265/MAX1267 can be used with an internal
or external reference voltage. An external reference
can be connected directly to REF or REFADJ.
14
______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
MAX1265/MAX1267
Table 5. Full Scale and Zero Scale for Unipolar and Bipolar Operation
UNIPOLAR MODE
BIPOLAR MODE
Zero scale
COM
Zero scale
Full scale
VREF + COM
Positive full scale
VREF/2 + COM
Negative full scale
-VREF/2 + COM
OUTPUT CODE
OUTPUT CODE
111 . . . 111
FS = REF + COM
111 . . . 110
ZS = COM
1 LSB =
100 . . . 010
FULL-SCALE
TRANSITION
REF
4096
FS =
011 . . . 110
ZS = COM
000 . . . 001
000 . . . 000
100 . . . 000
REF
+ COM
2
011 . . . 111
000 . . . 010
100 . . . 001
-REF
+ COM
2
REF
1 LSB =
4096
-FS =
111 . . . 111
011 . . . 111
111 . . . 110
011 . . . 110
111 . . . 101
011 . . . 101
100 . . . 001
000 . . . 001
100 . . . 000
000 . . . 000
0 1
(COM)
COM
2
- FS
FS
2048
INPUT VOLTAGE (LSB)
COM*
+FS - 1 LSB
INPUT VOLTAGE (LSB)
FS - 3/2 LSB
Figure 8. Unipolar Transfer Function
Shutdown Mode
Shutdown mode turns off all chip functions that draw quiescent current, reducing the typical supply current to
2µA immediately after the current conversion is completed. A rising edge on WR causes the MAX1265/MAX1267
to exit shutdown mode and return to normal operation.
To achieve full 12-bit accuracy with a 4.7µF reference
bypass capacitor, 50µs is required after power-up.
Waiting 50µs in standby mode, instead of in full-power
mode, can reduce power consumption by a factor of 3 or
more. When using an external reference, only 50µs is
required after power-up. Enter standby mode by performing a dummy conversion with the control byte specifying standby mode.
Note: Bypass capacitors larger than 4.7µF between
REF and GND result in longer power-up delays.
*COM ≤ VREF / 2
Figure 9. Bipolar Transfer Function
Transfer Function
Table 5 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figure 8 depicts the nominal unipolar input/output (I/O) transfer function, and Figure 9
shows the bipolar I/O transfer function. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1 LSB = (VREF / 4096).
Maximum Sampling Rate/
Achieving 300ksps
When running at the maximum clock frequency of
4.8MHz, the specified throughput of 265ksps is achieved
by completing a conversion every 18 clock cycles: 1
write cycle, 3 acquisition cycles, 13 conversion cycles,
and 1 read cycle. This assumes that the results of the
last conversion are read before the next control byte is
written. It is possible to achieve higher throughputs, up
to 300ksps, by first writing a control byte to begin the
______________________________________________________________________________________
15
MAX1265/MAX1267
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
1
CLK
WR
RD
; ;
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D11–D0
CONTROL
WORD
D7–D0
D11–
D0
CONTROL WORD
ACQUISITION
STATE
CONVERSION
ACQUISITION
SAMPLING INSTANT
Figure 10. Timing Diagram for Fastest Conversion
the data bus during acquisition or conversion can
cause additional supply noise, which can make it difficult to achieve true 12-bit performance.
SUPPLIES
Layout, Grounding, and Bypassing
+3V
*R = 5Ω
+3V
GND
+3V
DGND
4.7µF
0.1µF
VDD
GND
MAX1265
MAX1267
COM
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 11. Power-Supply and Grounding Connections
acquisition cycle of the next conversion, then reading the
results of the previous conversion from the bus. This
technique (Figure 10) allows a conversion to be completed every 16 clock cycles. Note that the switching of
16
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one star point (Figure 11) connecting the two ground
systems (analog and digital). For lowest noise operation, ensure the ground return to the star ground’s
power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply, VDD, could
impair operation of the ADC’s fast comparator. Bypass
VDD to the star ground with a network of two parallel
capacitors, 0.1µF and 4.7µF, located as close as to the
MAX1265/MAX1267s’ power-supply pin as possible.
Minimize capacitor lead length for best supply-noise
rejection and add an attenuation resistor (5Ω) if the
power supply is extremely noisy.
______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1265/MAX1267 is measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD (dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number
of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
Aperture Jitter
Total Harmonic Distortion
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Aperture Delay
Aperture delay (t AD ) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
SNR = (6.02 ✕ N + 1.76)dB
In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.

THD = 20 x log 

(V
2
2
)

+ V32 + V42 + V52 / V1

where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest distortion component.
Chip Information
TRANSISTOR COUNT: 5781
SUBSTRATE CONNECTED TO GND
______________________________________________________________________________________
17
MAX1265/MAX1267
Definitions
MAX1265/MAX1267
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Circuits
CLK
CLK
+3V
MAX1265 VDD
µP
CONTROL
INPUTS
CS
REF
WR
REFADJ
RD
D11
INT
0.1µF
µP
4.7µF CONTROL
INPUTS
CS
REF
WR
REFADJ
OUTPUT STATUS
D11
D10
D9
D9
D8
D8
D7
D7
D5
D4
D3
D2
D1
D0
CH5
D5
CH3
D4
ANALOG
INPUTS
4.7µF
INT
OUTPUT STATUS
D3
CH1
D2
CH0
D1
COM
D0
CH1
ANALOG
INPUTS
CH0
COM
GND
GND
µP DATA BUS
0.1µF
D6
CH4
CH2
+2.5V
RD
D10
D6
+3V
MAX1267 VDD
+2.5V
µP DATA BUS
Pin Configurations (continued)
TOP VIEW
D9 1
24 D10
D8 2
23 D11
D7 3
22 VDD
D6 4
21 REF
D5 5
D4 6
20 REFADJ
MAX1267
19 GND
D3 7
18 COM
D2 8
17 CH0
D1 9
16 CH1
D0 10
15 CS
INT 11
14 CLK
RD 12
13 WR
QSOP
18
______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________19
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX1265/MAX1267
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)