19-3273; Rev 3; 9/11 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock The MAX7033 fully integrated low-power CMOS superheterodyne receiver is ideal for receiving amplitudeshift-keyed (ASK) data in the 300MHz to 450MHz frequency range. The receiver has an RF input signal range of -114dBm to 0dBm. With few external components and a low-current power-down mode, it is ideal for cost-sensitive and power-sensitive applications typical in the automotive and consumer markets. The MAX7033 consists of a low-noise amplifier (LNA), a fully differential image-rejection mixer, an on-chip phaselocked loop (PLL) with integrated voltage-controlled oscillator (VCO), a 10.7MHz IF limiting amplifier stage with received-signal-strength indicator (RSSI), and analog baseband data-recovery circuitry. The MAX7033 also has a discrete one-step automatic gain control (AGC) that reduces the LNA gain by 35dB when the RF input signal exceeds -62dBm. The AGC circuitry offers an externally controlled hold feature. The MAX7033 is available in 28-pin TSSOP and 32-pin TQFN packages and is specified over the extended (-40°C to +105°C) temperature range. Features o Optimized for 315MHz or 433MHz Band o Operates from Single +3.3V or +5.0V Supplies o High Dynamic Range with On-Chip AGC o AGC Hold Circuit o 1ms AGC Release Time o Selectable Image-Rejection Center Frequency o Selectable x64 or x32 fLO/fXTAL Ratio o Low 5.2mA Operating Supply Current o < 3.5µA Low-Current Power-Down Mode for Efficient Power Cycling o 250µs Startup Time o Built-In 44dB RF Image Rejection o Better than -114dBm Receive Sensitivity o -40°C to +105°C Operation Applications Automotive Remote Keyless Entry Security Systems Home Automation Garage Door Openers Remote Controls Local Telemetry Wireless Sensors Typical Application Circuit appears at end of data sheet. Ordering Information PART TEMP RANGE PIN-PACKAGE MAX7033EUI+ -40°C to +105°C 28 TSSOP MAX7033ETJ+ -40°C to +105°C 32 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. 25 DATAOUT AGND 5 LNAOUT 6 MAX7033 AVDD XTAL1 XTAL2 SHDN PDOUT N.C. 29 28 27 26 25 26 PDOUT LNASRC 4 LNAIN 27 SHDN LNAIN 3 30 28 XTAL2 AVDD 2 LNASRC + XTAL1 1 31 TOP VIEW 32 Pin Configurations + N.C. 1 24 DATAOUT 24 VDD5 AGND 2 23 VDD5 23 DSP LNAOUT 3 22 DSP AVDD 7 22 DFFB AVDD 4 21 N.C. MIXIN1 8 21 OPP MIXIN1 5 20 DFFB MIXIN2 9 20 DSN MIXIN2 6 19 OPP AGND 10 19 DFO AGND 7 18 DSN IRSEL 11 18 IFIN2 IRSEL 8 17 DFO MIXOUT 12 17 IFIN1 13 14 15 16 N.C. XTALSEL IFIN1 IFIN2 12 11 DVDD AC 9 TSSOP 10 15 AC DGND 16 XTALSEL DVDD 14 MIXOUT DGND 13 MAX7033 TQFN ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX7033 General Description MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock ABSOLUTE MAXIMUM RATINGS VDD5 to AGND.......................................................-0.3V to +6.0V AVDD to AGND .....................................................-0.3V to +4.0V DVDD to DGND .....................................................-0.3V to +4.0V AGND to DGND.....................................................-0.1V to +0.1V IRSEL, DATAOUT, XTALSEL, AC, SHDN to AGND .............................-0.3V to (VDD5 + 0.3V) All Other Pins to AGND ..........................-0.3V to (VDVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 28-Pin TSSOP (derate 12.8mW/°C above +70°C) ..1025.6mW 32-Thin QFN (derate 21.3mW/°C above +70°C) ....1702.1mW Operating Temperature Range .........................-40°C to +105°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering 10s) ..................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (+3.3V OPERATION) (Typical Application Circuit, VAVDD = VDVDD = VDD5 = +3.0V to +3.6V, no RF signal applied, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD5 = +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL Supply Voltage VAVDD, VDVDD Supply Current IDD Shutdown Supply Current ISHDN Input-Voltage Low VIL Input-Voltage High VIH Input Logic Current High IIH CONDITIONS MIN TYP MAX UNITS +3.3V nominal supply voltage 3.0 3.3 3.6 V fRF = 315MHz 5.2 6.23 fRF = 433MHz 5.7 6.88 fRF = 315MHz 2.6 fRF = 433MHz 3.5 V SHDN = VDVDD V SHDN = 0V, VXTALSEL = 0V 0.4 VDVDD - 0.4 fRF = 375MHz, VIRSEL = VDD5/2 DATAOUT Output-Voltage High VOL VOH V μA VDD5 0.4 VDD5 1.0 1.1 fRF = 315MHz, VIRSEL = 0V DATAOUT Output-Voltage Low μA V 10 fRF = 433MHz, VIRSEL = VDD5 Image-Reject Select Voltage (Note 2) 8.0 mA V 0.4 ISINK = 10μA ISOURCE = 10μA 0.125 V VDVDD - 0.125 V DC ELECTRICAL CHARACTERISTICS (+5.0V OPERATION) (Typical Application Circuit, VDD5 = +4.5V to +5.5V, no RF signal applied, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS +5.0V nominal supply voltage 4.5 5.0 5.5 V Supply Voltage VDD5 Supply Current IDD V SHDN = VDD5 ISHDN V SHDN = 0V, VXTALSEL = 0V Shutdown Supply Current Input-Voltage Low 2 fRF = 315MHz 5.2 6.4 fRF = 433MHz 5.7 6.76 fRF = 315MHz 3.7 fRF = 433MHz 4.2 VIL _______________________________________________________________________________________ 9.8 0.4 mA μA V 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock (Typical Application Circuit, VDD5 = +4.5V to +5.5V, no RF signal applied, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25°C.) (Note 1) PARAMETER SYMBOL Input-Voltage High VIH Input Logic Current High IIH CONDITIONS TYP MAX VDD5 0.4 fRF = 375MHz, VIRSEL = VDD5/2 UNITS V 15 fRF = 433MHz, VIRSEL = VDD5 Image-Reject Select Voltage (Note 2) MIN μA VDD5 0.4 VDD5 1.5 1.1 fRF = 315MHz, VIRSEL = 0V V 0.4 DATAOUT Output-Voltage Low VOL ISINK = 10μA 0.125 V DATAOUT Output-Voltage High VOH ISOURCE = 10μA VDD5 0.125 V AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, VAVDD = VDVDD = VDD5 = +3.0V to +3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD5 = +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS Startup Time tON Receiver Input Frequency fRF Maximum Receiver Input Level Time for valid signal detection after V SHDN = VDVDD 300 Modulation depth >18dB Sensitivity (Note 3) Maximum Data Rate μs 450 0 Average carrier power level -120 Peak power level -114 LNA gain from low to high AGC Hysteresis 250 MHz dBm dBm 8 dB Switching time from low to high gain 1 ms Manchester coded 33 NRZ coded 66 kbps LNA IN HIGH-GAIN MODE 1 - j3.4 fRF = 375MHz 1 - j3.9 fRF = 315MHz 1 - j4.7 ZIN_LNA 1dB Compression Point P1dBLNA -22 dBm IIP3LNA -12 dBm -80 dBm 3 dB Input-Referred 3rd-Order Intercept LO Signal Feedthrough to Antenna Noise Figure NFLNA Normalized to 50Ω fRF = 433MHz Input Impedance _______________________________________________________________________________________ 3 MAX7033 DC ELECTRICAL CHARACTERISTICS (+5.0V OPERATION) (continued) MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, VAVDD = VDVDD = VDD5 = +3.0V to +3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD5 = +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LNA IN LOW-GAIN MODE Input Impedance 1dB Compression Point Input-Referred 3rd-Order Intercept ZIN_LNA Normalized to 50Ω (Note 4) fRF = 433MHz 1 - j3.4 fRF = 375MHz 1 - j3.9 fRF = 315MHz 1 - j4.7 P1dBLNA -10 dBm IIP3LNA -7 dBm -80 dBm 3 dB 35 dB IIP3MIX -18 dBm ZOUT_MIX 330 Ω 16 dB LO Signal Feedthrough to Antenna Noise Figure NFLNA Voltage-Gain Reduction AGC enabled (depends on tank Q) MIXER Input-Referred 3rd-Order Intercept Output Impedance Noise Figure NFMIX Image Rejection (Not Including LNA Tank) LNA/Mixer Voltage Gain fRF = 433MHz, VIRSEL = VDVDD 42 fRF = 375MHz, VIRSEL = VDVDD/2 44 fRF = 315MHz, VIRSEL = 0V 44 LNA in high-gain mode 48 LNA in low-gain mode 13 330Ω IF filter load dB dB INTERMEDIATE FREQUENCY (IF) Input Impedance Operating Frequency ZIN_IF fIF Bandpass response 3dB Bandwidth RSSI Linearity RSSI Dynamic Range RSSI Level AGC Threshold 330 Ω 10.7 MHz 10 MHz ±0.5 dB 80 dB PRFIN < -120dBm 1.15 PRFIN > 0dBm, AGC enabled 2.2 LNA gain from low to high 1.39 LNA gain from high to low 1.98 V V DATA FILTER Maximum Bandwidth 50 kHz 100 kHz DATA SLICER Comparator Bandwidth 4 _______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock (Typical Application Circuit, VAVDD = VDVDD = VDD5 = +3.0V to +3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VDD5 = +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL Maximum Load Capacitance CONDITIONS MIN CLOAD TYP MAX UNITS 10 pF Output High Voltage VDD5 V Output Low Voltage 0 V CRYSTAL OSCILLATOR VXTALSEL = 0V fRF = 433MHz Crystal Frequency (Note 5) 6.6128 VXTALSEL = VDD5 fXTAL fRF = 315MHz 13.2256 VXTALSEL = 0V 4.7547 VXTALSEL = VDD5 9.5094 Crystal Tolerance Input Capacitance From each pin to ground MHz 50 ppm 6.2 pF Note 1: 100% tested at TA = +25°C. Guaranteed by design and characterization over temperature. Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image-rejection setting is desired. Bypass to AGND with a 1nF capacitor in a noisy environment. Note 3: BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz. Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance includes the 15nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 50Ω in series with 2.2pF. Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (fRF - 10.7MHz)/64 for XTALSEL = 0V, and (fRF - 10.7MHz)/32 for XTALSEL = VDD5. Typical Operating Characteristics (Typical Application Circuit , VAVDD = VDVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) +85°C 5.2 5.0 4.8 4.6 +25°C -40°C MAX7033 toc02 +105°C 6.0 5.5 5.0 +85°C +25°C 4.0 4.4 4.2 6.5 4.5 3.2 3.3 1 fRF = 315MHz 0.1 -40°C 0.01 3.0 3.1 fRF = 433MHz 10 3.5 4.0 3.0 100 BIT-ERROR RATE (%) SUPPLY CURRENT (mA) +105°C SUPPLY CURRENT (mA) 5.8 5.4 7.0 MAX7033 toc01 6.0 5.6 BIT-ERROR RATE vs. AVERAGE CARRIER POWER SUPPLY CURRENT vs. RF FREQUENCY MAX7033 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 250 300 350 400 RF FREQUENCY (MHz) 450 500 -130 -128 -126 -124 -122 -120 -118 -116 -114 AVERAGE CARRIER POWER (dBm) _______________________________________________________________________________________ 5 MAX7033 AC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (Typical Application Circuit , VAVDD = VDVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) 2.2 2.0 3.5 2.2 2.5 2.0 1.5 1.8 0.5 -116 RSSI (V) fRF = 433MHz -114 RSSI (V) 1.8 VAC = 0V 1.6 1.6 1.4 -120 -1.5 1.4 fRF = 315MHz RSSI 1.2 -122 -15 10 35 60 85 -80 -60 -40 -20 0 -90 -70 -50 -30 TEMPERATURE (°C) RF INPUT POWER (dBm) IF INPUT POWER (dBm) LNA/MIXER VOLTAGE GAIN vs. IF FREQUENCY IMAGE REJECTION vs. RF FREQUENCY IMAGE REJECTION vs. TEMPERATURE 35 IMAGE REJECTION (dB) 45 49dB IMAGE REJECTION 25 LOWER SIDEBAND 15 FROM RFIN TO MIXOUT fRF = 315MHz 5 10 15 20 IF FREQUENCY (MHz) 25 45 40 fRF = 375MHz fRF = 315MHz fRF = 433MHz 30 fRF = 315MHz 44.5 44.0 43.5 43.0 fRF = 375MHz 42.5 42.0 fRF = 433MHz 41.5 35 -5 5 50 10 MAX7033 toc09 UPPER SIDEBAND -10 45.0 IMAGE REJECTION (dB) 55 55 MAX7033 toc07 65 0 -3.5 1.0 -140 -120 -100 110 -2.5 1.2 1.0 -124 -40 -0.5 DELTA -118 MAX7033 toc08 SENSITIVITY (dBm) -112 6 VAC = VDVDD MAX7033 toc06 2.4 41.0 40.5 30 280 300 320 340 360 380 400 420 440 460 480 RF FREQUENCY (MHz) -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 DELTA (%) IF BANDWIDTH = 280kHz MAX7033 toc05 AVERAGE CARRIER POWER 0.2% BER IF BANDWIDTH = 280kHz -110 2.4 MAX7033 toc04 -108 RSSI AND DELTA vs. IF INPUT POWER RSSI vs. RF INPUT POWER SENSITIVITY vs. TEMPERATURE SYSTEM GAIN (dB) MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock NORMALIZED IF GAIN vs. IF FREQUENCY S11 LOG MAGNITUDE PLOT OF RFIN 30 -15 -20 WITH INPUT MATCHING 20 10 0 -10 200MHz -20 315MHz -36dB -30 -25 -40 -30 -50 10 1 FREQUENCY (MHz) REGULATOR VOLTAGE vs. REGULATOR CURRENT PHASE NOISE vs. OFFSET FREQUENCY 0 MAX7033 toc13 2.9 -40°C 2.7 +25°C 2.5 2.3 +85°C 2.1 -20 PHASE NOISE (dBc/Hz) 3.1 fRF = 315MHz +105°C PHASE NOISE vs. OFFSET FREQUENCY -40 -60 -80 -100 1.7 10 20 30 40 REGULATOR CURRENT (mA) 50 60 -40 -60 -80 -100 -140 -140 0 fRF = 433MHz -20 -120 -120 1.9 0 PHASE NOISE (dBc/Hz) 3.3 REGULATOR VOLTAGE (V) 0 100 200 300 400 500 600 700 800 900 1000 100 IF FREQUENCY (MHz) 3.5 500MHz 315MHz MAX7033 toc15 -10 MAX7033 toc12 MAX7033 toc14 -5 S11 SMITH CHART PLOT OF RFIN MAX7033 toc11 40 S11 MAGNITUDE (dB) 0 NORMALIZED IF GAIN (dB) 50 MAX7033 toc10 5 10 100 1k 10k 100k OFFSET FREQUENCY (Hz) 1M 10M 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) _______________________________________________________________________________________ 7 MAX7033 Typical Operating Characteristics (continued) (Typical Application Circuit , VAVDD = VDVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033 Pin Description PIN TSSOP THIN QFN 1 29 FUNCTION XTAL1 Crystal Input 1 (See the Phase-Locked Loop section) 2, 7 4, 30 AVDD Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V low-dropout regulator, and should be bypassed to AGND with a 0.1μF capacitor as close as possible to the pin. Pin 7 must be externally connected to the supply from pin 2, and bypassed to AGND with a 0.01μF capacitor as close as possible to the pin. (See the Voltage Regulator section and the Typical Application Circuit.) 3 31 LNAIN Low-Noise Amplifier Input (See the Low-Noise Amplifier section) 4 32 LNASRC 5, 10 2, 7 AGND Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set the LNA input impedance (See the Low-Noise Amplifier section). Analog Ground Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter (See the LowNoise Amplifier section). 6 3 LNAOUT 8 5 MIXIN1 1st Differential Mixer Input. Connect to LC tank filter from LNAOUT. 9 6 MIXIN2 2nd Differential Mixer Input. Connect through a 100pF capacitor to VDD3 side of the LC tank. 11 8 IRSEL Image-Rejection Select. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL unconnected to center image rejection at 375MHz. Set VIRSEL = VDD5 to center image rejection at 433MHz. 12 9 MIXOUT 13 10 DGND Digital Ground 14 11 DVDD Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01μF capacitor as close as possible to the pin. (See the Typical Application Circuit.) 15 12 AC 16 14 XTALSEL 17 15 IFIN1 1st Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF capacitor as close to the pin as possible. 18 16 IFIN2 2nd Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz bandpass filter. 19 17 DFO Data Filter Output 20 18 DSN Negative Data Slicer Input 21 19 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter 22 20 DFFB Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter. 23 22 DSP Positive Data Slicer Input VDD5 +5V Supply Voltage. Bypass to AGND with a 0.01μF capacitor as close as possible to the pin. For +5V operation, VDD5 is the input to an on-chip voltage regulator whose +3.2V output appears at the pin 2 AVDD pin. (See the Voltage Regulator section and the Typical Application Circuit.) 24 23 25 24 26 26 27 8 NAME 27 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter. Automatic Gain Control. See Figure 1. Internally pulled down to AGND with a 100kΩ resistor. Crystal Divider Ratio Select. Drive XTALSEL low to select fLO/fXTAL ratio of 64, or drive XTALSEL high to select fLO/fXTAL ratio of 32. DATAOUT Digital Baseband Data Output PDOUT SHDN Peak-Detector Output Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a 100kΩ resistor. _______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock PIN NAME FUNCTION TSSOP THIN QFN 28 28 XTAL2 — 1, 13, 21, 25 N.C No Connection — — EP Exposed Pad (TQFN Only). Connect EP to GND. Crystal Input 2. Can also be driven with an external reference oscillator. (See the Crystal Oscillator section.) Functional Diagram LNASRC 4 LNAIN AVDD VDD5 AVDD DVDD DGND AGND 3 AC 15 LNAOUT 6 MIXIN1 MIXIN2 8 9 Q IMAGE REJECTION 2 24 IFIN1 17 28-PIN TSSOP PACKAGE IFIN2 18 0˚ AUTOMATIC GAIN CONTROL LNA MIXOUT 12 IRSEL 11 IF LIMITING AMPS ∑ 90˚ 3.2V REG I MAX7033 RSSI 7 14 13 5, 10 DIVIDE BY 64 VCO PHASE DETECTOR LOOP FILTER ÷1 DATA FILTER RDF1 100kΩ RDF2 100kΩ ÷2 CRYSTAL DRIVER 16 1 XTALSEL XTAL1 XTAL2 28 DATA SLICER POWERDOWN 27 SHDN 25 DATAOUT Detailed Description The MAX7033 CMOS superheterodyne receiver and a few external components provide the complete receive chain from the antenna to the digital output data. Depending on signal power and component selection, data rates as high as 33kbps Manchester (66kbps NRZ) can be achieved. The MAX7033 is designed to receive binary ASK data modulated in the 300MHz to 450MHz frequency range. ASK modulation uses a difference in amplitude of the carrier to represent logic 0 and logic 1 data. Voltage Regulator For operation with a single +3.0V to +3.6V supply voltage, connect AVDD, DVDD, and VDD5 to the supply voltage. 20 23 19 DSN DSP DFO 26 21 22 PDOUT OPP DFFB For operation with a single +4.5V to +5.5V supply voltage, connect VDD5 to the supply voltage. An on-chip voltage regulator drives one of the AVDD pins to approximately +3.2V. For proper operation, DVDD and both the AVDD pins must be connected together. Bypass VDD5, DVDD, and the pin 7 AVDD pin to AGND with 0.01μF capacitors, and the pin 2 AVDD pin to AGND with a 0.1μF capacitor, all placed as close as possible to the pins. Low-Noise Amplifier The LNA is an nMOS cascode amplifier with off-chip inductive degeneration, with a 3.0dB noise figure and an IIP3 of -12dBm. The gain and noise figures are dependent on both the antenna matching network at the LNA input and the LC tank network between the LNA output and the mixer inputs. _______________________________________________________________________________________ 9 MAX7033 Pin Description (continued) MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible input impedance match, such as a typical PCB trace antenna. A nominal value for this inductor with a 50Ω input impedance is 15nH, but is affected by PCB trace. The LC tank filter connected to LNAOUT comprises L3 and C2 (see the Typical Application Circuit). Select L3 and C2 to resonate at the desired RF input frequency. The resonant frequency is given by: fRF = 1 2π L TOTAL × CTOTAL where: LTOTAL = L3 + LPARASITICS. CTOTAL = C2 + CPARASITICS. LPARASITICS and CPARASITICS include inductance and capacitance of the PCB traces, package pins, mixer input impedance, LNA output impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation should be done to optimize the center frequency of the tank. Automatic Gain Control When the AC pin is low, the automatic gain-control (AGC) circuit monitors the RSSI output. As the RSSI output reaches 1.98V, which corresponds to RF input level of -62dBm, the AGC switches on the LNA gain reduction resistor. The resistor reduces the LNA gain by 35dB, thereby reducing the RSSI output by about 500mV. The LNA resumes high-gain mode when the RSSI level drops back below 1.39V (approximately -70dBm at RF input) for 1ms. The AGC has a hysteresis of 8dB. With the AGC function, the MAX7033 can reliably produce an ASK output for RF input levels up to 0dBm with modulation depth of 18dB. When the AC pin is high and SHDN goes high, the AGC circuit is disabled and the LNA is always in highgain mode. The AGC function can be resumed by bringing the AC pin low when SHDN is high. The MAX7033 features an AGC lock function that is asserted when the level at the AC pin transitions from low to high while SHDN is high. Locking the AGC locks the LNA in the current gain state. As shown in Figure 1, the AGC lock function can be enabled or disabled as long as the SHDN pin is high. Changing the state of AC when SHDN is low has no effect. Mixer A unique feature of the MAX7033 is the integrated image rejection of the mixer. This device eliminates the need for a costly front-end SAW filter for most applications. Advantages of not using a SAW filter are increased sensitivity, simplified antenna matching, less board space, and lower cost. The mixer cell is a pair of double balanced mixers that perform an IQ downconversion of the RF input to the 10.7MHz IF from a low-side injected LO (i.e., fLO = fRF fIF). The image-rejection circuit then combines these signals to achieve 44dB of image rejection. Low-side VIH SHDN PIN VIL VIH AC PIN VIL AGC LOCK AGC UNLOCK AGC LOCK AGC ENABLED AGC UNLOCK NO EFFECT NO EFFECT AGC DISABLED NO EFFECT AGC ENABLED Figure 1. AGC Lock Activation Cycles 10 ______________________________________________________________________________________ AGC DISABLED 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Phase-Locked Loop The PLL block contains a phase detector, charge pump, integrated loop filter, VCO, asynchronous 64x clock divider, and crystal oscillator driver. Besides the crystal, this PLL does not require any external components. The VCO generates a low-side LO. The relationship between the RF, IF, and crystal frequencies is given by: f -f fXTAL = RF IF 32 × M where: M = 1 (VXTALSEL = VDD5) or 2 (VXTALSEL = 0V) To allow the smallest possible IF bandwidth (for best sensitivity), minimize the tolerance of the reference crystal. Table 1. Component Values for Typical Application Circuit COMPONENT VALUE FOR fRF = 433MHz VALUE FOR fRF = 315MHz DESCRIPTION C1 100pF 100pF 5% C2 2pF 4pF ± 0.1pF C3 100pF 100pF 5% C4 100pF 100pF 5% C5 1500pF 1500pF 10% C6 220pF 220pF 5% C7 470pF 470pF 5% C8 0.47μF 0.47μF 20% C9 220pF 220pF 10% C10 0.01μF 0.01μF 20% C11 0.1μF 0.1μF 20% C12 15pF 15pF Depends on XTAL C13 15pF 15pF Depends on XTAL C14 0.01μF 0.01μF 20% C15 0.01μF 0.01μF 20% L1 56nH 120nH 5% or better* L2 15nH 15nH 5% or better* L3 15nH 27nH 5% or better* R1 5.1kΩ 5.1kΩ 5% R2 Open Open — R3 Short Short — X1 (÷64) 6.6128MHz** 4.7547MHz** Crystek or Hong Kong Crystal X1 (÷32) 13.2256MHz** 9.5094MHz** Crystek or Hong Kong Crystal Y1 10.7MHz ceramic filter 10.7MHz ceramic filter Murata *Wire wound recommended. **Crystal frequencies shown are for ÷64 (VXTALSEL = 0V) and ÷32 (VXTALSEL = VDD) ______________________________________________________________________________________ 11 MAX7033 injection is required due to the on-chip image-rejection architecture. The IF output is driven by a source follower biased to create a driving-point impedance of 330Ω; this provides a good match to the off-chip 330Ω ceramic IF filter. The IRSEL pin is a logic input that selects one of the three possible image-rejection frequencies. When VIRSEL = 0V, the image rejection is tuned to 315MHz. VIRSEL = VDD5/2 tunes the image rejection to 375MHz, and VIRSEL = VDD5 tunes the image rejection to 433MHz. The IRSEL pin is internally set to V DD5 /2 (image rejection at 375MHz) when it is left unconnected, thereby eliminating the need for an external VDD5/2 voltage. MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Intermediate Frequency and RSSI The IF section presents a differential 330Ω load to provide matching for the off-chip ceramic filter. The six internal AC-coupled limiting amplifiers produce an overall gain of approximately 65dB, with a bandpass-filter-type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz. The RSSI circuit demodulates the IF by producing a DC output proportional to the log of the IF signal level, with a slope of approximately 14.2mV/dB (see the Typical Operating Characteristics). Applications Information Crystal Oscillator The crystal oscillator in the MAX7033 is designed to present a capacitance of approximately 3pF between the XTAL1 and XTAL2. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. Crystals designed to operate with higher differential load capacitance always pull the reference frequency higher. For example, a 4.7547MHz crystal designed to operate with a 10pF load capacitance oscillates at 4.7563MHz with the MAX7033, causing the receiver to be tuned to 315.1MHz rather than 315.0MHz, an error of about 100kHz, or 320ppm. In actuality, the oscillator pulls every crystal. The crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance. Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: ⎞ C ⎛ 1 1 fP = M ⎜ × 106 2 ⎝ CCASE + CLOAD CCASE + CSPEC ⎟⎠ It is possible to use an external reference oscillator in place of a crystal to drive the VCO. AC-couple the external oscillator to XTAL2 with a 1000pF capacitor. Drive XTAL2 with a signal level of approximately -10dBm. ACcouple XTAL1 to ground with a 1000pF capacitor. Data Filter The data filter is implemented as a 2nd-order lowpass Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency should be set to approximately 1.5 times the fastest expected data rate from the transmitter. Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. The configuration shown in Figure 2 can create a Butterworth or Bessel response. The Butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of C5 and C6, use the following equations, along with the coefficients in Table 2: C5 = b a(100k)( π)(fC ) C6 = a 4(100k)( π)(fC ) where fC is the desired 3dB corner frequency. Table 2. Coefficents to Calculate C5 and C6 a b Butterworth (Q = 0.707) FILTER TYPE 1.414 1.000 Bessel (Q = 0.577) 1.3617 0.618 where: fP is the amount the crystal frequency pulled in ppm. CM is the motional capacitance of the crystal. CCASE is the case capacitance. CSPEC is the specified load capacitance. CLOAD is the actual load capacitance. When the crystal is loaded as specified, i.e., CLOAD = CSPEC, the frequency pulling equals zero. RSSI MAX7033 RDF1 100kΩ RDF2 100kΩ 22 DFFB 21 OPP 19 DFO C6 C5 Figure 2. Sallen-Key Lowpass Data Filter 12 ______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033 For example, to choose a Butterworth filter response with a corner frequency of 5kHz: 1.000 MAX7033 ≈ 450pF C5 = (1.414)(100kΩ)(3.14)(5kHz) C6 = 1.414 ≈ 225pF k Ω 4 100 ( )( )(3.14)(5kHz) DATA SLICER Choosing standard capacitor values changes C5 to 470pF and C6 to 220pF, as shown in the Typical Application Circuit. Data Slicer The data slicer takes the analog output of the data filter and converts it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. One input is supplied by the data filter output. Both comparator inputs are accessible offchip to allow for different methods of generating the slicing threshold, which is applied to the second comparator input. The suggested data slicer configuration uses a resistor (R1) connected between DSN and DSP with a capacitor (C4) from DSN to DGND (Figure 3). This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The values of R1 and C4 affect how fast the threshold tracks to the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower than the lowest expected data rate. Note that a long string of zeros or ones can cause the threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an equal number of zeros and ones, is used. To prevent continuous toggling of DATAOUT in the absence of an RF signal due to noise, add hysteresis to the data slicer as shown in Figure 4. 19 DFO 23 DSP R1 C4 Figure 3. Generating Data Slicer Threshold MAX7033 DATA SLICER 25 DATAOUT 20 DSN 23 DSP R4 19 DFO R1 R3 R2 C4 *OPTIONAL Figure 4. Generating Data Slicer Hysteresis MAX7033 Peak Detector The peak-detector output (PDOUT), in conjunction with an external RC filter, creates a DC output voltage equal to the peak value of the data signal. The resistor provides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data-filter output voltage. For faster data slicer response, use the circuit shown in Figure 5. 20 DSN 25 DATAOUT DATA SLICER 25 DATAOUT 20 DSN 23 DSP 19 DFO 26 PDOUT 25kΩ 47nF Figure 5. Using PDOUT for Faster Startup ______________________________________________________________________________________ 13 MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Layout Considerations A properly designed PCB is an essential part of any RF/microwave circuit. On high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are on the order of λ/10 or longer act as antennas. Keeping the traces short also reduces parasitic inductance. Generally, 1in of a PCB trace adds about 20nH of parasitic inductance. The parasitic inductance can have a dramatic effect on the effective inductance of a passive component. For example, a 0.5in trace connecting a 100nH inductor adds an extra 10nH of inductance or 10%. To reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. Also, use low-inductance connections to ground on all GND pins, and place decoupling capacitors close to all power-supply pins. Control Interface Considerations When operating the MAX7033 with a +4.5V to +5.5V supply voltage, the SHDN and AC pins can be driven by a microcontroller with either 3V or 5V interface logic levels. When operating the MAX7033 with a +3.0V to +3.6V supply, only 3V logic from the microcontroller is allowed. Typical Application Circuit VDD3 IF VDD IS VDD (SEE TABLE) THEN VDD3 IS 3.0V TO 3.6V CONNECTED TO VDD CREATED BY LDO, 4.5V TO 5.5V AVAILABLE AT AVDD (PIN 2) X1 C11 C13 1 RF INPUT 2 C1 L1 3 4 L2 5 6 C14 VDD3 7 L3 C3 8 C2 9 C4 10 C9 11 12 13 14 ** XTAL1 XTAL2 AVDD SHDN LNAIN PDOUT LNASRC MAX7033 DATAOUT AGND VDD5 LNAOUT DSP AVDD DFFB MIXIN1 OPP MIXIN2 DSN AGND DFO IRSEL IFIN2 MIXOUT IFIN1 DGND XTALSEL DVDD AC 28 C12 TO/FROM μP POWER-DOWN DATA OUT 27 26 R2 25 C15 24 R3 23 22 21 C7 20 19 18 17 R1 16 15 C5 Y1 C10 COMPONENT VALUES IN TABLE 1 **SEE THE MIXER SECTION. 14 C6 * IF FILTER IN OUT GND *SEE PHASE-LOCKED LOOP SECTION. ______________________________________________________________________________________ C8 FROM μP 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock PROCESS: CMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. LAND PACKAGE PACKAGE OUTLINE NO. PATTERN NO. TYPE CODE 28 TSSOP U28+1 21-0066 90-0171 32 TQFN-EP T3255+3 21-0140 90-0001 ______________________________________________________________________________________ 15 MAX7033 Chip Information MAX7033 315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock Revision History REVISION NUMBER REVISION DATE 0 7/04 Initial release 1/11 Updated Ordering Information, Pin Configurations, Absolute Maximum Ratings, DC Electrical Characteristics, AC Electrical Characteristics, Typical Operating Characteristics, Pin Description, Functional Diagram, Voltage Regulator and Layout Considerations sections, Typical Application Circuit, Chip Information, and Package Information 9/11 Updated input impedance values in AC Electrical Characteristics table; updated TOC3 and TOC4 labels in Typical Operating Characteristics; clarified equations in Pin Description and Phase-Locked Loop and Crystal Oscillator sections; updated components in Table 1; and added new Control Interface Considerations section 1 2 DESCRIPTION PAGES CHANGED — 1–9, 13, 14, 15 3–6, 11–14 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.